Digital circuit mechanisms for normalization functions

Abstract

The present disclosure includes a digital circuit that generates a value of a power of two raised to an input value. For example, the digital circuit may include combinatorial logic that receives a first digital bit representing an input mantissa of the input value and a second digital bit representing an input exponent of the input value. The combinatorial logic generates a plurality of output mantissas and a plurality of output exponents that correspond to approximations of the power of two raised to the input value when the input value is positive and negative and when the input exponent is above and below the first value. A selection circuit is configured to receive the output mantissa and the output exponent. The selection circuit includes a selection control input coupled to the input exponent and the input sign bit of the input value for selecting one of the output mantissas and one of the output exponents.

Description

Technical Field

[0001] Background

[0001] This disclosure relates to computing, and more particularly to digital circuits for normalization functions.

Background Art

[0002]

[0002] Artificial neural networks (hereinafter neural networks) are generally increasing in importance in artificial intelligence applications and modern computing. FIG. 1 shows an exemplary neural network. The neural network 100 receives input values corresponding to the recognized features. The input values are multiplied by weights (represented by side 101) and added (e.g., summed) together at vertex 102. An activation function is applied to the result at vertex 102 to generate an output value. The values are combined across multiple vertices and layers of vertices to produce a network output value corresponding to the result.

[0003]

[0003] Such systems generally "learn" to perform tasks by considering examples without being programmed using task-specific rules. Initially, the weights may be untrained. During the training phase, input values for corresponding known results are processed by the network, and the difference (or error) between the network output values is compared to the known values. The weights can be adjusted based on the error using a process known as backpropagation, in which the calculations flow in the reverse direction (e.g., from the output to the input). Training can involve continuously adjusting the weights over many input samples and corresponding known network output values. This is often referred to as the training phase. Once trained, the system can receive an input and produce a meaningful result (e.g., classification or recognition). This is often referred to as the inference phase.

Summary of the Invention

[0004]

[0004] As the popularity of neural networks increases, so does the complexity of the problems they solve. As the complexity of the problems increases, so does the size of the network and the computational complexity. One common and very time-consuming operation in neural networks is normalization. For example, when activations and weights are multiplied and summed across the vertices of a network, it is common to normalize the result. Softmax is one example of such a normalization function. Softmax can be used, for example, as the final activation function of a neural network to normalize the network's output to a probability distribution across predicted output classes. However, normalization functions often require complex numerical calculations that can slow down the network. The disclosures presented herein provide digital circuits and processing techniques that can be used more efficiently with normalization functions (and other applications).

[0005]

[0005] Various embodiments, examples and advantages are described in the following detailed description.

[0006] Brief explanation of the drawing

[0006] Various embodiments of the present disclosure are shown in the accompanying drawings, not as an example, but as an example. [Brief explanation of the drawing]

[0007] [Figure 1]

[0007] An exemplary neural network is shown. [Figure 2]

[0008] A digital circuit according to one embodiment is shown. [Figure 3]

[0009] A digital circuit according to another embodiment is shown. [Figure 4]

[0010] An exemplary digital circuit for generating a 2x approximation, according to another embodiment, is shown. [Figure 5A]

[0011] An exemplary digital circuit for generating a 4x approximation, according to another embodiment, is shown. [Figure 5B]

[0012] Another exemplary digital circuit for generating a 4x approximation, according to another embodiment, is shown. [Figure 6]

[0013] A normalization system according to one embodiment is shown. [Figure 7]

[0014] A method according to one embodiment is shown. [Figure 8]

[0015] Several embodiments of neural network processing systems are shown. [Modes for carrying out the invention]

[0008] Detailed explanation

[0016] In the following description, numerous examples and specific details are provided for explanatory purposes to provide a full understanding of the disclosure. Such examples and details should not be construed as unreasonably limiting the elements of the claims or the claimed subject matter as a whole. It will be apparent to those skilled in the art that, based on different claim language, the claimed subject matter may include some or all of the features in these examples, individually or in combination, and may further include variations and equivalents of the features and techniques described herein.

[0009]

[0017] The features and advantages of this disclosure are that it takes an input value (e.g., floating-point) and raises a power of 2 (e.g., 2, 4, ...) to the power of the input value x (e.g., 2 x ,4 xThe system includes a digital circuit that produces an output value corresponding to an approximation of the softmax function (etc.). As will be described in more detail below, the softmax function can be approximated using such a function. Advantageously, such a function can be implemented in combinational digital logic, for example, which may be able to generate an output without waiting for multiple clock cycles. Thus, some exemplary embodiments may be able to generate an output based solely on the current input, in contrast to sequential logic where the output depends not only on the current input but also on previous inputs (e.g., data is stored). This may result in faster, lower-latency systems, for example, that can implement many approximations of the softmax function.

[0010]

[0018] Figure 2 shows a digital circuit 200 according to one embodiment. The circuit 200 receives an input value 201 in floating-point representation. The input value (Xi) 201 is represented as an input exponent (e x ), input mantissa (m x ) and input sign bits (s x ) includes. The digital circuit 200 has an input mantissa m x The digital bits that represent the input exponent e x The system includes a combinational logic 210 that receives digital bits representing the input value and generates a plurality of output mantissas and a plurality of output exponents 250 corresponding to an approximation of the input value raised to the power of 2. In one exemplary embodiment, the combinational logic 210 generates a plurality of shifted versions of the input mantissa, which is shifted based on the input exponent to produce the output mantissas and output exponents. Advantageously, separate output mantissas and output exponents can be generated across four quadrants, for example, when the input value is positive and negative, and when the input exponent is above and below a first value.

[0011]

[0019] The digital circuit 200 further includes a selection circuit 220. The selection circuit 220 is configured to receive an output significand and an output exponent 250 and generate one final output significand 251 and one final output exponent 252. Thus, embodiments of the present disclosure may include two or more selection circuits, such as a multiplexer, within the selection circuit 220. The selection circuit 220 may include a selection control input coupled to the input exponent and input sign bit of the input value (Xi). Here, as shown in further embodiments below, the features of the present disclosure include selecting one of the output significands as the final output significand 251 and one of the output exponents as the final output exponent 252 based on the input exponent and input sign bit. The digital circuit 200 is to implement an approximation of a power of 2 raised to the input value (e.g., N x , N = 2, 4, 8, 16,...), so the output sign bit is a constant value 1 and may be wire-connected, for example, at 230. Therefore, the output value (Yi) 202 generated by the digital circuit 200 may also be a floating-point value including an exponent (e y ), a significand (m y ) and a sign bit (s y ). Advantageously, in some embodiments, the stream of input values (Xi) may be converted to output values (Yi) very quickly (e.g., on each clock cycle) for efficient calculation of an approximation of the softmax function.

[0012]

[0020] FIG. 3 shows a digital circuit according to another embodiment. The features and advantages of the present disclosure include shifting the significand of the input value based on the exponent to generate an output significand and an output exponent that can then be selected based on the input exponent and input sign bit. In this example, the digital circuit 314 receives an input value 312 including an input sign bit, an input exponent, and an input significand, and outputs a power of 2 raised to the input (e.g., 2 x , 4 xThis produces an output value 316 that is approximately equal to ). The digital circuit 314 includes a combinational logic 320, which in this example includes a shifter circuit 322. For example, multiple shifter circuits may receive an input mantissa and an input exponent. Features and advantages of this disclosure include shifting the input mantissa 330 based on the input exponent 332 to produce multiple output mantissas 336 and output exponent 338, which are coupled to selection circuits 326 and 328 for selecting one output mantissa / exponent pair as the final output based on the input sign bit 334 and the input exponent 332. The shifter circuits may produce left and right shifted versions of the input mantissa. For example, a right shifter circuit may include a first input coupled to the input mantissa 330 through a logic circuit configured to add the input mantissa to a constant, and a shift input coupled to the input exponent 332 through a logic circuit configured to negate the input exponent. In addition, the first left-shifter circuit may include, for example, a first input coupled to receive an input mantissa 330 and a shift input coupled to an input exponent 332. The right-shifted version of the input mantissa may be used to form the first and second output mantissas, and the lower bits of the left-shifted version of the input mantissa may be used to form the third and fourth output mantissas. Furthermore, the upper bits of the left-shifted version of the input mantissa may be used to form the first and second output exponents. Further examples and illustrations of these techniques are provided below.

[0013]

[0021] In some exemplary embodiments, the shifter circuit is a barrel shifter circuit, which is a digital circuit that can shift a data word by a specified number of bits using combinational logic (e.g., without using sequential logic at all, and without the associated delays resulting from storing data over time). Barrel shifters may be advantageous in applications where it is desirable to obtain the result on a single clock cycle, for example.

[0014]

[0022] Each output mantissa 336 is, for example, a specific pair of values ​​for the input exponent 332 and the input code bit 334 (e.g., s greater than or less than 1). x and e greater than or less than 0 or -1x It may have associated output exponents 338 corresponding to four sets of tuples for the given number. Selection circuits 326 and 328 are controlled by the input exponent 332 and the input sign bit 334. Thus, based on the input exponent 332 and the input sign bit 334, a final output mantissa 340 and final output exponent 342 may be selected from a plurality of output mantissas 336 and output exponents 338.

[0015]

[0023] Therefore, based on the input sign bit and input exponent, selection circuit 326 may produce different output mantissas, and selection circuit 328 may produce different output exponents. Firstly, when the input sign bit is positive and the input exponent is less than a first value (e.g., 0 or -1), selection circuits 326 and 328 may produce a final output mantissa containing a shifted version of the sum of the input mantissa and a constant, and an output exponent having a value of 0 (0). Secondly, when the input sign bit is positive and the input exponent is greater than a first value, selection circuits 326 and 328 may produce a final output mantissa containing the remainder of another shifted version of the input mantissa, and a final output exponent having a digital value of 1 shifted based on the input exponent added to the integer quotient of the shifted version of the input mantissa. Thirdly, when the input sign bit is negative and the input exponent is less than a first value, the selection circuits 326 and 328 may produce a final output mantissa containing a first shifted version of the sum of the input mantissa and a constant subtracted from a second constant, and a final output exponent having a value of negative 1 (-1). Finally, when the input sign bit is negative and the input exponent is greater than a first value, the selection circuits 326 and 328 may produce a final output mantissa containing a second shifted version of the input mantissa subtracted from a second constant, and the negation of the second output exponent minus 1. Various exemplary implementations of the above techniques and further illustrations are provided below.

[0016] Example Implementation

[0024] Figure 4 shows another embodiment, 2 xAn exemplary digital circuit 400 for generating an approximation of is shown. The digital circuit 400 includes a right shifter circuit 410, a left shifter circuit 412, and a left shifter circuit 414. The input mantissa 450 is coupled to an adder circuit 402. The adder circuit 402 further receives a constant value (N) 401 and outputs the sum of the input mantissa and the constant (N). For example, the input mantissa (m) can take values ​​from 0 to 128. x , 0≦m x For <128), the constant N may be equal to 128. In various embodiments, the adder 402 may be replaced with OR logic for implementation, for example, as shown in the further examples below (e.g., 128 or m x The output of adder 402 is coupled to the input of right shifter 410. The shift input of right shifter 410, which controls the shift operation, is coupled to input exponent 451 through negation circuit (-x) 408, and input exponent (e x ) accepts the negative number of the input exponent (-e x This produces a right-shifted version of the input mantissa 450, which has values ​​from 0 to 128, as follows: (128+m x )>>-(e x )

[0017]

[0025] The above right-shifter version of the input mantissa is 2 when the input sign bit is +1 and the input exponent is less than 0. x The first output mantissa for the value is 460.

[0018]

[0026] The input mantissa 450 is also coupled to the input of the left shifter 412. The shift input of the left shifter 412 is coupled to the input exponent 451. Thus, the left shifter 412 produces a left-shifted version of the input mantissa. The lower bits of the left-shifted version of the input mantissa form a remainder function. In this example, when the input sign bit is +1 and the input exponent is 0 or greater, the lower bits of the left-shifted version of the input mantissa are 2 x This corresponds to the second output mantissa 461 for the value of . (m x <<(ex ))mod 128.

[0019]

[0027] In this example, the first and second output mantissas 460-461 are coupled to a multiplexer (Mux) 416. The output of Mux 416 is coupled to the input of Mux 420, and the output of Mux 420 produces the final output mantissa. Mux 416 and 420 have selection control signals Select 0 and Select 1 based on input code bit 452 and input exponent 451 values ​​for selecting one of the output mantissas 460-461.

[0020]

[0028] Right and left-shifted versions of the input mantissa can be subtracted from a constant (M) to form an additional output mantissa. In this example, the output of Mux416 is coupled to a constant subtraction logic circuit 418 (Mx) that subtracts the output of Mux416 from a constant value (e.g., 127 for mantissas with values ​​between 0 and 128). Therefore, the output of the subtraction circuit can be one of the following: 127-(128+m x )>>-(e x ), or 127-(m x <<(e x ))mod 128.

[0021]

[0029] When the input sign bit is -1 and the input exponent is positive or negative, these alternative outputs are 2 x The third and fourth output mantissas are formed for the value of . Either output mantissa may be selected by Mux420 as the final output mantissa.

[0022]

[0030] Multiple output exponents can also be generated from the shifter circuit. In various embodiments, the output exponent is the input exponent (2) obtained by raising the upper bits of the left-shifted input mantissa to the power of 2. ex This can result from adding to the value of ). In this example, the digital circuit 400 further includes a left shifter circuit 414 having an input coupled to a value of 1 (e.g., the binary value of 1 or the bit value of 1) and a shift input coupled to the input exponent 451, and by left shifting 1 by the input exponent 2 exThis is achieved. The higher bits from the left shifter 412 form an integer division function (DIV). Therefore, the outputs of shifter 412 and shifter 414 are added in adder 422, which can produce an output exponent 464 as follows.

number

[0023]

[0031] The output of adder 422 is further combined through the negation circuit (-1-x) 424 to produce another output exponent 465, as follows:

number

[0024]

[0032] Finally, output exponent 464 is coupled to the first input of Mux432, and output exponent 465 is coupled to the second input of Mux432. The value 0 (428) and the negative value 1 (-1) (430) are coupled to the other inputs of Mux432. x The final output mantissa and exponent for this can be selected as follows:

[0025] [Table 1]

[0026]

[0033] Therefore, the digital circuit 400 further includes control logic 470 configured to receive an input exponent and an input sign bit and generate control signals (Select 0, Select 1) to mantissa select circuits (e.g., Mux 416 and 420) and exponent select circuits (e.g., Mux 432). The selection control signals Select 0 and Select 1 configure a multiplexer such that when the input sign bit is positive and the input exponent is less than 0, the output of Mux 420 is coupled to the output of the right shifter circuit 410 and the output of Mux 432 is coupled to the value 0 428. In addition, the selection control signals Select 0 and Select 1 configure a multiplexer such that when the input sign bit is positive and the input exponent is 0 or greater, the output of Mux 420 is coupled to the lower bit of the left shifter circuit 412 and the output of the exponent select circuit is coupled to the sum of the upper bit of the left shifter circuit 412 and the power of 2 corresponding to the input exponent. Next, the selection control signals Select 0 and Select 1 configure the multiplexer such that when the input sign bit is positive and the input exponent is less than 0, the output of Mux420 is coupled to the output of the right shifter circuit 410 through the constant subtraction logic circuit 418, and the output of the multiplexer 432 is coupled to the constant negative value of 1 (-1). Finally, the selection control signals Select 0 and Select 1 configure the multiplexer such that when the input sign bit is negative and the input exponent is greater than a first value, the output of Mux420 is coupled to the lower bit of the left shifter circuit through the constant subtraction logic circuit 418, and the output of the multiplexer 432 is coupled to the negative sum of the upper bit of the left shifter circuit 412 and the power of 2 corresponding to the input exponent.

[0027]

[0034] Mux416, 420, and 432 are examples of selection circuits, while the other circuits in Figure 4 are one exemplary combinational logic mechanism that takes a first digital bit representing the input mantissa of the input value and a second digital bit representing the input exponent of the input value to generate multiple output mantissas and multiple output exponents.

[0028]

[0035] Figure 5A shows a different embodiment of 4 xAn exemplary digital circuit 500A for generating an approximation is shown. As shown in this example, the technique described above is 4 x It can also be used to implement digital circuits for generating approximations. 4 x For approximation purposes, the mantissa is obtained by adding the input exponent to a constant (for example, e x It is shifted based on +1). Therefore, the digital circuit 500A further includes a +1 adder circuit that adds a value of 1 to the input exponent. In this example, as described above, the adder between the input mantissa and the shifter 410 is replaced by OR logic. The following table shows the behavior of the digital circuit 500A.

[0029] [Table 2]

[0030]

[0036] Mux416, 420, and 432 are examples of selection circuits, while the other circuits in Figure 5A are further exemplary combinational logic mechanisms for receiving a first digital bit representing the input mantissa of an input value and a second digital bit representing the input exponent of an input value, and generating multiple output mantissas and multiple output exponents.

[0031]

[0037] Figure 5B shows a different embodiment of 4 x Another exemplary digital circuit 500B for generating an approximation is shown. In this example, Mux418 is removed, and Mux520 has one input coupled to the input mantissa and another input coupled to the input mantissa through OR logic 502. In this example, shifter 521 is a bidirectional shifter whose shift direction (left / right) is set by the shift polarity input (in this case, the input sign bit). For a shift polarity input s, the shift is as follows (s==0: no shift; S>0: position s, shifted to the left; S<0: position s, shifted to the right). The behavior of digital circuit 500B is the same as shown in Table 2 above. Removing adder circuit (+1) 504 results in the same behavior as shown in Table 1 above.

[0032]

[0038] Mux416, 420, and 432 are further examples of selection circuits, and the other circuits in Figure 5B are further exemplary combinational logic mechanisms for receiving a first digital bit representing the input mantissa of an input value and a second digital bit representing the input exponent of an input value, and generating multiple output mantissas and multiple output exponents.

[0033]

[0039] Figure 6 shows a normalization system 600 according to one embodiment. In this example, the input vector is A x To determine A, it is taken by approximation circuit 602, where A is a power of 2. Circuit 602 can be implemented using one of the techniques described above. Circuit 602 can be used to determine a normalization function such as an approximation of the softmax function. x The value of ΣA is generated. For example, the value of Ax may be stored in buffer 604. The values ​​can be added together in summation circuit 606. The divider circuit 608 adds the values ​​in buffer 604 and the summation value ΣA x Access the normalized value: A x / ΣA x This can result in the normalized value being coupled to, for example, a matrix multiplication circuit 610. In some embodiments, the normalized value is used, for example, to process neural network data.

[0034]

[0040] The following shows how the circuit behavior described above can approximate the softmax function. The softmax function is defined as follows:

number

[0041] At Softmax

number

number

[0035]

[0042] Here, s x is the sign of x (for example, s x = +1 or s x =-1), e x is the exponent of x (for example, -7 ≤ e x <=7), m x is the mantissa of x (for example, 0 ≤ m x <128). In bfloat16,

number

[0036]

[0043] The softmax function can be approximated using powers of 2. For example, Softmax2 can be defined as follows:

number

[0037]

[0044] Note that Softmax(x) = Softmax2(log2(e)*x) = Softmax2(1.44*x). In other words, to obtain a better approximation, 2 x Before calling the circuit mechanism that approximates it, we can multiply x by 1.44.

[0038]

[0045] next,

number

number

[0039]

[0046]

number

number

number

[0040]

[0047] There are four cases regarding the sign bit and input exponent.

[0041]

[0048] Case A:s x = +1 and e x <0 (for example, a small positive number):

number

[0049] Case B:s x = +1 and e x ≥ 0 (for example, a large positive number):

number

[0042]

[0050] This is -7≦e xNote that since this involves shifting and "bit picking" using <=7, the implementation is very simple. (For example, m x The bits are left-shifted, and as described above, the lower 7 bits are used in the mantissa and the higher bits are used in the exponent.

[0051] Case C:s x =-1 and e x <0 (for example, a small negative number):

number

[0052] Case D:s x =-1 and e x ≥ 0 (for example, a large negative number):

number

[0043]

[0053] The following shows a softmax approximation using powers of 4. For example, Softmax4 can be defined as follows:

number

[0044]

[0054] next,

number

number

[0045]

[0055]

number

number

number

[0046]

[0056] Case A:s x = +1 and e x <-1 (for example, a small positive number):

number

[0047]

[0057] Case B:s x = +1 and e x ≥ -1 (for example, a large positive number):

number

[0048]

[0058] In this case as well, the implementation is -7≦e x Includes shifts and "bit picking" using <=7. (For example, m x (The bits are left-shifted, and the lower 7 bits may be used in the mantissa, and the higher bits may be used in the exponent.)

[0049]

[0059] Case C:s x =-1 and e x <-1 (for example, a small negative number):

number

[0050]

[0060] Case D:s x =-1 and e x ≥ -1 (for example, a large negative number):

number

[0051]

[0061] Figure 7 shows a method 700 according to one embodiment. In 702, a first digital bit and a second digital bit are received into the digital circuit. The first digital bit represents the mantissa of the input value, and the second digital bit represents the exponent of the input value. The input value may be in floating-point format and may further include, for example, a sign bit. 702 generates a plurality of output mantissas and a plurality of output exponents. The output mantissas and output exponents are powers of 2 raised to the power of the input value x (for example, 2 x ,4 x This corresponds to an approximation of ,...). In 706, one of a plurality of output mantissas and one of a plurality of output exponents are selected based on the input exponent and input sign bit. Thus, method 700 can be used, for example, to approximate the softmax function in a neural network. x , 4 x It generates digital values ​​(for example, in floating-point format) that correspond to approximations such as the above. The circuit for outputting a digital value that approximates the result of raising 2 to the power of the input value can be used in other applications as well.

[0052]

[0062] Figure 8 shows a neural network processing system according to several embodiments. In various embodiments, the neural network according to the Disclosure may be implemented and trained within a hardware environment including one or more neural network processors. The neural network processor may refer to, for example, various graphics processing units (GPUs) (e.g., GPUs for processing neural networks produced by Nvidia Corp®), field-programmable gate arrays (FPGAs) (e.g., FPGAs for processing neural networks produced by Xilinx®), or various application-specific integrated circuits (ASICs) or neural network processors having hardware architectures optimized for neural network computation. In this exemplary environment, one or more servers 1002, which may have the architecture shown in Figure 9 above, may be coupled to a plurality of controllers 1010(1) to 1010(M) through a communication network 1001 (e.g., switches, routers, etc.). The controllers 1010(1) to 1010(M) may also include the architecture shown in Figure 9 above. Each controller 1010(1) to 1010(M) may be coupled to one or more NN processors, such as processors 1011(1) to 1011(N) and 1012(1) to 1012(N). NN processors 1011(1) to 1011(N) and 1012(1) to 1012(N) may include various configurations of functional processing blocks and memory optimized for neural network processing such as training or inference. The NN processor in Figure 8 may include digital circuits described herein for normalizing values ​​(e.g., approximating a softmax function). The NN processor is optimized for neural network computation. Server 1002 may configure controller 1010 with NN models and input data to the models, which can be loaded and executed in parallel by NN processors 1011(1) to 1011(N) and 1012(1) to 1012(N). The models may include, for example, layers and associated weights as described above. An NN processor can load a model, apply inputs, and produce output results.The NN processor can also implement training algorithms, for example. The digital circuits described herein can be used for both training and inference, for example.

[0053] Further exemplary embodiments

[0063] In various embodiments, this disclosure includes systems, methods, and apparatus for generating approximations that may be used for normalization. The following examples may be used individually or in various combinations.

[0054]

[0064] In one embodiment, the disclosure includes a digital circuit comprising: a combinational logic that receives a first digital bit representing an input mantissa of an input value and a second digital bit representing an input exponent of an input value, and which generates a plurality of output mantissas and a plurality of output exponents corresponding to an approximation of a power of 2 raised by the input value when the input value is positive and negative and when the input exponent is greater than and less than a first value; and a digital circuit comprising two or more selection circuits configured to receive the plurality of output mantissas and a plurality of output exponents, the selection circuits including a selection control input coupled to the input exponent and input sign bit of the input value for selecting one of the plurality of output mantissas and one of the plurality of output exponents.

[0055]

[0065] In another embodiment, the Disclosure includes a method for generating a normalized value, comprising: receiving a first digital bit representing the input mantissa of an input value and a second digital bit representing the input exponent of an input value in a combinational logic including one or more shifter circuits; generating a plurality of output mantissas and a plurality of output exponents corresponding to an approximation of a power of 2 raised by the input value when the input value is positive and negative and when the input exponent is greater than and less than a first value; and selecting one of the plurality of output mantissas and one of the plurality of output exponents based on the input exponent and input sign bit of an input value using two or more selection circuits configured to receive the plurality of output mantissas and a plurality of output exponents.

[0056]

[0066] In another embodiment, the disclosure includes a digital circuit comprising: combinational logic means for receiving a first digital bit representing an input mantissa of an input value and a second digital bit representing an input exponent of an input value, and combinational logic means for generating a plurality of output mantissas and a plurality of output exponents corresponding to an approximation of a power of 2 raised by the input value when the input value is positive and negative and when the input exponent is greater than and less than a first value; and selection circuit means for receiving the plurality of output mantissas and a plurality of output exponents and selecting one of the plurality of output mantissas and one of the plurality of output exponents based on the input exponent and input sign bit of the input value.

[0057]

[0067] In one embodiment, the combinational logic generates multiple shifted versions of the input mantissa based on the input exponent, resulting in multiple output mantissas and multiple output exponents.

[0058]

[0068] In one embodiment, two or more selection circuits, when the input sign bit is positive and the input exponent is less than a first value, produce a first output mantissa containing the sum of a first shifted version of the input mantissa and a first constant, and a first output exponent having a value of 0; when the input sign bit is positive and the input exponent is greater than a first value, produce a second output mantissa containing the remainder of a second shifted version of the input mantissa, and add a digital value of 1 shifted based on the input exponent to the integer quotient of the second shifted version of the input mantissa. This produces a second output exponent having a value of 1 (-1), a first shifted version of the input mantissa, a third output mantissa containing the sum of the first constants minus the second constant when the input sign bit is negative and the input exponent is less than the first value, and a third output exponent having a value of negative 1 (-1), and a fourth output mantissa containing the remainder of the second shifted version of the input mantissa minus the second constant when the input sign bit is negative and the input exponent is greater than the first value, and the negation of the second output exponent minus 1.

[0059]

[0069] In one embodiment, the combinational logic includes one or more shifter circuits having an input coupled to an input mantissa and a shift input coupled to an input exponent, wherein the one or more shifter circuits produce left and right shifted versions of the input mantissa.

[0060]

[0070] In one embodiment, a right-shifted version of the input mantissa is used to form the first and second output mantissas, and the lower bits of a left-shifted version of the input mantissa are used to form the third and fourth output mantissas.

[0061]

[0071] In one embodiment, a right-shifted version of the input mantissa is subtracted from a constant to form a second output mantissa.

[0062]

[0072] In one embodiment, a left-shifted version of the input mantissa is subtracted from a constant to form a fourth output mantissa.

[0063]

[0073] In one embodiment, the upper bits of the left-shifted version of the input mantissa are used to form the first and second output exponents.

[0064]

[0074] In one embodiment, the upper bits of the left-shifted version of the input mantissa are added to the value generated based on the input exponent to form the first and second output exponents.

[0065]

[0075] In one embodiment, the value generated based on the input exponent includes bits that have been left-shifted based on the input exponent.

[0066]

[0076] In one embodiment, the added upper bits of the left-shifted version of the input mantissa and the value generated based on the input exponent are negated to produce a second output exponent.

[0067]

[0077] In one embodiment, one or more shifter circuits include barrel shifter circuits.

[0068]

[0078] In one embodiment, one or more shifter circuits include a right shifter circuit having a first input coupled to the input mantissa through a logic circuit configured to add the input mantissa to a constant, and a shift input coupled to the input exponent through a logic circuit configured to negate the input exponent, and a first left shifter circuit having a first input coupled to receive the input mantissa and a shift input coupled to the input exponent.

[0069]

[0079] In one embodiment, one or more shifter circuits further include a second left shifter circuit having a first input coupled to receive a digital value of 1 and a shift input coupled to an input exponent, wherein the outputs of the first left shifter circuit and the second left shifter circuit are added together.

[0070]

[0080] In one embodiment, two or more selection circuits include a first multiplexer having a first input coupled to the output of a right shifter circuit and a second input coupled to the lower bits of a first left shifter circuit.

[0071]

[0081] In one embodiment, the two or more selection circuits further include a second multiplexer having a first input coupled to the output of a first multiplexer, and a second input coupled to the output of the first multiplexer through a logic circuit configured to subtract a value on the input of the logic circuit from a constant.

[0072]

[0082] In one embodiment, two or more selection circuits include a multiplexer, the multiplexer having a first input coupled with the upper bits of a first left shifter circuit and a power of 2 corresponding to the exponent, a second input coupled with the negative version of the sum, a third input coupled with a value of 0, and a fourth input coupled with a value of negative 1 (-1), and an output that produces a final output exponent.

[0073]

[0083] In one embodiment, the digital circuit further includes control logic configured to receive an input exponent and an input sign bit, and to generate control signals to at least a mantissa selector and an exponent selector, wherein when the input sign bit is positive and the input exponent is less than a first value, the output of the mantissa selector is coupled to the output of the right shifter circuit, and the output of the exponent selector is coupled to the value 0, and when the input sign bit is positive and the input exponent is greater than a first value, the output of the mantissa selector is coupled to the lower bit of the left shifter circuit, and the output of the exponent selector is coupled to the upper bit of the first left shifter circuit, The output of the mantissa selection circuit is coupled to the sum of the value of the power corresponding to the input exponent, and when the input sign bit is positive and the input exponent is less than the first value, the output of the mantissa selection circuit is coupled to the output of the right shifter circuit through the constant subtraction logic circuit, and the output of the exponent selection circuit is coupled to the value of the constant negative 1 (-1), and when the input sign bit is negative and the input exponent is greater than the first value, the output of the mantissa selection circuit is coupled to the lower bit of the left shifter circuit through the constant subtraction logic circuit, and the output of the exponent selection circuit is coupled to the lower bit of the sum of the value of the power corresponding to the input exponent, and the upper bit of the first left shifter circuit and the negative number of the sum of the value of the power corresponding to the input exponent, and the value of the exponent selection circuit is coupled to the negative number of the sum of the value of the power corresponding to the input exponent, and the value of the sum of the value of the power corresponding to the input exponent, and the value of the exponent selection circuit.

[0074]

[0084] The above description illustrates various embodiments of the Disclosure, along with examples of how aspects of a particular embodiment may be carried out. These examples should not be considered sole embodiments, but are presented to demonstrate the flexibility and advantages of a particular embodiment as defined by the appended claims. Based on the above Disclosure and the appended claims, other configurations, embodiments, implementations, and equivalents may be adopted without departing from the scope of the Disclosure as defined by the claims.

Claims

1. It is a digital circuit, A combinational logic that receives a first digital bit representing the input mantissa of an input value and a second digital bit representing the input exponent of the input value, and generates a plurality of output mantissas and a plurality of output exponents corresponding to an approximate value of a power of 2 raised to the power of the input value, when the input value is positive and negative, and when the input exponent is greater than and less than a first value, Two or more selection circuits configured to receive the plurality of output mantissas and the plurality of output exponents, wherein the two or more selection circuits include selection control inputs coupled to the input exponent and input sign bit of the input value in order to select one of the plurality of output mantissas and one of the plurality of output exponents. Digital circuits including

2. The digital circuit according to claim 1, wherein the combinational logic generates a plurality of shifted versions of the input mantissa based on the input exponent to produce the plurality of output mantissas and the plurality of output exponents, and the digital circuit further includes control logic configured to receive the input exponent and the input sign bit, and to generate control signals to at least a mantissa selection circuit and an exponent selection circuit.

3. The two or more selection circuits described above are When the input sign bit is positive and the input exponent is less than a first value, a first output mantissa is provided, which includes the sum of a first shifted version of the input mantissa and a first constant, and a first output exponent having a value of 0. When the input sign bit is positive and the input exponent is greater than the first value, a second output mantissa containing the remainder of the second shifted version of the input mantissa, and a second output exponent having a digital value of 1 shifted based on the input exponent added to the integer quotient of the second shifted version of the input mantissa, When the input sign bit is negative and the input exponent is less than the first value, a third output mantissa comprising the first shifted version of the input mantissa, the sum of the first constants subtracted from the second constant, and a third output exponent having a value of negative 1 (-1), and When the input sign bit is negative and the input exponent is greater than the first value, a fourth output mantissa is obtained by subtracting the remainder of the second shifted version of the input mantissa from the second constant, and the negative of the second output exponent minus 1. A digital circuit according to claim 1 that produces the following.

4. The digital circuit according to claim 1, wherein the combinational logic includes one or more shifter circuits having an input coupled to the input mantissa and a shift input coupled to the input exponent, the one or more shifter circuits producing left and right shifted versions of the input mantissa.

5. The digital circuit according to claim 4, wherein a right-shifted version of the input mantissa is used to form a first output mantissa and a second output mantissa, and the lower bits of a left-shifted version of the input mantissa are used to form a third output mantissa and a fourth output mantissa.

6. The digital circuit according to claim 5, wherein the right-shifted version of the input mantissa is subtracted from a constant to form the second output mantissa.

7. The digital circuit according to claim 5, wherein the left-shifted version of the input mantissa is subtracted from a constant to form the fourth output mantissa.

8. The digital circuit according to claim 4, wherein the upper bits of the left-shifted version of the input mantissa are used to form a first output exponent and a second output exponent, and the upper bits of the left-shifted version of the input mantissa are added to a value generated based on the input exponent to form the first output exponent and the second output exponent.

9. The digital circuit according to claim 8, wherein the value generated based on the input exponent includes bits that have been left-shifted based on the input exponent.

10. The digital circuit according to claim 8, wherein the added upper bits of the left-shifted version of the input mantissa and the value generated based on the input exponent are negated to produce the second output exponent.

11. The digital circuit according to claim 4, wherein the one or more shifter circuits include barrel shifter circuits.

12. The one or more shifter circuits described above are: A right shifter circuit having a first input coupled to the input mantissa through a logic circuit configured to add the input mantissa to a constant, and a shift input coupled to the input exponent through a logic circuit configured to negate the input exponent, and A first left shifter circuit having a first input coupled to receive the input mantissa and a shift input coupled to the input exponent. The digital circuit according to claim 4, including the above.

13. The digital circuit according to claim 12, wherein the one or more shifter circuits further include a second left shifter circuit having a first input coupled to receive a digital value of 1 and a shift input coupled to the input exponent, the outputs of the first left shifter circuit and the second left shifter circuit being added together.

14. The digital circuit according to claim 12, wherein the two or more selection circuits include a first multiplexer having a first input coupled to the output of the right shifter circuit and a second input coupled to the lower bits of the first left shifter circuit, and the two or more selection circuits further include a second multiplexer having a first input coupled to the output of the first multiplexer and a second input coupled to the output of the first multiplexer through a logic circuit configured to subtract a value on the input of the logic circuit from a constant.

15. The two or more selection circuits include a multiplexer, and the multiplexer is The first input is formed by combining the upper bits of the first left shifter circuit with the sum of the power values ​​of 2 corresponding to the input exponent. A second input coupled to the negative version of the aforementioned sum, A third input coupled to a value of 0, and A fourth input coupled to the value of negative 1 (-1), and Output that produces the final power exponent The digital circuit according to claim 12, including the following:

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