Image sensor device

Abstract

To improve performance of an image sensor device.SOLUTION: An image sensor device 100 comprises: a pixel array 110 that has a plurality of digital pixels (DP); a high speed scanner 121; a pixel driver 120 that controls a DP; and a digital logic circuit 130 that executes a digital signal processing motion against a digital signal output from the DP. The DP contains a photodetector, a comparator, and a memory circuit. The high speed scanner comprises: a first flip flop (FF) that receives a reading trigger signal with a clock signal, and outputs a first reset activation signal in a reset activation signal; and a second FF that receives the clock signal and the first reset activation signal, and outputs the first signal activation signal in the signal activation signal. The pixel array outputs a reset sampling value stored in the memory circuit in response to the first reset activation signal, and outputs a signal sampling value stored in the memory circuit in response to the first signal activation signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an image sensor device having improved performance.

Background Art

[0002] An image sensor converts an optical signal into an electrical signal. In recent years, with the development of the computer industry and the communication industry, the demand for image sensors with improved performance has been increasing in various fields such as digital cameras, camcorders, smartphones, tablet PCs, notebook computers, game devices, security cameras, and medical micro cameras.

[0003] Conventional image sensors have operated based on analog pixels. Each of the analog pixels outputs an analog signal corresponding to an optical signal, and the analog signal is converted into a digital signal. However, since the above-mentioned analog signal is vulnerable to noise and coupling compared to a digital signal, there has been a problem in processing a high-resolution image signal.

Prior Art Documents

Patent Documents

[0004] [[ID=3​​​​​​​​​​​​​​​​​​​​​​​​​ U.S. Patent Application Publication No. 2010 / 0157083 [Patent Document 8] Korean Registered Patent Publication No. 10-0640960 [Patent Document 9] Japanese Patent Publication No. 2019-102968 [Overview of the project] [Problems that the invention aims to solve]

[0005] The present invention has been made in view of the problems of the conventional image sensors described above, and the object of the present invention is to provide an image sensor device having improved performance. [Means for solving the problem]

[0006] To achieve the above objective, the present invention provides an image sensor device comprising: a pixel array having a plurality of digital pixels; a high-speed scanner configured to generate a reset activation signal and a signal activation signal; a pixel driver configured to control the plurality of digital pixels; and a digital logic circuit configured to perform digital signal processing operations on the digital signals output from the plurality of digital pixels, wherein each of the plurality of digital pixels includes a photodetector, a comparator, and a memory circuit, and the high-speed scanner receives a clock signal and a read trigger signal, and the reset The pixel array includes a first flip-flop that outputs a first reset activation signal among the activation signals, and a second flip-flop that receives the clock signal and the first reset activation signal and outputs a first signal activation signal among the signal activation signals, wherein the pixel array outputs a reset sampling value stored in the memory circuit in response to the first reset activation signal, and outputs a signal sampling value stored in the memory circuit in response to the first signal activation signal, and the digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface, wherein the sensor controller is supplied from an external device via the input / output interface. The aforementioned clock signal and read trigger signal Based on control information CI which includes the above, the operation of the image sensor device is controlled; the sensor controller provides the clock signal and the read trigger signal to the high-speed scanner; and the digital signal processing unit receives the digital signal from the pixel array, including the reset sampling value and the signal sampling value, performs digital signal processing on the received digital signal, and determines the final digital value corresponding to the optical signal sensed by the digital pixel.

[0007] Furthermore, an image sensor device according to the present invention made to achieve the above objective is an image sensor device comprising: a pixel array having a plurality of digital pixels; a high-speed scanner configured to generate a reset activation signal and a signal activation signal; a pixel driver configured to control the plurality of digital pixels; and a digital logic circuit configured to perform digital signal processing operations on the digital signals output from the plurality of digital pixels, wherein each of the plurality of digital pixels includes a photodetector, a comparator, and a memory circuit, and the pixel array stores the data in the memory circuit at high speed based on the reset activation signal and the signal activation signal. The high-speed scanner outputs a reset sampling value and a signal sampling value, and includes a first flip-flop that receives a clock signal and a read trigger signal and outputs a first reset activation signal from the reset activation signals, a first dummy flip-flop that receives the clock signal and the first reset activation signal and outputs a first dummy signal, and a second flip-flop that receives the clock signal and the first dummy signal and outputs a first signal activation signal from the signal activation signals, and the digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface, the sensor controller being supplied from an external device via the input / output interface. The aforementioned clock signal and read trigger signalBased on control information CI which includes the above, the operation of the image sensor device is controlled; the sensor controller provides the clock signal and the read trigger signal to the high-speed scanner; the digital signal processing unit receives the digital signal from the pixel array, including the reset sampling value and the signal sampling value, performs digital signal processing on the received digital signal, determines a final digital value corresponding to the optical signal sensed by the digital pixel; the first flip-flop outputs the logic level of the read trigger signal as the first reset activation signal in response to the clock signal; the first dummy flip-flop outputs the logic level of the first reset activation signal received in response to the clock signal as the first dummy signal; and the second flip-flop outputs the logic level of the first dummy signal received in response to the clock signal as the first signal activation signal.

[0008] Furthermore, an image sensor device according to the present invention made to achieve the above objective is an image sensor device comprising: a high-speed scanner that generates a reset activation signal and a signal activation signal; a first digital pixel having a first photodetector, a first memory cell that stores reset sampling values ​​from the first photodetector, and a second memory cell that stores signal sampling values; a second digital pixel having a second photodetector, a third memory cell that stores reset sampling values ​​from the second photodetector, and a fourth memory cell that stores signal sampling values; a pixel driver configured to control the first and second digital pixels; and the first and second digital pixelsThe high-speed scanner comprises a digital logic circuit configured to perform digital signal processing operations on the digital signal output therefrom, wherein the first to fourth memory cells are connected to a plurality of bit lines, the first memory cell is connected to a first reset activation signal of the reset activation signals, the second memory cell is connected to a first signal activation signal of the signal activation signals, the third memory cell is connected to a second reset activation signal of the reset activation signals, and the fourth memory cell is connected to a second signal activation signal of the signal activation signals, and the high-speed scanner comprises a first flip-flop that receives a clock signal and a read trigger signal and outputs the first reset activation signal, and a first dummy flip-flop that receives the clock signal and the first reset activation signal and outputs a first dummy signal. The digital logic circuit includes a second flip-flop that receives the clock signal and the first dummy signal and outputs the first signal activation signal; a second dummy flip-flop that receives the clock signal and the first signal activation signal and outputs the second dummy signal; a third flip-flop that receives the clock signal and the second dummy signal and outputs the second reset activation signal; a third dummy flip-flop that receives the clock signal and the second reset activation signal and outputs the third dummy signal; and a fourth flip-flop that receives the clock signal and the third dummy signal and outputs the second signal activation signal. The digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface, the sensor controller being supplied from an external device via the input / output interface. The aforementioned clock signal and read trigger signal Based on control information CI which includes the above, the operation of the image sensor device is controlled; the sensor controller provides the clock signal and the read trigger signal to the high-speed scanner; and the digital signal processing unit receives the digital signal including the reset sampling value and the signal sampling value from the first and second digital pixels, performs digital signal processing on the received digital signal, and determines the final digital value corresponding to the optical signal sensed by the digital pixel.

Advantages of the Invention

[0009] According to the image sensor device of the present invention, reset sampling values and signal sampling values stored in the memory at high speed via a high-speed scanner can be output. Thereby, an image sensor device with improved performance can be provided.

Brief Description of the Drawings

[0010] [Figure 1] It is a block diagram showing a schematic configuration of an image sensor device according to an embodiment of the present invention. [Figure 2A] It is a block diagram showing, as an example, the pixel driver of FIG. 1. [Figure 2B] It is a block diagram showing, as an example, the schematic configuration of the digital logic circuit of FIG. 1. [Figure 3A] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 3B] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 3C] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 3D] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 3E] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 3F] It is a diagram for explaining the digital pixel of FIG. 1 in more detail. [Figure 4] It is a block diagram showing, as an example, the schematic configuration of the row driver of FIG. 2A. [Figure 5A] It is a block diagram showing, as an example, the schematic configuration of the pixel array and the high-speed scanner of FIG. 1. [Figure 5B] It is a block diagram showing, as an example, the schematic configuration of the cluster of FIG. 5A. [Figure 6]Figure 5A is a circuit diagram illustrating the schematic configuration of the subscanner as an example. [Figure 7A] Figure 5A is a timing diagram showing multiple cluster activation signals as an example. [Figure 7B] This is a timing diagram illustrating the operation of the image sensor device shown in Figure 1 as an example. [Figure 8A] Figure 5A is a circuit diagram illustrating the schematic configuration of the subscanner as an example. [Figure 8B] This is a timing diagram illustrating the operation of the image sensor device shown in Figure 1 as an example. [Figure 9A] This block diagram shows an example of the schematic configuration of the row driver in Figure 2A. [Figure 9B] This block diagram shows an example of the schematic configuration of the row driver in Figure 2A. [Figure 10] This is a block diagram showing a schematic configuration of an image sensor device according to an embodiment of the present invention. [Figure 11] This block diagram shows an example of a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention. [Figure 12] Figure 11 is a block diagram showing a detailed configuration example of the camera module. [Modes for carrying out the invention]

[0011] Next, specific examples of embodiments for implementing the image sensor device according to the present invention will be described with reference to the drawings.

[0012] Figure 1 is a block diagram showing a schematic configuration of an image sensor device according to an embodiment of the present invention. Referring to Figure 1, the image sensor device 100 includes a pixel array 110, a pixel driver 120, and a digital logic circuit 130. In an exemplary embodiment, the image sensor device 100 may be a camera module included in a variety of electronic devices such as CCTV, black boxes, digital cameras, smartphones, tablet PCs, and notebooks.

[0013] Conventional CIS (CMOS Image Sensor) based image pixels output analog signals based on optical signals. Analog signals from CIS-based image pixels are converted to digital signals by separate analog-to-digital converters arranged in columns. In this case, there is a problem in that noise or coupling can occur during the transfer of the analog signal converted from the CIS-based image pixels to the analog-to-digital conversion circuit, thereby degrading the quality of the final image.

[0014] The pixel array 110 according to an embodiment of the present invention includes a plurality of digital pixels (DP). Each of the multiple digital pixel DPs is configured to sense an external optical signal and output a digital signal DOUT corresponding to the sensed optical signal.

[0015] For example, a digital pixel display (DP) includes a photodetector (PDT), an analog-to-digital converter (ADC), and a memory circuit (MCT). A photodetector (PDT) is configured to convert an externally detected optical signal into an electrical signal, i.e., an analog signal. The analog-to-digital converter (ADC) is configured to convert the analog signal output from the photodetector (PDT) into a digital signal. The memory circuit MCT is configured to store the digital signal DOUT converted by the analog-to-digital converter ADC and to output the stored digital signal DOUT. As described above, the digital pixel DP according to the embodiment of the present invention differs from conventional CIS image pixels in that it outputs a digital signal DOUT at the pixel level.

[0016] The pixel driver 120 outputs a variety of control signals (CTRL) for controlling multiple digital pixels DP included in the pixel array 110 (e.g., photodetector control signals, memory control signals, ramp signals, count information, etc.). Based on the control signal CTRL generated from the pixel driver 120, each of the multiple digital pixels DP performs a series of pixel operations or image detection operations, such as detecting an optical signal and generating an analog signal, converting the analog signal to a digital signal, storing the digital signal, and outputting the stored digital signal.

[0017] In an exemplary embodiment, the pixel driver 120 includes a high-speed scanner 121. The high-speed scanner 121 generates a reset activation signal and a signal activation signal to output the digital signal DOUT, which is stored at high speed in the memory circuit MCT. The high-speed scanner 121 provides a reset activation signal and a signal activation signal to the pixel array 110. The reset activation signal and the signal activation signal may be included in the control signal CTRL. The reset sampling value and signal sampling value may be included in the digital signal DOUT.

[0018] The digital logic circuit 130 performs digital signal processing on the digital signal DOUT received from the pixel array 110 and provides the final image to an external device (for example, an Image Signal Processor (ISP), an Application Processor (AP), etc.). In an exemplary embodiment, the digital logic circuit 130 provides a drive signal to the pixel driver 120 according to the control of an external device. The pixel driver 120 operates in response to the drive signal.

[0019] As described above, unlike conventional CIS devices, each of the multiple digital pixel DPs according to the embodiment of the present invention generates and outputs a digital signal DOUT at the pixel level. Therefore, the deformation of the digital signal DOUT output from multiple digital pixels DP is reduced, allowing for high-speed processing of the image signal.

[0020] Figure 2A is a block diagram illustrating the pixel driver shown in Figure 1 as an example. Referring to Figures 1 and 2A, the pixel driver 120 includes a counter CNT, a row driver RDV, a lamp generator RAMP, and a voltage generator VGER.

[0021] The counter CNT sequentially increases or decreases the value of the code CODE in response to a predetermined clock (e.g., an operating clock or a system clock) within a predetermined time. In other words, the value of the code changes sequentially over time. The row driver RDV generates control signals to control each of the multiple digital pixels DP. For example, the row driver RDV generates a photodetector control signal (CS_PD) to control each of the photodetectors PDTs of multiple digital pixels DP. The row driver RDV generates memory control signals (CS_MC) to control the memory circuit MCT of each of the multiple digital pixel DPs.

[0022] In an exemplary embodiment, the row driver RDV includes a high-speed scanner 121. The high-speed scanner 121 generates a reset activation signal and a signal activation signal, thereby outputting the reset sampling value and signal sampling value stored in the memory circuit MCT at high speed. The reset activation signal and signal activation signal may be included in the memory control signal (CS_MC).

[0023] The RAMP lamp generator generates the VRAMP lamp signal. The ramp signal VRAMP is used as a reference signal for comparison with analog signals in digital pixel DP. In an example embodiment, the ramp signal VRMAP may be a signal that decreases or increases at a constant rate (i.e., an increasing / decreasing signal with a single slope). The voltage generator VGER is configured to generate various voltages necessary for the operation of the image sensor device 100 (e.g., power supply voltage VDDA, bias voltage VB, etc.).

[0024] The photodetector control signal (CS_PD), memory circuit (CS_MC), code CODE, and ramp signal VRAMP may be included in the control signal CTRL, as described with reference to Figure 1. In an exemplary embodiment, each of the multiple digital pixel DPs included in the pixel array 110 operates based on various signal codes, such as (CS_PD), (CS_MC), VRAMP, VDDA, VB, etc., generated from the pixel driver 120 as described with reference to Figure 2A.

[0025] Figure 2B is a block diagram illustrating the schematic configuration of the digital logic circuit shown in Figure 1 as an example. Referring to Figures 1 and 2B, the digital logic circuit 130 includes a sensor controller 131, a digital signal processing unit 132, and an input / output interface 133.

[0026] The sensor controller 131 is configured to control various operations of the image sensor device 100. For example, the sensor controller 131 controls various operations of the image sensor device 100 based on control information CI provided from an external device (e.g., ISP, AP, etc.) via the input / output interface 133. The sensor controller 131 is a timing controller for controlling the operating timing of the pixel driver 120. In an exemplary embodiment, the pixel driver 120 generates the various signals described above based on timing signals from the sensor controller 131.

[0027] In an example embodiment, the sensor controller 131 provides the high-speed scanner 121 with a clock signal, a cluster activation signal, a read trigger signal, and the like. Clock signals, cluster activation signals, and read trigger signals are included in the control information CI.

[0028] The digital signal processing unit 132 receives the digital signal DOUT from the pixel array 110 and performs digital signal processing on the received digital signal DOUT. In an exemplary embodiment, the digital signal DOUT output from one pixel array 110 includes a reset sampling value and a signal sampling value. The digital signal processing unit 132 determines the final digital value corresponding to the optical signal sensed by a single digital pixel DP by performing calculation operations on the reset sampling value and the signal sampling value.

[0029] The final image data (IMG) is generated by combining the final digital values ​​determined for each of the multiple digital pixels. In other words, correlated double sampling (CDS) is performed through the operation of the digital signal DOUT generated by the operation of the analog-to-digital converter ADC or comparator included in the digital pixel DP, and the operation of the digital signal processing unit 132 included in the digital logic circuit 130.

[0030] The input / output interface 133 is configured to provide control information CI from an external device (e.g., ISP, AP, etc.) or to output the final image data IMG. In an example embodiment, the input / output interface 330 exchanges the above-mentioned information with an external device based on a predetermined protocol. In an exemplary embodiment, the input / output interface 330 may include a physical layer for supporting the predetermined protocol described above.

[0031] Figures 3A to 3F are diagrams that provide a more detailed explanation of the digital pixels in Figure 1. Various structures of digital pixels according to embodiments of the present invention will be described with reference to Figures 3A to 3D, but the scope of the present invention is not limited thereto. In order to easily explain the technical concept of the present invention, the structure or operation of the digital pixel DP will be described based on an example circuit diagram or block diagram. However, the scope of the present invention is not limited thereto, and the digital pixel DP can be modified into various forms.

[0032] In the following, for the sake of clarity and conciseness of the drawings, detailed explanations or reference numerals for components that are identical or similar to those described above will be omitted. Components omitted below are implemented by each or a combination thereof of the overall embodiments described in the detailed description of the present invention.

[0033] Referring to Figures 1, 2, and 3A-3E, the digital pixel DP includes a photodetector PDT, a comparator COMP, and a memory circuit MCT. The photodetector PDT is configured to output a detection signal DET in response to a pixel control signal (CS_PD) from the pixel driver 120. For example, referring to Figure 3B, the digital pixel DPa includes a photodetector PDTa, a comparator COMPa, and a memory circuit MCT.

[0034] As shown in Figure 3B, the photodetector PDTa includes a photodiode PD, a transfer transistor TX, and a reset transistor RX. The photodiode PD is connected between the ground node and the transfer transistor TX and is configured to accumulate photocharge in response to the intensity of light incident from an external source. The transfer transistor TX is connected between the floating diffusion node FD and the photodiode PD and operates in response to the transfer signal TG. For example, a transfer transistor TX is configured to transfer the charge accumulated in a photodiode PD in response to a transfer signal TG to a floating diffusion node FD.

[0035] The reset transistor RX is connected between the power supply voltage VDDA and the floating diffusion node FD, and operates in response to the reset signal RG. For example, the reset transistor RX resets the voltage level of the floating diffusion node FD in response to the reset signal RG. In an example embodiment, the pixel control signal (CS_PD) includes the transfer signal TG and the reset signal RG described above. In this example embodiment, the voltage of the floating diffusion node FD (i.e., VFD) changes in response to the operation of the photodetector PDTa, and this is output as a detection signal DEF.

[0036] The comparator COMPa compares the detection signal DET from the photodetector PDTa (or the voltage VFD of the floating diffusion node FD) with the ramp signal VRAMP and outputs a comparison signal (COMP_OUT) according to the comparison result. In an exemplary embodiment, the comparator COMPa can be implemented using a low-power comparator. For example, as shown in Figure 3B, the comparator COMPa includes first to third NMOS transistors (MN1 to MN3) and first to fourth NMOS transistors (MN1 to MN4).

[0037] The first PMOS transistor MP1, the first NMOS transistor MN1, and the third NMOS transistor MN3 are connected in series between the power supply voltage VDDA and the ground voltage GND. The gate of the first PMOS transistor MP1 is connected between the first PMOS transistor MP1 and the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the floating spread node FD and configured to receive the detection signal DEF. The gate of the third NMOS transistor NM3 is configured to receive the bias voltage VB. The second PMOS transistor MP2 and the second NMOS transistor MN2 are connected in series between the power supply voltage VDDA and one end of the third NMOS transistor MN3. The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1. The gate of the second NMOS transistor MN2 is configured to receive the ramp signal VRAMP. The third PMOS transistor MP3 and the fourth NMOS transistor MN4 are connected in series between the power supply voltage and the ground voltage. The gate of the third PMOS transistor MP3 is connected between the second PMOS transistor MP2 and the second NMOS transistor MN2. The gate of the fourth NMOS transistor MN4 is configured to receive the bias voltage VB.

[0038] In the comparator COMPa shown in Figure 3B, when the detection signal DET is lower than the ramp signal VRAMP, the comparison signal (COMP_OUT) has a logic high level, and when the detection signal DET is higher than the ramp signal VRAMP, the comparison signal (COMP_OUT) has a logic low level. In this example embodiment, the structure of the comparator COMPa shown in Figure 3B is illustrative, and the scope of the present invention is not limited thereto. The comparator COMPa has various forms of comparator or differential amplifier structures configured to compare a detection signal DEF with a ramp signal VRAMP and output a comparison signal (COMP_OUT) according to the comparison result.

[0039] The memory circuit MCT is configured to either store the code CODE in response to the comparison signal (COMP_OUT) and the memory control signal (CS_MC), or to output the stored code as the digital signal DOUT. For example, as shown in Figure 3B, the memory circuit MCT includes first and second selection circuits (SEL1, SEL2), as well as a plurality of memory cells (MC1, MC2).

[0040] Each of the multiple memory cells (MC1, MC2) may be a DRAM, SRAM, latch, or any other form of data storage element configured to store the code at a specific timing. Each of the multiple memory cells (MC1, MC2) is connected to the first and second word lines (WL1, WL2), as well as the bit line BL. Each of the multiple memory cells (MC1, MC2) stores a code CODE provided via bit line BL according to the levels of the first and second word lines (WL1, WL2), or outputs the stored code CODE as a digital signal DOUT via bit line BL.

[0041] In an example embodiment, the number of first memory cells MC1 among the multiple memory cells (MC1, MC2) is N (where N is a natural number greater than 2), and the number of second memory cells MC2 among the multiple memory cells (MC1, MC2) is M (where M is a natural number). In this example embodiment, the number N of the first memory cells MC1 and the number M of the second memory cells MC2 are either the same or different.

[0042] In an example embodiment, the first memory cell MC1 is configured to store a reset sampling value R, and the second memory cell MC2 is configured to store a signal sampling value S. The first memory cell MC1 is connected to the first word line WL1 and the bit line BL, and the second memory cell MC2 is connected to the second word line WL2 and the bit line BL.

[0043] Referring to Figure 3C, the digital pixel DPb includes a photodetector PDTb, a comparator COMPb, and a memory circuit MCT. The comparator COMPb includes a first capacitor C1 connected between the floating diffusion node FD and the first NMOS transistor MN1. The comparator COMPb includes a second capacitor C2 connected between the second NMOS transistor MN2 and the ramp signal VRAMP.

[0044] The first and second capacitors (C1, C2) may be passive elements, MOS (Metal Oxide Semiconductor) transistors, MIM (Metal Insulator Metal) capacitors, cell capacitors, etc. The other components and their operations are similar to those described above, so a detailed explanation of them will be omitted.

[0045] Referring to Figure 3D, the digital pixel DPC includes a photodetector PDTc, a comparator COMPC, and a memory circuit MCT. The photodetector PDTc includes first to fourth photodiodes (PD1 to PD4), first to fourth transfer transistors (TX1 to TX4), a reset transistor RX, and first to eleventh NMOS transistors (MN1 to MN11). Each of the first to fourth photodiodes (PD1 to PD4) is connected between a ground node and a corresponding transfer transistor (TX1 to TX4) and is configured to accumulate photocharge in accordance with the intensity of light incident from an external source. For example, the first photodiode PD1 may be connected between the ground node and the first transfer transistor TX1. The remaining photodiodes (PD2~PD4) are similar, so a detailed explanation will be omitted.

[0046] The first transfer transistor TX1 is connected between the first photodiode PD1 and the first node N1. The second transfer transistor TX2 is connected between the second photodiode PD2 and the first node N1. The third transfer transistor TX3 is connected between the third photodiode PD3 and the second node N2. The fourth transfer transistor TX4 is connected between the fourth photodiode PD4 and the fourth node N4.

[0047] Each of the gates of the first to fourth transfer transistors (TX1 to TX4) is configured to receive the corresponding transfer signal TG. For example, the gate of the first transfer transistor TX1 is configured to receive the first transfer signal TG1. The remaining transfer transistors (TX2-TX4) are similar, so a detailed explanation will be omitted.

[0048] The reset transistor RX is connected between the power supply voltage VDDA and the third node N3 and operates in response to the reset signal RG. The first NMOS transistor MN1 is connected between the first node N1 and the third node N3 and operates in response to the first gate signal GS1. The second NMOS transistor MN2 is connected between the second node N2 and the third node N3 and operates in response to the second gate signal GS2.

[0049] In an example embodiment, the photodetector (PDTc) includes a Source Follower Amplifier (SF amplifier). The SF amplifier includes the third to sixth NMOS transistors (MN3 to MN6). The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series between the power supply voltage VDDA and the fourth node N4. The gate of the third NMOS transistor MN3 is connected to the first node N1. The fourth NMOS transistor MN4 operates in response to the third gate signal GS3. The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected in series between the power supply voltage VDDA and the fourth node N4. The gate of the fifth NMOS transistor MN5 is connected to the second node N2. The sixth NMOS transistor, MN6, operates in response to the fourth gate signal, GS4.

[0050] The seventh NMOS transistor MN7 is connected between the power supply voltage VDDA and the fourth node N4 and operates in response to the fifth gate signal GS5. The eighth and ninth NMOS transistors (MN8, MN9) are connected in series between the fourth node N4 and the ground node. The eighth NMOS transistor, MN8, operates in response to the sixth gate signal, GS6. The ninth NMOS transistor, MN9, operates in response to the seventh gate signal, GS7. The tenth and eleventh NMOS transistors (MN10, MN11) are connected in series between the power supply voltage VDDA and the fourth node N4. The 10th NMOS transistor MN10 operates in response to the 8th gate signal GS8, and the 11th NMOS transistor MN11 operates in response to the 9th gate signal GS9.

[0051] The comparator COMPC includes the first to fourth PMOS transistors (MP1 to MP4), the twelfth to eighteenth NMOS transistors (MN12 to MN18), and the first and second capacitors (C1, C2). The first capacitor C1 is connected between the fourth node N4 and the fifth node N5. The second capacitor C2 is connected between the ninth node N9 and the ramp signal VRAMP. The first and second capacitors (C1, C2) may be passive elements, MOS (Metal Oxide Semiconductor) transistors, MIM (Metal Insulator Metal) capacitors, cell capacitors, etc.

[0052] The first PMOS transistor MP1 is connected between the power supply voltage VDDA and the sixth node N6 and operates in response to the tenth gate signal GS10. The second PMOS transistor MP2 is connected between the power supply voltage VDDA and the sixth node N6. The gate of the second PMOS transistor MP2 is connected to the sixth node N6. The third PMOS transistor MP3 is connected between the power supply voltage VDDA and the seventh node N7. The gate of the third PMOS transistor MP3 is connected to the gate of the second PMOS transistor MP2. The fourth PMOS transistor MP4 is connected between the power supply voltage VDDA and the seventh node N7 and operates in response to the eleventh gate signal GS11.

[0053] The 12th NMOS transistor MN12 is connected between the 6th node N6 and the 5th node N5 and operates in response to the 12th gate signal GS12. The 13th NMOS transistor MN13 is connected between the 6th node N6 and the 8th node N8. The gate of the 13th NMOS transistor MN13 is connected to the 5th node N5. The 14th NMOS transistor MN14 is connected between the 7th node N7 and the 9th node N9 and operates in response to the 13th gate signal GS13. The 15th NMOS transistor MN15 is connected between the 7th node N7 and the 8th node N8. The gate of the 15th NMOS transistor MN15 is connected to the 9th node N9.

[0054] NMOS transistors 16 through 18 (MN16 through MN18) are connected in series between node 8 (N8) and the ground node. The 16th NMOS transistor MN16 operates in response to the 14th gate signal GS14, the 17th NMOS transistor MN17 operates in response to the 15th gate signal GS15, and the 18th NMOS transistor MN17 operates in response to the 16th gate signal GS16.

[0055] The comparator COMPc outputs the voltage of the 7th node N7 as a comparison signal (COMP_OUT) to the memory circuit MCT. The other components and their operations are the same as those described above, so a detailed explanation of them will be omitted.

[0056] The first selection circuit SEL1 is configured to control the first and second word lines (WL1, WL2) in response to a comparison signal (COMP_OUT) and a memory control signal (CS_MC). For example, as shown in Figure 3E, the first selection circuit SEL1 includes the first switch SW1. Each of the first switches SW1 is configured to provide a first voltage V1 to either the first word line WL1 or the second word line WL2 in response to a comparison signal (COMP_OUT) and a memory control signal (CS_MC). In an example embodiment, the first voltage V1 is a high voltage that activates each of the multiple memory cells (MC1, MC2) (for example, if the memory cells are DRAM, a high voltage that activates the selection transistor).

[0057] For example, the memory control signal (CS_MC) includes first and second sampling signals (SMP1, SMP2) and first and second read signals (RD1, RD2). The first sampling signal SMP1 is a signal for storing the reset sampling value R in the first memory cell MC1, and the second sampling signal SMP2 is a signal for storing the signal sampling value S in the second memory cell MC2. The first read signal RD1 is a signal for outputting the reset sampling signal R stored in the first memory cell MC1 as a digital signal DOUT, and the second read signal RD2 is a signal for outputting the signal sampling signal stored in the second memory cell MC2 as a digital signal DOUT. However, the scope of the present invention is not limited thereto, and the memory control signal (CS_MC) for controlling the memory circuit 113 can be modified in various ways.

[0058] When the first sampling signal SMP1 or the first reading signal RD1 is activated, the first switch SW1 provides a first voltage V1 to the first word line WL1 in response to the falling edge (or rising edge) of the comparison signal (COMP_OUT). This activates the first memory cell MC1 connected to the first word line WL1, and either the value of code CODE is stored in the activated first memory cell MC1, or the value stored in the activated first memory cell MC1 (e.g., the reset sampling value R) is output.

[0059] When the second sampling signal SMP2 or the second reading signal RD2 is activated, the first switch SW1 provides a second voltage V2 to the second word line WL2 in response to the falling edge (or rising edge) of the comparison signal (COMP_OUT). This activates the second memory cell MC2 connected to the second word line WL2, and either the value of code CODE is stored in the activated second memory cell MC2, or the value stored in the activated second memory cell MC2 (e.g., the signal sampling value S) is output.

[0060] As described above, the first selection circuit SEL1 selects at least one group from the first memory cell MC1 and the second memory cell MC2 in response to the comparison signal (COMP_OUT) and the memory control signal (CS_MC).

[0061] The second selection circuit SEL2 is configured to either provide a code CODE to bit line BL in response to a memory control signal (CS_MC), or to output a digital signal DOUT from bit line BL. For example, as shown in Figure 3E, the second selection circuit SEL2 includes the second switch SW2. The second switch SW2 is configured to connect bit line BL to one of the following groups in response to the memory control signal (CS_MC): a line that receives code CODE and a line that outputs the digital signal DOUT.

[0062] For example, when the first sampling signal SMP1 or the second sampling signal SMP2 is activated, the second switch SW2 connects bit line BL to the line that receives the code CODE. In this case, the code CODE provided from the counter CNT is provided to the first memory cell MC1 or the second memory cell MC2 via the bit line BL. When the first read signal RD1 or the second read signal RD2 is activated, the second switch SW2 connects bit line BL to the line that outputs the digital signal DOUT. In this case, the value stored in the first memory cell MC1 or the second memory cell MC2 (for example, the reset sampling value R or the signal sampling value S) is output as the digital signal DOUT.

[0063] In this exemplary embodiment, the first selection circuit SEL1 and the second selection circuit SEL2 shown in Figure 3E are illustrative examples, and the scope of the present invention is not limited thereto. For example, each of the first and second selection circuits (SEL1, SEL2) can be modified in various ways to store or read information (e.g., reset sampling value R or signal sampling value S) corresponding to a memory cell corresponding to a digital pixel DP. In an example embodiment, each of the first and second selection circuits (SEL1, SEL2) can be varied depending on the number of word lines, the number of bit lines, the word line routing scheme, and the bit line routing scheme. In the exemplary embodiment, the first and second selection circuits (SEL1, SEL2) are shown to be included in a single pixel DP, but the scope of the present invention is not limited thereto. For example, the first and second selection circuits (SEL1, SEL2) may be configured to be arranged in units of pixel groups, each containing multiple digital pixels.

[0064] As described above, the digital pixel DP according to the embodiment of the present invention is configured to generate an analog signal corresponding to light received from an external source, and to convert the generated analog signal into a digital signal for output. The following provides a schematic explanation of the operation of the digital pixel display (DP), referring to Figure 3F.

[0065] As shown in Figure 3F, the first sampling signal SMP1 is activated from the first time point t1 to the third time point t3. In other words, a sampling operation is performed on the reset level of the photodetector 111 within the time period from the first time point t1 to the third time point t3.

[0066] For example, during the activation of the first sampling signal SMP1, the ramp generator RAMP outputs a ramp signal VRAMP that decreases steadily (i.e., decreases to a single slope), and the counter CNT sequentially outputs a code CODE that increases or decreases at predetermined intervals. At this point in time t2, the level of the ramp signal VRAMP becomes lower than the level of the floating diffusion node FD (i.e., VFD) of the photodetector PDT. In this case, the comparison operation of the comparator COMP causes the output signal (COMP_OUT) to transition from a high level to a low level.

[0067] At the falling edge of the output signal (COMP_OUT) of comparator COMP (i.e., at the second time point t2), the first sampling signal SMP1 is in an activated state, so the second selection circuit SEL2 provides the code CODE to bit line BL, and the first selection circuit SEL1 activates the first memory cell MC1. In other words, at the second time point t2, the value of code CODE is stored in the first memory cell MC1 as the reset sampling value R.

[0068] Subsequently, in response to the transfer signal TG activated at the fourth time point t4, the transfer transistor TX of the photodetector PDT is turned on, and the charge accumulated by the photodiode PD is transferred to the floating diffusion node FD. As a result, at the fourth time point t4, the level of the floating diffusion node FD (i.e., VFD) (or the detection signal DET) decreases by a level corresponding to the transferred charge.

[0069] Subsequently, the second sampling signal SMP2 is activated from the fifth time point t5 to the seventh time point t7. In other words, a signal sampling operation is performed on the detection signal DEF from the photodetector PDT during the time period from the 5th time point t5 to the 7th time point t7.

[0070] For example, as described above, during the activation of the second sampling signal SMP2, the ramp generator RAMP outputs the ramp signal VRAMP, and the counter CNT outputs the code CODE. At this time, at the sixth time point t6, the detection signal DEF may be lower than the detection signal DEF. In this case, the output signal of the comparator COMP (COMP_OUT) transitions from a high level to a low level.

[0071] At the falling edge of the output signal (COMP_OUT) of comparator COMP (i.e., the 6th time point T6), the second sampling signal SMP2 is activated, so the second selection circuit SEL2 provides the code CODE to bit line BL, and the second memory cell MC2 is activated by the second selection circuit SEL2. In other words, at the sixth time point T6, the value S of code CODE is stored in the second memory cell MC2.

[0072] Subsequently, within the activation interval of the first read signal RD1, the first memory cell MC1 is activated by the first selection circuit SEL1, and the bit line BL is connected to the output signal line (i.e., the line that outputs the digital signal DOUT) by the second selection circuit SEL2. In this case, the value stored in the first memory cell MC1 (i.e., the reset sampling value R) is output as the digital signal DOUT.

[0073] Subsequently, within the activation interval of the second read signal RD2, the second memory cell MC2 is activated by the second selection circuit SEL2, and the bit line BL is connected to the output signal line by the second selection circuit SEL2. In this case, the value stored in the second memory cell MC2 (i.e., the signal sampling value S) is output as the digital signal DOUT. Subsequently, at time point T8, the reset transistor RX is turned on in response to the activation of the reset signal RG, thereby resetting the level VFD of the floating diffusion node FD.

[0074] In an example embodiment, the digital signal DOUT (or reset sampling value R and signal sampling value S) output from the memory circuit MCT is provided to the digital logic circuit 130 via the sensing amplifier SA. In an example embodiment, the sensing amplifier SA is arranged in units of columns of multiple pixels included in the pixel array 110.

[0075] The structure or operation of the digital pixel DP described with reference to Figures 3A to 3F is illustrative and the scope of the present invention is not limited thereto. The structure or operation of digital pixel display (DP) can be varied depending on the method of implementing the digital pixel display.

[0076] Figure 4 is a block diagram illustrating the row driver in Figure 2A as an example. Referring to Figures 2A and 4, the row driver RDVa includes a high-speed scanner 121, a front circuit 122, a decoder 123, a logic circuit 124, and a driver 125. The row driver RDVa generates control signals to control each of the multiple digital pixels DP.

[0077] The front circuit 122 receives a drive signal from the sensor controller 131. The front circuit 122 controls or adjusts the received drive signals and provides them to each component of the row driver RDVa. For example, the front circuit 122 is configured to perform a retiming operation that rearranges the drive signals received from the sensor controller 131.

[0078] The decoder 123 decodes the signals received from the front circuit 122 or the sensor controller 131 and generates an activation signal to select a row to activate. Because the decoder 123 performs a wider variety of calculation operations compared to the high-speed scanner 121, it may be difficult to switch between multiple rows at high speed. For example, switching rows takes at least 800ns. The logic circuit 124 outputs various control signals to the driver 125 for controlling the digital pixel DP based on signals received from the front circuit 122, decoder 123, and sensor controller 131.

[0079] The driver 125 is connected to the logic circuit 124. The driver 125 converts the voltage level of the signal provided by the logic circuit 124 to a voltage level that the pixel array 110 can process. For example, driver 125 converts the voltage level of a signal that swings between low voltage and ground voltage to a signal level that swings between high voltage and ground voltage. The driver 125 provides the converted signal to the pixel array 110.

[0080] The high-speed scanner 121 receives a clock signal CLK, a cluster activation signal CEN, and a read trigger signal RTRIG from the sensor controller 131. Furthermore, the high-speed scanner 121 receives the cluster activation signal CEN and the read trigger signal RTRIG from the logic circuit 124. The high-speed scanner 121 outputs a reset activation signal (R_EN) and a signal activation signal (S_EN). The read trigger signal RTRIG is used to generate the reset activation signal (R_EN) and the signal activation signal (S_EN). The read trigger signal RTRIG is used to start or initiate the output operation of the digital signal DOUT in cluster CL in Figure 5A. The high-speed scanner 121 generates a reset activation signal (R_EN) and a signal activation signal (S_EN) in response to the read trigger signal RTRIG. The reset activation signal (R_EN) and the signal activation signal (S_EN) are sometimes referred to as the scanner output signal SO.

[0081] The high-speed scanner 121 outputs a reset sampling value R and a signal sampling value S at high speed by providing a reset activation signal (R_EN) and a signal activation signal (S_EN) to the pixel array 110. In other words, the high-speed scanner 121 provides the pixel array 110 with a reset activation signal (R_EN) and a signal activation signal (S_EN) to select multiple rows sequentially or randomly. For example, the high-speed scanner 121 requires at least 200 ns to switch the row of the pixel array 110 to be activated. The reset activation signal (R_EN) and the signal activation signal (S_EN) are included in the memory control signal (CS_MC), as explained with reference to Figure 2A. The reset activation signal (R_EN) corresponds to the first read signal RD1 in Figure 3E, and the signal activation signal (S_EN) corresponds to the second read signal RD2.

[0082] In other words, the image sensor device 100, which uses digital pixels, stores the reset sampling value R and the signal sampling value S in a memory cell and outputs the stored reset sampling value R and signal sampling value S to the digital signal processing unit 132. Therefore, in the operation of the digital signal output that outputs a reset sampling value R and a signal sampling value S, the rows are selected or switched at high speed to improve the operational performance of the digital signal output. Therefore, an image sensor device 100 with improved performance is provided. The operation of the high-speed scanner 121 according to the present invention will be described in more detail with reference to the following figures.

[0083] Figure 5A is a block diagram showing an example of the schematic configuration of the pixel array and high-speed scanner in Figure 1, and Figure 5B is a block diagram showing an example of the schematic configuration of the cluster in Figure 5A. For the sake of simplicity in the diagrams, unnecessary components have been omitted for explanation, and in the embodiments of Figures 5A and 5B, only the memory cell MC of the digital pixel DP is shown.

[0084] Referring to Figures 1, 4, 5A, and 5B, the pixel array 110 includes multiple cluster groups (CG1 to CG4). Each of the cluster groups (CG1 to CG4) contains multiple clusters. For example, the first cluster group CG1 includes the first part (CL11~CL14) of multiple clusters, the second cluster group CG2 includes the second part (CL21~CL24) of multiple clusters, the third cluster group CG3 includes the third part (CL31~CL34) of multiple clusters, and the fourth cluster group CG4 includes the fourth part (CL41~CL44) of multiple clusters. However, the scope of the present invention is not limited thereto, and the number of cluster groups and the number of clusters included in a cluster group can be increased or decreased depending on the implementation method.

[0085] Each of the multiple cluster groups (CG1 to CG4) outputs a digital signal. For example, the first cluster group CG1 outputs the first digital signal DOUT1, the second cluster group CG2 outputs the second digital signal DOUT2, the third cluster group CG3 outputs the third digital signal DOUT3, and the fourth cluster group CG4 outputs the fourth digital signal DOUT4. Each of the digital signals (DOUT1 to DOUT4) includes a reset sampling value and a signal sampling value.

[0086] The high-speed scanner 121 includes the first to fourth sub-scanners (121_1 to 121_4). Each of the first to fourth subscanners (121_1 to 121_4) receives a clock signal CLK, a read trigger signal RTRIG, and a corresponding cluster activation signal (CEN, CEN1 to CEN4). The cluster activation signals (CEN1~CEN4) are signals used to select the cluster that will perform the digital signal output operation from among multiple clusters.

[0087] For example, the first subscanner SS1 receives the first cluster activation signal CEN1 and provides the first scanner output signal SO1 to the pixel array 110. The second subscanner SS2 receives the second cluster activation signal CEN2 and provides the second scanner output signal SO2 to the pixel array 110. The third subscanner SS3 receives the third cluster activation signal CEN3 and provides the third scanner output signal SO3 to the pixel array 110. The fourth subscanner SS4 receives the fourth cluster activation signal CEN4 and provides the fourth scanner output signal SO4 to the pixel array 110.

[0088] The first scanner output signal SO1 is output to the fifth part (CL11, CL21, CL31, CL41) of the multiple clusters. The second scanner output signal SO2 is output to the sixth part (CL12, CL22, CL32, CL42) of the multiple clusters. The third scanner output signal SO3 is output to the seventh part (CL13, CL23, CL33, CL43) of the multiple clusters. The fourth scanner output signal SO4 is output to the eighth part (CL14, CL24, CL34, CL44) of the multiple clusters.

[0089] When the first cluster activation signal CEN1 goes high, the first subscanner SS1 responds to the clock signal CLK and the read trigger signal RTRIG by outputting a first scanner output signal SO1 which includes a reset activation signal (R_EN) and a signal activation signal (S_EN). In response to the first scanner output signal SO1 it receives, the pixel array 110 outputs the reset sampling value and signal sampling value stored in the fifth part (CL11, CL21, CL31, CL41) of the multiple clusters via the corresponding digital signals (DOUT1 to DOUT3). The remaining cluster activation signals (CEN2-CEN4) are similar, so a detailed explanation will be omitted.

[0090] Each of the clusters (CL11 to CL44) receives a corresponding scanner output signal (SO1 to SO4) from the high-speed scanner 121. Each of the multiple clusters (CL11 to CL44) outputs a reset sampling value R and a signal sampling value S sequentially or randomly based on the scanner output signals (SO1 to SO4).

[0091] Referring to Figure 5B, cluster CL includes multiple banks (B1 to B4). The cluster configuration shown in Figure 5B is an example, and the scope of the present invention is not limited thereto. For example, the number of banks formed in a cluster CL, the number of memory cells contained in a bank, the number of digital pixels corresponding to one bank, the number of word lines, or the number of bit lines can be varied in many ways.

[0092] Each of the multiple banks (B1 to B4) contains multiple memory cells. In other words, each of the multiple banks (B1 to B4) implements an array of memory cell MCs of multiple digital pixel DP memory circuits MCTs. For example, each of the multiple banks (B1 to B4) contains memory cells MC arranged in the first to fourth rows and the first to second columns. The first bank B1 contains multiple memory cells (MC11~MC42), the second bank B2 contains multiple memory cells (MC51~MC82), the third bank B3 contains multiple memory cells (MC91~MCc2), and the fourth bank B4 contains multiple memory cells (MCd1~MCg2).

[0093] Assume that each of the multiple banks (B1 to B4) corresponds to two digital pixels (DP). For example, of the memory cells (MC11 to MC42) included in the first bank B1, the first portion (MC11, MC12, MC21, MC22) corresponds to the first digital pixel DP1, and of the memory cells (MC11 to MC42) included in the first bank B1, the second portion (MC31, MC32, MC41, MC42) corresponds to the second digital pixel DP2. In other words, the first bank B1 stores the reset sampling value R and the signal sampling value S of the first and second digital pixels (DP1, DP2). The remaining banks (B2-B3) are similar, so a detailed explanation will be omitted.

[0094] Each memory cell (MC11 to MCg2) included in cluster CL is connected to a word line (WL1 to WL16) and a bit line (BL1, BL2), respectively. As mentioned above, the memory cells (MC11 to MCg2) are configured to store the corresponding digital signal DOUT, i.e., the reset sampling value R or the signal sampling value S.

[0095] The cluster CL receives reset activation signals (R_EN1~R_EN8) and signal activation signals (S_EN1~S_EN8) from the high-speed scanner 121 via word lines (WL1~WL16). The cluster CL outputs the stored reset sampling value R and signal sampling value S as multiple digital bit signals (DB1 to DB4) via bit lines (BL1 and BL2). In other words, each of the digital signals (DOUT1 to DOUT4) in Figure 5A contains multiple digital bit signals (DB1 to DB4).

[0096] In this example embodiment, the first bank B1 receives (R_EN1, S_EN1, R_EN2, S_EN2), the second bank B2 receives (R_EN3, S_EN3, R_EN4, S_EN4), the third bank B3 receives (R_EN5, S_EN5, R_EN6, S_EN6), and the fourth bank B4 receives (R_EN7, S_EN7, R_EN8, S_EN8).

[0097] The memory cells located in the first row (MC11, MC12) receive the first reset activation signal (R_EN1) via the first word line WL1. In response to the first reset activation signal (R_EN1) (or when the first reset activation signal (R_EN1) goes high), the reset sampling value R stored in the memory cells (MC11, MC12) located in the first row is output as digital bit signals (DB1, DB2) via the bit lines (BL1, BL2). The memory cells located in the second row (MC21, MC22) receive the first signal activation signal (S_EN1) via the second word line WL2. In response to the first signal activation signal (S_EN1) (or when the first signal activation signal (S_EN1) goes high), the signal sampling value S stored in the memory cells (MC21, MC22) located in the second row is output as digital bit signals (DB1, DB2) via the bit lines (BL1, BL2).

[0098] The memory cells located in the third row (MC31, MC32) receive the second reset activation signal (R_EN2) via the third word line WL3. In response to the second reset activation signal (R_EN2), the reset sampling value R stored in the memory cells (MC31, MC32) located in the third row is output as digital bit signals (DB1, DB2) via the bit lines (BL1, BL2). The memory cells located in the fourth row (MC41, MC42) receive the second signal activation signal (S_EN2) via the fourth word line WL4. In response to the second signal activation signal (S_EN2), the signal sampling value S stored in the memory cells (M421, MC42) located in the fourth row is output as digital bit signals (DB1, DB2) via the bit lines (BL1, BL2). The memory cells in the remaining banks (B2-B3) are similar, so a detailed explanation will be omitted.

[0099] Figure 6 is a circuit diagram showing the subscanner from Figure 5A as an example. Referring to Figures 5A and 6, the subscanner SSa receives the read trigger signal RTRIG, the cluster activation signal CENx, and the clock signal CLK from the sensor controller 131. The subscanner SSa provides the scanner output signal SO to the pixel array 110. In other words, the subscanner SSa outputs the first to eighth reset activation signals (R_EN1 to R_EN8) and the first to eighth signal activation signals (S_EN1 to S_EN8). The subscanner SSa includes the 1st to 16th flip-flops (FF1 to FF16) and the 1st and gate A1. However, the scope of the present invention is not limited thereto, and the number of flip-flops included in the subscanner SSa can be increased or decreased depending on the method of implementation.

[0100] The first AND gate A1 receives the clock signal CLK and the cluster activation signal CEN. The first AND gate A1 performs logical operations on the clock signal CLK and the cluster activation signal CENx. The first AND gate A1 outputs the result of performing a logical operation on the clock signal CLK and the cluster activation signal CENx as the cluster clock signal (C_CLK).

[0101] Each of the 1st to 16th flip-flops (FF1 to FF16) includes a clock input terminal, an input terminal D, and an output terminal Q. The first to sixteenth flip-flops (FF1 to FF16) receive the cluster clock signal (C_CLK) via the club input terminal, receive the input signal via input terminal D, and output the output signal via output terminal Q.

[0102] Of the multiple flip-flops (FF1 to FF16), each of the odd-numbered flip-flops (FF1, FF3, FF5, FF7, FF9, FF11, FF13, FF15) outputs the first to eighth reset activation signals (R_EN1 to R_EN8). Of the multiple flip-flops (FF1 to FF16), each of the even-numbered flip-flops (FF2, FF4, FF6, FF8, FF10, FF12, FF14, FF16) outputs the 1st to 8th signal activation signals (S_EN1 to S_EN8).

[0103] Multiple flip-flops (FF1-FF16) operate in response to a cluster clock signal (C_CLK). Each of the multiple flip-flops (FF1-FF16) responds to the rising edge (or falling edge) of the cluster clock signal (C_CLK) by outputting the logic level of the input signal (e.g., high or low level) as an output signal via output terminal Q.

[0104] Multiple flip-flops (FF1 to FF16) are connected in series. In other words, multiple flip-flops (FF1 to FF16) are connected in a chain structure. For example, the first reset activation signal (R_EN1) output from the output terminal Q of the first flip-flop FF1 is input as an input signal via the input terminal D of the second flip-flop FF2. The first signal activation signal (S_EN1) output from the output terminal Q of the second flip-flop FF2 is input as an input signal via the input terminal D of the third flip-flop FF3. The second reset activation signal (R_EN2), output from the output terminal Q of the third flip-flop FF3, is input as an input signal via the input terminal D of the fourth flip-flop FF4. The second signal activation signal (S_EN2) output from the output terminal Q of the fourth flip-flop FF4 is input as an input signal via the input terminal D of the fifth flip-flop FF5. The remaining flip-flops (FF5-FF16) are connected in a similar manner, and a detailed explanation of their connection will be omitted.

[0105] In an example embodiment, to prevent clock racing, the subscanner SSa receives the clock signal CLK and the read trigger signal RTRIG in opposite directions. For example, the subscanner SSa receives a clock signal CLK that travels in the first direction and a read trigger signal RTRIG that travels in the second direction, which is opposite to the first direction.

[0106] Figure 7A is a timing diagram showing multiple cluster activation signals as an example in Figure 5A, and Figure 7B is a timing diagram showing the operation of the image sensor device in Figure 1 as an example. Referring to Figures 5A and 7A, within the first cluster output section COUT1, the first cluster activation signal CEN1 is logically high, the second cluster activation signal CEN2 is logically low, the third cluster activation signal CEN3 is logically low, and the fourth cluster activation signal CEN4 is logically low.

[0107] Within the second cluster output section COUT2, the first cluster activation signal CEN1 is logically low, the second cluster activation signal CEN2 is logically high, the third cluster activation signal CEN3 is logically low, and the fourth cluster activation signal CEN4 is logically low. Within the third cluster output section COUT3, the first cluster activation signal CEN1 is logically low, the second cluster activation signal CEN2 is logically low, the third cluster activation signal CEN3 is logically high, and the fourth cluster activation signal CEN4 is logically low. Within the fourth cluster output section COUT4, the first cluster activation signal CEN1 is logically low, the second cluster activation signal CEN2 is logically low, the third cluster activation signal CEN3 is logically low, and the fourth cluster activation signal CEN4 is logically high.

[0108] The read trigger signal RTRIG is used to start or initiate the digital signal DOUT output operation in cluster CL. The read trigger signal RTRIG is activated for each cluster. For example, the read trigger signal RTRIG transitions from logical low to logical high at the first time point t1, the third time point t3, the fifth time point t5, and the seventh time point t7, and from logical high to logical low at the second time point t3, the fourth time point t4, and the sixth time point t6.

[0109] The read trigger signal RTRIG is activated before the cluster activation signals (CEN1~CEN4) are activated. For example, the read trigger signal RTRIG is activated from the first time point t1 to the second time point t2, and then the first cluster activation signal CEN1 is activated from the second time point t2 to the fourth time point t4. The read trigger signal RTRIG is activated from the third time point t3 to the fourth time point t4, and then the second cluster activation signal CEN2 is activated from the fourth time point t4 to the sixth time point t6. The read trigger signal RTRIG is activated from time 5 t5 to time 6 t6, and then the third cluster activation signal CEN3 is activated from time 6 t6 to time 8 t8. The read trigger signal RTRIG is activated from time point 7 t7 to time point 8 t8, and then the fourth cluster activation signal CEN4 is activated from time point 8 t8 to time point 9 t9.

[0110] Within the first cluster output section COUT1, the first cluster activation signal CEN1 is logically high, thus activating the first subscanner SS1. In other words, the multiple flip-flops (FF1~FF16) of the first subscanner SS1 receive a cluster clock signal (C_CLK) to toggle. Therefore, the first subscanner SS1 provides the first scanner output signal SO1 to the clusters (CL11, CL21, CL31, CL41) connected to the first subscanner SS1. The clusters (CL11, CL21, CL31, CL41) connected to the first subscanner SS1 output the stored reset sampling value R and signal sampling value S in response to the first scanner output signal SO1.

[0111] Within the second cluster output section COUT2, the second cluster activation signal CEN2 is logically high, so the second subscanner SS2 is activated, and the clusters connected to the second subscanner SS2 (CL12, CL22, CL32, CL42) output the stored reset sampling value R and signal sampling value S in response to the second scanner output signal SO2.

[0112] Within the third cluster output section COUT3, the third cluster activation signal CEN3 is logically high, so the third subscanner SS3 is activated, and the clusters connected to the third subscanner SS3 (CL13, CL23, CL33, CL43) output the stored reset sampling value R and signal sampling value S in response to the third scanner output signal SO3. Within the fourth cluster output section COUT4, the fourth cluster activation signal CEN4 is logically high, so the fourth subscanner SS4 is activated, and the clusters connected to the fourth subscanner SS4 (CL14, CL24, CL34, CL44) output the stored reset sampling value S and signal sampling value S in response to the fourth scanner output signal SO4.

[0113] Referring to Figure 7B, when the first cluster activation signal CEN1 is logically high, the first subscanner SS1 is activated and outputs the first scanner output signal SO1. Within the first cluster output section COUT1, the first cluster activation signal CEN1 is logically high. In other words, at the second time point t2, the first cluster activation signal CEN1 transitions from logical low to logical high, and at the fourth time point t4, it transitions from logical high to logical low. Within the first cluster output section COUT1, the first subscanner SS1 is activated and outputs the first scanner output signal SO1. The clusters (CL11, CL21, CL31, CL41) connected to the first subscanner SS1 output the stored reset sampling value R and signal sampling value S in response to the first scanner output signal SO1.

[0114] The first reset activation signal (R_EN1) is activated in the first reset output section ROUT1, the first signal activation signal (S_EN1) is activated in the first signal output section SOUT1, the second reset activation signal (R_EN2) is activated in the second reset output section ROUT2, and the second signal activation signal (S_EN2) is activated in the second signal activation output section SOUT2. The remaining reset activation signals (R_EN3~R_EN8) and the remaining signal activation signals (S_EN3~S_EN8) are similar, so a detailed explanation will be omitted.

[0115] In the first reset output section ROUT1, only the first reset activation signal (R_EN1) is logically high (or activated), while the remaining signals (R_EN2~R_EN8, S_EN1~S_EN8) are logically low (or deactivated). Therefore, the reset sampling value R1 stored in the memory cells (MC11, MC12) connected to the first word line WL1 is output via the bit lines (BL1, BL2) as digital bit signals (DB1, DB2) or digital signal DOUT1.

[0116] In the first signal output section SOUT1, only the first signal activation signal (S_EN1) is logically high, and the remaining signals (R_EN1~R_EN8, S_EN2~S_EN8) are logically low. Therefore, the signal sampling value S1 stored in the memory cells (MC21, MC22) connected to the second word line WL2 is output as the digital signal DOUT1 via the bit lines (BL1, BL2). The remaining signals (R_EN2~R_EN8, S_EN2~S_EN8) are similar, so a detailed explanation will be omitted.

[0117] As described above, the subscanner SSa generates reset activation signals (R_EN1~R_EN8) and signal activation signals (S_EN1~S_EN8) to sequentially select rows. As a result, the image sensor device 100 outputs the reset sampling value and signal sampling value stored in the memory cell to the digital signal processing unit 132 at high speed.

[0118] Figure 8A is a circuit diagram illustrating the schematic configuration of the subscanner shown in Figure 5A as an example. Referring to Figures 5A and 8A, the subscanner SSb generates reset activation signals (R_EN1~R_EN8), signal activation signals (S_EN1~S_EN8), and multiple dummy signals (dS1~dS15) in order to output the reset sampling value R and signal sampling value S stored in the memory cell at high speed. The subscanner SSb includes the 1st to 16th flip-flops (FF1 to FF16), the 1st to 15th dummy flip-flops (dFF1 to dFF15), and 1 and gate A1. However, the scope of the present invention is not limited thereto, and the number of flip-flops containing subscanners SSb and the number of dummy flip-flops can be increased or decreased depending on the implementation.

[0119] The first AND gate A1 receives the clock signal CLK and the cluster activation signal CENx. The first AND gate A1 performs logical operations on the clock signal CLK and the cluster activation signal CENx. The first AND gate A1 outputs the result of a logical operation performed on the clock signal CLK and the cluster activation signal CENx as the cluster clock signal (C_CLK).

[0120] Each of the multiple flip-flops (FF1~FF16) and multiple dummy flip-flops (dFF1~dFF15) includes a clock input terminal, an input terminal D, and an output terminal Q. Each of the multiple flip-flops (FF1~FF16) and multiple dummy flip-flops (dFF1~dFF15) receives a cluster clock signal (C_CLK) via the clock input terminal, receives an input signal via input terminal D, and outputs an output signal via output terminal Q.

[0121] Of the multiple flip-flops (FF1 to FF16), each of the odd-numbered flip-flops (FF1, FF3, FF5, FF7, FF9, FF11, FF13, FF15) outputs the first to eighth reset activation signals (R_EN1 to R_EN8). Of the multiple flip-flops (FF1 to FF16), each of the even-numbered flip-flops (FF2, FF4, FF6, FF8, FF10, FF12, FF14, FF16) outputs the 1st to 8th signal activation signals (S_EN1 to S_EN8). The 1st to 15th dummy flip-flops (dFF1 to dFF15) each output the 1st to 15th dummy signals (dS1 to dS15).

[0122] Each of the multiple flip-flops (FF1-FF16) and multiple dummy flip-flops (dFF1-dFF15) operates in response to the cluster clock signal (C_CLK). Each of the multiple flip-flops (FF1-FF16) and multiple dummy flip-flops (dFF1-dFF15) responds to the rising edge (or falling edge) of the cluster clock signal (C_CLK) by outputting the logic level (e.g., high or low level) of the input signal via the output terminal Q.

[0123] Each of the multiple flip-flops (FF1-FF16) and the multiple dummy flip-flops (dFF1-dFF15) is connected in alternating series. In other words, multiple flip-flops (FF1 to FF16) and multiple dummy flip-flops (dFF1 to dFF15) are connected in a chain structure. For example, the first reset activation signal (R_EN1) output from the output terminal Q of the first flip-flop FF1 is input as an input signal via the input terminal D of the first dummy flip-flop dFF1. The first dummy signal dS1, output from the output terminal Q of the first dummy flip-flop dFF1, is input as an input signal via the input terminal D of the second flip-flop FF2. The first signal activation signal (S_EN1) output from the output terminal Q of the second flip-flop FF2 is input as an input signal via the input terminal D of the second dummy flip-flop dFF2. The second dummy signal dS2, output from the output terminal Q of the second dummy flip-flop dFF2, is input as an input signal via the input terminal D of the third flip-flop FF3.

[0124] The second reset activation signal (R_EN2), output from the output terminal Q of the third flip-flop FF3, is input as an input signal via the input terminal D of the third dummy flip-flop dFF3. The third dummy signal dS3, output from the output terminal Q of the third dummy flip-flop dFF3, is input as an input signal via the input terminal D of the fourth flip-flop FF4. The second signal activation signal (S_EN2) output from the output terminal Q of the fourth flip-flop FF4 is input as an input signal via the input terminal D of the fourth dummy flip-flop dFF4. The fourth dummy signal dS4, output from the output terminal Q of the fourth dummy flip-flop dFF4, is input as an input signal via the input terminal D of the fifth flip-flop FF5. The remaining flip-flops (FF5-FF16) and the remaining dummy flip-flops (dFF5-dFF16) may be connected in a similar manner, and a detailed explanation of this is omitted.

[0125] Figure 8B is a timing diagram illustrating the operation of the image sensor device shown in Figure 1 as an example. Referring to Figures 8A and 8B, the timing of the rising edge (or falling edge) of the clock signal CLK is adjusted to prevent the logic high intervals of the reset activation signals (R_EN1~R_EN8) and the logic high intervals of the signal activation signals (S_EN1~S_EN8) from overlapping or overlapping.

[0126] In other words, using multiple dummy flip-flops (dFF1~dFF15), the subscanner SSb widens the difference between the logic high intervals (or activation intervals) of adjacent reset activation signals (R_EN1~R_EN8) and the logic high intervals of signal activation signals (S_EN1~S_EN8). The first cluster activation signal CEN1 is logically high during the first cluster output interval COUT1. In other words, the first cluster activation signal CEN1 transitions from logical low to logical high at the second time point t2, and from logical high to logical low at the fourth time point t4.

[0127] The subscanner SSb receives a clock signal CLK that is different from a typical clock signal. In the embodiment shown in Figure 7B, the subscanner SSa receives a typical clock signal CLK in which the interval between rising edges (or falling edges) of the clock signal CLK is constant. In contrast, in the embodiment shown in Figure 8B, the subscanner SSb can receive the clock signal CLK of a process in which the interval between the rising edge (or falling edge) of the clock signal CLK is changed.

[0128] . For example, the clock signal CLK transitions from logical low to logical high at the second time point t2, and from logical high to logical low at the tenth time point t10. The clock signal CLK transitions from logical low to logical high at time 11 (t11) after the second time point t2 and the first time point T1, and then transitions from logical high to logical low at time 12 (t12). The clock signal CLK transitions from logical low to logical high at time 13 (t13), which is after the second time period T2 (shorter than the first time period T1), from time 11 (t11), and then transitions from logical high to logical low at time 14 (t14). The clock signal CLK transitions from logical low to logical high at time 15 t15, after the 1st time T1, from time 13 t13, and then transitions from logical high to logical low at time 16 t16. The clock signal CLK transitions from logical low to logical high at time 17 (t17) from time 15 (t15) through time 2 (t2), and then transitions from logical high to logical low at time 18 (t18). The clock signal CLK from time point 18 (t18) to time point 4 (t4) is the same, so a detailed explanation will be omitted. The first time period T1 can be N times the second time period T2 (where N is a natural number greater than 1).

[0129] As shown in Figure 8B, the time interval between rising edges (or falling edges) of the clock signal CLK is not constant but changes. In other words, the time interval between the rising edge (or falling edge) of the clock signal CLK repeats between the first time period T1 and the second time period T2. Specifically, a rising edge of the clock signal CLK occurs at the second time point t2, a rising edge of the clock signal CLK occurs at the 11th time point t11 ​​(after the first time point T1), a rising edge of the clock signal CLK occurs at the 13th time point t13 (after the second time point T2), a rising edge of the clock signal CLK occurs at the 15th time point t15 (after the first time point T1), and a rising edge of the clock signal CLK occurs at the 17th time point t17 (after the second time point T2).

[0130] As shown in Figure 8B, the first reset activation signal (R_EN1) transitions from logical low to logical high at the second time point t2, and from logical high to logical low at the eleventh time point t11. The first dummy signal dS1 transitions from logical low to logical high at time 11 t11, and from logical high to logical low at time 13 t13. The first signal activation signal (S_EN1) transitions from logical low to logical high at time 13 t13, and from logical high to logical low at time 15 t15. The second dummy signal dS2 transitions from logical low to logical high at time 15 (t15) and from logical high to logical low at time 17 (t17). The remaining reset activation signals (R_EN2~R_EN8), signal activation signals (S_EN2~S_EN8), and remaining dummy signals (dS3~dS15) are similar, so a detailed explanation is omitted.

[0131] By changing the interval between rising edges (or falling edges) of the clock signal CLK, the interval between the logic high interval of an adjacent reset activation signal and the logic high interval of a signal activation signal is increased by a second time T2. In other words, the first reset activation signal (R_EN1) transitions from logical high to logical low at the 11th time point t11, and the first signal activation signal (S_EN1) transitions from logical low to logical high at the 13th time point t13, from the 11th time point t11 ​​onwards, during the second time point T2. This prevents the logic high interval of the reset activation signal from overlapping with the logic high interval of the signal activation signal.

[0132] Figures 9A and 9B are block diagrams illustrating the schematic configuration of the row driver shown in Figure 2A as an example. Referring to Figures 2A and 9A, the row driver RDVb includes a high-speed scanner 121, a front circuit 122, a decoder 123, a logic circuit 124, and a driver 125. For the sake of clarity, a detailed explanation of the aforementioned components will be omitted.

[0133] In the embodiment shown in Figure 9A, the high-speed scanner 121 is connected between the logic circuit 124 and the driver 125. In other words, the high-speed scanner 121 provides multiple scanner output signals (SO1 to SO4) to the driver 125. The driver 125 converts the voltage levels of multiple scanner output signals (OS1 to OS4) and provides them to the pixel array 110.

[0134] Referring to Figure 9B, the row driver RDVc includes a high-speed scanner 121, a front circuit 122, a decoder 123, a logic circuit 124, and a driver 125. For the sake of clarity, a detailed explanation of the aforementioned components will be omitted. In the embodiment shown in Figure 9B, the high-speed scanner 121 is connected between the decoder 123 and the logic circuit 124. In other words, the high-speed scanner 121 provides multiple scanner output signals (SO1 to SO4) to the logic circuit 124. The logic circuit 124 outputs various control signals (CTRL) based on multiple scanner output signals (OS1 to OS4).

[0135] Figure 10 is a block diagram showing a schematic configuration of an image sensor device according to an embodiment of the present invention. Referring to Figure 10, the image sensor device 200 includes a pixel array 210, a row driver 220, an analog-to-digital converter (ADC) 230, an output circuit 240, and a control logic circuit 250.

[0136] Pixel array 210 contains multiple pixels PX. Each of the multiple pixels is configured to output an electrical signal, or analog signal, that is proportional to the intensity of the incident light, based on the light incident from the outside. In an exemplary embodiment, each of the multiple pixels is combined with a different color filter (e.g., R, G, B, etc.) to receive light waves of different wavelengths.

[0137] The multiple pixels that make up the pixel array 210 include multiple pixel groups PG. Each pixel group PG contains two or more pixels. The pixels that make up a pixel group PG share one floating spread node. However, the present invention is not limited thereto, and pixels constituting a pixel group PG may also share multiple floating diffuse nodes. For example, a pixel group PG may contain nine pixels PX arranged in a 3x3 grid, or four pixels PX arranged in a 2x2 grid, but the number of pixels constituting a pixel group PG is not limited to these.

[0138] A pixel group (PG) contains pixels of the same type to output information related to the same color. For example, a pixel group PG includes red (R) pixels that convert light waves in the red spectral region into electrical signals, green (Gr, Gb) pixels that convert light waves in the green spectral region into electrical signals, or blue (B) pixels that convert light waves in the blue spectral region into electrical signals. To achieve this, multiple color filters are formed on the pixel group PG, creating a multi-color filter array (Multi-CFA). A color filter array can be formed based on at least one of a variety of patterns, such as a Bayer pattern or a Tetra pattern.

[0139] The row driver 220 is configured to control multiple pixels included in the pixel array 210. For example, the row driver 220 generates a variety of control signals (e.g., shutter signals, transfer signals, reset signals, selection signals, etc.) for controlling multiple pixels. In an example embodiment, the row driver 220 can control multiple pixels on a row-by-row basis, but the scope of the present invention is not limited thereto. For example, the row driver 220 includes a high-speed scanner 221, as described with reference to Figures 1 to 9B. The high-speed scanner 221 is configured to generate scanner output signals (or reset activation signals and signal activation signals) for rapidly sequentially or randomly selecting multiple rows.

[0140] In this example embodiment, the image sensor device 200 operates in global shutter mode. The entire signal, photoelectrically transformed from all photodiodes (PD) within a single frame, is transmitted simultaneously to a floating spread node (FD), which then sequentially outputs the corresponding video signals from the selected row. The high-speed scanner 221 according to an embodiment of the present invention generates a reset activation signal (R_EN) and a signal activation signal (S_EN), and outputs a reset sampling value R and a signal sampling value S at high speed.

[0141] The ADC230 converts the analog signals formed from each of multiple pixels into digital signals and outputs the converted digital signals as data. In an example embodiment, the ADC230 generates data based on correlated double sampling (CDS). Although not shown in the figure, the image sensor device 200 may further include a memory circuit or memory configured to store data output from the ADC230, or a lamp generator configured to generate a lamp signal used to operate the ADC230.

[0142] The output circuit 240 transmits the image output from the ADC 230 to an external device (for example, a display or storage device). The control logic circuit 250 is configured to control various components within the image sensor device 200 according to the control of an external control device (e.g., an image sensor controller or an application processor).

[0143] Figure 11 is a block diagram showing an example of a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention, and Figure 12 is a block diagram showing a detailed configuration example of the camera module in Figure 11. Referring to Figure 11, the electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

[0144] Camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). The figure simply shows an embodiment in which three camera modules (1100a, 1100b, and 1100c) are arranged, but the embodiment is not limited thereto. In some embodiments, the camera module group 1100 may be modified and implemented to include only two camera modules. In some embodiments, the camera module group 1100 may be modified and implemented to include n camera modules (where n is a natural number greater than or equal to 4).

[0145] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 12, but the following description also applies to other camera modules (1100a, 1100c) depending on the embodiment. Referring to Figure 12, the camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device unit 1150.

[0146] The prism 1105 alters the path of the light L incident from the outside, including the reflective surface 1107 of the light-reflecting material. In some embodiments, the prism 1105 changes the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 rotates the reflective surface 1107 of the light-reflecting material in direction A around the central axis 1106, or rotates the central axis 1106 in direction B, thereby changing the path of light L incident in the first direction X to the perpendicular second direction Y. At this time, OPFE1110 also moves in a third direction Z that is perpendicular to the first direction X and the second direction Y.

[0147] In some embodiments, as shown in the figure, the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the embodiments are not limited thereto. In some embodiments, the prism 1105 can move in the positive (+) or negative (-)B direction by approximately 20 degrees, between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be the same angle in the positive (+) or negative (-)B direction, or to approximately similar angles within a range of approximately 1 degree. In some embodiments, the prism 1105 can move the reflective surface 1107 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the extension of the central axis 1106.

[0148] The OPFE1110 includes, for example, an optical lens consisting of m (where m is a natural number) groups. m lenses move in the second direction Y to change the optical zoom ratio of camera module 1100b. For example, if the basic optical zoom magnification of camera module 1100b is Z, then when the m optical lenses included in OPFE1110 are moved, the optical zoom magnification of camera module 1100b is changed to 3Z, 5Z, or 5Z or greater. The OPFE1110 may further include optical lenses (e.g., anamorphic lenses) consisting of n (where n is a natural number) groups on the entire surface of the m lenses described above.

[0149] The actuator 1130 moves the OPFE 1110 or optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing.

[0150] The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses an image of the object to be sensed using light L provided through an optical lens. Furthermore, the image sensor 1142 includes a high-speed scanner configured to generate a reset activation signal and a signal activation signal for high-speed row selection, as described with reference to Figures 1 to 10. The image sensor 1142 outputs a reset sampling value and a signal sampling value at high speed based on the reset activation signal and the signal activation signal.

[0151] The control logic 1144 controls the overall operation of the camera module 1100b. For example, the control logic 1144 controls the operation of the camera module 1100b according to control signals provided via the control signal line CSLb.

[0152] Memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 contains information necessary for the camera module 1100b to generate image data using light L supplied from an external source. Calibration data 1147 may include, for example, information regarding the degree of rotation, focal length, and optical axis as described above. If the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 may include the focal length values ​​for each position (or state) of the optical lens and information related to autofocusing.

[0153] The storage device unit 1150 stores image data sensed via the image sensor 1142. The storage device unit 1150 is located outside the image sensing device 1140 and is implemented in a stacked configuration with the sensor chips that make up the image sensing device 1140. In some embodiments, the storage device unit 1150 is implemented using EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited to this.

[0154] Referring to both Figures 11 and 12, in some embodiments, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Therefore, each of the multiple camera modules (1100a, 1100b, 1100c) contains calibration data 1147 that is either identical or different to each other, corresponding to the operation of the actuator 1130 contained within it.

[0155] In some embodiments, of the multiple camera modules (1100a, 1100b, 1100c), one camera module (e.g., 1100b) is a folded lens type camera module including the prism 1105 and OPFE 1110 described above, while the remaining camera modules (e.g., 1100a, 1100b) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but embodiments are not limited thereto.

[0156] In some embodiments, of the multiple camera modules (1100a, 1100b, 1100c), one camera module (e.g., 1100c) is a vertical depth camera that extracts depth information using, for example, infrared (IR). In this case, the application processor 1200 merges the image data provided by these depth cameras with the image data provided by another camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0157] In some embodiments, among the plurality of camera modules (1100a, 1100b, 1100c), at least two camera modules (for example, 1100a, 1100b) have different observation fields of view (Field of View, viewing angle). In this case, for example, among the plurality of camera modules (1100a, 1100b, 1100c), the optical lenses of at least two camera modules (for example, 1100a, 1100b) may be different from each other, but are not limited thereto.

[0158] Note that in some embodiments, the viewing angles of each of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also be different from each other, but are not limited thereto.

[0159] In some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) is physically separated and arranged from each other. That is, instead of a plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of one image sensor 1142, independent image sensors 1142 are arranged inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0160] Referring to FIG. 11 again, the application processor 1200 includes an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 is implemented separately from the plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the plurality of camera modules (1100a, 1100b, 1100c) are implemented separately on separate semiconductor chips.

[0161] The image processing device 1210 includes a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216. The image processing device 1210 may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of a plurality of camera modules (1100a, 1100b, 1100c).

[0162] The image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processor (1212a, 1212b, 1212c) via image signal lines (ISLa, ISLb, ISLc) that are separated from each other. For example, the image data generated from the camera module 1100a is provided to the sub-image processor 1212a via the image signal line ISLa, the image data generated from the camera module 1100b is provided to the sub-image processor 1212b via the image signal line ISLb, and the image data generated from the camera module 1100c is provided to the sub-image processor 1212c via the image signal line ISLc. Such transfer of image data is performed, for example, using a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0163] On the other hand, in some embodiments, one sub-image processor is arranged to correspond to a plurality of camera modules. For example, instead of the sub-image processors 1212a and 1212c being implemented separately as shown in the figure, they are integrated and implemented as a single sub-image processor, and the image data provided from camera modules 1100a and 1100c are selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0164] The image data provided to each sub-image processor (1212a, 1212b, 1212c) is provided to the image generator 1214. The image generator 1214 generates an output image using image data provided by each sub-image processor (1212a, 1212b, 1212c) according to the generating information or mode signal.

[0165] Specifically, the image generator 1214 generates an output image by merging at least a portion of the image data generated from camera modules (1100a, 1100b, 1100c) having different field-of-view angles, according to the image generation information or mode signal. Furthermore, the image generator 1214 selects one of the image data generated from camera modules (1100a, 1100b, 1100c) having different field-of-view angles, according to the image generation information or mode signal, and generates an output image. In some embodiments, the image generation information includes a zoom signal (or zoom factor). In some embodiments, the mode signal may be, for example, a signal based on a mode selected by the user.

[0166] If the image generation information is a zoom signal (zoom factor), and each camera module (1100a, 1100b, 1100c) has a different field of view (field of view angle), the image generator 1214 performs different operations depending on the type of zoom signal. For example, if the zoom signal is the first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then the merged image signal and the image data output from camera module 1100b that was not used in the merging are used to generate the output image. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate the output image. However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0167] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c), and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range. In some embodiments, the image generator 1214 performs a compensation operation on the second image to generate an image in which the color difference with the final image generated in the first mode is mitigated.

[0168] The camera module controller 1216 provides control signals to each camera module (1100a, 1100b, 1100c). Control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via isolated control signal lines (CSLa, CSLb, CSLc).

[0169] Of the multiple camera modules (1100a, 1100b, 1100c), one is designated as the master camera (e.g., 1100b) depending on the image generation information or mode signal, including the zoom signal, while the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. This information is included in the control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) via isolated control signal lines (CSLa, CSLb, CSLc).

[0170] Depending on the zoom factor or operating mode signal, the camera modules operating as master and slave are changed. For example, if camera module 1100a has a wider field of view than camera module 1100b and exhibits a lower zoom factor, camera module 1100b will operate as the master and camera module 1100a will operate as the slave. Conversely, when the zoom factor indicates a high zoom magnification, camera module 1100a operates as the master and camera module 1100b operates as the slave.

[0171] In some embodiments, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 sends a sink enable signal to camera module 1100b. Camera module 1100b, which is provided with such a sync enable signal, generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules (1100a, 1100c) via the sync signal line SSL. Camera module 1100b and camera modules (1100a, 1100c) send image data to the application processor 1200 in synchronization with such a sync signal.

[0172] In some embodiments, the control signals provided from the camera module controller 1216 to multiple camera modules (1100a, 1100b, 1100c) include mode information corresponding to the mode signal. Based on this mode information, the multiple camera modules (1100a, 1100b, 1100c) operate in a first operating mode and a second operating mode in relation to the sensing speed.

[0173] Multiple camera modules (1100a, 1100b, 1100c) generate an image signal at a first speed in the first operating mode (for example, an image signal at a first frame rate), encode it at a second speed higher than the first speed (for example, an image signal at a second frame rate higher than the first frame rate), and send the encoded image signal to the application processor 1200. In this case, the second velocity is 30 times or less the first velocity.

[0174] The application processor 1200 stores the received image signal, that is, the image signal to be encoded, in the internally provided memory 1230 or the external storage unit 1400 of the application processor 1200, and then reads out and decodes the encoded image signal from the memory 1230 or the storage 1400, and displays the image data generated based on the decoded image signal. For example, among the plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device 1210, the corresponding sub-processor can execute decoding and also execute image processing on the decoded image signal.

[0175] In the second operation mode, the plurality of camera modules (1100a, 1100b, 1100c) generate an image signal at a third speed lower than the first speed (for example, generate an image signal at a third frame rate lower than the first frame rate), and send the image signal to the application processor 1200. The image signal provided to the application processor 1200 is an unencoded signal. The application processor 1200 executes image processing on the received image signal or stores the image signal in the memory 1230 or the storage device 1400.

[0176] The PMIC 1300 supplies power, for example, a power supply voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies the first power to the camera module 1100a via the power signal line PSLa, supplies the second power to the camera module 1100b via the power signal line PSLb, and supplies the third power to the camera module 1100c via the power signal line PSLc.

[0177] The PMIC1300 responds to the power control signal PCON from the application processor 1200 to generate power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c) and adjusts the power levels. The power control signal PCON includes power adjustment signals for each operating mode of multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode includes a low power mode, in which case the power control signal PCON includes information about the camera module operating in low power mode and the set power level. The power levels supplied to each of the multiple camera modules (1100a, 1100b, 1100c) are either the same or different from one another. The power level will be changed dynamically.

[0178] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0179] 100 Image Sensor Devices 110-pixel array 120 Pixel Driver 121 High-Speed ​​Scanner 130 Digital Logic Circuits 131 Sensor Controller 132 Digital signal processing unit 133 Input / Output Interfaces

Claims

1. An image sensor device, A pixel array having multiple digital pixels, A high-speed scanner configured to generate a reset activation signal and a signal activation signal, A pixel driver configured to control the plurality of digital pixels, The system includes a digital logic circuit configured to perform digital signal processing operations on the digital signals output from the plurality of digital pixels, Each of the aforementioned plurality of digital pixels includes a photodetector, a comparator, and a memory circuit. The high-speed scanner receives a clock signal and a read trigger signal, and includes a first flip-flop that outputs a first reset activation signal from among the reset activation signals, It includes a second flip-flop that receives the clock signal and the first reset activation signal and outputs the first signal activation signal from among the signal activation signals, The pixel array outputs a reset sampling value stored in the memory circuit in response to the first reset activation signal, and outputs a signal sampling value stored in the memory circuit in response to the first signal activation signal. The digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface. The sensor controller controls the operation of the image sensor device based on control information CI, which includes the clock signal and the read trigger signal, provided from an external device via the input / output interface. The sensor controller provides the clock signal and the read trigger signal to the high-speed scanner. The image sensor device is characterized in that the digital signal processing unit receives the digital signal including the reset sampling value and the signal sampling value from the pixel array, performs digital signal processing on the received digital signal, and determines a final digital value corresponding to the optical signal sensed by the digital pixel.

2. The first flip-flop outputs the logic level of the read trigger signal received in response to the received clock signal as the first reset activation signal. The image sensor device according to claim 1, characterized in that the second flip-flop outputs the logic level of the first reset activation signal received in response to the received clock signal as the first signal activation signal.

3. The aforementioned clock signal is the first clock signal, The image sensor device according to claim 1, characterized in that the high-speed scanner includes a first AND gate configured to receive a second clock signal and a cluster activation signal, and to output the result of performing a logical operation on the second clock signal and the cluster activation signal as the first clock signal.

4. The pixel driver is configured to generate a photodetector control signal provided to the photodetector and a memory control signal provided to the memory circuit, A lamp generator configured to generate a lamp signal provided to the comparator, The image sensor device according to claim 1, further comprising a counter configured to generate code provided to the memory circuit.

5. The row driver provides the high-speed scanner directly to the pixel array with the reset activation signal and the signal activation signal, A front circuit configured to perform a retiming operation to rearrange the received drive signals, A decoder configured to decode and generate an activation signal, A logic circuit configured to output a control signal for controlling the plurality of digital pixels in response to an activation signal received from the decoder, The image sensor device according to claim 4, further comprising a driver configured to convert the voltage level of the control signal received from the logic circuit.

6. The aforementioned row driver is the high-speed scanner, A front circuit configured to perform a retiming operation to rearrange the received drive signals, A decoder configured to decode and generate an activation signal, A logic circuit configured to output control signals for controlling the plurality of digital pixels in response to an activation signal received from the decoder, The image sensor device according to claim 4, further comprising a driver configured to convert the voltage levels of the control signal received from the logic circuit, the reset activation signal received from the high-speed scanner, and the signal activation signal.

7. An image sensor device, A pixel array having multiple digital pixels, A high-speed scanner configured to generate a reset activation signal and a signal activation signal, A pixel driver configured to control the plurality of digital pixels, The system includes a digital logic circuit configured to perform digital signal processing operations on the digital signals output from the plurality of digital pixels, Each of the aforementioned plurality of digital pixels includes a photodetector, a comparator, and a memory circuit. The pixel array outputs the reset sampling value and the signal sampling value stored in the memory circuit at high speed based on the reset activation signal and the signal activation signal. The high-speed scanner includes a first flip-flop that receives a clock signal and a read trigger signal and outputs a first reset activation signal from among the reset activation signals, A first dummy flip-flop that receives the clock signal and the first reset activation signal and outputs a first dummy signal, It includes a second flip-flop that receives the clock signal and the first dummy signal and outputs a first signal activation signal from among the signal activation signals, The digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface. The sensor controller controls the operation of the image sensor device based on control information CI, which includes the clock signal and the read trigger signal, provided from an external device via the input / output interface. The sensor controller provides the clock signal and the read trigger signal to the high-speed scanner. The digital signal processing unit receives the digital signal from the pixel array, including the reset sampling value and the signal sampling value, performs digital signal processing on the received digital signal, and determines the final digital value corresponding to the optical signal sensed by the digital pixel. The first flip-flop outputs the logic level of the read trigger signal as the first reset activation signal in response to the clock signal. The first dummy flip-flop outputs the logic level of the first reset activation signal received in response to the clock signal as the first dummy signal. The image sensor device is characterized in that the second flip-flop outputs the logic level of the first dummy signal received in response to the clock signal as the first signal activation signal.

8. The first reset activation signal is activated at the first rising edge of the clock signal. The first dummy signal is activated at the second rising edge of the clock signal. The first signal activation signal is activated at the third rising edge of the clock signal. The image sensor device according to claim 7, characterized in that the time interval between the first rising edge and the second rising edge is greater than the time interval between the second rising edge and the third rising edge.

9. An image sensor device, A high-speed scanner that generates a reset activation signal and a signal activation signal, A first digital pixel having a first photodetector, a first memory cell for storing reset sampling values ​​from the first photodetector, and a second memory cell for storing signal sampling values, A second digital pixel having a second photodetector, a third memory cell for storing reset sampling values ​​from the second photodetector, and a fourth memory cell for storing signal sampling values, A pixel driver configured to control the first and second digital pixels, The system includes a digital logic circuit configured to perform digital signal processing operations on the digital signals output from the first and second digital pixels, The first to fourth memory cells are connected to multiple bit lines, The first memory cell is connected to the first reset activation signal among the reset activation signals, The second memory cell is connected to the first signal activation signal among the signal activation signals, The third memory cell is connected to the second reset activation signal among the reset activation signals, The fourth memory cell is connected to the second signal activation signal among the signal activation signals, The high-speed scanner includes a first flip-flop that receives a clock signal and a read trigger signal and outputs the first reset activation signal, A first dummy flip-flop that receives the clock signal and the first reset activation signal and outputs a first dummy signal, A second flip-flop that receives the clock signal and the first dummy signal and outputs the first signal activation signal, A second dummy flip-flop receives the aforementioned clock signal and the first signal activation signal and outputs a second dummy signal, A third flip-flop that receives the clock signal and the second dummy signal and outputs the second reset activation signal, A third dummy flip-flop that receives the aforementioned clock signal and the aforementioned second reset activation signal and outputs a third dummy signal, It includes a fourth flip-flop that receives the clock signal and the third dummy signal and outputs the second signal activation signal, The digital logic circuit includes a sensor controller, a digital signal processing unit, and an input / output interface. The sensor controller controls the operation of the image sensor device based on control information CI, which includes the clock signal and the read trigger signal, provided from an external device via the input / output interface. The sensor controller provides the clock signal and the read trigger signal to the high-speed scanner. The image sensor device is characterized in that the digital signal processing unit receives the digital signal including the reset sampling value and the signal sampling value from the first and second digital pixels, performs digital signal processing on the received digital signal, and determines a final digital value corresponding to the optical signal sensed by the digital pixel.

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