Searchable array circuit and related method using load-matched signals for reduced hit signal timing margin

Abstract

The CAM array of compare memory cell circuits includes a decode column corresponding to each set, with each set including at least one row of compare memory cell circuits. Each decode column receives a set clock signal addressing a corresponding set and generates a set match signal for each row of the corresponding set. A column compare circuit generates compare data indicative of bits of a compare tag. A row match circuit generates, for each row, a row match signal in response to the set match signal indicating that the compare tag matches the binary tag stored in that row. The circuitry and loads in the decode column used to generate the set clock signal correspond to the circuitry generating the row match signal in each column of the CAM array, thereby reducing timing margins for match indications and shortening access times to the CAM array.

Description

[Technical Field]

[0001] The technology disclosed herein relates to memory arrays, and more specifically to associative random-access memory (CAM-RAM) arrays. [Background technology]

[0002] Computers and electronic devices process information stored in binary format. Numerous different techniques exist for storing binary data. The technique chosen for storing binary data in a particular situation depends on various factors, including the amount of time the binary data must be stored, the frequency of access to the binary data, whether the data must be stored without power, and the speed at which the binary data must be accessed by processing elements. Binary data can be stored in an array of memory cell circuits on an integrated circuit (IC). The array includes rows and columns of memory cell circuits efficiently arranged on a semiconductor substrate. If the storage location of desired binary data in random access memory (RAM) is known, the processor can access the binary information by identifying the row and column.

[0003] In some situations, the location of binary data can be tracked not by tracking row and column information, but by identifiers (often called tags) based on the binary data itself. The location of desired binary data can be found by locating the corresponding identifier. Identifiers can be constructed from some bits of the binary data, or binary patterns can be generated using algorithms that take the binary data as input. Identifiers are stored at the location corresponding to the binary data so that the location of the binary data can be determined when the identifier is found. In an exhaustive random access method, all identifiers in the array can be read and compared with known identifiers of the desired binary data. However, the time required for such an approach significantly increases the time it takes for the processor to access the desired binary. Instead, content-addressable memory (CAM) has the ability to compare known identifiers of the desired binary data with all identifiers stored in the array. When a matching identifier is found, the location of the desired binary data can be determined. This approach is faster than the exhaustive method, but to further minimize data access time for the CAM array, it is desirable to minimize the time required to compare known identifiers with identifiers (tags) in the array. [Overview of the project]

[0004] Illustrative embodiments disclosed herein include a searchable array circuit using load-matched signals for a reduced hit signal timing margin. The associative memory (CAM) includes a multi-column and multi-row comparison memory cell circuit for storing bits of a binary tag. Triggered by a clock signal, the comparison tag is compared with the binary tags stored in each row of the CAM array to determine which row contains a binary tag that matches the comparison tag, if present. A comparison bit signal indicating the comparison bit of the comparison tag is provided to each column of the comparison memory cell circuit for comparison with the corresponding bit of the binary tag stored in each row. A hit signal, also referred to herein as a row match signal, is an indication that, based on the comparison in each column, the comparison tag matches a binary tag in the row.

[0005] In an exemplary embodiment, the CAM array includes at least one decode column, each decode column corresponding to one set, and each set includes at least one row of comparison memory cell circuitry. Each decode column receives a set clock signal for addressing the corresponding set and generates a set match signal for each row of the corresponding set. A column comparison circuit generates, in each column, comparison true data and comparison complement data indicating the bits of the comparison tag. A row match circuit generates a row match signal for each row in response to a set match signal, indicating that the comparison tag matches the binary tag stored in that row. In one example, each row may include a row match line, and the row match circuit may generate a row match signal for that row in response to the row match line indicating that the comparison tag matches the binary tag in that row. Thus, row match signals are generated in response to both the set clock signal and the row match line, and both the set clock signal and the row match line are triggered by the clock signal. The timing difference between the activation of the set clock signal and the indication of a comparison tag match on the row matching line depends on the difference in propagation delay, which is influenced by manufacturing process variations in each circuit and the number of loads on each circuit. In an exemplary embodiment, the circuit and loads on it used to generate the set clock signal in the decode column correspond to the circuits that generate the row matching signal in each column of the CAM array. Such correspondence reduces the timing margin of the match indication, thereby shortening the access time to the CAM array.

[0006] In an exemplary embodiment, an array of comparator memory circuits is disclosed. The array of comparator memory circuits comprises at least one set, each set having at least one row of a plurality of rows of comparator memory circuits, each row of the plurality of rows configured to store a binary tag. The array of comparator memory circuits comprises a plurality of columns of comparator memory circuits, each column of the plurality of columns having a comparator memory circuit in each row of the plurality of rows. The array of comparator memory circuits comprises at least one decode column, each of which corresponds to one set of the at least one set, and the decode column is configured to receive a set clock signal for the corresponding set and to generate a set match signal on a set match line in each row of the corresponding set. The array of comparator memory circuits comprises a dynamic comparator circuit having a set clock circuit, a column comparator circuit, and a row match circuit. The set clock circuit is configured to generate a set clock signal for each of the at least one decode column to address the corresponding set. The column comparison circuit is configured to generate true comparison data for each of the multiple columns, indicating the true comparison bit of the comparison tag. The row matching circuit is configured to generate a row matching signal for each of the multiple rows, in response to the set matching signal generated in that row, indicating that the comparison tag matches the binary tag stored in that row.

[0007] In another exemplary embodiment, an integrated circuit having an array of comparator memory circuits is disclosed. The array of comparator memory circuits comprises at least one set, each set having at least one row of a plurality of rows of comparator memory circuits, each row of the plurality of rows configured to store a binary tag. The array of comparator memory circuits comprises a plurality of columns of comparator memory circuits, each column of the plurality of columns having a comparator memory circuit in each row of the plurality of rows. The array of comparator memory circuits comprises at least one decode column, each of which corresponds to one set of the at least one set, and the at least one decode column is configured to receive a set clock signal for the corresponding set and to generate a set match signal on a set match line in each row of the corresponding set. The array of comparator memory circuits comprises a dynamic comparator circuit having a set clock circuit, a column comparator circuit, and a row match circuit. The set clock circuit is configured to generate a set clock signal for each of the at least one decode column to address the corresponding set. The column comparison circuit is configured to generate true comparison data for each of the multiple columns, indicating the true comparison bit of the comparison tag. The row matching circuit is configured to generate a row matching signal for each of the multiple rows, in response to the set matching signal generated in that row, indicating that the comparison tag matches the binary tag stored in that row. [Brief explanation of the drawing]

[0008] The drawings in the accompanying drawings, which are incorporated into this specification and constitute part of this specification, illustrate several aspects of this disclosure and, together with the descriptions, serve to illustrate the principles of this disclosure. [Figure 1] This is a schematic diagram of a comparison memory cell circuit used in an associative memory (CAM) array, including a 6-transistor (6T) static random-access memory (SRAM) cell circuit and true compare and complement compare circuits coupled to the matching line. [Figure 2]This is a schematic diagram of a CAM array that includes a 6T SRAM cell circuit as shown in Figure 1 within a row of memory cell circuits. [Figure 3] Figure 2 is a timing diagram showing the timing margin of the set clock used to generate a hit signal indicating that a comparison tag matches a binary tag stored within a row of the CAM array. The timing margin depends on process variability. [Figure 4] This is a schematic diagram of a CAM array, such as the one in Figure 2, which has a programmable delay in the clock signal to adjust for process variations and reduce timing margins. [Figure 5] This is a schematic diagram of an exemplary CAM array that includes a decode sequence corresponding to each set to receive a set clock signal, generate a set match signal, and generate a hit signal indicating a match, with a reduced timing margin. [Figure 6] This is a schematic diagram of a non-comparison memory cell circuit within a CAM array for storing data that is not subject to comparison. [Figure 7] Figure 5 is a schematic diagram of an exemplary modified non-comparative memory cell circuit for forming the decoded column circuit corresponding to each row of the comparison memory cell circuit of the CAM array. [Figure 8] This is a schematic diagram of a CAM array that includes an alternative example of a non-comparison memory cell circuit in the decode sequence, further modified to fine-tune the delay of the set match signal with the row match line. [Figure 9] This is a schematic diagram of a CAM array in which the decode sequence is separated from the non-comparative memory cell circuit. [Figure 10] This is a block diagram of an exemplary processor-based system including multiple devices coupled to a system bus, where any CAM array within the processor-based system may be any of the CAM arrays in Figures 5, 8, and 9. [Modes for carrying out the invention]

[0009] Illustrative embodiments disclosed herein include a searchable array circuit using load-matched signals for a reduced hit signal timing margin. The associative memory (CAM) includes a multi-column and multi-row comparison memory cell circuit for storing bits of a binary tag. Triggered by a clock signal, the comparison tag is compared with the binary tags stored in each row of the CAM array to determine which row contains a binary tag that matches the comparison tag, if present. A comparison bit signal indicating the comparison bit of the comparison tag is provided to each column of the comparison memory cell circuit for comparison with the corresponding bit of the binary tag stored in each row. A hit signal, also referred to herein as a row match signal, is an indication that, based on the comparison in each column, the comparison tag matches a binary tag in the row.

[0010] In an exemplary aspect, the CAM array includes at least one decode column where each decode column corresponds to one set, and each set includes at least one row of comparison memory cell circuits. Each decode column receives a set clock signal for addressing the corresponding set and generates a set match signal for each row in the corresponding set. The column comparison circuit generates comparison true data and comparison complement data indicating bits of the comparison tag in each column. The row match circuit generates a row match signal indicating that the comparison tag matches the binary tag stored in the row in response to the set match signal for each row. In one example, each row can include a row match line, and the row match circuit can generate a row match signal for the row in response to the row match line indicating that the comparison tag matches the binary tag within the row. Thus, the row match signal is generated in response to both the set clock signal and the row match line, and both the set clock signal and the row match line are triggered by a clock signal. The difference in timing between the activation of the set clock signal and the indication of the comparison tag match on the row match line depends on the propagation delay difference affected by the manufacturing process variation in each circuit and the number of loads on each circuit. In an exemplary aspect, the circuit used to generate the set clock signal within the decode column and the load thereon correspond to the circuit for generating the row match signal within each column of the CAM array. Such correspondence reduces the timing margin of the match indication, thereby shortening the access time to the CAM array.

[0011] Before describing exemplary embodiments of associative memory (CAM) arrays shown in Figures 5-9, we will first describe existing CAM array circuits and their operation with reference to Figures 1-4. A CAM array is configured to compare, for example, a comparison bit pattern (comparison tag) known to a processor with a bit pattern (binary tag) stored in the CAM array. The location of a binary tag that matches the comparison tag indicates the location where the desired data corresponding to the comparison tag is stored. To minimize the time required to access the desired binary data in the CAM array, the time required to compare the comparison tag with all binary tags and generate a match indication must be minimized.

[0012] Figure 1 is a schematic diagram of a comparison memory cell circuit 100 that may be used to store bits of a binary tag in a CAM array (not shown). The comparison memory cell circuit 100 includes a 6-transistor (6T) static random access memory cell circuit 102. The comparison memory cell circuit 100 also includes a true comparison circuit 104T and a complement comparison circuit 104C coupled to a match line 106. The true comparison circuit 104T and the complement comparison circuit 104C are used to compare true data 108T in a true data node 110T with comparison true data 112T, and to compare complement data 108C in a complement data node 110C with comparison complement data 112C, respectively. The complement data 108C is a complement to the true data 108T (e.g., inversely). The results of the comparison are shown on the match line 106.

[0013] During operation, the matching line 106 is powered by a pre-charge circuit (not shown) via the power supply voltage (V DD It is pre-charged to the power supply voltage (V). Transistor 114A in the true comparator circuit 104T is coupled to the true data node 110T, and the true data node 110T is set to the power supply voltage (V). DD ) is turned on by being in (this corresponds, for example, to true data 108T being binary "1"). In this example, true data 108T being binary "0" means that true data node 110T is at ground voltage (V SS)(e.g., 0 volts). The transistor 114B in the true comparison circuit turns on when the comparison complement data 112C is binary "1" (voltage V DD ). Thus, there is a mismatch between the true data 108T and the comparison true data 112T. Therefore, when both the true data 108T and the comparison complement data 112C are binary "1", both transistors 114A and 114B turn on and the match line 106 is discharged to the ground voltage V SS , indicating a mismatch. The match line 106 is a wiring or conductive element coupled to the transistor 114A and the transistor 116A.

[0014] Similarly, the transistor 116A in the complement comparison circuit 104C is coupled to the complement data node 110C and turns on when the complement data 108C is binary "1". The transistor 116B in the complement comparison circuit turns on when the comparison true data 112T is binary "1". Thus, there is a mismatch between the true data 108T and the comparison true data 112T. Therefore, when both the complement data 108C and the comparison true data 112T are binary "1", both transistors 116A and 116B turn on and the match line 106 is discharged to the ground voltage V SS . Thus, the match line 106 in the discharged state (e.g., 0 volts) indicates a mismatch between the true data 108T and the comparison true data 112T regardless of the polarity of the true data 108T. In a CAM array (not shown), the match line 106 can be shared among a plurality of comparison memory cell circuits 100 that store bits of binary tags. The match line 106 remains charged to indicate that all bits of the binary tag stored in the CAM array match the corresponding bits of the comparison tag. The time to discharge the match line 106 depends on the capacitance C 106 of the match line 106 and the current flowing through the true comparison circuit 104T or the complement comparison circuit 104C. The capacitance C 106This is partially determined by the length of the matching line 106 and the number of loads, such as transistors, to which the matching line 106 is coupled or electrically connected.

[0015] Figure 2 is a schematic diagram of a CAM array 200 containing rows 202 of comparison memory cell circuits 204, each corresponding to a comparison memory cell circuit 100 in Figure 1. The CAM array 200 in Figure 2 contains only one set 206, and set 206 contains only row 202, but the CAM array 200 can contain multiple rows 202 within set 206, and / or can contain multiple sets 206, each having at least one of those multiple rows 202. Row 202 contains six comparison memory cell circuits 204, but row 202 may contain more or fewer comparison memory cell circuits 204 depending on the number of bits in the binary tag BT stored in row 202. Details of one of these comparison memory cell circuits 204 are shown for reference. Each comparison memory cell circuit 204 corresponds to a column 208 of the CAM array 200. Thus, any additional row 202 in the CAM array 200 will contain a comparison memory cell circuit 204 within each of these columns 208.

[0016] The comparison memory cell circuit 204 includes a memory cell circuit 210, which may be the 6T SRAM cell circuit 102 in Figure 1 or another type of memory cell circuit. The comparison memory cell circuit 204 includes a true comparison circuit 212T corresponding to the true comparison circuit 104T in Figure 1, and a complement comparison circuit 212C corresponding to the complement comparison circuit 104C. The true comparison circuit 212T and the complement comparison circuit 212C compare the true data 214T stored in the comparison memory cell circuit 204 with the comparison true data 216T, and the complement data 214C stored in the comparison memory cell circuit 204 is compared with the comparison complement data 216C. The true data 214T and the complement data 214C represent one bit of the binary tag BT stored in row 202. The comparison true data 216T and the comparison complement data 216C represent one bit of the comparison tag CT corresponding to the data accessed by the processor. If the comparison tag CT matches one of the binary tags BT stored in the CAM array 200, the data corresponding to that binary tag BT can be accessed within the CAM array 200.

[0017] Each comparison memory cell circuit 204 is coupled to a match line 218. The match line 218 is precharged by a precharge circuit 220 controlled by a match line precharge signal MLP. The match line 218 is discharged (i.e., pulled down) if a mismatch is detected in any of the comparison memory cell circuits 204 in a row 202. The match line 218 and the set clock signal 222 are received by the row match circuit 224. The set clock signal 222 indicates that a row 202 in set 206 (and any other row 202 in set 206) is subject to comparison with the comparison tag CT. When the set clock signal 222 is active, the state of the match line 218 determines whether the hit signal 226 is activated to indicate that the comparison tag CT matches the binary tag BT stored in the row 202. Each of the rows 202 in the CAM array 200 contains one of several row match circuits 224.

[0018] Returning to the comparison memory cell circuit 204, the transistor 228A of the true comparison circuit 212T is coupled to a true data node 230T that stores true data 214T within the memory cell circuit 210. The transistor 228B of the true comparison circuit 212T receives complementary comparison data 216C. When both the true data node 230T and the complementary comparison data 216C are at the power supply voltage V DD and indicate a mismatch, both the transistor 228A and the transistor 228B are turned on, and the true comparison circuit 212T discharges the match line 218. Alternatively, when both the complementary data node 230C of the memory cell circuit 210 and the comparison true data 216T are at the power supply voltage V DD , the complementary comparison circuit 212C discharges the match line 218.

[0019] The column comparison circuit 232 receives a comparison true bit 234T and a complementary comparison bit 234C that are the true and complementary values of the corresponding bits of the comparison tag CT. The column comparison circuit 232 generates comparison true data 216T and complementary comparison data 216C based on the comparison true bit 234T and the complementary comparison bit 234C, respectively. The comparison true data 216T and the complementary comparison data 216C are maintained at the ground voltage V SS until activated by the clock signal CLK. When the clock signal CLK is activated, depending on the values of the comparison true bit 234T and the complementary comparison bit 234C, one of the comparison true data 216T and the complementary comparison data 216C is driven to the power supply voltage V DD . If the true data 214T does not match the comparison true data 216T, one of the true comparison circuit 212T and the complementary comparison circuit 212C discharges the match line 218. Similar comparisons are performed in the other comparison memory cell circuits 204 within all the columns 208 in the row 202, and any one of these comparison memory cell circuits 204 can discharge the match line 218.

[0020] The set clock signal 222 is generated by the set address circuit 236 and is activated by the clock signal CLK to address the corresponding set 206. The set address circuit 236 receives the set address signal 238, which is in an active state, to indicate that set 206 is addressed. The set address circuit 236 activates the set clock signal 222 when the set address signal 238 is active and the clock signal CLK is activated.

[0021] Since both the set clock signal 222 and the match line 218 contribute to the hit signal 226, and both are activated in response to the CLK signal, the state of the hit signal 226 is indicated within the timing margin after the activation of the CLK signal. The timing margin depends on the propagation delay of the set address signal 238 before it reaches the set address circuit 236 and before it passes through the set address circuit 236 in response to the clock signal CLK. The timing margin also depends on the time required to discharge the match line 218 through one or more of the comparison memory cell circuits 204 in row 202. The time required to discharge the match line 218 after the activation of the clock signal CLK depends on the propagation delay through the column comparison circuit 232 and the number of loads on the comparison true data 216T and comparison complement data 216C. The number of loads on the comparison true data 216T and comparison complement data 216C depends on the number of rows 202 in the CAM array 200. In addition, the time required to discharge the match line 218 depends on the total capacitance C of the match line 218. 218 It depends on the total capacitance C 218 This depends on the number of comparison memory cell circuits 204 (i.e., bits in the binary tag BT) to which the matching line 218 is joined within row 202.

[0022] It should be obvious that the propagation delay through the set-address circuit 236 is typically much shorter in time than the time required to discharge the match line 218. The circuit paths from the column comparison circuit 232 and the match line 218 are more complex than the paths through the set-address circuit 236. In addition, such propagation timing can be affected by manufacturing process variations, introducing timing uncertainty that increases the timing margin for generating match or mismatch indications on the hit signal 226.

[0023] It is desirable to reduce the propagation timing imbalance between the circuit path from the set clock signal 222 to the hit signal 226 and the circuit path from the comparison true bit 234T and comparison complement bit 234C to the hit signal 226. Reducing such an imbalance makes it possible to reduce the timing margin for the hit signal 226, which in turn shortens the access time of the CAM array 200.

[0024] Figure 3 is a timing diagram 300 showing the signals within the CAM array 200, and includes the timing margin of the set clock signal 222 used to generate a hit signal in response to an indication on the match line 218 of whether the comparison tag CT matches the binary tag BT in the CAM array in Figure 2.

[0025] In this example, the clock signal CLK is a square wave with a 50% duty cycle, but the duty cycle may be longer or shorter. The match line precharge signal MLP, which controls the precharge circuit 220, is low-active and is deactivated at time T1 in response to the activation of the clock signal CLK. At time T2, the true comparison bit 234T and the complement comparison bit 234C are provided to the column comparator circuit 232. In case of mismatch, the match line 218 is discharged within the timing margin between time T3 and time T4. After time T4, the hit signal 226 becomes active. At time T5, the clock signal CLK is activated again, and at time T6, the true comparison bit 234T and the complement comparison bit 234C are again provided to the column comparator circuit 232. In the case of a match, the match line 218 is not discharged, but in the case of a mismatch, the match line 218 can be discharged at any time within the timing margin between time T7 and time T8. Therefore, a charged match line 218 will not reliably show a match until after time T8. Consequently, it is desirable to reduce the timing margin to shorten the access time of the CAM array 200 in Figure 2, because shortening the time it takes for the processor to access the CAM array 200 allows for an increase in the processor speed for higher performance of the electronic device or application.

[0026] Figure 4 is a schematic diagram of a CAM array 400, similar to the CAM array 200 in Figure 2. In one example of a technique to reduce timing margins, the CAM array 400 includes a programmable delay PD in the clock signal CLK to adjust the timing of the set clock signal 222 so that it is better synchronized with the discharge time of the matching line 218. The programmable delay PD can delay the set clock signal 222 by adding a delay to the clock signal CLK to compensate for manufacturing process variations. Using a programmable delay PD requires a calibration step in each integrated circuit in which the CAM array 400 is manufactured. A CAM array is desirable in which the circuit path from the set address signal 238 to the hit signal 226 and the circuit path from the compare true bit 234T (or compare complement bit 234C) to the hit signal 226 are more closely synchronized (e.g., have a smaller timing margin) without a calibration step.

[0027] Figure 5 is a schematic diagram showing an exemplary CAM array 500 including a decode sequence 502 corresponding to each set 504. The CAM array 500 in Figure 5 includes only one set 504 and therefore only one decode sequence 502, but may include multiple sets 504. The decode sequence 502 receives a set address signal 506 and generates a set match signal 508 at each row 510 of each set 504 so that a set match signal 508 and a match indication on the row match line 512 are generated within a reduced timing margin. Figure 5 shows the decode sequence 502 corresponding to one row 510 in a set 504. Before explaining how the decode sequence 502 reduces the timing margin, we first provide a detailed description of the comparison memory cell circuit 514.

[0028] The CAM array 500 corresponds functionally to the CAM array 200 in Figure 2. Row 510 includes a plurality of comparison memory cell circuits 514, corresponding to the comparison memory cell circuit 204 in row 202 in Figure 2. The CAM array 500 may also include additional sets 504, each containing one or more rows 510. Each comparison memory cell circuit 514 includes a true comparison circuit 516T and a complement comparison circuit 516C that discharge the row matching line 512 in response to a mismatch between the stored true data 518T stored in the comparison memory cell circuit 514 and the comparison true data 520T provided to the CAM array 500. The complement comparison circuit 516C is coupled to the row matching line 512 and discharges the row matching line 512 in response to a mismatch between the stored complement data 518C stored in the comparison memory cell circuit 514 and the comparison complement data 520C provided to the CAM array 500.

[0029] The CAM array 500 receives comparison true data 520T and comparison complement data 520C on the true comparison bit line 521T and the complement comparison bit line 521C, respectively. The true comparison circuit 516T in the comparison memory cell circuit 514 is coupled to the row matching line 512 of the row 510 containing the comparison memory cell circuit 514, and the row matching line 512 is connected to, for example, a ground voltage V SS It is coupled to a fixed voltage such as V. The true comparison circuit 516T is controlled by the stored true data 518T and the comparison complement data 520C on the complement comparison bit line 521T. The row match line 512 is a wire, metal trace, or other conductive element coupled to the true comparison circuit 516T and the complement comparison circuit 516C. The true comparison circuit 516T connects the row match line 512 to the ground voltage V to indicate that the comparison true data 520T received on the true comparison bit line 521T does not match the stored true data 518T stored in the comparison memory cell circuit 514 (for example, it is of the opposite binary polarity). SS The time required to discharge the row matching line 512 is the capacitance C of the row matching line 512. 512 This depends on the current capacity of the true comparator circuit 516T or the complement comparator circuit 516C. 512This is partially determined by the length of the row matching line 512 and the number of loads, such as transistors, to which the row matching line 512 is coupled or electrically connected.

[0030] The stored true data 518T is one bit of the binary tag BT stored in row 510. The comparison true data 520T is a bit of the comparison tag CT provided for comparison with the binary tag BT stored in the CAM array 500. In other words, each binary tag BT is stored in one of the multiple comparison memory cell circuits 514 in row 510. The number of bits in the binary tag BT may correspond to the number of columns 522 in the comparison memory cell circuit 514 of the CAM array 500. The true comparison bit line 521T receives the comparison true data 520T for its column 522, and the complement comparison bit line 521C receives the complement comparison complement data 520C for the comparison true data 520T.

[0031] The comparison of the comparison tag CT with the binary tag BT in row 510, and the generation of an indication that the comparison tag CT matches the binary tag BT, are performed by a dynamic comparator circuit 524. The dynamic comparator circuit 524 includes a column comparison circuit 526 that, for each column 522, generates a comparison true data 520T on the true comparison bit line 521T and a comparison complement data 520C on the complement comparison bit line 521C for the comparison memory cell circuit 514 in each row 510. The comparison true data 520T and the comparison complement data 520C are generated in response to the activation of the clock signal CLK, based on the comparison true bit 528T and the comparison complement bit 528C, respectively. The comparison true bit 528T and the comparison complement bit 528C indicate the bits of the comparison tag CT.

[0032] As described above, the CAM array 500 includes one decode sequence 502 for each set 504. The dynamic comparator circuit 524 includes a set clock circuit 530 that generates a set clock signal 532 for each decode sequence 502 to address the corresponding set 504 (i.e., the set 504 corresponding to that decode sequence 502). The set clock signal 532 is generated in response to a clock signal CLK and based on a set address signal 506. The set clock signal 532 controls matching in the set 504. Specifically, the set clock signal 532 provided to each row 510 of the set 504 is used to generate a set match signal 508. The dynamic comparator circuit 524 includes a row match circuit 534 that receives the set match signal 508 and the row match line 512. The row matching circuit 534 generates a row matching signal 536 for each row 510 in response to a set matching signal 508 within row 510, indicating that the comparison tag CT matches the binary tag BT stored within row 510. The row matching signal 536 corresponds to the hit signal 226 in Figure 2.

[0033] The row match signal 536 is generated based on the row match line 512 and the set match signal 508. Both the match indication on the row match line 512 and the activation of the set match signal 508 are triggered by the clock signal CLK. The difference in the delays of each of these signals following the activation of the clock signal CLK determines the timing margin. Therefore, these delays are described individually below to explain the reduction in the timing margin in the row match signal 536. The delay from the activation of the clock signal CLK to the indication of a match on the row match line 512 depends on several factors.

[0034] With respect to the first factor, the comparison complement data 520C is generated by the column comparator circuit 526 based on the comparison complement bit 528C in response to the clock signal CLK. The comparison complement data 520C and the stored true data 518T are coupled to the true comparator circuit 516T in each row 510. The true comparator circuit 516T includes a stored data transistor 537T1 controlled by the stored true data 518T and a comparator data transistor 537T2 controlled by the comparison complement data 520C. Both the stored true data 518T and the comparison complement data 520C are at the same voltage (e.g., power supply voltage V DD If both are binary “1”, this indicates a mismatch, and both the stored data transistor 537T1 and the comparison data transistor 537T2 are turned on and the row matching line 512 is discharged. The complement comparator circuit 516C also includes a stored data transistor 537C1 controlled by the stored complement data 518C and a comparison data transistor 537C2 controlled by the comparison true data 520T. If both the stored complement data 518C and the comparison true data 520T are “1”, indicating a mismatch, the complement comparator circuit 516C is turned on and the row matching line 512 is discharged.

[0035] Regarding the second factor, the propagation time of the comparison true data 520T is partially determined by the number of rows 510 in the CAM array 500 and the wiring length, which correspond to the number of loads on the wiring. The comparison true data 520T of each column 522 of the comparison memory cell circuit 514 is coupled to the true comparison circuit 516T in each row 510. The comparison complement data 520C has the same number of loads as the comparison true data 520T.

[0036] Regarding the third factor, the time required to discharge the row matching line 512 to indicate mismatch depends on the capacitance C512, which in turn depends on the length and the number of loads on the row matching line 512, both of which depend on the number of comparison memory cell circuits 514 in row 510 (i.e., the number of columns 522 in row 510). The discharge time also depends on the number of bits of the binary tag BT stored in row 510 that do not match the corresponding bits of the comparison tag CT. The number of mismatched bits determines the number of true comparator circuits 516T and complement comparator circuits 516C that discharge the row matching line 512 in parallel. The time required to discharge the row matching line 512 decreases with increasing number of mismatched bits because more true comparator circuits 516T or complement comparator circuits 516C are turned on to discharge the row matching line 512 in parallel.

[0037] The decoded sequence 502 synchronizes and improves the set match signal 508 with respect to the match indication on the row match line 512. The three factors mentioned above regarding the delay of the row match line 512 are now compared with the corresponding factors for the set match signal 508.

[0038] Firstly, the set clock signal 532 is generated by the set clock circuit 530 based on the set address signal 506 in response to the activation of the clock signal CLK. The decode sequence 502 includes a pull-down circuit 538 corresponding to each row 510 of the CAM array 500. The set clock signal 532 controls the first transistor 540 of the pull-down circuit 538 to turn on or turn off (e.g., conduct or deconduct) depending on the state of the set clock signal 532. The pull-down circuit 538 is controlled by a constant voltage source (e.g., power supply voltage V DD or ground voltage V SS It includes a second transistor 542 controlled by ), and therefore the second transistor 542 is either always on or always off.

[0039] Specifically, in row 510 of set 504 corresponding to decode sequence 502, the second transistor 542 remains turned on (i.e., conduction) under the power supply voltage V DD It is coupled to. In row 510 of set 504 which does not correspond to decode sequence 502, the second transistor 542 is connected to the ground voltage V SS This is coupled to the second transistor 542, leaving it turned off (i.e., not conducting). Thus, the pull-down circuit 538 in row 510 of set 504 corresponding to decode sequence 502 is controlled by the set clock signal 532. The pull-down circuits 538 in row 510 of other sets 504 that do not correspond to decode sequence 502 are always off, regardless of the state of the set clock signal 532 coupled to the first transistor 540.

[0040] Secondly, the propagation time of the set clock signal 532 is partially determined by the supply of the set clock signal 532 to the load in each of the rows 510 (i.e., the first transistor 540). When the set clock signal 532 for set 504 is activated, the set match line 544 of each row 510 in set 504 is discharged. The set match signal 508 is generated on the set match line 544.

[0041] Thirdly, the time required to discharge the set match line 544 and gate the row match line 512 of the same row 510 depends on the number of decode columns 502, because even though the pull-down circuit 538 in only one decode column 502 actually discharges the set match line, the set match line 544 is coupled to the pull-down circuit 538 in each decode column, increasing the number of loads on the set match line 544. Comparing the set match line 544 to the row match line 512, the number of loads on the set match line 544 may be less than the number of columns 522 to which the row match line 512 is coupled, but this difference may be offset by the fact that the set match line 544 is longer in length than the row match line 512, which increases the capacitance of the set match line 544.

[0042] The set match line 544 extends along row 510 from row match circuit 534 to the decode column 502 located at the opposite end of the CAM array 500. To further increase the delay of the set match line 532, a delay circuit 546 may be included within row match circuit 534. In another embodiment, row match line 512 is coupled to precharge circuit 548 and set match line 544 is coupled to precharge circuit 550.

[0043] As shown above, the factors causing delays in the match indications on row match line 512 and set match line 544 become very similar with the addition of the decode column 502. Due to the similarity between the respective circuits, manufacturing and process variations tend to affect both delays to a similar degree. Consequently, the difference between the respective delays is reduced, which decreases the timing margin of the row match signal 536.

[0044] The decode sequence 502 shown in Figure 5 is implemented within a non-comparison memory cell circuit 552 corresponding to row 510. In a CAM array 500 containing multiple rows 510, there is one decode sequence 502 corresponding to each row 510, and each contains multiple non-comparison memory cell circuits 552. In a CAM array 500 containing multiple sets 504, each set 504 contains a decode sequence 502, each such decode sequence 502 contains a non-comparison memory cell circuit 552 corresponding to each row 510. Each decode sequence 502 contains a set clock circuit 530.

[0045] The non-comparative memory cell circuit 552 is capable of storing stored data (e.g., 1 bit) that can be read by the read bit circuit 554 in response to the read word line RWL. Typically, information such as process ID and / or parity bits is stored in the non-comparative memory cell circuit 552 because it is not subject to comparison. The non-comparative memory cell circuit 552 does not include the true comparator circuit 516T and complement comparator circuit 516C found in the comparator memory cell circuit 516. Thus, the decode column 502 can actually be implemented within the non-comparative memory cell circuit 552 of the CAM array 500. The decode column 502 can be incorporated into an existing column of the non-comparative memory cell circuit 552 by adding a pull-down circuit 538, a set clock signal 532, and a set match line 544, as described with reference to Figures 6 and 7. Thus, by implementing the decode column 502 within the CAM array 500, the timing margin of the row match signal 536 can be reduced without increasing the size (i.e., area).

[0046] The first transistor 540 and the second transistor 542 in each of the pull-down circuits 538 may be, for example, metal-oxide-semiconductor (MOS) field-effect transistors (FETs) (MOSFETs). The set clock signal 532 is coupled to the gate terminal of the first transistor 540 to control the conductivity of the pull-down circuit 538 through time. The set clock circuit 530 may take the logical AND of the set address signal 506 and the clock signal CLK.

[0047] Figure 6 is a schematic diagram showing details of a non-comparison memory cell circuit 600 in an example including a 6T SRAM cell circuit 602. The 6T SRAM cell circuit 602 includes cross-coupled inverters 604T and 604C that provide a true memory node 606T and a complement memory node 606C. The true memory node 606T and the complement memory node 606C are written via a pass gate 608. In Figure 6, the complement memory node 606C is read via a read bit circuit 610, such as the read bit circuit 554 shown in Figure 5. Further details of the 6T SRAM memory cell circuit 602 are outside the scope of this disclosure and are not presented here. When the comparison memory cell circuit 514 is compared with the non-comparison memory cell circuit 600, the read bit circuit 610 occupies the area of ​​the non-comparison memory cell circuit 600 that would be occupied by the complement comparison circuit 516C in the comparison memory cell circuit 514. The non-comparison memory cell circuit 600 does not include any other circuit coupled to the true memory node 606T, while the comparison memory cell circuit 514 has the true comparison circuit 516T located there.

[0048] Figure 7 is a schematic diagram of a non-comparative memory cell circuit 700, which includes the non-comparative memory cell circuit 600 of Figure 6 and the pull-down circuit 538 of Figure 5. In this regard, implementing the decode sequence 502 shown in Figure 5 involves simply adding the pull-down circuit 538 to the non-comparative memory cell circuit 600 without increasing the area, for a CAM array with a reduced timing margin.

[0049] Figure 8 shows an example of a decode sequence 800 that includes a non-comparison memory cell circuit 802, which corresponds to a non-comparison memory cell circuit 700 with additional pull-down circuits 804A and 804B coupled to the set-match line 806. The set-match line 806 corresponds to the set-match line 544 in Figure 5. The pull-down circuits 804A and 804B load the set-match line 806 to match the load of the row-match line 512 in Figure 5. These additional loads provide a means to fine-tune the increase in capacitance of the set-match line 806, so that the propagation delay of the set-match line 806 better matches the propagation delay of the row-match line 512 and further reduces the timing margin of the row-match signal (not shown).

[0050] Figure 9 is a schematic diagram showing a CAM array 900 including sets 902A and 902B, each of which includes two rows 904. Although not shown in Figure 9, each row 904 includes multiple comparison memory cell circuits, such as the comparison memory cell circuit 514 in Figure 5, to store bits of the binary tag BT. The CAM array 900 includes a decode sequence 906A corresponding to set 902A and a decode sequence 906B corresponding to set 902B. A set clock circuit (not shown) generates a set clock signal 908A for set 902A and a set clock signal 908B for set 902B. A pull-down circuit 910 corresponding to each row 904 in decode sequences 906A and 906B receives set match signals 908A and 908B, respectively. The pull-down circuit 910 may be included in a non-comparison memory cell circuit (not shown), such as the non-comparison memory cell circuit 552 in Figure 5. Alternatively, the decode sequences 906A and 906B may include only the pull-down circuit 910 within the CAM array 900, separate from the comparison memory cell circuit and non-comparison memory cell circuit, which are not shown.

[0051] The first transistor 912 of each pull-down circuit 910 in decode sequence 906A receives a set clock signal 908A indicating that set 902A is being addressed. The first transistor 912 of each pull-down circuit 910 in decode sequence 906B receives a set clock signal 908B indicating that set 902B is being addressed. The second transistor 916 in each of the pull-down circuits 910 is coupled to a fixed voltage source. In row 904 of set 902A, the second transistor 916 in decode sequence 906A is coupled to a power supply voltage V such that the pull-down circuits 910 in row 904 of set 902A are controlled by the set clock signal 908A. DD It is coupled to the set clock signal 908B, so that the pull-down circuit 910 in the set clock signal 904 of set 902B is controlled by the power supply voltage V DD It will be joined to

[0052] However, in row 904 of set 902A, the second transistor 916 in decode column 906B is such that the pull-down circuit 910 in row 904 of set 902A is always off, and the ground voltage V SS In row 904 of set 902B, the second transistor 916 in decode column 906A also keeps the pull-down circuit 910 in row 904 of set 902B in decode column 906A always off, so as to the ground voltage V SSThey are coupled together. That is, in decode sequence 906A, each pull-down circuit 910 corresponding to each row 904 in set 902A activates the set match line 918A or 920A in row 904 in response to receiving the set clock signal 908A for the corresponding set 902A. In decode sequence 906B, each pull-down circuit 910 corresponding to row 904 in set 902B activates the set match signal 918B or 920B corresponding to row 904 in response to receiving the set clock signal 908B for the corresponding set 902B. In decode sequence 906A, each pull-down circuit 910 corresponding to row 904 in set 902B does not activate the set match signal 918A or 918B, and in decode sequence 906B, the pull-down circuit 910 in each row 904 in set 902A does not activate the set match signal 918B or 920B.

[0053] Even if the set clock signals 908A and 908B do not control a specific pull-down circuit 910, the first transistor 912 to which they are coupled provides a load that contributes to the capacitance of the set clock signals 908A and 908B, better replicating the load of the comparative true data 520T and comparative complement data 520C in Figure 5, and helping to reduce the timing margin of the set match signal 508 and row match line 512 in Figure 5.

[0054] Figure 10 is a block diagram of an exemplary processor-based system 1000, which includes a processor 1002 (e.g., a microprocessor) including an instruction processing circuit 1004. The processor-based system 1000 can be one or more circuits included in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or something similar. More specifically, the processor 1002 may be an EDGE instruction set microprocessor, or another processor that implements an instruction set that supports explicit consumer naming to convey generated values ​​obtained by the execution of producer instructions. The processor 1002 is configured to execute instruction processing logic for performing the operations and steps described herein. In this example, the processor 1002 includes an instruction cache 1006 for temporary, high-speed access memory storage of instructions accessible by the instruction processing circuit 1004. Instructions fetched or prefetched from memory, for example, from main memory 1008 on the system bus 1010, are stored in the instruction cache 1006. The data may be stored in a cache memory 1012 coupled to the system bus 1010 for low-latency access by the processor 1002. The instruction processing circuit 1004 is configured to process the instructions fetched into the instruction cache 1006 and process those instructions for execution.

[0055] The processor 1002 and the main memory 1008 are coupled to a system bus 1010 and can be coupled to peripheral devices included in the processor-based system 1000. As is well known, the processor 1002 communicates with these other devices by exchanging address information, control information, and data information over the system bus 1010. For example, the processor 1002 can communicate bus transaction requests to a memory controller 1014 in the main memory 1008, which is an example of a slave device. Although not shown in Figure 10, there may be multiple system buses 1010, each comprising a different fabric. In this example, the memory controller 1014 is configured to provide memory access requests to a memory array 1016 in the main memory 1008. The memory array 1016 consists of an array of storage bit cells for storing data. The main memory 1008 may, in non-limiting examples, be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM)).

[0056] Other devices can be connected to the system bus 1010. As shown in Figure 10, these devices may include, for example, main memory 1008, one or more input devices 1018, one or more output devices 1020, a modem 1022, and one or more display controllers 1024. The (one or more) input devices 1018 may include any type of input device, including but not limited to input keys, switches, and voice processors. The (one or more) output devices 1020 may include any type of output device, including but not limited to audio, video, and other visual indicators. The modem 1022 may be any device configured to enable data exchange with the network 1026. The network 1026 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. The modem 1022 may be configured to support any desired type of communication protocol. The processor 1002 may also be configured to access one or more display controllers 1024 on the system bus 1010 to control information sent to one or more displays 1028. The one or more displays 1028 may include any type of display, including, but is not limited to, cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, and the like.

[0057] The processor-based system 1000 in Figure 10 may include a set of instructions 1030 executed by the processor 1002 for any desired application according to the instructions. The instructions 1030 may be stored in main memory 1008, the processor 1002, and / or the instruction cache 1006 as an example of a non-temporary computer-readable medium 1032. The instructions 1030 may also reside entirely or at least partially in main memory 1008 and / or the processor 1002 during their execution. The instructions 1030 may further be transmitted or received over network 1026 via modem 1022, such that network 1026 includes computer-readable medium 1032.

[0058] Although the computer-readable medium 1036 is shown as a single medium in the exemplary embodiment, the term “computer-readable medium” should be interpreted to include a single medium or multiple mediums (e.g., a centralized or distributed database, and / or an associated cache and server) that store one or more sets of instructions. The term “computer-readable medium” should also be interpreted to include any medium capable of storing, encoding, or transporting instruction sets for execution by a processing device, causing the processing device to execute one or more of the methods of the embodiments disclosed herein. The term “computer-readable medium” should therefore be interpreted to include, but are not limited to, solid-state memory, optical media, and magnetic media.

[0059] Any IC in the processor-based system 1000 may include a CAM array containing a decode sequence corresponding to each set, each of which receives a set address signal and generates a set match signal for each row of the set, such that the set match signal and match indication on the row match line are generated within a reduced timing margin, as shown in Figure 5.

[0060] The embodiments disclosed herein include a variety of steps. The steps of the embodiments disclosed herein may be formed by hardware components, or they may be embodied in machine-executable instructions, which may be used to program a general-purpose processor or a dedicated processor with instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0061] Embodiments disclosed herein may be provided as computer program products or software that include a machine-readable medium (or computer-readable medium) storing instructions, which can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes machine-readable storage media (e.g., ROM, random-access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices), and similar devices.

[0062] Unless otherwise specified, and as is clear from the preceding explanation, throughout this explanation, any use of terms such as “processing,” “computing,” “decision,” and “display” is understood to refer to the operation and processes of a computer system or similar electronic computing device that manipulates and converts data and memory, represented as physical (electronic) quantities in the registers of a computer system, into other data, similarly represented as physical quantities in the memory or registers of the computer system or other such information storage, transmission, or display devices.

[0063] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various systems can be used with programs following the teachings herein, or it may be advantageous to construct more specialized devices to perform the required method steps. From the above description, the structures required for these diverse systems will become clear. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0064] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, as instructions stored in memory or other computer-readable media and executed by a processor or other processing device, or as a combination of both. The components of the distributed antenna system described herein may, for example, be used in some circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and may be configured to store any desired type of information. To clearly demonstrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their function. How such functions are implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art may implement the described functions in various ways for specific applications, but such implementation decisions should not be construed as causing a departure from the scope of these embodiments.

[0065] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or run on a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A controller may also be a processor. While a processor may be a microprocessor, it may instead be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of multiple computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0066] The embodiments disclosed herein can be embodied in hardware and in instructions stored in hardware, and may reside, for example, in RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or other forms of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0067] Furthermore, the operational steps described in any of the exemplary embodiments herein are provided for the purpose of providing examples and explanations. The described operations may be performed in many different sequences other than those illustrated. Also, an operation described in one operational step may actually be performed in several different steps. Moreover, one or more operational steps described in the exemplary embodiments may be combined. As those skilled in the art will also understand, information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips which may be mentioned throughout this description may be represented by voltage, current, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0068] Unless otherwise specified, none of the methods described herein are intended to be construed as requiring the steps to be performed in a specific order. Therefore, if a method claim does not actually describe the order in which the steps should be followed, or if it is not otherwise specifically stated in the claim or description that the steps are limited to a particular order, no particular order is intended to be presumed.

[0069] It will be understood by those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, subcombinations, and variations of disclosed embodiments incorporating the spirit and content of the invention will be conceivable to those skilled in the art, the invention should be construed to include all of the appended claims and their equivalents.

Claims

1. An array of comparison memory cell circuits, At least one set, each set having at least one row of a plurality of rows of a comparison memory cell circuit, wherein each row of the plurality of rows is configured to store a binary tag, The plurality of columns of the comparison memory cell circuit, each of which has a comparison memory cell circuit within each row of the plurality of rows, At least one decoded sequence, each of which corresponds to one of the at least one sets, and which at least one decoded sequence The set clock signal for the corresponding set is received, A set match signal is generated on the set match line within each row of the corresponding set. A decode sequence configured as follows: It is a dynamic comparator circuit, A set clock circuit configured to generate the set clock signal for addressing the corresponding set for each of the at least one decode sequence, A column comparison circuit configured to generate true comparison data indicating the true comparison bit of the comparison tag for each of the aforementioned multiple columns, and A row matching circuit is configured to generate a row matching signal for each of the plurality of rows, in response to the set matching signal generated in that row, indicating that the comparison tag matches the binary tag stored in that row. A dynamic comparator circuit having, An array of comparison memory cell circuits having the following characteristics.

2. The array of comparison memory cell circuits according to claim 1, wherein each of the plurality of rows further has a row matching line, and the row matching circuit is further configured to generate the row matching signal for a row in response to the row matching line indicating that the comparison tag matches the binary tag stored in that row.

3. The array of comparison memory cells according to claim 2, wherein each comparison memory cell circuit is configured to store stored true data corresponding to the comparison true bit of the binary tag, and stored complement data which is a complement of the stored true data.

4. Each comparison memory circuit further, The row matching line of the row having the comparison memory cell circuit, A true comparison bit line configured to receive the true comparison data for a column having the comparison memory cell circuit, It has a true comparison circuit coupled to it, The true comparison circuit is configured to couple the row matching line to a first voltage in order to indicate that the comparison true data received on the true comparison bit line does not match the stored true data stored in the comparison memory cell circuit. The array of comparison memory cell circuits according to claim 3.

5. The column comparison circuit is further configured to generate comparison complement data for each of the plurality of columns, which is a complement to the comparison true data of the binary tag and indicates the comparison complement bit of the comparison tag. Each comparison memory cell circuit further has a complement comparison circuit configured to couple the row matching line of the row having the comparison memory cell circuit to the first voltage, in order to indicate that the comparison complement data for the column having the comparison memory cell circuit does not match the stored complement data stored in the comparison memory cell circuit. The array of comparison memory circuits according to claim 4.

6. The array of comparison memory cells according to claim 5, wherein the true comparison circuit further comprises a first transistor controlled by the stored true data stored in the comparison memory cell circuit and a second transistor controlled by the comparison complement data for the column having the comparison memory cell circuit.

7. The array of comparison memory cells according to claim 5, wherein the complement comparison circuit further comprises a third transistor controlled by the stored complement data stored in the comparison memory cell circuit, and a fourth transistor controlled by the comparison true data for the column having the comparison memory cell circuit.

8. The array of comparison memory cells according to claim 1, wherein the set clock circuit is further configured to generate the set clock signal for each of the at least one decode sequence in response to a clock signal and a set address signal corresponding to the set.

9. The array of comparison memory cells according to claim 8, wherein the column comparison circuit is further configured to generate the comparison true data for each of the plurality of columns in response to the clock signal, based on the comparison true bit of the binary tag.

10. Each of the at least one decode sequence has a pull-down circuit within each of the plurality of rows of the comparison memory cell circuit, and each pull-down circuit is coupled to the set match line in the corresponding row. In the decode sequence corresponding to one of the sets mentioned above, Each pull-down circuit corresponding to a row in the set is configured to activate the set matching line in the row in response to receiving the set clock signal for the corresponding set. Each pull-down circuit corresponding to a row in another set of the at least one set is configured not to activate the set matching line in that row. An array of comparison memory cell circuits according to claim 1.

11. Each decode sequence is configured to receive the set clock signal for the corresponding set generated by the set clock circuit, Each pull-down circuit has a first transistor controlled by the set clock signal and a second transistor coupled to a fixed voltage source. An array of comparison memory cell circuits according to claim 10.

12. In each row within the corresponding set, the voltage source is the power supply voltage V ＤＤ It has, In each row that is not within the corresponding set, the voltage source is the ground voltage V ＳＳ Having, The array of comparison memory cell circuits according to claim 11.

13. Each decoded sequence further has a non-comparison memory cell circuit coupled to the read bit line within each row, and the non-comparison memory cell circuit is Memory cell circuit, A read transistor circuit configured to read stored data stored in the non-comparison memory cell circuit in response to the activation of a read word signal, An array of comparison memory cell circuits according to claim 11, having the above characteristics.

14. The array of comparison memory cells according to claim 3, wherein each of the comparison memory cell circuits has a static random access memory (SRAM) cell circuit.

15. An integrated circuit having an array of comparison memory cell circuits, wherein the array of comparison memory cell circuits is At least one set, each set having at least one row of a plurality of rows of a comparison memory cell circuit, wherein each row of the plurality of rows is configured to store a binary tag, The plurality of columns of the comparison memory cell circuit, each of which has a comparison memory cell circuit within each row of the plurality of rows, At least one decoded sequence, each of which corresponds to one of the at least one sets, and which at least one decoded sequence The set clock signal for the corresponding set is received, A set match signal is generated on the set match line within each row of the corresponding set. A decode sequence configured as follows: It is a dynamic comparator circuit, A set clock circuit configured to generate the set clock signal for addressing the corresponding set for each of the at least one decode sequence, A column comparison circuit configured to generate true comparison data indicating the true comparison bit of the comparison tag for each of the aforementioned multiple columns, and A row matching circuit is configured to generate a row matching signal for each of the plurality of rows, in response to the set matching signal generated in that row, indicating that the comparison tag matches the binary tag stored in that row. A dynamic comparator circuit having, An integrated circuit that utilizes a special function.

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