Power converter

Abstract

The inverter (10) includes a multilevel circuit having multiple switching elements (Q1 to Q4) and converts the first to third DC voltages supplied from the DC positive bus (L1), DC neutral bus (L2), and DC negative bus (L3) into AC voltages which are supplied to the load. The control device generates a reference AC voltage by superimposing the third harmonic of the voltage command value onto a sinusoidal voltage command value. The control device compares a carrier signal having peak-to-peak values ​​corresponding to the DC voltage between the DC positive bus and the DC negative bus with the reference AC voltage to generate gate signals for turning the multiple switching elements (Q1 to Q4) on and off. The control device detects the load factor of the power converter from the output current detected by the current detector (11). In the first case, when the load factor is greater than a predetermined threshold, the control device increases the amount of third harmonic superimposition on the voltage command value compared to the second case, when the load factor is less than or equal to the threshold.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device.

Background Art

[0002] Japanese Patent Application Laid-Open No. 3-82396 (Patent Document 1) discloses a pulse width modulation (PWM) type inverter device. This inverter device includes a DC power supply, an inverter composed of switching elements and diodes connected in antiparallel, a reference voltage generator that outputs a reference voltage waveform serving as a reference for the output frequency and output voltage, a carrier generator that outputs a carrier wave, a PWM circuit that compares the reference voltage waveform and the carrier wave and generates a gate signal for the switching signal, a drive circuit that drives the switching elements in response to the gate signal of the PWM circuit, and an output frequency setter that sets the carrier frequency.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is an inverter (three-level inverter) that includes a multi-level circuit for converting a positive DC voltage, a neutral point voltage, and a negative DC voltage into an AC voltage, converts DC power into AC power, and supplies it to a load. The multi-level circuit includes first to fourth switching elements and first to fourth diodes connected in antiparallel to the first to fourth switching elements, respectively.

[0005] In such an inverter, when the first to fourth switching elements are driven on and off according to the gate signal of the PWM circuit, the power loss of the first and second switching elements becomes greater than that of the third and fourth switching elements due to factors such as the voltage applied to the first and second switching elements being greater than the voltage applied to the third and fourth switching elements. As a result, heat tends to concentrate in the first and second switching elements. This tendency becomes more pronounced during overload operation of the inverter.

[0006] To prevent damage to the first and second switching elements due to overheating, it is necessary to select switching elements that can withstand heat concentration and to design a cooling structure that suppresses heat concentration. On the other hand, if the inverter is operated within a range below the rated load during normal operation and the time during which the inverter is operating under overload is short, the above-mentioned measures against heat concentration may be an over-design for the operation of the power converter. As a result, there is a concern that the power converter will be unnecessarily made more expensive and larger.

[0007] This disclosure has been made to solve the aforementioned problem, and the object of this disclosure is to disperse the heat concentration on some switching elements during overload operation in a power converter equipped with an inverter having a multilevel circuit. [Means for solving the problem]

[0008] A power converter according to one aspect of the present disclosure comprises a variable DC power supply, a first capacitor, a second capacitor, an inverter, a current detector for detecting the output current of the inverter, and a control device. The variable DC power supply is connected between a DC positive bus and a DC negative bus. The first capacitor is connected between the DC positive bus and the DC neutral bus. The second capacitor is connected between the DC neutral bus and the DC negative bus. The inverter includes a multilevel circuit having a plurality of switching elements and converts first to third DC voltages supplied from the DC positive bus, DC neutral bus and DC negative bus into AC voltages which are supplied to the load. The control device controls the on / off drive of the plurality of switching elements using pulse width modulation. The control device generates a reference AC voltage by superimposing the third harmonic of a voltage command value onto a sinusoidal voltage command value. The control device is configured to generate gate signals for turning multiple switching elements on and off by comparing a carrier signal having peak-to-peak values ​​corresponding to the DC voltage between the DC positive busbar and the DC negative busbar with a reference AC voltage. The control device detects the load factor of the power converter from the output current detected by the current detector. The control device detects if the load factor is greater than a predetermined threshold. 2 In this case, the load factor is below the threshold. 1 Compared to the previous case, this increases the amount of third-harmonic superimposition relative to the voltage command value. [Effects of the Invention]

[0009] According to this disclosure, in a power converter equipped with an inverter having a multilevel circuit, heat concentration on some switching elements during overload operation can be dispersed. [Brief explanation of the drawing]

[0010] [Figure 1] This is a circuit block diagram showing the configuration of an uninterruptible power supply to which a power converter according to this embodiment is applied. [Figure 2] This is a block diagram showing an example of the hardware configuration of a control device. [Figure 3] This is a circuit block diagram showing the configuration of the inverter and its surrounding components. [Figure 4] This block diagram shows the configuration of the part of the control device related to inverter control. [Figure 5] This figure shows the waveform of the reference AC voltage. [Figure 6] This is a circuit block diagram showing the configuration of the gate control circuit. [Figure 7] This is a time chart showing the waveforms of a reference AC voltage, a triangular wave signal, and a gate signal. [Figure 8] This is a block diagram showing an example configuration of a third-harmonic generation circuit. [Figure 9] This is a block diagram showing an example configuration of a reference voltage generation circuit. [Figure 10] This block diagram shows the configuration of the parts of the control unit related to the control of the converter and the bidirectional chopper. [Figure 11] This is a time chart showing the waveforms of the reference AC voltage, triangular wave signal, and gate signal in the overload region. [Figure 12] This figure shows the simulation results of power loss occurring in the inverter. [Figure 13] This is a circuit block diagram showing a first modified example of this embodiment. [Figure 14] This is a circuit block diagram showing a second modified example of this embodiment. [Figure 15] This is a circuit block diagram showing a third modification of this embodiment. [Modes for carrying out the invention]

[0011] The embodiments of this disclosure will be described in detail below with reference to the drawings. The same or corresponding parts in the drawings will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0012] FIG. 1 is a circuit block diagram showing the configuration of an uninterruptible power supply device 1 to which a power conversion device according to an embodiment of the present disclosure is applied. The uninterruptible power supply device 1 temporarily converts three-phase AC power from a commercial AC power supply 21 into DC power, and then converts the DC power into three-phase AC power and supplies it to a load 24. In FIG. 1, for simplicity of drawing and description, only the circuit of a portion corresponding to one phase (for example, the U phase) of the three phases (U phase, V phase, W phase) is shown.

[0013] As shown in FIG. 1, the uninterruptible power supply device 1 includes an AC input terminal T1, a bypass input terminal T2, a battery terminal T3, and an AC output terminal T4. The AC input terminal T1 receives commercial-frequency AC power from the commercial AC power supply 21. The bypass input terminal T2 receives commercial-frequency AC power from a bypass AC power supply 22. The bypass AC power supply 22 may be a commercial AC power supply or a generator.

[0014] The battery terminal T3 is connected to a battery 23. The battery 23 stores DC power. The battery 23 corresponds to an example of a “power storage device”. An electric double-layer capacitor or a flywheel may be connected instead of the battery 23. The AC output terminal T4 is connected to the load 24. The load 24 is driven by the AC power supplied from the uninterruptible power supply device 1.

[0015] The uninterruptible power supply device 1 further includes electromagnetic contactors 2, 8, 14, 16, current detectors 3, 11, capacitors 4, 9, 13, reactors 5, 12, a converter 6, a bidirectional chopper 7, an inverter 10, a semiconductor switch 15, an operation unit 17, and a control device 18.

[0016] The electromagnetic contactor 2 and reactor 5 are connected in series between the AC input terminal T1 and the AC node of the converter 6. The electromagnetic contactor 2 is controlled by the control device 18. When AC power is supplied normally from the commercial AC power supply 21 (when the commercial AC power supply 21 is healthy), the electromagnetic contactor 2 is turned on. When AC power is no longer supplied normally from the commercial AC power supply 21 (when the commercial AC power supply 21 fails), the electromagnetic contactor 2 is turned off. The current detector 3 detects the AC input current Ii flowing between the commercial AC power supply 21 and the converter 6 and provides the control device 18 with a signal Iif indicating the detected value.

[0017] The instantaneous value of the AC input voltage Vi appearing at node N1 between the electromagnetic contactor 2 and the reactor 5 is detected by the control device 18. Based on the detected value of the AC input voltage Vi, the control device 18 determines whether or not a power outage has occurred. The control device 18 also controls the converter 6 and other components in synchronization with the AC input voltage Vi.

[0018] Capacitor 4 is connected to node N1. Capacitor 4 and reactor 5 constitute a low-pass filter, allowing AC power at commercial frequency to pass from the commercial AC power supply 21 to the converter 6, while preventing switching frequency signals generated in the converter 6 from passing through to the commercial AC power supply 21.

[0019] The converter 6 is controlled by the control device 18 and, when the commercial AC power supply 21 is functioning properly, converts AC power to DC power and outputs it to the DC line L1. The output voltage of the converter 6 can be controlled to a desired value. The DC line L1 constitutes the "DC positive busbar". The converter 6 corresponds to one embodiment of a "variable DC power supply".

[0020] When the commercial AC power supply 21 is interrupted, the converter 6 is shut down. The capacitor 9 is connected to the DC line L1 and smooths the voltage of the DC line L1. The instantaneous value of the DC voltage VDC appearing on the DC line L1 is detected by the control device 18. When the commercial AC power supply 21 is functioning properly, the control device 18 controls the converter 6 so that the DC voltage VDC on the DC line L1 becomes the reference DC voltage VDC*.

[0021] The DC line L1 is connected to the high-voltage side node of the bidirectional chopper 7, and the low-voltage side node of the bidirectional chopper 7 is connected to the battery terminal T3 via an electromagnetic contactor 8. The electromagnetic contactor 8 is turned on when the uninterruptible power supply 1 is in use and turned off, for example, during maintenance of the uninterruptible power supply 1 and the battery 23. The instantaneous value of the terminal voltage VB of the battery 23 appearing at the battery terminal T3 is detected by the control device 18.

[0022] The bidirectional chopper 7 is controlled by the control device 18 and, when the commercial AC power supply 21 is functioning properly, stores the DC power generated by the converter 6 in the battery 23. In the event of a power outage of the commercial AC power supply 21, the bidirectional chopper 7 supplies the DC power from the battery 23 to the inverter 10 via the DC line L1. The instantaneous value of the terminal voltage VB of the battery 23, which appears at the battery terminal T3, is detected by the control device 18. The bidirectional chopper 7 corresponds to one embodiment of a "variable DC power supply".

[0023] The control device 18 controls the bidirectional chopper 7 so that the battery voltage VB becomes the reference DC voltage VB* when the commercial AC power supply 21 is functioning properly, and controls the bidirectional chopper 7 so that the DC voltage VDC of the DC line L1 becomes the reference DC voltage VDC* when the commercial AC power supply 21 fails. The DC line L1 is connected to the DC node of the inverter 10.

[0024] The inverter 10 is controlled by the control device 18. The inverter 10 converts the DC power supplied from the converter 6 or bidirectional chopper 7 (variable DC power supply) via the DC line L1 into AC power of commercial frequency and outputs it to the output node (AC terminal) 10a.

[0025] In other words, when the commercial AC power supply 21 is functioning properly, the inverter 10 converts the DC power supplied from the converter 6 via the DC line L1 into AC power, and when the commercial AC power supply 21 fails, it converts the DC power supplied from the battery 23 via the bidirectional chopper 7 into AC power. The output voltage of the inverter 10 is controllable to a desired value.

[0026] The output node 10a (AC terminal) of the inverter 10 is connected to the first terminal (node ​​N2) of the electromagnetic contactor 14 via the reactor 12, and the second terminal of the electromagnetic contactor 14 is connected to the AC output terminal T4. The capacitor 13 is connected to node N2. The reactor 12 and capacitor 13 constitute a low-pass filter, allowing the commercial frequency AC power generated by the inverter 10 to pass through the AC output terminal T4, while preventing the switching frequency signals generated by the inverter 10 from passing through the AC output terminal T4.

[0027] The electromagnetic contactor 14 is controlled by the control device 18 and is turned on in inverter power supply mode when AC power generated by the inverter 10 is supplied to the load 24, and turned off in bypass power supply mode when AC power from the bypass AC power supply 22 is supplied to the load 24.

[0028] The instantaneous value of the AC output voltage Vo appearing at node N2 is detected by the control device 18. The current detector 11 detects the current Io flowing between the inverter 10 and the load 24 and provides the control device 18 with a signal Iof indicating the detected value. The output current Io of the inverter 10 corresponds to the "load current". The control device 18 controls the inverter 10 so that the AC output voltage Vo becomes the reference AC voltage Vo*.

[0029] The semiconductor switch 15 includes a pair of thyristors connected in antiparallel to each other and is connected between the bypass input terminal T2 and the AC output terminal T4. The electromagnetic contactor 16 is connected in parallel to the semiconductor switch 15. The semiconductor switch 15 is controlled by the control device 18, is normally off, and instantly turns on in the event of a failure of the inverter 10, supplying AC power from the bypass AC power supply 22 to the load 24. The semiconductor switch 15 turns off after a predetermined time has elapsed since it was turned on.

[0030] The electromagnetic contactor 16 is turned off in inverter power supply mode, which supplies AC power generated by the inverter 10 to the load 24, and turned on in bypass power supply mode, which supplies AC power from the bypass AC power supply 22 to the load 24. The electromagnetic contactor 16 also turns on if the inverter 10 fails and supplies AC power from the bypass AC power supply 22 to the load 24.

[0031] The control unit 17 includes multiple buttons operated by the user of the uninterruptible power supply 1, an image display unit that displays various information, and other components. By operating the control unit 17, the user can turn the power of the uninterruptible power supply 1 on and off, and select one of the following modes: bypass power supply mode, inverter power supply mode, etc.

[0032] The control device 18 controls the entire uninterruptible power supply 1 based on the AC input voltage Vi, AC input current Ii, DC voltage VDC, terminal voltage VB of the battery 23, AC output voltage Vo, AC output current Io, reference DC voltages VDC*, VB*, reference AC voltage Vo*, and signals from the operation unit 17.

[0033] Figure 2 is a block diagram showing an example of the hardware configuration of the control device 18. Typically, the control device 18 can be configured using a microcomputer with a predetermined program pre-stored in it.

[0034] In the example shown in Figure 2, the control unit 18 includes a CPU (Central Processing Unit) 102, a memory 104, and an input / output (I / O) circuit 106. The CPU 102, memory 104, and I / O circuit 106 can exchange data with each other via a bus 108. A program is stored in a portion of the memory 104, and the CPU 102 can execute this program to realize various functions described later. The I / O circuit 106 inputs and outputs signals and data to and from the outside of the control unit 18.

[0035] Alternatively, unlike the example in Figure 2, at least a portion of the control device 18 can be configured using circuits such as FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit). Furthermore, at least a portion of the control device 18 can also be configured using analog circuits.

[0036] Figure 3 is a circuit block diagram showing the configuration of the inverter 10 and its surrounding components as shown in Figure 1. As shown in Figure 3, DC lines L1 to L3 are connected between the converter 6 and the inverter 10. DC line L2 is connected to the neutral point NP and is set to the neutral point voltage (e.g., 0V). DC line L2 constitutes the "DC neutral bus," and DC line L3 constitutes the "DC negative bus."

[0037] Capacitor 9 includes two capacitors 9a and 9b. Capacitor 9a is connected between DC lines L1 and L2. Capacitor 9b is connected between DC lines L2 and L3. Capacitor 9a corresponds to one embodiment of the "first capacitor," and capacitor 9b corresponds to one embodiment of the "second capacitor."

[0038] When the commercial AC power supply 21 is functioning properly, converter 6 converts AC power from the commercial AC power supply 21 into DC power and supplies it to DC lines L1 to L3. At this time, converter 6 charges capacitors 9a and 9b so that the DC voltage VDC between DC lines L1 and L3 becomes the reference DC voltage VDC*, the DC voltage VDCa between DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between DC lines L2 and L3 becomes VDC* / 2. The DC voltage VDC is the sum of the DC voltages VDCa and VDCb (VDC = VDCa + VDCb).

[0039] The voltages of DC lines L1, L2, and L3 are set to a positive DC voltage (+VDC* / 2), a neutral point voltage (0V), and a negative DC voltage (-VDC* / 2), respectively. When the commercial AC power supply 21 is interrupted, the converter 6 stops operating.

[0040] When the commercial AC power supply 21 is functioning properly, the bidirectional chopper 7 stores the DC power generated by the converter 6 in the battery 23. At this time, the bidirectional chopper 7 charges the battery 23 so that the terminal voltage VB of the battery 23 becomes the reference DC voltage VB*.

[0041] The bidirectional chopper 7 supplies DC power from the battery 23 to the inverter 10 in the event of a power outage of the commercial AC power supply 21. At this time, the bidirectional chopper 7 charges capacitors 9a and 9b so that the DC voltage VDC between DC lines L1 and L3 becomes the reference DC voltage VDC*, and the terminal voltages VDCa and VDCb of capacitors 9a and 9b are each VDC* / 2.

[0042] When the commercial AC power supply 21 is functioning properly, the inverter 10 converts the DC power generated by the converter 6 into AC power at the commercial frequency and supplies it to the load 24. When the commercial AC power supply 21 is shut off, the inverter 10 converts the DC power generated by the bidirectional chopper 7 into AC power at the commercial frequency and supplies it to the load 24.

[0043] The inverter 10 consists of a multilevel circuit that generates a commercial frequency AC output voltage Vo based on a positive DC voltage (first DC voltage), a neutral point voltage (second DC voltage), and a negative DC voltage (third DC voltage) supplied from DC lines L1 to L3.

[0044] Specifically, the inverter 10 includes IGBTs (Insulated Gate Bipolar Transistors) Q1 to Q4 and diodes D1 to D4. Each IGBT Q1 to Q4 corresponds to one embodiment of the "first to fourth switching elements". In Figure 3, IGBTs (Insulated Gate Bipolar Transistors) are used as switching elements, but any semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be used.

[0045] Diodes D1 to D4 are connected in antiparallel to IGBTs Q1 to Q4, respectively. Diodes D1 to D4 are provided to allow freewheeling current to flow when the corresponding IGBT is off. If the switching element is a MOSFET, diodes D1 to D4 may be composed of parasitic diodes (body diodes).

[0046] IGBTQ1 (the first switching element) is connected between the DC line L1 (the DC positive busbar) and the output node 10a (the AC terminal). The collector of IGBTQ1 is connected to the DC line L1, and its emitter is connected to the output node 10a.

[0047] The IGBTQ2 (second switching element) is connected between the DC line L2 (DC neutral bus) and the output node 10a. The collector of the IGBTQ2 is connected to the output node 10a, and its emitter is connected to the DC line L3.

[0048] The collectors of IGBTQ3 (third switching element) and IGBTQ4 (fourth switching element) are connected to each other, and their emitters are connected to DC line L2 and output node 10a, respectively. Output node 10a is connected to node N2 via reactor 12.

[0049] In inverter 10, during the first period when the reference AC voltage Vo* is positive, IGBTQ2 and Q4 are set to the off and on states, respectively, and IGBTQ1 and Q3 are turned on alternately. During the second period when the reference AC voltage Vo* is negative, IGBTQ1 and Q3 are set to the off and on states, respectively, and IGBTQ2 and Q4 are turned on alternately.

[0050] During the first period, when IGBTQ1 is turned on, a positive DC voltage is output from DC line L1 to output node 10a via IGBTQ1. When IGBTQ3 is turned on, output node 10a is connected to DC line L2 via diode D4 and IGBTQ3, and DC line L2 is connected to output node 10a via diode D3 and IGBTQ4, so that output node 10a is at its neutral point voltage. Therefore, during the first period, a positive DC voltage and the neutral point voltage are output alternately to output node 10a.

[0051] During the second period, when IGBTQ2 is turned on, output node 10a is connected to DC line L3 via IGBTQ2, and output node 10a is given a negative DC voltage. Also, when IGBTQ4 is turned on, DC line L2 is connected to output node 10a via diode D3 and IGBTQ4, and output node 10a is connected to DC line L2 via diode D4 and IGBTQ3, and output node 10a is given a neutral point voltage. Therefore, during the second period, negative DC voltage and neutral point voltage are alternately output to output node 10a.

[0052] Figure 4 is a block diagram showing the configuration of the part of the control device 18 related to the control of the inverter 10. The function of each block shown in Figure 4 can be realized by at least one of software processing and hardware processing by the control device 18.

[0053] As shown in Figure 4, the control device 18 is configured to control the on / off drive of IGBTQ1 to Q4 (Figure 3) that constitute the multilevel circuit using pulse width modulation (PWM). Specifically, the control device 18 includes a reference voltage generation circuit 31, a voltage detector 32, subtractors 33 and 35, an output voltage control circuit 34, an output current control circuit 36, a load factor detector 37, a third harmonic generation circuit 38, an adder 39, a reference voltage generation circuit 40, and a gate control circuit 41.

[0054] The reference voltage generation circuit 31 generates a reference AC voltage Vr, which is a sine wave signal at commercial frequency. The phase of the reference AC voltage Vr is synchronized with the phase of the AC input voltage Vi of the corresponding phase (e.g., U phase) among the three phases (U phase, V phase, W phase).

[0055] The voltage detector 32 detects the instantaneous value of the AC output voltage Vo at node N2 (Figure 1) and outputs a signal Vof indicating the detected value. The subtractor 33 calculates the deviation ΔVo between the reference AC voltage Vr and the output signal Vof from the voltage detector 32.

[0056] The output voltage control circuit 34 generates a current command value Ior by performing a proportional or proportional-integral operation on the deviation ΔVo. The subtractor 35 calculates the deviation ΔIo between the current command value Ior and the signal Iof from the current detector 11. The output current control circuit 36 ​​generates a voltage command value Vor by performing a proportional or proportional-integral operation on the deviation ΔIo. The voltage command value Vor is a sine wave signal at commercial frequency.

[0057] The load factor detector 37 detects the load factor LF of the uninterruptible power supply 1 based on the signal Iof from the current detector 11 and the rated current of the uninterruptible power supply 1, and outputs a signal φLF indicating the detected value to the third harmonic generation circuit 38 and the reference voltage generation circuit 40. In this specification, the load factor LF represents the ratio of the load current, with the point at which the output current Io (load current) of the inverter 10 becomes the rated current (i.e., rated load) being 100%.

[0058] The third harmonic generation circuit 38 generates a third harmonic 3f·k1 superimposed on the voltage command value Vor. The third harmonic generation circuit 38 sets the superposition amount k1 of the third harmonic relative to the voltage command value Vor based on the load factor LF detected by the load factor detector 37. This superposition amount k1 is the ratio of the amplitude of the third harmonic 3f to the amplitude of the voltage command value Vor. The third harmonic generation circuit 38 generates the third harmonic 3f·k1 by multiplying a sine wave signal 3f with a frequency three times that of the voltage command value Vor (i.e., the commercial frequency) by the superposition amount k1. The third harmonic generation circuit 38 will be explained in more detail later.

[0059] The adder 39 adds the voltage command value Vor from the output current control circuit 36 ​​and the third harmonic 3f·k1 from the third harmonic generation circuit 38 to generate a reference AC voltage Vo*. Figure 5 shows the waveform of the reference AC voltage Vo*.

[0060] The reference AC voltages Vou*, Vov*, and Vow* for the three phases (U-phase, V-phase, W-phase) are defined as follows, assuming a superposition amount of the third harmonic 3f k1 = 1 / 6.

[0061]

number

[0062] TIFF0007848357000002.tif11114

[0063] TIFF0007848357000003.tif10114

[0064] However, E0 is the peak-to-peak value of the triangular wave signal, which will be described later, and is equal in magnitude to half the DC voltage VDC (E0 = VDC / 2).

[0065] Here, the maximum value of sinθ + (1 / 6)sin(3θ) is √3 / 2, so even when α = 2 / √3, the maximum value of the reference AC voltage Vo* is less than or equal to the peak-to-peak value E0 of the triangular wave signal (i.e., VDC / 2). This makes it possible to switch IGBTQ1~Q4 on and off for the entire duration of the reference AC voltage Vo* in PWM.

[0066] In the sinusoidal comparison method, which compares a sinusoidal voltage command value Vor with a triangular wave signal, the maximum fundamental amplitude of the outputtable phase voltage Vo is VDC / 2, and the maximum fundamental amplitude of the line voltage is √3 / 2 times VDC ≈ 0.87VDC.

[0067] In contrast, in the method shown in Figure 5, where the third harmonic 3f·k1 is superimposed on the voltage command value Vor, the third harmonic cancels out, resulting in the maximum value of the fundamental wave amplitude of the line voltage becoming VDC, which can increase the voltage utilization rate by approximately 15.5% compared to the sinusoidal comparison method.

[0068] Returning to Figure 4, the reference voltage generation circuit 40 generates a reference DC voltage VDC* based on the load factor LF detected by the load factor detector 37. The reference voltage generation circuit 40 will be explained in more detail later.

[0069] The gate control circuit 41 generates gate signals φ1 to φ4 for controlling the inverter 10 of the corresponding phase. Figure 6 is a circuit block diagram showing the configuration of the gate control circuit 41. As shown in Figure 6, the gate control circuit 41 consists of an oscillator 51, triangular wave generators 52, 53, comparators 54, 55, buffers 56, 58, and negation (NOT) circuits 57, 59.

[0070] Oscillator 51 outputs a clock signal with a frequency sufficiently higher than the commercial frequency. Triangular wave generators 52 and 53 output triangular wave signals Cua and Cub, respectively, with the same frequency as the output clock signal of oscillator 51. Triangular wave signal Cua is a signal that changes on the positive side. Triangular wave signal Cub is a signal that changes on the negative side. Triangular wave signals Cua and Cub correspond to one embodiment of a "carrier wave signal". The carrier wave signal may also be a sawtooth wave.

[0071] The triangular wave generators 52 and 53 adjust the peak-to-peak values ​​of the triangular wave signals Cua and Cub based on the reference DC voltage VDC* provided by the reference voltage generation circuit 40 (Figure 4). The triangular wave generators 52 and 53 set the peak-to-peak values ​​of the triangular wave signals Cua and Cub to half the magnitude of the reference DC voltage VDC*. Note that half the reference DC voltage VDC* is greater than the amplitude of the reference AC voltage Vo*.

[0072] According to this, the peak-to-peak value of the triangular wave signals Cua and Cub becomes larger than the amplitude of the reference AC voltage Vo*, so the IGBT is switched on and off every period of the triangular wave signal. As a result, the inverter 10 can generate an AC output voltage Vo with an amplitude proportional to the amplitude of the reference AC voltage Vo*.

[0073] The comparator 54 compares the high and low values ​​of the reference AC voltage Vo* and the triangular wave signal Cua from the triangular wave generator 52, and outputs a PWM signal φ54 indicating the comparison result. The frequency of the PWM signal φ54 is a value corresponding to the frequency of the triangular wave signal Cua. The pulse width of the PWM signal φ54 changes according to the level of the reference AC voltage Vo*.

[0074] The comparator 55 compares the high and low values ​​of the reference AC voltage Vo* and the triangular wave signal Cub from the triangular wave generator 53, and outputs a PWM signal φ55 indicating the comparison result. The frequency of the PWM signal φ55 is a value corresponding to the frequency of the triangular wave signal Cub. The pulse width of the PWM signal φ55 changes according to the level of the reference AC voltage Vo*.

[0075] Buffer 56 supplies the PWM signal φ54 to the inverter 10 as gate signal φ1. NOT circuit 57 inverts the PWM signal φ54 and supplies it to the inverter 10 as gate signal φ3.

[0076] Buffer 58 supplies the PWM signal φ55 to inverter 10 as gate signal φ2. NOT circuit 59 inverts the PWM signal φ55 and supplies it to inverter 10 as gate signal φ4.

[0077] Figure 7 is a time chart showing the waveforms of the reference AC voltage Vo*, the triangular wave signals Cua and Cub, and the gate signals φ1 to φ4. The reference AC voltage Vo* is a signal obtained by adding the voltage command value Vor, which is a sine wave signal at commercial frequency, and the third harmonic 3f·k1, as shown in Figure 5. In Figure 7, the amount of the third harmonic superimposed on the voltage command value Vor, k1, is set to 1 / 6.

[0078] The minimum value of the triangular wave signal Cua is 0V, and its maximum value is higher than the positive peak value of the reference AC voltage Vo*. The maximum value of the triangular wave signal Cub is 0V, and its minimum value is lower than the negative peak value of the reference AC voltage Vo*. The triangular wave signals Cua and Cub are in phase, and their phases are synchronized with the phase of the reference AC voltage Vo*. The frequencies of the triangular wave signals Cua and Cub are higher than the frequency of the reference AC voltage Vo* (commercial frequency).

[0079] As shown in Figures 7(A) and (B), when the level of the triangular wave signal Cua is higher than the reference AC voltage Vo*, the gate signal φ1 becomes L level, and when the level of the triangular wave signal Cua is lower than the reference AC voltage Vo*, the gate signal φ1 becomes H level.

[0080] During the first period when the reference AC voltage Vo* is positive, the pulse width of the gate signal φ1 increases as the reference AC voltage Vo* rises. During the second period when the reference AC voltage Vo* is negative, the gate signal φ1 is fixed at an L level. As shown in Figures 7(B) and (E), the gate signal φ3 is the inverse signal of the gate signal φ1.

[0081] As shown in Figures 7(A) and (C), when the level of the triangular wave signal Cub is lower than the reference AC voltage Vo*, the gate signal φ2 becomes L level, and when the level of the triangular wave signal Cub is higher than the reference AC voltage Vo*, the gate signal φ2 becomes H level.

[0082] During the first period when the reference AC voltage Vo* is positive, the gate signal φ2 is fixed at an L level. During the second period when the reference AC voltage Vo* is negative, the pulse width of the gate signal φ2 increases as the reference AC voltage Vo* decreases. As shown in Figures 7(C) and (D), the gate signal φ4 is the inverse signal of the gate signal φ2.

[0083] During periods when gate signals φ1 and φ2 are both at a low level, and gate signals φ3 and φ4 are both at a high level (e.g., t0-t1, t2-t3, t4-t5, t6-t7), IGBTQ1 and Q2 are both turned off, while IGBTQ3 and Q4 are turned on. As a result, the neutral point voltage (0V) of the DC line L2 is output to output node 10a via IGBTQ3 and Q4.

[0084] During periods when gate signals φ1 and φ4 are both at a high level, and gate signals φ2 and φ3 are both at a low level (e.g., t1-t2, t3-t4, t5-t6), IGBTQ1 and Q4 are both turned on, while IGBTQ2 and Q3 are turned off. As a result, the positive DC voltage (+VDC / 2) of DC line L1 is output to output node 10a via IGBTQ1.

[0085] During periods when gate signals φ2 and φ3 are both at a high level, and gate signals φ1 and φ4 are both at a low level (e.g., t7-t8, t9-t10, t11-t12, t13-14), IGBTQ2 and Q3 are both turned on, while IGBTQ1 and Q4 are turned off. As a result, the negative DC voltage (-VDC / 2) of DC line L3 is output to output node 10a via IGBTQ2.

[0086] As shown in Figures 7(B) to (E), when the waveforms of the gate signals φ1 to φ4 change, an AC output voltage Vo with the same waveform as the reference AC voltage Vo* shown in Figure 7(A) is output between node N2 and neutral point NP. Note that while Figures 7(A) to (E) show the waveforms of the reference AC voltage Vo* and signals Cua, Cub, and φ1 to φ4 corresponding to the U phase, the waveforms of the reference AC voltage and signals corresponding to the V phase and W phase are similar. However, the phases of the reference AC voltage and signals corresponding to the U phase, V phase, and W phase are shifted by 120 degrees each.

[0087] The AC output voltages Vou, Vov, and Vow of the U, V, and W phases are each superimposed with third harmonics, but the line voltages (Vuv=Vou-Vov, Vvw=Vov-Vow, Vwu=Vow-Vou) become sine wave signals at commercial frequency because the third harmonics cancel each other out.

[0088] As described above, by employing a method in which the third harmonic 3f·k1 is superimposed on the voltage command value Vor for the PWM control of the inverter 10, the voltage utilization rate can be improved compared to the sine wave comparison method.

[0089] On the other hand, in inverter 10, the power loss of IGBTQ1 and Q2 tends to be greater than the power loss of IGBTQ3 and Q4. The power loss of an IGBT includes conduction loss, which is the power loss that occurs when the IGBT is energized, and switching loss (SW loss), which is the power loss that occurs when the IGBT is switching.

[0090] In both the power losses of IGBTQ1 and Q2, and the power losses of IGBTQ3 and Q4, the conduction loss is greater than the switching loss. The conduction loss of an IGBT is proportional to the product of the IGBT's on-resistance, collector current, and on-time. The switching loss of an IGBT is proportional to the product of the IGBT's maximum collector-emitter voltage, maximum collector current, switching time (turn-on time + turn-off time), and switching frequency.

[0091] Furthermore, if SiC-MOSFETs are used instead of IGBTs for the first to fourth switching elements constituting the inverter 10, the switching loss is significantly reduced, and the power loss of each switching element becomes predominantly due to conduction loss.

[0092] The tendency for the conduction losses of IGBTQ1 and Q2 to be greater than those of IGBTQ3 and Q4 becomes more pronounced in the overload region where the load factor exceeds the rated load. This is because in the overload region, the collector current of the IGBT increases as the load current increases.

[0093] Due to this relationship of conduction losses, heat generation in inverter 10 is concentrated in IGBTQ1 and Q2. In particular, in the overload region, the difference in conduction losses between IGBTQ1 and Q2 and IGBTQ3 and Q4 increases, which can make the concentration of heat generation in IGBTQ1 and Q2 even more pronounced.

[0094] To prevent damage to IGBTQ1 and Q2 due to overheating, it is necessary to select switching elements that can withstand thermal damage and to design a cooling structure that can suppress heat concentration in IGBTQ1 and Q2. On the other hand, in the operation of the uninterruptible power supply (UPS) 1, if the inverter 10 is operated within a range below the rated load during normal operation and the time during overload operation is shorter than the time during normal operation, the above-mentioned measures against heat concentration may be an over-design for the operation of the UPS 1. As a result, there is a concern that the UPS 1 will be unnecessarily increased in cost and size.

[0095] To address these concerns, in this embodiment, the amount of third harmonic superimposition k1 relative to the voltage command value Vor is set to be variable according to the load factor LF of the uninterruptible power supply 1. Specifically, in the third harmonic generation circuit 38 shown in Figure 4, the amount of third harmonic superimposition k1 relative to the voltage command value Vor is increased in the overload region.

[0096] By increasing the amount of third harmonic superposition k1, as described later, the proportion of the on-period of IGBTQ1 and Q2 in one period of the reference AC voltage Vo* decreases, while the proportion of the on-period of IGBTQ3 and Q4 increases. This reduces the current flow of IGBTQ1 and Q2, thereby reducing their conduction losses, while increasing the current flow of IGBTQ3 and Q4, thereby increasing their conduction losses. As a result, the imbalance between the power losses of IGBTQ1 and Q2 and those of IGBTQ3 and Q4 is reduced, and the heat concentration of IGBTQ1 and Q2 can be dispersed.

[0097] Figure 8 is a block diagram showing an example configuration of the third harmonic generation circuit 38 shown in Figure 4. As shown in Figure 8, the third harmonic generation circuit 38 is configured to include a superposition amount setting unit 60 and a multiplier 61.

[0098] The superposition amount setting unit 60 sets the superposition amount k1 of the third harmonic relative to the voltage command value Vor based on the load factor LF indicated by the output signal φLF of the load factor detector 37. In some cases, as shown in Figure 8, the superposition amount setting unit 60 sets the superposition amount k1 from the load factor LF by referring to a predetermined relationship between the load factor LF and the superposition amount k1.

[0099] In the above relationship, in the region where the load factor LF is less than or equal to the threshold Lth (first case), the superposition amount k1 is set to 1 / 6. On the other hand, in the region where the load factor LF exceeds the threshold Lth (second case), the superposition amount k1 is set to a value greater than 1 / 6. This threshold Lth is set to, for example, the rated load (100%). However, the threshold Lth may be set to a value smaller than the rated load (100%) depending on the degree of imbalance between the power loss of IGBTQ1 and Q2 and the power loss of IGBTQ3 and Q4.

[0100] In the example in Figure 8, in the region where the load factor LF exceeds the threshold Lth (second case), the superposition amount k1 is set to increase continuously in accordance with the increase in the load factor LF. However, the relationship between the load factor LF and the superposition amount k1 in that region is not limited to this. For example, the superposition amount k1 may be increased from 1 / 6 to a value greater than 1 / 6 in response to the load factor LF exceeding the threshold Lth. Alternatively, in the region where the load factor LF exceeds the threshold Lth, the superposition amount k1 may be increased stepwise in accordance with the increase in the load factor LF.

[0101] Furthermore, as the amount of third harmonic superposition k1 increases, the waveform of the reference AC voltage Vo* deviates significantly from the original sinusoidal voltage command value Vor. As a result, distortion originating from the third harmonic may occur in the waveforms of the line voltages (Vuv=Vou-Vov, Vvw=Vov-Vow, Vwu=Vow-Vou) of the AC output voltages Vou, Vov, and Vow of the U, V, and W phases. This distortion in the line voltage waveform may interfere with the operation of the load 24. Therefore, as shown in Figure 8, an upper limit k1max is set for the superposition amount k1. This upper limit k1max can be set experimentally or through simulation to avoid interfering with the operation of the load 24.

[0102] The multiplier 61 multiplies the superposition amount k1 set by the superposition amount setting unit 60 by a sine wave signal 3f with a frequency three times that of the voltage command value Vor (i.e., the commercial frequency) to generate a third harmonic 3f·k1.

[0103] Here, as shown in equations (1) to (3) above, when the superposition amount k1 is 1 / 6, the maximum value of the reference AC voltage Vo* is less than or equal to the peak-to-peak value of the triangular wave signal (i.e., VDC / 2). On the other hand, when the superposition amount k1 is greater than 1 / 6, the maximum value of the reference AC voltage Vo* becomes greater than the peak-to-peak value of the triangular wave signal (i.e., VDC / 2). In this case, during the period when the reference AC voltage Vo* is greater than the peak-to-peak value of the triangular wave signal, the IGBT will not switch on and off, resulting in problems such as the loss of proportionality between the amplitude of the AC output voltage Vo and the amplitude of the reference AC voltage Vo*, and an increase in the harmonic components of the AC output voltage Vo.

[0104] To avoid such problems, it is necessary to increase the peak-to-peak value (i.e., VDC / 2) of the triangular wave signal in accordance with the increase in the amount of third harmonic superposition k1. Therefore, in this embodiment, the reference DC voltage VDC* is increased in accordance with the amount of third harmonic superposition k1. This causes IGBTQ1~Q4 to operate in a constantly on / off state.

[0105] Figure 9 is a block diagram showing an example configuration of the reference voltage generation circuit 40 shown in Figure 4. As shown in Figure 9, the reference voltage generation circuit 40 is configured to include an increase amount setting unit 71 and a multiplier 72.

[0106] The rise amount setting unit 71 sets the rise amount k2 of the reference DC voltage VDC* based on the load factor LF indicated by the output signal φLF of the load factor detector 37. In some cases, as shown in Figure 9, the rise amount setting unit 71 sets the rise amount k2 from the load factor LF by referring to a predetermined relationship between the load factor LF and the rise amount k2.

[0107] In the above relationship, in the region where the load factor LF is below the threshold Lth (case 1), the increase amount k2 is set to 1.0. On the other hand, in the region where the load factor LF exceeds the threshold Lth (case 2), the increase amount k2 is set to a value greater than 1.0.

[0108] In the example in Figure 9, in the region where the load factor LF exceeds the threshold Lth (second case), the increase amount k2 is set to increase continuously in accordance with the increase in the load factor LF. However, the relationship between the load factor LF and the increase amount k2 in this region is not limited to this. For example, the increase amount k2 may be increased from 1.0 to a value greater than 1.0 in response to the load factor LF exceeding the threshold Lth. Alternatively, in the region where the load factor LF exceeds the threshold Lth, the increase amount k2 may be increased in stages in accordance with the increase in the load factor LF.

[0109] Furthermore, as the reference DC voltage VDC* (i.e., DC voltage VDC) is increased, the switching losses in each switching element of the converter 6, bidirectional chopper 7, and inverter 10 increase, which may reduce the operating efficiency of the uninterruptible power supply 1. For this reason, as shown in Figure 9, an upper limit k2max is set for the increase amount k2. This upper limit k2max can be set based on the minimum DC voltage VDC necessary to ensure the on / off operation of the IGBT, taking into account the upper limit k1max of the superimposed amount k1.

[0110] The multiplier 72 multiplies the rise amount k2 set by the rise amount setting unit 71 by the reference value VDCr of the reference DC voltage VDC* to generate the reference DC voltage VDC* = VDCr × k2.

[0111] Returning to Figure 1, the control device 18 controls the converter 6 or bidirectional chopper 7 so that the DC voltage VDC between DC lines L1 and L3 becomes the reference DC voltage VDC*, the DC voltage VDCa between DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between DC lines L2 and L3 becomes VDC* / 2.

[0112] Figure 10 is a block diagram showing the configuration of the parts of the control device 18 related to the control of the converter 6 and the bidirectional chopper 7. The control device 18 further includes a power failure detector 62, a reference voltage generation circuit 64, and a control unit 65.

[0113] The power outage detector 62 detects whether a power outage has occurred in the commercial AC power supply 21 based on the AC input voltage Vi supplied from the commercial AC power supply 21, and outputs a power outage detection signal φF indicating the detection result to the control unit 65. For example, the power outage detector 62 determines that a power outage has occurred in the commercial AC power supply 21 when the effective value of the AC input voltage Vi falls below a lower limit. When the commercial AC power supply 21 is healthy, the power outage detection signal φF is set to the H level. When a power outage occurs in the commercial AC power supply 21, the power outage detection signal φF is set to the L level.

[0114] As explained in Figure 9, the reference voltage generation circuit 40 generates a reference DC voltage VDC* based on the load factor LF indicated by the output signal φLF of the load factor detector 37. The reference voltage generation circuit 40 outputs the generated reference DC voltage VDC* to the control unit 65.

[0115] The reference voltage generation circuit 64 generates a reference DC voltage VB* according to the type of battery 23 and outputs it to the control unit 65. The reference DC voltage VB* is the DC voltage applied to the battery 23 when charging the battery 23.

[0116] The control unit 65 controls the converter 6 and the bidirectional chopper 7 based on signals such as φF from the power outage detector 62, the reference DC voltage VDC* from the reference voltage generation circuit 40, the reference DC voltage VB* from the reference voltage generation circuit 64, the DC voltage VDC between DC lines L1 and L3, the terminal voltage VB of the battery 23, and the AC input current Ii indicated by the output signal Iif of the current detector 3.

[0117] Specifically, when the power outage detection signal φF is at the H level (when the commercial AC power supply 21 is healthy), the control unit 65 controls the converter 6 so that the DC voltage VDC becomes the reference DC voltage VDC*, the DC voltage VDCa between DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between DC lines L2 and L3 becomes VDC* / 2. The control unit 65 also controls the bidirectional chopper 7 so that the terminal voltage VB of the battery 23 becomes the reference DC voltage VB*.

[0118] When the power outage detection signal φF is at the L level (during a power outage of the commercial AC power supply 21), the control unit 65 stops the operation of the converter 6. The control unit 65 controls the bidirectional chopper 7 so that the DC voltage VDC becomes the reference DC voltage VDC*, the DC voltage VDCa between DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between DC lines L2 and L3 becomes VDC* / 2.

[0119] Figure 11 is a time chart showing the waveforms of the reference AC voltage Vo*, triangular wave signals Cua and Cub, and gate signals φ1 to φ4 in the overload region, and is shown in comparison with Figure 7.

[0120] In Figure 11, the reference AC voltage Vo* is a signal obtained by adding the voltage command value Vor and the third harmonic 3f·k1, similar to Figure 7. However, in Figure 11, the amount of the third harmonic superimposed on the voltage command value Vor, k1, is set to a value greater than 1 / 6 (for example, k1 = 1 / 3). Therefore, the maximum value of the reference AC voltage Vo* is greater than the maximum value of the reference AC voltage Vo* shown in Figure 7.

[0121] Furthermore, in Figure 11, the peak-to-peak values ​​of the triangular wave signals Cua and Cub are increased by increasing the reference DC voltage VDC* (i.e., DC voltage VDC) in accordance with the increase in the reference AC voltage Vo*.

[0122] Comparing Figure 11 with Figure 7, it can be seen that increasing the amount of third harmonic superposition k1 increases the oscillation of the waveform of the reference AC voltage Vo* due to the third harmonic. As shown in Figures 11(A), (B), and (E), in the first period when the reference AC voltage Vo* is positive polarity, the oscillation of the reference AC voltage Vo* causes the pulse width of the gate signal φ1 to decrease while the pulse width of the gate signal φ3 increases compared to Figure 7. As shown in Figures 11(A), (C), and (D), in the second period when the reference AC voltage Vo* is negative polarity, the oscillation of the reference AC voltage Vo* causes the pulse width of the gate signal φ2 to decrease while the pulse width of the gate signal φ4 increases compared to Figure 7.

[0123] Thus, in the first period when the reference AC voltage Vo* is positive, increasing the amount of third harmonic superposition k1 reduces the proportion of the IGBTQ1 on-period in the first period, while increasing the proportion of the IGBTQ3 on-period. The decrease in the proportion of the IGBTQ1 on-period reduces the amount of current flowing through IGBTQ1 in the first period, thus reducing the conduction loss of IGBTQ1. On the other hand, the increase in the proportion of the IGBTQ3 on-period increases the amount of current flowing through IGBTQ3 in the first period, thus increasing the conduction loss of IGBTQ3.

[0124] In the second period, when the reference AC voltage Vo* is negative, increasing the amount of third harmonic superposition k1 reduces the proportion of the IGBTQ2 ON period in the second period, while increasing the proportion of the IGBTQ4 ON ​​period. The decrease in the proportion of the IGBTQ2 ON period reduces the amount of current flowing through IGBTQ2 in the second period, thus reducing the conduction loss of IGBTQ2. On the other hand, the increase in the proportion of the IGBTQ4 ON ​​period increases the amount of current flowing through IGBTQ4 in the second period, thus increasing the conduction loss of IGBTQ4.

[0125] As a result, in the overload region, the conduction losses of IGBTQ1 and Q2 decrease while the conduction losses of IGBTQ3 and Q4 increase. This reduces the imbalance between the power losses of IGBTQ1 and Q2 and those of IGBTQ3 and Q4, thereby dispersing the heat concentration of IGBTQ1 and Q2.

[0126] Figure 12 shows the simulation results of power loss occurring in the inverter 10. Figure 12 is a diagram that explains the breakdown of power loss occurring in the inverter 10 in the overload region.

[0127] The left side of Figure 12 shows the breakdown of power loss when the amount of third harmonic superposition k1 is 1 / 6. The right side of Figure 12 shows the breakdown of power loss when the amount of third harmonic superposition k1 is 1 / 2.

[0128] Referring to the left side of Figure 12, when k1 = 1 / 6, the conduction loss of IGBTQ1 and Q2 is approximately three times greater than the conduction loss of IGBTQ3 and Q4. Furthermore, the ratio of the power loss of IGBTQ1 and Q2 to the power loss of IGBTQ3 and Q4 is 4:1, indicating a large imbalance between the power loss of IGBTQ1 and Q2 and the power loss of IGBTQ3 and Q4.

[0129] Referring to the right side of Figure 12, increasing k1 from 1 / 6 to 1 / 2 reduces the conduction loss of IGBTQ1 and Q2 by approximately 10%. In contrast, the conduction loss of IGBTQ3 and Q4 increases by approximately 60%. The conduction loss of IGBTQ1 and Q2 is approximately 1.8 times greater than that of IGBTQ3 and Q4. The ratio of power loss of IGBTQ1 and Q2 to power loss of IGBTQ3 and Q4 is 2:1, indicating that the imbalance between the power loss of IGBTQ1 and Q2 and the power loss of IGBTQ3 and Q4 has been improved.

[0130] In the example shown in Figure 12, increasing the amount of third harmonic superposition k1 increases the power loss generated in the inverter 10, but the imbalance between the power loss of IGBTQ1 and Q2 and the power loss of IGBTQ3 and Q4 is improved, indicating that the heat concentration of IGBTQ1 and Q2 is dispersed. As a result, countermeasures against heat concentration of IGBTQ1 and Q2 during overload operation can be mitigated, thereby suppressing cost increases and size increases for the uninterruptible power supply 1.

[0131] (Modified version of this embodiment) Figure 13 is a circuit block diagram showing a first modification of this embodiment, and is shown in comparison with Figure 3. The inverter 10 according to the first modification differs from the inverter 10 shown in Figure 3 in that IGBTQ3 and IGBTQ4 are connected in reverse. That is, the emitters of IGBTQ3 and Q4 are connected to each other, and the collectors of IGBTQ3 and Q4 are connected to output node 10a and DC line L2, respectively. The first modification provides the same effects as the embodiment described above.

[0132] Figure 14 is a circuit block diagram showing a second modification of this embodiment, and is shown in comparison with Figure 3. The inverter 10 according to the second modification differs from the inverter 10 shown in Figure 3 in the connection relationships of IGBTQ3, Q4 and diodes D3, D4.

[0133] The collector of IGBTQ3 is connected to the cathode of diode D4, and the emitter of IGBTQ3 is connected to DC line L2. The anode of diode D4 is connected to output node 10a. The collector of IGBTQ4 is connected to the cathode of diode D3, and the emitter of IGBTQ4 is connected to output node 10a. The anode of diode D3 is connected to DC line L2. In the second modification example, the same effects as the embodiment described above can be obtained.

[0134] Figure 15 is a circuit block diagram showing a third modification of this embodiment, and is shown in comparison with Figure 3. The inverter 10 according to the third modification has a different configuration from the inverter 10 shown in Figure 3.

[0135] As shown in Figure 15, the inverter 10 includes IGBTQ1 to Q4 and diodes D1 to D6. The collector of IGBTQ1 (first switching element) is connected to DC line L1, and the emitter of IGBTQ1 is connected to the collector of IGBTQ4 (fourth switching element). The emitter of IGBTQ4 is connected to output node 10a. The collector of IGBTQ3 (third switching element) is connected to output node 10a, and the emitter of IGBTQ3 is connected to the collector of IGBTQ2 (second switching element). The emitter of IGBTQ2 is connected to DC line L3.

[0136] Diodes D1 to D4 are connected in antiparallel to IGBTQ1 to Q4, respectively. The anode of diode D5 (the fifth diode) is connected to the emitter of IGBTQ3, and its cathode is connected to DC line L2. The anode of diode D6 (the sixth diode) is connected to DC line L2, and its cathode is connected to the collector of IGBTQ4.

[0137] In inverter 10, during the first period, IGBTQ2 and Q4 are set to the off state and the on state respectively, and IGBTQ1 and Q3 are turned on alternately. During the second period, IGBTQ1 and Q3 are set to the off state and the on state respectively, and IGBTQ2 and Q4 are turned on alternately.

[0138] During the first period, when IGBTQ1 is turned on, a positive DC voltage is output from DC line L1 to output node 10a via IGBTQ1 and Q4. When IGBTQ3 is turned on, output node 10a is connected to DC line L2 via IGBTQ3 and diode D5, and DC line L2 is connected to output node 10a via diode D6 and IGBTQ4, so that output node 10a is at its neutral point voltage. Therefore, during the first period, a positive DC voltage and the neutral point voltage are alternately output to output node 10a.

[0139] During the second period, when IGBTQ2 is turned on, output node 10a is connected to DC line L3 via IGBTQ2 and Q3, and output node 10a is given a negative DC voltage. Also, when IGBTQ4 is turned on, DC line L2 is connected to output node 10a via diode D6 and IGBTQ4, and output node 10a is connected to DC line L2 via IGBTQ3 and diode D5, and output node 10a is given a neutral point voltage. Therefore, during the second period, negative DC voltage and neutral point voltage are alternately output to output node 10a.

[0140] The configuration and operation of the control device 18 are the same as those shown in Figures 4 to 6 and 8 to 10, so their explanation will not be repeated. The waveforms of the reference AC voltage Vo*, the triangular wave signals Cua and Cub, and the gate signals φ1 to φ4 are as shown in Figures 7 and 11. Therefore, the same effects as the embodiment described above can be obtained in the third modified example.

[0141] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included. [Explanation of symbols]

[0142] 1 Uninterruptible Power Supply, 2,8,14,16 Electromagnetic Contactor, 3,11 Current Detector, 4,9,9a,9b,13 Capacitor, 5,12 Reactor, 6 Converter, 7 Bidirectional Chopper, 10 Inverter, 15 Semiconductor Switch, 17 Operating Unit, 18 Control Unit, 21 Commercial AC Power Supply, 22 Bypass AC Power Supply, 23 Battery, 24 Load, 31,40,64 Reference Voltage Generation Circuit, 32 Voltage Detector, 33,35 Subtractor, 34 Output Voltage Control Circuit, 36 Output Current Control Circuit, 37 Load Factor Detector, 38 Third Harmonic Generation Circuit, 39 Adder, 41 Gate Control Circuit, 51 Oscillator, 52,53 Triangular Wave Generator, 54,55 Comparator, 56,58 Buffer, 60 Superposition Amount Setting Unit, 61,72 Multiplier, 62 Power Failure Detector, 65 Control unit, 71 Increase amount setting unit, 102 CPU, 104 Memory, 106 I / O circuit, 108 Bus, L1~L3 DC lines, T1 AC input terminal, T2 Bypass input terminal, T3 Battery terminal, T4 AC output terminal.

Claims

1. A power conversion device, A variable DC power supply connected between the positive DC busbar and the negative DC busbar, A first capacitor connected between the DC positive busbar and the DC neutral busbar, A second capacitor connected between the DC neutral busbar and the DC negative busbar, An inverter comprising a multilevel circuit having multiple switching elements, which converts the first to third DC voltages supplied from the DC positive bus, the DC neutral bus, and the DC negative bus into AC voltages and supplies them to a load, A current detector for detecting the output current of the inverter, The system includes a control device that controls the on / off operation of the plurality of switching elements using pulse width modulation, The control device is A reference AC voltage is generated by superimposing the third harmonic of a sinusoidal voltage command value onto the said voltage command value. The system is configured to generate gate signals for driving the plurality of switching elements on and off by comparing a carrier signal having a peak-to-peak value corresponding to the DC voltage between the DC positive bus and the DC negative bus with the reference AC voltage. The control device is The load factor of the power converter is detected from the value of the output current detected by the current detector. A power converter that, in the second case where the load factor is greater than a predetermined threshold, increases the amount of superposition of the third harmonic on the voltage command value compared to the first case where the load factor is less than or equal to the threshold.

2. The power conversion device according to claim 1, wherein, in the second case, the control device increases the amount of superposition of the third harmonic to the voltage command value in accordance with the increase in the load factor.

3. The control device is In the first case described above, the amount of superposition of the third harmonic is set to 1 / 6, In the second case, the power conversion device according to claim 1, wherein the amount of superposition of the third harmonic is set to a value greater than 1 / 6.

4. The control device is configured to control the variable DC power supply so that the DC voltage between the DC positive busbar and the DC negative busbar becomes the reference DC voltage. The power conversion device according to claim 1, wherein the control device increases the reference DC voltage compared to the first case in the second case.

5. The power conversion device according to claim 4, wherein the control device increases the reference DC voltage in response to an increase in the load factor such that, in the second case, the peak-to-peak value of the carrier signal is greater than or equal to the amplitude of the reference AC voltage.

6. The aforementioned multilevel circuit is The AC terminal that receives the aforementioned AC voltage, A first switching element connected between the DC positive busbar and the AC terminal, A second switching element connected between the DC negative bus and the AC terminal, A third switching element connected between the DC neutral bus and the AC terminal, and a fourth switching element connected between the first terminal of the third switching element and the AC terminal, or between the second terminal of the third switching element and the DC neutral bus, The first to fourth switching elements are each connected in antiparallel to the first to fourth diodes, The control device is During the first period when the reference AC voltage is positive, the first and third switching elements are alternately turned on, and during the second period when the reference AC voltage is negative, the first and third switching elements are kept in the off and on states, respectively. The power conversion device according to any one of claims 1 to 5, wherein the second and fourth switching elements are alternately turned on during the second period, and the second and fourth switching elements are kept in an off state and an on state, respectively, during the first period.

7. The aforementioned multilevel circuit is The AC terminal that receives the aforementioned AC voltage, A first switching element connected between the DC positive busbar and the AC terminal, A third switching element connected between the DC neutral bus and the AC terminal, A second switching element connected between the first terminal of the third switching element and the DC negative busbar, A fourth switching element connected between the first terminal of the first switching element and the AC terminal, The first to fourth diodes are connected in antiparallel to the first to fourth switching elements, A fifth diode connected between the first terminal of the third switching element and the DC neutral bus, It includes a sixth diode connected between the DC neutral bus and the first terminal of the first switching element, The control device is During the first period when the reference AC voltage is positive, the first and third switching elements are alternately turned on, and during the second period when the reference AC voltage is negative, the first and third switching elements are kept in the off and on states, respectively. The power conversion device according to any one of claims 1 to 5, wherein the second and fourth switching elements are alternately turned on during the second period, and the second and fourth switching elements are kept in an off state and an on state, respectively, during the first period.

8. The variable DC power supply includes a converter that converts the AC voltage supplied from the AC power supply into the first to third DC voltages and supplies them to the DC positive bus, the DC neutral bus, and the DC negative bus. The power conversion device according to claim 4 or 5, wherein the control device controls the converter so that the DC voltage between the DC positive busbar and the DC negative busbar becomes the reference DC voltage when the AC power supply is healthy.

9. The variable DC power supply further includes a bidirectional chopper that exchanges DC power between the DC positive busbar, the DC neutral busbar, and the DC negative busbar and the power storage device. The power conversion device according to claim 8, wherein the control device stops the operation of the converter when the AC power supply is interrupted, and controls the bidirectional chopper so that the DC voltage between the DC positive busbar and the DC negative busbar becomes the reference DC voltage.

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