Insulated gate semiconductor device

Abstract

To provide an insulated-gate semiconductor device capable of achieving a high threshold voltage with a low-cost material.SOLUTION: An insulated-gate semiconductor device comprises: a gate insulating film 5 consisting of a silicon oxide film provided on an upper surface of a channel formation region 3 made of silicon carbide; a nitride termination layer 6 provided at an interface between the channel formation region 3 and the gate insulating film 5 and in which silicon is terminated with nitrogen; and a main gate electrode 7 provided on the gate insulating film 5, controlling a surface potential of the channel formation region 3 and including a conductive oxide film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an insulated gate type semiconductor device, and more particularly to an insulated gate type semiconductor device using silicon carbide (SiC). [Background technology]

[0002] In SiC-based MOS field-effect transistors (FETs), a high threshold voltage (Vth) is required for safe operation. By controlling the threshold voltage to a high level and reducing the impurity concentration in the channel region, the channel mobility can be increased, and the on-resistance of the MOSFET can be lowered. In the case of n-type channel MOSFETs, one possible method for achieving a high threshold voltage is to use a p-type polysilicon layer as the gate electrode instead of the conventional n-type polysilicon layer.

[0003] When forming a gate insulating film, such as a silicon oxide (SiO2) film, on a SiC semiconductor layer, a high density of interface states is created. This reduces channel mobility, degrading the electrical characteristics of the MOSFET, such as its on-resistance. Typically, after forming the gate insulating film, a nitriding treatment is performed by heating in a gas containing nitrogen (N) to reduce the density of interface states at the gate insulating film interface. However, this nitriding treatment lowers the threshold voltage. Furthermore, if the p-type impurity concentration in the channel region of the MOSFET is increased to obtain a high threshold voltage, the influence of interface states becomes stronger, leading to a more severe decrease in channel mobility.

[0004] As mentioned above, using a p-type polysilicon layer as the gate electrode allows for a higher threshold voltage and increased channel mobility. However, the work function difference between n-type silicon (Si) and p-type Si is approximately 0.8 eV, making it difficult to achieve a threshold voltage of 0.8 V or higher even when using a p-type polysilicon layer as the gate electrode.

[0005] Patent Document 1 discloses a configuration in which a semiconductor material with a work function of 5.1 eV or higher is used as the gate electrode of a SiC-MOSFET. Patent Document 2 describes using an oxide semiconductor in the channel region and using a conductive oxide film such as molybdenum oxide with a work function of 5 eV or higher as the gate electrode, and further states that the conductive oxide film may be used in a laminated structure with a material with good conductivity. Patent Document 3 discloses using a laminated structure of a metal with a high work function such as nickel (Ni), platinum (Pt), and palladium (Pd) and a high melting point metal as the gate electrode of a gallium nitride (GaN) heterojunction (HJ) FET. High work function metals such as Ni, Pt, and Pd have higher material costs than p-type polysilicon, which leads to increased manufacturing costs for MOSFETs. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2005-19494 [Patent Document 2] Patent No. 5825744 [Patent Document 3] Japanese Patent Publication No. 2004-22773 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] In view of the above problems, the present invention aims to provide an insulated gate semiconductor device that can achieve a high threshold voltage using inexpensive materials. [Means for solving the problem]

[0008] In order to achieve the above object, one aspect of the present invention is an insulated gate semiconductor device including: (a) a gate insulating film made of a silicon oxide film provided on the upper surface of a channel formation region made of silicon carbide; (b) a nitride termination layer provided at the interface between the channel formation region and the gate insulating film, in which silicon is terminated with nitrogen; and (c) a main gate electrode provided on the gate insulating film and including a conductive oxide film for controlling the surface potential of the channel formation region.

Advantages of the Invention

[0009] According to the present invention, an insulated gate semiconductor device capable of realizing a high threshold voltage with inexpensive materials can be provided.

Brief Description of the Drawings

[0010] [Figure 1] It is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to an embodiment of the present invention. [Figure 2] It is a schematic cross-sectional view for explaining an example of a process of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 3] It is a schematic cross-sectional view for explaining an example of a process following FIG. 2 of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 4] It is a schematic cross-sectional view for explaining an example of a process following FIG. 3 of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 5] It is a schematic cross-sectional view for explaining an example of a process following FIG. 4 of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 6] It is a schematic cross-sectional view for explaining an example of a process following FIG. 5 of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 7] It is a schematic cross-sectional view for explaining an example of a process following FIG. 6 of a method for manufacturing an insulated gate semiconductor device according to an embodiment. [Figure 8] It is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to a comparative example. [Figure 9]This table shows an example of the evaluation results of an insulated gate type semiconductor device according to the embodiment. [Figure 10] This is a schematic cross-sectional view showing another example of an insulated gate type semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the embodiments shown below are illustrative examples of devices and methods for realizing the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the materials, shapes, structures, arrangements, etc. of the components described below.

[0012] In this specification, the source region of a MOS transistor is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), one main region can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be reversed and read accordingly. In the following explanation, the case where the first conductivity type is p-type and the second conductivity type, which is the opposite, is n-type will be explained as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Also, the + and - attached to n and p mean that they are semiconductor regions with relatively higher or lower impurity densities compared to semiconductor regions without + and - attached, respectively. However, even if two semiconductor regions are attached to the same n, it does not mean that the impurity densities of each semiconductor region are exactly the same. Furthermore, in this specification, in the notation of Miller indices, "-" means a bar attached to the exponent immediately following it, and a negative exponent is indicated by placing "-" before the exponent.

[0014] An insulated gate semiconductor device according to an embodiment of the present invention is a lateral MOSFET using an oxide film made of SiO2 as the gate insulating film. As shown in Figure 1, it has a channel formation region (base region) 3 of first conductivity type (p-type), and an inverted channel is formed on the surface of the channel formation region 3. Above the channel formation region 3, a second conductivity type (n-type) with a high impurity density is formed. +Main regions 4a and 4b of the channel-forming region 3, for example, a source region (first main region) 4a and a drain region (second main region) 4b, are selectively provided. An insulated gate type electrode structure (5,7,8) is provided on the upper surface of the channel-forming region 3, spanning the source region 4a and the drain region 4b, via a nitrogen (N)-terminated nitride-terminated layer 6. The insulated gate type electrode structure (5,7,8) consists of a gate insulating film 5 made of an SiO2 film and gate electrodes (control electrodes) (7,8) on the gate insulating film 5. The gate electrodes (7,8) consist of a main gate electrode 7 and a sub-gate electrode 8, and electrostatically control the surface potential of the channel-forming region 3 via the gate insulating film 5 to form an inverted channel on the surface of the channel-forming region 3. The main gate electrode 7 of the gate electrodes (7,8) is provided on the gate insulating film 5, and the sub-gate electrode 8 is provided on the main gate electrode 7. A surface gate electrode 9 is provided on the sub-gate electrode 8.

[0015] The gate insulating film 5 of the MOSFET is an oxide film made of SiO2, and can be a thermal oxide film such as oxygen (O2) dry oxidation or wet oxidation, or a deposited oxide film such as sputtering, thermochemical vapor deposition (thermal CVD), or plasma CVD. The gate insulating film 5 may have a thickness of 30 nm to 100 nm. In addition, boron (B) atoms diffused by a solid diffusion source such as boron nitride (BN) are 1 × 10⁻¹⁶ 19 cm -3 The above 5 x 10 20 cm -3 It may be contained in the following concentration range.

[0016] The main gate electrode 7 of the gate electrode (7,8) has p + A conductive oxide film having a work function of approximately 5 eV or more, preferably 6 eV or more, of polysilicon is used. The thickness of the main gate electrode 7 is preferably 5 nm to 100 nm to prevent an increase in gate resistance. As the conductive oxide film, tungsten oxide (WO) is used. 3-x (0≦x<1), molybdenum oxide (MoO 3-x(0 < x ≤ 1)), vanadium pentoxide (V2O5), chromium oxide (CrO3), rhenium oxide (ReO3), etc. can be used. As the sub-gate electrode 8, a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as phosphorus (P) or boron (B), or a conductive film having a higher conductivity than the main gate electrode 7 such as nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), etc. is used. The thickness of the sub-gate electrode 8 is preferably 100 nm or more and 300 nm or less in order to ensure a low gate resistance. When molybdenum (Mo) or tungsten (W) is used as the sub-gate electrode 8, the gate resistance can be kept low even when oxygen contained in the main gate electrode 7 diffuses. As the surface gate electrode 9, a metal film such as aluminum (Al) can be used.

[0017] Tungsten oxides include tungsten trioxide (WO3) of an n-type semiconductor and tungsten dioxide (WO2) of a conductor. WO3 has a work function of about 6.7 eV, a conductivity of about 10 -6 S / m, and a melting point of about 1473 °C. WO2 has a work function of about 4.5 eV, a conductivity of 10 4 S / cm or more, and a melting point of about 1700 °C. Considering the work function and conductivity, as the composition x of tungsten oxide (WO 3-x ), 0.3 ≤ x ≤ 0.7 is desirable. When x is greater than 0.7, the work function becomes less than 6 eV, leading to a reduction in the threshold voltage. When x is less than 0.3, the gate resistance increases. Tungsten oxide has high thermal stability, and it is possible to perform a high-temperature process at about 1400 °C after forming the gate electrodes (7, 8).

[0018] Molybdenum oxides include molybdenum trioxide (MoO3) of an n-type semiconductor and molybdenum dioxide (MoO2) of a conductor. MoO3 has a work function of about 6.9 eV, a conductivity of about 10 -5 S / m, and a melting point of about 795 °C. MoO2 has a work function of about 6.0 eV, a conductivity of about 10 6 S / cm, and a melting point of about 1100 °C. Considering the work function, conductivity, and thermal stability in addition, for molybdenum oxide (MoO 3-xFor the composition x of the material, 0, 5 ≤ x ≤ 1 is desirable. Even if x is 0, i.e., the work function is lower compared to MoO3, a value of 6.0 eV or higher can be secured. If x is less than 0.5, the thermal stability decreases and the gate resistance increases. In addition, vanadium oxide (V2O5), chromium oxide (CrO3), and rhenium oxide (ReO3) have low melting points of 690°C, 197°C, and 400°C, respectively, so if they are used, measures such as lowering the post-processing temperature, thinning the film, and lamination with high heat-resistant materials are necessary.

[0019] The channel formation region 3 is formed by epitaxial growth on a substrate 1 made of n-type SiC semiconductor, as shown in Figure 1. A source electrode 9a and a drain electrode 9b are provided so as to be in physical contact with the source region 4a and drain region 4b, respectively. The source electrode 9a and drain electrode 9b are ohmic-connected to the source region 4a and drain region 4b, respectively. The source electrode 9a and drain electrode 9b are made of, for example, a single layer film of Al or nickel silicide (NiSi x A metal film can be used in which titanium nitride (TiN) and Al are layered in that order. Although not shown in the diagram, the source electrode 9a and the channel formation region 3 are electrically connected by p + The type of contact region is separated from the source region 4a and located in the channel formation region 3.

[0020] SiC crystals exist in various crystalline polymorphs, the main being cubic 3C and hexagonal 4H and 6H. Reported band gaps at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the embodiment of the present invention, an insulated gate semiconductor device will be described using 4H-SiC. In the embodiment, the substrate 1 is a semiconductor substrate (SiC substrate) made of SiC. When using a SiC substrate, the channel formation region 3 is exemplified as a structure composed of an epitaxial layer (SiC layer) made of SiC. The plane orientation of the SiC substrate will be described using the (0001) plane (Si plane), but the (11-20) plane (a plane), (1-100) plane (m plane), and (000-1) plane (C plane) may also be used.

[0021] As shown in FIG. 1, in the insulated gate semiconductor device according to the embodiment, a voltage is applied to the gate electrodes (7, 8) to form an inversion layer serving as a channel at the interface between the gate insulating film 5 and the channel formation region 3. At this time, by applying a voltage between the source electrode 9a and the drain electrode 9b, carriers (electrons) are injected from the source region 4a into the channel. The injected carriers travel through the channel and flow into the drain region 4b.

[0022] Normally, when the SiO2 film used for the gate insulating film 5 is formed by a thermal oxidation method or the like, C atoms remain at the interface between the SiO2 film and the SiC semiconductor layer, and a high density of interface states is formed. When electrons are trapped by the interface states, the electron mobility decreases due to Coulomb scattering or the like. A method of reducing the interface state density by terminating the interface between the SiO2 film and the SiC semiconductor layer with N atoms has been proposed. However, when a high-concentration nitride region is formed at the interface between the SiO2 film and the SiC semiconductor layer, the threshold voltage of the semiconductor device decreases.

[0023] The threshold voltage of the MOSFET increases in proportion to the work function of the gate electrode material. In the insulated gate semiconductor device according to the embodiment, a conductive oxide film having a high work function such as tungsten oxide (WO 3-x (0 ≦ x < 1)) or molybdenum oxide (MoO 3-x (0 < x ≦ 1)) is used for the main gate electrode 7 in contact with the gate insulating film 5. The conductive oxide film has a lower material cost than high work function metals such as Ni, Pt, Pd, etc., which are high work function metals. Thus, according to the insulated gate semiconductor device according to the embodiment, a high threshold voltage of the semiconductor device can be realized with an inexpensive material. In order to realize the main gate electrode 7 having a work function of 6.0 eV or more and high thermal stability, in tungsten oxide (WO 3-x ), 0, 3 ≦ x ≦ 0.7, and in molybdenum oxide (MoO 3-xIn this case, 0 and 5 ≤ x ≤ 1 should be set. Also, as mentioned above, the conductive oxide film used for the main gate electrode 7 has low conductivity. Therefore, a conductive material with higher conductivity than the main gate electrode 7 is used for the secondary gate electrode 8. As a result, it is possible to suppress the increase in gate resistance. Alternatively, a mixed material of molybdenum oxide and tungsten oxide may be used.

[0024] <Manufacturing method for semiconductor devices> Next, using the process diagrams shown in Figures 2 to 7, the manufacturing method of the semiconductor device according to the embodiment will be explained using Example 1 of a lateral MOSFET as an example. It should be noted that the MOSFET manufacturing method described below is just one example, and it is of course possible to realize this invention using various other manufacturing methods, including this modification, as long as it falls within the scope of the claims.

[0025] First, an n-type SiC substrate (substrate) 1 is prepared with n-type impurities such as nitrogen (N) added. Substrate 1 is a 4H-SiC substrate with a (0001) plane (Si plane). First, substrate 1 is cleaned by RCA cleaning, which involves heating hydrogen peroxide with alkali or acid, and then treated with hydrogen fluoride (HF) and dried. On the upper surface of substrate 1, 1.5 × 10⁻⁶ p-type impurities such as Al are added. 17 cm -3 A p-type channel-forming region (base region) 3 doped with a concentration of is epitaxially grown. From the upper side of the channel-forming region 3, n-type impurities such as N are selectively implanted using photolithography and ion implantation techniques. The implanted n-type impurity ions are activated by heat treatment. As a result, n is formed on the upper part of the channel-forming region 3. + Source regions 4a and n of type + The drain region 4b of type is selectively embedded.

[0026] As shown in Figure 2, an oxide film 5b made of SiO2 with a wavelength of about 60 nm is formed on the upper surface of the channel-forming region 3 by heating in a 100% O2 gas atmosphere at a temperature of 1100°C to 1300°C, for example, about 1200°C, for about 160 minutes. Although a dry oxide film is exemplified as the oxide film 5b, a wet oxide film may also be used, as well as an oxide film deposited by thermal CVD, plasma CVD, etc. For example, the oxide film 5b may be deposited using silane (SiH4) gas and oxygen (O2) gas in a reduced-pressure thermal CVD at a pressure of about 0.2 Pa and a temperature of about 600°C.

[0027] Next, the material is subjected to nitriding treatment by heating it for about 60 minutes at a temperature between 1150°C and 1300°C, for example, around 1250°C, in a gas atmosphere containing 10% nitric oxide (NO) gas added to N2 gas. As a result of this nitriding treatment, an intermediate nitrided layer 6a is formed at the interface between the oxide film 5b and the channel formation region 3, source region 4a, and drain region 4b, as shown in Figure 3. Nitrous oxide (N2O) gas may be used instead of NO for the nitriding treatment.

[0028] After nitriding, as shown in Figure 4, a WO layer of about 10 nm thick is applied to the upper surface of the oxide film 5b using a sputtering method or the like. 3-x A conductive oxide film 7a consisting of WO2 is deposited. Specifically, a WO2 sintered body is used as the sputtering target material, and a discharge gas of argon (Ar) and oxygen (O2) in a 9:1 ratio is introduced and the process is carried out by high-frequency (RF) discharge or direct current (DC) discharge at a pressure of about 4 Pa. 3-x The composition can be controlled by the mixing ratio of Ar gas and O2 gas in the discharge gas. Alternatively, WO3 or WO3 can be used as the target material. 3-x Other sintered materials such as may be used, and W metal may also be used. In addition, the conductive oxide film 7a WO 3-x The conductive oxide film 7a may be deposited using methods such as vacuum deposition or electron beam deposition. 3-x MoO may be deposited. 3-xIt can also be deposited by sputtering, vacuum deposition, electron beam deposition, etc. Alternatively, metal-organic chemical vapor deposition (MOCVD) using molybdenum dioxide acetylacetonate (MoO2(acac)2) as the material may be used.

[0029] As shown in Figure 5, a conductive film 8a made of n-type polysilicon doped with P to a thickness of approximately 200 nm is deposited on the upper surface of the conductive oxide film 7a by low-pressure chemical vapor deposition (LPCVD) or the like. When a metal film such as Ni, Ti, Mo, or W is used as the conductive film 8a, it is deposited using sputtering, vapor deposition, or the like.

[0030] Next, a photoresist film is applied to the upper surface of the conductive film 8a. Using photolithography or similar techniques, the photoresist film is patterned to form an etching mask 20, as shown in Figure 6. Using the etching mask 20, the conductive film 8a, conductive oxide film 7a, oxide film 5b, and intermediate nitride layer 6a are selectively removed by dry etching with sulfur hexafluoride (SF6) / carbon tetrafluoride (CF4) / oxygen (O2) gas. As a result, as shown in Figure 7, source contact holes and drain contact holes are opened, and the patterns of the gate insulating film 5 and nitride termination layer 6, spanning the source region 4a and drain region 4b, are selectively left on the upper surface of the channel formation region 3. Guard electrodes (7,8) are formed on the gate insulating film 5.

[0031] A metal layer, such as a nickel (Ni) film with a thickness of approximately 50 nm, is deposited on the upper surfaces of the gate insulating film 5, source contact hole, and drain contact hole using sputtering or electron beam deposition. The Ni metal layer is patterned using photolithography and RIE techniques. Subsequently, a rapid heat treatment (RTA) is performed in an N2 gas atmosphere at a temperature between 900°C and 1000°C, for example, around 950°C, for about 3 minutes. In this way, a silicide (NiSi) is selectively deposited on the upper surfaces of the source contact hole and drain contact hole, although not shown in the diagram. xA contact layer made of a film is formed. By means of a sputtering method, a vacuum evaporation method, etc., a metal film such as Al with a thickness of about 100 nm is deposited, and the Al metal film is patterned by photolithography technology, dry etching, etc. to form gate electrodes (7, 8), a source electrode 9a, and a drain electrode 9b. As a result, an insulated gate type electrode structure (5, 7, 8) is formed on the upper surface of the channel formation region 3 via a nitride termination layer 6 so as to straddle a part of the ends of the source region 4a and the drain region 4b. In this way, the MOSFET of Example 1 is completed as an insulated gate type semiconductor device according to the embodiment shown in FIG. 1.

[0032] <Evaluation of MOSFET> As Example 2 of the semiconductor device according to the embodiment, an n-channel MOSFET was fabricated in the same process as in Example 1 except that Al, which is a p-type impurity doped in the channel formation region 3, was set to a concentration of 1.5×10 16 cm -3 . Also, for comparison with Examples 1 and 2, a comparative example having a doped polysilicon film of a conventional structure without a conductive oxide film as a gate electrode 8b was fabricated in the same manner as shown in FIG. 8. For the n-channel MOSFETs of Examples 1, 2, and the comparative example fabricated in this way, the transistor characteristics were measured and the field-effect mobility and the threshold voltage were evaluated.

[0033] FIG. 9 shows the evaluation results of the maximum field-effect mobility and the threshold voltage of Example 1, Example 2, and the comparative example. As shown in FIG. 9, in Example 1, the field-effect mobility is almost the same as that of the comparative example in which a conductive oxide film is not used for the gate electrode, but a significant increase in the threshold voltage was confirmed. In Example 2, since the channel formation region 3 has a low impurity concentration, the threshold voltage is lower than that in Example 1 and is about the same as that of the comparative example, but the field-effect mobility shows a higher value than that of Example 1 and the comparative example. Thus, according to the semiconductor device according to the embodiment, by using a conductive oxide film with a high work function for the main gate electrode 7, it is possible to realize a high threshold voltage and a high field-effect mobility.

[0034] In the semiconductor device according to this embodiment, a conductive oxide film is used as the main gate electrode 7. During operation of the semiconductor device, the chip temperature rises, and oxygen is removed from the conductive oxide film through a reaction with the conductive film used for the sub-gate electrode 8, which may make it impossible to stably maintain the work function of the conductive oxide film. To maintain the work function of the main gate electrode 7, a barrier metal layer 10 made of titanium nitride (TiN) or titanium (Ti), which has excellent thermal stability, may be provided between the main gate electrode 7 and the sub-gate electrode 8, as shown in Figure 10. When a barrier metal layer 10 is provided, it is also possible to use a highly reactive metal film such as Al as the sub-gate electrode 8.

[0035] (Other embodiments) As described above, an insulated gate semiconductor device according to an embodiment of the present invention has been described, but the discussion and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0036] As described above, in the semiconductor device according to the embodiment of the insulated gate type semiconductor device, a lateral MOSFET using 4H-SiC was exemplified, but it is also possible to apply it to semiconductor devices using 6H-SiC and 3C-SiC. Furthermore, it is also possible to apply it to planar gate vertical MOSFETs and trench gate vertical MOSFETs.

[0037] Thus, the present invention naturally includes various embodiments not described herein, such as configurations that arbitrarily apply the configurations described in the above embodiments and each of their modifications. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable based on the above description. [Explanation of symbols]

[0038] 1, 2... Substrate (SiC substrate) 3…Channel formation region (base region) 4a...Source area (first main area) 4b...Drain region (second main region) 5…Gate Insulator 6… Nitriding Termination Layer 7…Gate electrode (control electrode) 9a... Source electrode 9b...Drain electrode 9…Surface Gate 10… Barrier metal layer

Claims

1. A gate insulating film made of a silicon oxide film is provided on the upper surface of a channel-forming region made of silicon carbide, A nitride-terminated layer, in which silicon is terminated with nitrogen, is provided at the interface between the channel-forming region and the gate insulating film, A main gate electrode, which includes a conductive oxide film provided on the gate insulating film and controlling the surface potential of the channel formation region, A secondary gate electrode containing a conductor with higher conductivity than the conductive oxide film is provided on the main gate electrode. Equipped with, An insulated gate semiconductor device characterized in that the thickness of the main gate electrode is 5 nm or more and 100 nm or less, and the thickness of the sub gate electrode is 100 nm or more and 300 nm or less.

2. A gate insulating film made of a silicon oxide film provided on the upper surface of a channel-forming region made of silicon carbide, A nitride-terminated layer, in which silicon is terminated with nitrogen, is provided at the interface between the channel-forming region and the gate insulating film, A main gate electrode, which includes a conductive oxide film provided on the gate insulating film and controlling the surface potential of the channel formation region, A secondary gate electrode containing a conductor with higher conductivity than the conductive oxide film is placed on the main gate electrode, A barrier metal layer provided between the main gate electrode and the secondary gate electrode. An insulated gate semiconductor device characterized by having the following features.

3. The conductive oxide film is WO ３－ｘ An insulated gate semiconductor device according to claim 1 or 2, characterized by containing tungsten oxide (0 ≤ x < 1).

4. The conductive oxide film is MoO ３－ｘ An insulated gate semiconductor device according to claim 1 or 2, characterized by containing molybdenum oxide consisting of (0 < x ≤ 1).

5. The insulated gate semiconductor device according to any one of claims 1 to 4, characterized in that the conductive oxide film has a work function of 6 eV or more.

6. The insulated gate type semiconductor device according to any one of claims 1 to 5, characterized in that the secondary gate electrode is made of polysilicon, nickel, titanium, molybdenum, or tungsten.

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