Semiconductor module

Abstract

The present invention improves the adhesion between a bonding section of a metal wiring plate and a sealing resin in a semiconductor module. This semiconductor module (1) has: a layered substrate (2) in which a plurality of circuit plates (22) are disposed on an upper surface of an insulating plate (20); a semiconductor element (3) disposed on the upper surface of at least one circuit plate; and a metal wiring plate (4) disposed on the upper surface of the semiconductor element. The metal wiring plate has: a plate-like bonding section (40) bonded to the upper surface of the semiconductor element with a bonding material (S3) therebetween; and a plurality of roughening recess sections (45) which roughen the upper surface of the bonding section, wherein each of the plurality of roughening recess sections has a hexagonal shape when viewed in a plan view.

Description

Technical Field

[0001] The present invention relates to a semiconductor module.

Background Art

[0002] A semiconductor module has a substrate provided with semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a FWD (Free Wheeling Diode), and is used in an inverter device or the like.

[0003] In this type of semiconductor module, for example, in Patent Documents 1-3, semiconductor elements are arranged on an insulating substrate (which may be called a laminated substrate), and a metal wiring board (which may be called a lead frame) for wiring is arranged on the upper surface electrode of the semiconductor element. The metal wiring board is formed into a predetermined shape by pressing, for example, a metal plate. One end of the metal wiring board is electrically joined to the upper surface electrode via a joining material such as solder.

[0004] In a semiconductor module, a sealing resin is filled inside a case member, and the internal structure including the metal wiring board is covered with the sealing resin. In order to improve the adhesion strength of the sealing resin to the metal wiring board, in Patent Document 4, a groove in the shape of an ant groove whose opening part is narrower than the width of the bottom is formed in the metal wiring board, and in Patent Document 5, a plurality of lattice-shaped grooves are formed in the metal wiring board.

[0005] In Patent Documents 6-9, it is described that a plurality of dimples are formed on the surface of the metal wiring board, and protrusions (return parts, return sections, key parts) are provided on the inner walls of the dimples to improve the adhesion strength of the sealing resin. As a method of forming such dimples, a hole is formed by the first pressing process, and the second pressing process is performed on the periphery of the hole to deform a part of the hole and project the protrusion on the inner wall.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-088448 [Patent Document 2] Japanese Patent Publication No. 2016-139635 [Patent Document 3] Japanese Patent Publication No. 2015-176871 [Patent Document 4] Japanese Patent Application Publication No. 6-163773 [Patent Document 5] Japanese Patent Publication No. 2021-077718 [Patent Document 6] Japanese Patent Application Publication No. 7-273270 [Patent Document 7] Japanese Patent Publication No. 2005-191178 [Patent Document 8] Japanese Patent Publication No. 2017-005124 [Patent Document 9] Japanese Patent Publication No. 2007-258587 [Overview of the project] [Problems that the invention aims to solve]

[0007] Incidentally, in this type of semiconductor module, the power semiconductor element generates heat during switching operation. In the structure described above, where a metal wiring board is soldered to the surface of the power semiconductor element, fluctuations in internal stress caused by temperature changes may cause distortion at the joint. As a result, it is conceivable that the adhesion of the sealing resin to the joint portion of the metal wiring board may decrease.

[0008] This invention has been made in view of the above, and one of its objectives is to provide a semiconductor module that can improve the adhesion between the joint of a metal wiring board and the sealing resin. [Means for solving the problem]

[0009] A semiconductor module according to one aspect of the present invention includes a laminated substrate having a plurality of circuit boards arranged on an upper surface of an insulating board, a semiconductor element arranged on an upper surface of at least one of the circuit boards, and a metal wiring board arranged on an upper surface of the semiconductor element. The metal wiring board has a plate-shaped bonding portion bonded to the upper surface of the semiconductor element via a bonding material, and has a plurality of roughened recesses for roughening the upper surface of the bonding portion. The plurality of roughened recesses are each hexagonal in plan view.

Advantages of the Invention

[0010] According to the present invention, it is possible to improve the adhesion between the bonding portion of the metal wiring board and the sealing resin in the semiconductor module.

Brief Description of the Drawings

[0011] [Figure 1] It is a schematic view of the semiconductor device according to the present embodiment as viewed from above. [Figure 2] It is a cross-sectional view of the semiconductor device shown in FIG. 1 cut along the line A-A. [Figure 3] It is an enlarged view of the metal wiring board according to the present embodiment. [Figure 4] It is a plan view showing a specific example of a semiconductor module to which the metal wiring board according to the present embodiment is applied. [Figure 5] It is an equivalent circuit diagram of the semiconductor device according to the present embodiment. [Figure 6] It is a plan view of the first bonding portion of the metal wiring board shown in FIG. 3 when viewed in the direction of arrow B. [Figure 7] It is a cross-sectional view cut along the line C-C of FIG. 6. [Figure 8] It is an enlarged view of the D portion of FIG. 6. [Figure 9] It is an enlarged view of the D portion of FIG. 6. [Figure 10] It is a plan view showing a first modification example of the roughened recess provided in the first bonding portion of the metal wiring board. [Figure 11] It is a plan view showing a second modification example of the roughened recess provided in the first bonding portion of the metal wiring board.

Best Mode for Carrying Out the Invention

[0012] Hereinafter, a semiconductor module and a semiconductor device to which the present invention is applicable will be described. First, referring to FIGS. 1 to 5, the overall semiconductor module and semiconductor device, and the schematic configuration of the metal wiring board included in the semiconductor module and semiconductor device will be described. FIG. 1 is a schematic view of the semiconductor device according to the present embodiment as viewed from above. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 cut along the line A-A. FIG. 3 is an enlarged view of the metal wiring board according to the present embodiment. FIG. 4 is a plan view showing a specific example of a semiconductor module to which the metal wiring board according to the present embodiment is applied. FIG. 5 is an equivalent circuit diagram of the semiconductor device according to the present embodiment. Here, as the semiconductor element 3, a configuration in which an inverse parallel circuit of an IGBT and an FWD is connected in series is adopted.

[0013] Also, in the following figures, the longitudinal direction of the semiconductor module (cooler) will be defined as the X direction, the short-side direction of the semiconductor module (cooler) will be defined as the Y direction, and the height direction (thickness direction of the substrate) will be defined as the Z direction. Also, the longitudinal direction of the semiconductor module indicates the direction in which a plurality of circuit boards are arranged. The illustrated X, Y, and Z axes are orthogonal to each other and form a right-handed system. Also, in some cases, the X direction may be referred to as the left-right direction, the Y direction may be referred to as the front-back direction, and the Z direction may be referred to as the up-down direction. These directions (front-back, left-right, up-down directions) are expressions used for convenience of explanation, and depending on the mounting posture of the semiconductor module, the correspondence with each of the XYZ directions may change. For example, the heat dissipation surface side (cooler side) of the semiconductor module will be referred to as the lower surface side, and the opposite side will be referred to as the upper surface side. Also, in this specification, a plan view means a case where the upper surface or the lower surface of the semiconductor module is viewed from the Z direction. Also, the aspect ratios in each drawing and the size relationships between each member are only represented by schematic diagrams, and thus do not necessarily match. For convenience of explanation, it is also assumed that the size relationships between each member are exaggerated.

[0014] The semiconductor device 100 according to this embodiment is applicable to power conversion devices such as inverters for industrial or automotive motors. As shown in Figures 1 and 2, the semiconductor device 100 is configured by placing a semiconductor module 1 on the upper surface of a cooler 10. The cooler 10 can be configured in any way with respect to the semiconductor module 1.

[0015] The cooler 10 releases heat from the semiconductor module 1 to the outside and has a rectangular parallelepiped shape overall. Although not specifically shown in the figures, the cooler 10 is constructed by providing multiple fins on the underside of a base plate and housing these fins in a water jacket. However, the cooler 10 is not limited to this configuration and can be modified as appropriate.

[0016] The semiconductor module 1 is constructed by arranging a laminated substrate 2, semiconductor elements 3, and metal wiring boards 4, etc., inside a case 11.

[0017] The laminated substrate 2 is composed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate. The laminated substrate 2 is constructed by stacking an insulating plate 20, a heat sink 21, and a plurality of circuit boards 22, and is formed in a rectangular shape when viewed from above.

[0018] Specifically, the insulating plate 20 is formed as a plate-like body having an upper surface and a lower surface, and has a rectangular shape in plan view that is elongated in the X direction. The insulating plate 20 may be formed from ceramic materials such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or aluminum oxide (Al2O3) and zirconium oxide (ZrO2).

[0019] Furthermore, the insulating plate 20 may be formed from, for example, a thermosetting resin such as epoxy resin or polyimide resin, or a composite material using glass or ceramic material as a filler in a thermosetting resin. Preferably, the insulating plate 20 is flexible and may be formed from a material containing, for example, a thermosetting resin. The insulating plate 20 may also be called an insulating layer or insulating film.

[0020] The heat sink 21 has a predetermined thickness in the Z direction and a rectangular shape in plan view that is long in the Y direction. The heat sink 21 is made of a metal plate with good thermal conductivity, such as copper or aluminum. The heat sink 21 is placed on the lower surface of the insulating plate 20. The lower surface of the heat sink 21 is the mounting surface to the cooler 10, which is the mounting site for the semiconductor module 1, and also functions as a heat dissipation surface (heat dissipation area) for releasing heat from the semiconductor module 1. The heat sink 21 is joined to the upper surface of the cooler 10 via a bonding material S1 such as solder. The heat sink 21 may also be placed on the upper surface of the cooler 10 via a thermal conductive material such as thermal grease or thermal compound.

[0021] Multiple circuit boards 22 each have a predetermined thickness and are arranged on the upper surface of the insulating board 20. Each circuit board 22 is formed in an electrically independent island shape. For example, a circuit board 22 has a rectangular shape in plan view and is arranged in a line in the X direction on the insulating board 20. Note that the number of circuit boards 22 is not limited to two as shown in Figure 1, and can be changed as appropriate. Three or more circuit boards 22 may be arranged on the insulating board 20 as shown in Figure 4. Furthermore, the shape, arrangement, etc., of the circuit boards 22 are not limited to these and can be changed as appropriate. These circuit boards 22 are formed from metal plates with good thermal conductivity, such as copper or aluminum. The circuit boards 22 may also be called circuit layers or circuit patterns.

[0022] A semiconductor element 3 is arranged on the upper surface of a predetermined circuit board 22 (the circuit board 22 on the negative side in the X direction) via a bonding material S2 such as solder. The semiconductor element 3 is formed in a rectangular shape in plan view using a semiconductor substrate such as silicon (Si) or silicon carbide (SiC). The semiconductor element 3 may be a power semiconductor element. Switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes such as FWDs (Free Wheeling Diodes) can be used as semiconductor elements 3.

[0023] In this embodiment, the semiconductor element 3 is composed of an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0024] The semiconductor element 3 is not limited to those described above and may be constructed by combining the switching elements, diodes, etc. For example, the IGBT element and the FWD element may be constructed separately. Also, an RB (Reverse Blocking)-IGBT with sufficient voltage resistance against reverse bias may be used as the semiconductor element 3. Furthermore, the shape, number, and placement of the semiconductor element 3 can be changed as appropriate.

[0025] Furthermore, the semiconductor element 3 has electrodes (not shown) formed on its upper and lower surfaces. For example, the upper electrode is composed of an emitter electrode (source electrode) or a gate electrode, and the lower electrode is composed of a collector electrode (drain electrode).

[0026] In this embodiment, the semiconductor element 3 is a so-called vertical switching element in which the above-described functional elements are formed on a semiconductor substrate, but it is not limited to this and may also be a horizontal switching element.

[0027] A metal wiring board 4 is placed on the upper surface of the semiconductor element 3. The metal wiring board 4 is composed of a plate-like body having an upper surface and a lower surface, and is formed from a metal material such as copper, copper alloy, aluminum alloy, or iron alloy. The metal wiring board 4 is formed into a predetermined shape, for example, by press working. Note that the shape of the metal wiring board 4 shown below is merely an example and can be changed as appropriate. The metal wiring board may also be called a lead frame.

[0028] The metal wiring board 4 according to this embodiment is a long body that extends in the X direction so as to straddle a plurality of circuit boards 22 in a plan view, and has a crank shape that is bent multiple times in a side view. Specifically, as shown in Figures 2 and 3, the metal wiring board 4 is composed of a first joint portion 40 that is joined to the upper surface (upper electrode) of the semiconductor element 3 via a bonding material S3, a second joint portion 41 that is joined to the upper surface of the circuit board 22 on the positive X side via a bonding material S4, and a connecting portion 42 that connects the first joint portion 40 and the second joint portion 41.

[0029] The width of the metal wiring board 4 in the Y direction is uniform from the first joint 40 to the second joint 41. Furthermore, the first joint 40, the second joint 41, and the connecting portion 42 are arranged in a line along the X direction in a plan view. However, the width of the metal wiring board 4 in the Y direction does not need to be uniform from the first joint 40 to the second joint 41; as shown in Figure 4, they may have different widths. Also, the first joint 40, the second joint 41, and the connecting portion 42 do not need to be arranged in a line; as shown in Figure 4, they may be arranged diagonally offset from each other.

[0030] The first joint portion 40 is formed in a rectangular shape smaller than the outer shape of the semiconductor element 3 in a plan view and includes a plate-like portion having an upper surface and a lower surface. At the end of the first joint portion 40 on the positive X-direction side (connecting portion 42 side), a first bent portion 43 is formed that bends at approximately a right angle and rises upward. One end (left end) of the connecting portion 42 is connected to the upper end of the first bent portion 43.

[0031] The second joint 41 is formed in a rectangular shape smaller than the outer shape of the circuit board 22 in a plan view and includes a plate-like portion having an upper surface and a lower surface. At the end of the second joint 41 on the negative X-direction side (connecting portion 42 side), a second bent portion 44 is formed that bends at approximately a right angle and rises upward. The other end (right end) of the connecting portion 42 is connected to the upper end of the second bent portion 44.

[0032] The connecting portion 42 extends horizontally, with one end connected to the first bent portion 43 and the other end connected to the second bent portion 44, as described above.

[0033] The length of the first bent portion 43 in the Z direction is shorter than that of the second bent portion 44 by the thickness of the semiconductor element 3. In other words, the first joint portion 40 and the second joint portion 41 are located at different heights. More specifically, the first joint portion 40 is located at a higher position than the second joint portion 41.

[0034] The shape, number, and placement of the metal wiring boards 4 described above are merely examples and can be modified as appropriate without limitation. As will be described in detail later, as shown in Figure 4, multiple (for example, four) metal wiring boards 4 may be arranged for a single semiconductor module. In this embodiment, the semiconductor elements 3, metal wiring boards 4, and the main terminals described later form an inverter circuit, for example, as shown in Figure 5.

[0035] The laminated substrate 2, semiconductor element 3, and metal wiring board 4 are surrounded by a case 11. The case 11 has a rectangular annular cylindrical or frame shape in plan view and is formed of, for example, synthetic resin. The case 11 may be formed of, for example, a thermosetting resin material such as epoxy resin or silicone rubber. The lower end of the case 11 is bonded to the upper surface of the cooler 10 via adhesive (not shown), and the upper end extends to a position sufficiently higher than the upper surface of the metal wiring board 4. In this way, the case 11 surrounds the laminated substrate 2, semiconductor element 3, and metal wiring board 4, defining a space for housing the laminated substrate 2, semiconductor element 3, and metal wiring board 4.

[0036] The internal space defined by case 11 is filled with sealing resin 5. The sealing resin 5 may be filled up to the top edge of case 11. This seals the laminated substrate 2, semiconductor element 3, and metal wiring board 4. The entire metal wiring board 4 is covered with sealing resin 5.

[0037] The sealing resin 5 may be composed of, for example, a thermosetting resin. Preferably, the sealing resin 5 contains at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamideimide. For example, epoxy resin mixed with filler is preferred for the sealing resin 5 from the viewpoint of insulating properties, heat resistance, and heat dissipation.

[0038] Furthermore, as shown in the specific example in Figure 4, the case 11 may be provided with a plurality of main terminals 60 for the main current and a plurality of control terminals 61 for control. The main terminals 60 are formed as long, plate-shaped bodies and are embedded in the side walls of the case 11. In Figure 4, two main terminals 60 constituting the N terminal and P terminal are arranged side by side in the X direction on the side wall of the case 11 located on the negative side in the Y direction. In addition, a main terminal 60 constituting the M terminal is arranged on the side wall of the case 11 located on the positive side in the Y direction.

[0039] As described above, in this embodiment, an inverter circuit like the one shown in Figure 5 is formed by the semiconductor element 3, the metal wiring board 4, and the main terminals 60, etc. These main terminals 60 (N terminal, P terminal, M terminal) correspond to IN(N) (which may also be called the low-potential input terminal or negative terminal), IN(P) (which may also be called the high-potential input terminal or positive terminal), and OUT(M) (which may also be called the output terminal or intermediate terminal) in Figure 5, respectively.

[0040] Furthermore, the control terminal 61 is formed as a long, plate-like body and is embedded in the side wall of the case 11 located on the positive side in the Y direction. The control terminal 61 is electrically connected to a predetermined control electrode of the semiconductor element 3 via a wiring member such as a bonding wire. These main terminals 60 and control terminals 61 are formed from metal materials such as copper, copper alloys, aluminum alloys, and iron alloys, and have predetermined electrical conductivity and predetermined mechanical strength. The shape, number, and arrangement of the main terminals 60 and control terminals 61 are not limited to these and can be changed as appropriate.

[0041] Incidentally, in semiconductor modules, it is necessary to prevent delamination from progressing along the interface between the metal wiring board and the sealing resin. One way to reduce delamination is to increase the surface area of ​​the metal wiring board and improve the adhesion (anchor effect) between the metal wiring board and the sealing resin. One way to increase the surface area of ​​the metal wiring board is to create an uneven surface to roughen it.

[0042] In this embodiment, a configuration is used to roughen the upper surface of a metal wiring board by providing roughened recesses. The arrangement density of the multiple roughened recesses is increased, and the peeling of the sealing resin from the metal wiring board is made less likely to progress, thereby improving the anchoring effect compared to conventional structures.

[0043] Specifically, in this embodiment, the upper surface of the first joint 40 of the metal wiring board 4 constituting the semiconductor module 1 is targeted for roughening. Figure 6 is a plan view of the first joint 40 of the metal wiring board 4 shown in Figure 3, viewed in the direction of arrow B. Figure 7 is a cross-sectional view taken along line CC in Figure 6. Figures 8 and 9 are enlarged views of portion D in Figure 6.

[0044] As shown in Figure 6, the first joint portion 40, which is rectangular in plan view, has a tip edge 40a at the tip end in the X direction (the end opposite to the connecting portion 42), and a boundary portion 40b at the end opposite to the tip edge 40a in the X direction, which forms the boundary with the first bent portion 43. The tip edge 40a and the boundary portion 40b are both linear in shape and extend in the Y direction. The first joint portion 40 also has a pair of lateral edges 40c and 40d that extend in the X direction and connect the ends of the tip edge 40a and the boundary portion 40b. The tip edge 40a, the boundary portion 40b, the lateral edges 40c and 40d constitute the outer edge of the first joint portion 40, which is rectangular in plan view.

[0045] As shown in Figure 6, the upper surface of the first joint 40 is roughened by providing multiple roughened recesses 45. Each roughened recess 45 is hexagonal in plan view. Delamination at the interface between the first joint 40 and the sealing resin 5 tends to occur from the edges (outer edges) of the first joint 40. As will be described in detail later, the hexagonal roughened recesses 45 can be arranged at high density, and by providing roughened recesses 45 evenly across the upper surface of the first joint 40, it is possible to suppress the progression of delamination that occurs at the edges of the first joint 40 toward the inner region of the first joint 40.

[0046] As shown in Figure 7, each roughened recess 45 is a bottomed recess having a base surface 45a at one end (downward) in the Z direction and opening at the other end (upward) in the Z direction to the upper surface of the first joint 40. The base surface 45a is a regular hexagon and has six inner wall surfaces 45b extending in the Z direction from each of the six sides of the base surface 45a. In other words, each roughened recess 45 has a hexagonal prism shape enclosed by the base surface 45a and the six inner wall surfaces 45b. All of the roughened recesses 45 have the same shape, size, and depth.

[0047] As shown in Figure 7, a coating film F may be interposed at the interface between the upper surface of the first joint 40 and the sealing resin 5.

[0048] By providing multiple roughened recesses 45, the upper surface of the first joint 40 is roughened, increasing its surface area and improving the adhesion (anchor effect) between the upper surface of the first joint 40 and the sealing resin 5. Furthermore, as shown in Figure 7, it is preferable that the sealing resin 5 is contained within the roughened recesses 45. This allows for an even greater anchoring effect. Therefore, it is possible to suppress the delamination and progression of the sealing resin 5 on the upper surface of the metal wiring board 4 above the semiconductor element 3 due to thermal stress.

[0049] The arrangement of the multiple roughened recesses 45 will now be described in detail. As shown in Figure 8, the multiple roughened recesses 45 are arranged so that their centers lie on grid points Q of a hexagonal grid (equilateral triangular grid) in a plan view, and are oriented in the same direction. Therefore, two adjacent roughened recesses 45 are arranged so that their nearest inner wall surfaces 45b are parallel to each other. There is a predetermined gap K between two adjacent roughened recesses 45 (between the nearest inner wall surfaces 45b). The multiple roughened recesses 45 are arranged at equal intervals across the entire upper surface of the first joint 40 so that the gap K is uniform.

[0050] By applying hexagonal roughened recesses 45 in plan view, the roughened recesses 45 can be arranged at high density on the upper surface of the first joint 40. In particular, by positioning the center of each roughened recess 45 on a grid point Q of the hexagonal grid in plan view, and arranging multiple roughened recesses 45 in the same orientation, the spacing K between the roughened recesses 45 can be narrowed, making it possible to form a large number of roughened recesses 45 on the upper surface of the first joint 40 in a space-efficient manner. Therefore, compared to the case where roughened recesses with a rectangular shape in plan view are used, an improvement in the anchoring effect due to surface roughening can be achieved.

[0051] Furthermore, this embodiment not only has a high density of roughened recesses 45, but also excels at preventing the progression of peeling of the sealing resin 5 from the metal wiring board 4 for the reasons described below.

[0052] The upper surface of the first joint 40 has multiple rows of roughened recesses, each consisting of multiple roughened recesses 45 spaced apart in a first direction. The first direction is the direction in which any straight line parallel to the upper surface of the first joint 40 extends. Two adjacent rows of roughened recesses are positioned with the positions of their roughened recesses 45 offset from each other in the first direction, and have overlapping regions (overlapping regions) in a second direction perpendicular to the first direction, where parts of their roughened recesses 45 overlap.

[0053] Referring to Figure 9, the rows of roughened recesses and overlapping regions will be explained. For example, the X direction is considered the first direction, and the Y direction is considered the second direction. Multiple roughened recesses 45 arranged at intervals (interval K) in the X direction are called rows of roughened recesses 45X. In Figure 9, a series of roughened recesses 45 included in each row of roughened recesses 45X is represented by being enclosed in a dashed-dot frame. In the row of roughened recesses 45X, the distance between the centers of the roughened recesses 45 arranged in the X direction is called the pitch RX.

[0054] As shown in Figure 9, two rows of roughened recesses 45X adjacent in the Y direction are arranged with the positions of their roughened recesses 45 offset in the X direction. More specifically, two rows of roughened recesses 45X adjacent in the Y direction are arranged alternately with the positions of their roughened recesses 45 offset in the X direction by a distance of half the pitch RX (half-pitch). This makes it possible to bring two adjacent rows of roughened recesses 45X closer together in the Y direction. The two adjacent rows of roughened recesses 45X are arranged so that one roughened recess 45 of one row of roughened recesses 45X fits between two roughened recesses 45 of the other row of roughened recesses 45X. As a result, two rows of roughened recesses 45X adjacent in the Y direction have an overlapping region Va in the intermediate region in the Y direction where parts of each other's roughened recesses 45 exist alternately. The overlapping region Va is an elongated region with a predetermined width in the Y direction and extending in the X direction.

[0055] In the formation region of each row of roughened recesses 45X, multiple roughened recesses 45 are arranged in the X direction, so the peeling of the sealing resin 5 from the metal wiring board 4 in the X direction can be suppressed. In addition, there is an overlap region Va between two adjacent rows of roughened recesses 45X in the Y direction, and in the overlap region Va, parts of the multiple roughened recesses 45 of the two rows of roughened recesses 45X are arranged alternately, so the peeling of the sealing resin 5 from the metal wiring board 4 in the X direction can be suppressed. Therefore, in the area targeted for roughening on the upper surface of the first joint 40, roughened recesses 45 are always arranged on a straight line extending in the arbitrarily set X direction, and there are no areas where the entire X direction is a non-roughened region (an area where roughened recesses 45 have not been formed).

[0056] Next, we will explain the case where the Y direction is the first direction and the X direction is the second direction. Multiple roughened recesses 45 arranged at intervals in the Y direction are called roughened recess rows 45Y. In Figure 9, a series of roughened recesses 45 included in each roughened recess row 45Y are represented by being enclosed in a dashed-dot frame. In the roughened recess row 45Y, the distance between the centers of the roughened recesses 45 arranged in the Y direction is called the pitch RY.

[0057] Two rows of roughened recesses 45Y adjacent to each other in the X direction are positioned with the positions of their roughened recesses 45 offset in the Y direction, resulting in an alternating arrangement where the positions are offset in the Y direction by half a pitch (half-pitch) of the pitch RY. This makes it possible to bring two adjacent rows of roughened recesses 45Y closer together in the X direction. The two adjacent rows of roughened recesses 45Y are positioned so that one roughened recess 45 of one row of roughened recesses 45Y fits between two roughened recesses 45 of the other row of roughened recesses 45Y. As a result, two rows of roughened recesses 45Y adjacent to each other in the X direction have an overlapping region Vb in the intermediate region in the X direction where parts of each other's roughened recesses 45 exist alternately. The overlapping region Vb is an elongated region with a predetermined width in the X direction and extending in the Y direction.

[0058] In the formation region of each row of roughened recesses 45Y, multiple roughened recesses 45 are arranged in the Y direction, so the peeling of the sealing resin 5 from the metal wiring board 4 in the Y direction can be suppressed. In addition, there is an overlapping region Vb between two adjacent rows of roughened recesses 45Y in the X direction, and in the overlapping region Vb, parts of the multiple roughened recesses 45 of the two rows of roughened recesses 45Y are arranged alternately, so the peeling of the sealing resin 5 from the metal wiring board 4 in the Y direction can be suppressed. Therefore, in the area of ​​roughening on the upper surface of the first joint 40, roughened recesses 45 are always arranged on a straight line extending in the Y direction that is arbitrarily set, and there are no areas in the Y direction that are entirely non-roughened regions (areas where roughened recesses 45 are not formed).

[0059] Furthermore, in this embodiment, the roughened recesses 45 are always located not only on any straight line extending in the X direction and any straight line extending in the Y direction, but also on any straight line extending in a direction intersecting the X and Y directions (diagonal direction), and there are no areas where the entire diagonal direction is a non-roughened region (an area where roughened recesses 45 are not formed).

[0060] For example, as an example of an oblique direction, Figure 9 shows an oblique direction T1. The direction perpendicular to the oblique direction T1 is denoted as the orthogonal direction T2. ​​The oblique direction T1 is inclined at 60° (120°) with respect to the X direction and 30° (150°) with respect to the Y direction. We will now explain the case where the oblique direction T1 is the first direction and the orthogonal direction T2 is the second direction. Multiple roughened recesses 45 arranged at intervals in the oblique direction T1 are called roughened recess rows 45T. In Figure 9, a series of roughened recesses 45 included in each roughened recess row 45T are represented by being enclosed in a frame with a dashed line. In the roughened recess rows 45T, the distance between the centers of the roughened recesses 45 arranged in the direction of the oblique direction T1 is called the pitch RT.

[0061] Two rows of roughened recesses 45T adjacent to each other in the orthogonal direction T2 are positioned with the positions of their roughened recesses 45 offset from each other in the diagonal direction T1, in an alternating arrangement with the positions offset by half a pitch (half-pitch) in the diagonal direction T1. This makes it possible to bring two adjacent rows of roughened recesses 45T closer together in the orthogonal direction T2. ​​The two adjacent rows of roughened recesses 45T are positioned closer together in the orthogonal direction T2 such that one roughened recess 45 of one row of roughened recesses 45T fits between two roughened recesses 45 of the other row of roughened recesses 45T. As a result, two rows of roughened recesses 45T adjacent to each other in the orthogonal direction T2 have an overlapping region Vc in the intermediate region of the orthogonal direction T2 where parts of each other's roughened recesses 45 alternately exist. The overlapping region Vc has a predetermined width in the orthogonal direction T2 and is an elongated region extending in the diagonal direction T1.

[0062] In the formation region of each row of roughened recesses 45T, multiple roughened recesses 45 are arranged in an oblique direction T1, so the peeling of the sealing resin 5 from the metal wiring board 4 in the oblique direction T1 can be suppressed. In addition, there is an overlap region Vc between two rows of roughened recesses 45T adjacent to each other in the orthogonal direction T2, and in the overlap region Vc, parts of the multiple roughened recesses 45 of the two rows of roughened recesses 45T are arranged alternately, so the peeling of the sealing resin 5 from the metal wiring board 4 in the oblique direction T1 can be suppressed. Therefore, in the area of ​​roughening target on the upper surface of the first joint 40, roughened recesses 45 are always located on a straight line extending in an arbitrarily set oblique direction T1, and there are no areas where the entire oblique direction T1 is a non-roughened region (an area where roughened recesses 45 are not formed).

[0063] In Figure 9, the X direction, Y direction, and diagonal direction T1 are shown as examples of directions in which the non-roughened region is not continuous on the upper surface of the first joint 40 (first direction). However, in the arrangement structure of the roughened recess 45 of this embodiment, there are no locations in any direction within the range of roughening on the upper surface of the first joint 40 where the non-roughened region is continuous in a straight line.

[0064] For example, although details are omitted, even if the orthogonal direction T2 in Figure 9 is taken as the first direction and the diagonal direction T1 as the second direction, the same conditions as above (overlap of two adjacent rows of roughened recesses) are met, and the same effect can be obtained. In other words, in the area targeted for roughening on the upper surface of the first joint 40, roughened recesses 45 are always located on a straight line extending in the arbitrarily set orthogonal direction T2, and there are no areas where the entire orthogonal direction T2 is a non-roughened region (an area where roughened recesses 45 have not been formed).

[0065] Therefore, if delamination of the sealing resin 5 from the metal wiring board 4 occurs at the end (outer edge) of the first joint 40, the roughened recess 45 is present in any direction from that end toward the inside of the first joint 40, thus providing an effect to prevent the delamination from progressing.

[0066] In the embodiments shown in Figures 6 to 9, the individual roughened recesses 45, which form a hexagon in plan view, are arranged so that two of the six inner wall surfaces 45b are parallel to the Y direction. A modified example in which the roughened recesses 45 are arranged in a different orientation is shown in Figures 10 and 11.

[0067] The first modified example shown in Figure 10 is in which the individual roughened recesses 45, which form a hexagon in plan view, are arranged so that two of the six inner wall surfaces 45b are parallel to the X direction. In other words, the orientation of the individual roughened recesses 45 is rotated by 90° (270°) relative to the orientation of the roughened recesses 45 shown in Figure 6.

[0068] The second modification shown in Figure 11 involves arranging the individual roughened recesses 45, which form a hexagon in plan view, so that all six inner wall surfaces 45b are oriented so that they are not parallel to the X and Y directions. Specifically, the orientation of the individual roughened recesses 45 is rotated by 45° (135°) relative to the orientation of the roughened recesses 45 shown in Figure 6.

[0069] Both the first and second modified examples are similar to the above embodiment in that multiple roughened recesses 45 can be densely arranged on the upper surface of the first joint 40, and there are no areas where the unroughened area is linearly continuous in the area roughened by the multiple roughened recesses 45 (the roughened recesses 45 are always located on any straight line along the upper surface of the first joint 40). Therefore, the same effects as the above embodiment can be obtained.

[0070] In the second modified example shown in Figure 11, the six inner wall surfaces 45b of the roughened recess 45 are not parallel to the leading outer edge 40a, boundary 40b, lateral outer edge 40c, and lateral outer edge 40d of the first joint 40, resulting in a slight bias in the density of the roughened recesses 45 on the outer edge side of the first joint 40.

[0071] In contrast, in the embodiment shown in Figure 6, two of the six inner wall surfaces 45b of the roughened recess 45 are parallel to the tip outer edge 40a and boundary portion 40b of the first joint 40, and the roughened recess 45 is evenly distributed along the lateral outer edge 40c and lateral outer edge 40d. Furthermore, in the first modified example shown in Figure 10, two of the six inner wall surfaces 45b of the roughened recess 45 are parallel to the lateral outer edge 40c and lateral outer edge 40d of the first joint 40, and the roughened recess 45 is evenly distributed along the tip outer edge 40a and boundary portion 40b.

[0072] Therefore, when the first joint 40, which is rectangular in plan view, is to be roughened, considering the efficiency of arranging the roughened recesses 45 near the end (outer edge) of the first joint 40, it is preferable to arrange the multiple roughened recesses 45 such that two of the six inner wall surfaces 45b are oriented parallel to the end (outer edge) of the first joint 40.

[0073] As described above, the configuration of this embodiment and its modified examples provides a high effect in preventing the sealing resin 5 from peeling off the upper surface of the first joint portion 40 of the metal wiring board 4, and improves the adhesion between the metal wiring board 4 and the sealing resin 5. The multiple roughened recesses 45 that roughen the upper surface of the first joint portion 40 are each simple hexagonal shapes in plan view, which has the advantage of being easy to form on the metal wiring board 4 at low cost. For example, the roughened recesses 45 can be formed by press working on the metal wiring board 4.

[0074] Since the semiconductor element 3, which is a heat source, is located directly below the first joint 40, the first joint 40 is greatly affected by the anchoring effect due to surface roughening. Therefore, it is desirable to provide a plurality of roughened recesses 45 on the upper surface of at least the first joint 40 of the metal wiring board 4.

[0075] For the parts of the metal wiring board 4 other than the first joint 40, namely the connecting portion 42, the first bend portion 43, and the second bend portion 44, the influence on the peeling of the sealing resin 5 is smaller compared to the first joint 40, so the presence or absence of roughened recesses 45 can be appropriately selected. For example, by roughening only the first joint 40, the processing cost of the metal wiring board 4 can be reduced. In this case, the surfaces of the second joint 41, the connecting portion 42, the first bend portion 43, and the second bend portion 44 are flat, and their surface roughness may be the same as the surface roughness of the lower surface of the first joint 40.

[0076] In the above embodiment, multiple roughened recesses 45 are arranged at equal intervals across substantially the entire upper surface of the first joint portion 40 of the metal wiring board 4. However, a portion of the upper surface of the first joint portion 40 may be a non-roughened region without roughened recesses 45. For example, when connecting wires to the upper surface of the first joint portion 40, the location where the wires are connected may be a non-roughened region. Furthermore, protrusions that project upward from the metal wiring board 4, or through holes that penetrate the upper and lower surfaces of the metal wiring board 4, can also be applied as non-roughened regions. In any case, roughened recesses 45 can be provided at high density around the non-roughened region, thus obtaining the above-mentioned effects of the roughened recesses 45.

[0077] In the above embodiment, the multiple roughened recesses 45 provided on the upper surface of the first joint 40 have the same depth in the Z direction. By making the depth of the multiple roughened recesses 45 the same, the roughening process is made easier, and the shape accuracy of the first joint 40 is made easier to control. However, the depth of the multiple roughened recesses is not limited, and it is also possible to adopt a configuration in which roughened recesses of different depths are mixed.

[0078] In the above embodiment, the multiple roughened recesses 45 provided on the upper surface of the first joint 40 are all the same size in plan view, but it is also possible to make some of the roughened recesses different in size. For example, in the second modified example shown in Figure 11, in the region near the outer edge along the tip outer edge 40a, boundary portion 40b, lateral outer edge 40c, and lateral outer edge 40d of the first joint 40, roughened recesses with a smaller area in plan view than the roughened recesses 45 may be arranged. This makes it possible to efficiently roughen the surface up to the vicinity of the outer edge of the first joint 40 while obtaining the above-mentioned effect of the roughened recesses 45.

[0079] Although this embodiment and its variations have been described, other embodiments may also be combinations of the above embodiment and its variations, either entirely or partially.

[0080] Furthermore, in the above embodiment, the number and placement of semiconductor elements are not limited to the above configuration and can be changed as appropriate.

[0081] Furthermore, in the above embodiment, the number and layout of the circuit boards are not limited to the above configuration and can be changed as appropriate.

[0082] Furthermore, although the above embodiment describes a configuration in which the laminated substrate and semiconductor elements are formed in a rectangular or square shape in plan view, the configuration is not limited to this. These configurations may be formed in polygonal shapes other than those described above.

[0083] Furthermore, this embodiment is not limited to the embodiments and modifications described above, and may be modified, substituted, or transformed in various ways without departing from the spirit of the technical idea. Moreover, if the technical idea can be realized in a different way by advances in the technology or by other derived technologies, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea.

[0084] The key features of the above embodiment are summarized below. The semiconductor module according to the above embodiment comprises a laminated substrate on which a plurality of circuit boards are arranged on the upper surface of an insulating board, a semiconductor element arranged on the upper surface of at least one of the circuit boards, and a metal wiring board arranged on the upper surface of the semiconductor element, wherein the metal wiring board has a plate-shaped joint portion joined to the upper surface of the semiconductor element via a bonding material, and has a plurality of roughening recesses that roughen the upper surface of the joint portion, and each of the plurality of roughening recesses is hexagonal in plan view.

[0085] Furthermore, the multiple roughened recesses are arranged such that their centers lie on the grid points of the hexagonal grid in a plan view of the joint, and they are all oriented in the same direction.

[0086] Furthermore, the upper surface of the joint has multiple rows of roughened recesses arranged at intervals in a first direction, where two adjacent rows of roughened recesses are positioned with the positions of their roughened recesses offset from each other in the first direction, and have overlapping regions in a second direction perpendicular to the first direction where parts of their roughened recesses overlap.

[0087] Furthermore, the joint is rectangular in plan view, and the first direction and the second direction include a direction parallel to the outer edge of the joint and a direction intersecting the outer edge of the joint.

[0088] Furthermore, the joint is rectangular in plan view, and each of the roughened recesses has six inner wall surfaces that form a hexagon in plan view, with two of them oriented parallel to the outer edge of the joint. [Industrial applicability]

[0089] As described above, the present invention has the effect of improving the adhesion between the joint portion of a metal wiring board and the sealing resin, and is particularly useful for semiconductor modules used in industrial or electrical equipment.

[0090] This application is based on Japanese Patent Application No. 2022-177079, filed on November 4, 2022. All of its contents are included here. [Explanation of symbols]

[0091] 1: Semiconductor module 2: Multilayer substrate 3: Semiconductor elements 4:Metal wiring board 5: Sealing resin 10:Cooler 11: Case 20: Insulating board 21: Heat sink 22: Circuit board 40: 1st joint (joint) 40a: Outer edge of tip (outer edge) 40b: Boundary (outer edge) 40c: Lateral outer edge (outer edge) 40d: Lateral outer edge (outer edge) 41:Second joint 42:Connection part 43: 1st bending part 44:Second bending part 45: Roughened recess 45a: Bottom 45b: Inner wall surface 45T: Rows of roughened recesses 45X: Rows of roughened recesses 45Y: Rows of roughened depressions 60: Main terminal 61: Control terminal 100: Semiconductor Device F: Coating film S1: Bonding material S2: Bonding material S3: Joining material S4: Joining material T1: Diagonal direction (first direction, second direction) T2: Orthogonal direction (first direction, second direction) VA: Overlap Region Vb: Overlap region Vc: Overlap region X: X direction (first direction, second direction) Y: Y direction (first direction, second direction)

Claims

1. A laminated substrate in which multiple circuit boards are arranged on the upper surface of an insulating board, A semiconductor element disposed on the upper surface of at least one of the circuit boards, The semiconductor element comprises a metal wiring board disposed on the upper surface of the semiconductor element, The metal wiring board has a plate-shaped joint portion joined to the upper surface of the semiconductor element via a bonding material, The upper surface of the joint has a plurality of roughening recesses, and each of the plurality of roughening recesses is hexagonal in plan view. The orientation of each of the six inner wall surfaces of the plurality of roughened recesses is different from the orientation of the outer edge of the joint. A semiconductor module wherein the roughened recess located in the outer edge region of the joint has a smaller area in plan view than the roughened recess located in regions other than the outer edge region.

2. The semiconductor module according to claim 1, wherein the plurality of roughened recesses are arranged such that their centers are located on the grid points of a hexagonal grid in a plan view of the joint, and are all oriented in the same direction.

3. The upper surface of the joint has a plurality of rows of roughened recesses, each of which is arranged at intervals in the first direction. The semiconductor module according to claim 1 or claim 2, wherein two adjacent rows of roughened recesses are arranged with the positions of the roughened recesses offset from each other in the first direction, and have overlapping regions in a second direction perpendicular to the first direction.

4. The semiconductor module according to claim 1, wherein the roughened recess is a bottomed hole having a bottom surface.

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