Silicon carbide MOSFET device and method for manufacturing the same

Abstract

The present application discloses a silicon carbide MOSFET device and a manufacturing method thereof, the silicon carbide MOSFET comprises a first voltage shield structure and a second voltage shield structure, which can improve the voltage resistance performance of the device, avoid the breakdown problem of the gate insulating dielectric layer, improve the device's resistance to electrostatic effects in harsh environments and high voltage spikes in circuits, and enhance the surge voltage resistance and overvoltage protection capability of the device; further, the first trench is used to implant ions to form the first voltage shield structure, and the second trench is used to implant ions to form the second voltage shield structure, which can realize a deep ion implantation area in the silicon carbide epitaxial layer without the need for high-dose, high-energy ion implantation, and has a simple manufacturing process and low manufacturing cost.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on May 6, 2022, with an application number of 202210484974.6 and an invention title of "Silicon Carbide MOSFET Device and Manufacturing Method Thereof", and all of its content is incorporated herein by reference. This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on May 6, 2022, with an application number of 202221074903.0 and an invention title of "Silicon Carbide MOSFET Device", and all of its content is incorporated herein by reference.

[0002] This application relates to the technical field of semiconductor devices, and more specifically, to silicon carbide MOSFET devices and manufacturing methods thereof.

Background Art

[0003] Due to its excellent properties, SiC material has strong attraction in high-power applications and has become one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and vertical gate trench-structured UMOSFETs.

[0004] As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a DMOSFET, including an N+ (N-type highly doped) base 2, an N- (N-type lightly doped) drift area 3 provided on the surface of the base 2, a P-type well area 4 located within the drift area 3, and a source area 5 located within the P-type well area. The source area 5 includes an N+ doped area 51 and a P+ (P-type highly doped) doped area 52, and a source 6 is provided on the surfaces of the N+ doped area 51 and the P+ doped area 52. A gate dielectric layer 7 is provided on the surface of the drift area 3, and a gate 8 is on the surface of the gate dielectric layer 7. A drain 1 is on the surface of the base 2 on the side away from the drift area 3.

[0005] The DMOSFET structure utilizes planar diffusion technology, using a high-melting-point material, such as a polysilicon gate, as a mask. The edges of the polysilicon gate define the P-base area and the N+ source area. The name DMOS originates from this dual diffusion process. Surface channel regions are formed by the difference in lateral diffusion between the P-type base area and the N+ source area.

[0006] As shown in Figure 2, Figure 2 is a schematic diagram of the structure of a UMOSFET, and the differences from the structure in Figure 1 are as follows: the UMOSFET is provided with a U-shaped groove, the surface of the U-shaped groove is covered with a gate dielectric layer 7, and the gate 8 is filled into the U-shaped groove. The name of the vertical gate trench structure UMOSFET comes from the U-shaped trench structure. This U-shaped trench structure is formed in the gate area by reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active area channel width), which significantly reduces the on-characteristic resistance of the device.

[0007] Following years of industry research, several manufacturers have taken the lead in launching commercial products for planar SiC MOSFETs. While modern technology allows for smaller MOS cell sizes in conventional lateral DMOSFET structures, it cannot reduce on-resistance. The main reason for this is the limitation of the JFET neck area resistance; even with smaller photolithography sizes, the on-resistance per unit area remains around 2 mΩ·cm. 2 The resistance is less likely to decrease, and a trench structure can effectively solve this problem. As shown in Figure 2, the U-shaped trench structure uses trench etching technology in the memory storage capacitor manufacturing process to change the conductive channel direction from horizontal to vertical, eliminating the JFET neck resistance compared to a normal structure, significantly increasing cell density, and improving the current processing capability of the power semiconductor.

[0008] However, in actual manufacturing processes and applications, SiC UMOSFETs still have several problems: 1) Due to the high electric field in the SiC drift area, the electric field on the gate insulating dielectric layer is high, and this problem is exacerbated at trench corners. The gate insulating dielectric layer is rapidly destroyed by high drain voltages, resulting in poor resistance to electrostatic effects in harsh environments and high-voltage spikes in the circuit. 2) Since SiC power MOSFETs are mainly applied in high-voltage, high-frequency, high-current fields, parasitic parameters in the circuit can cause spike glitches during high-frequency switching. As shown in Figure 3, Figure 3 is a waveform diagram of voltage overshoot and oscillation phenomena at the switching moment of the MOSFET. As can be seen from Figure 3, this can cause instantaneous overvoltage on the current path of the device, increase losses during the switching process, or form large surge voltages due to changes in power load, etc. Therefore, the surge voltage withstand capability and overvoltage protection of the MOSFET are also very important. Conventional MOSFET devices themselves do not possess surge voltage self-suppression capabilities or overvoltage protection capabilities; therefore, in practical applications, it is generally necessary to design complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits. Such externally placed suppression and overvoltage protection circuits often have time delays, and high-frequency spike voltage surges during the actual switching process are still absorbed by the device itself, which can lead to the destruction or invalidation of the device's channel area and the gradual invalidation of the ohmic contact area between the gate structure and electrodes, resulting in reliability issues for the device. 3) Due to limitations in ion implantation depth, it is difficult to implement many targeted trench gate protection structures and surge-resistant designs in the process. Generally, the trench depth for forming the gate is 1 μm to 2 μm or more, and the actual manufacturing process of embedded protection structures to protect the gate structure inside the trench cannot be completed directly by ion implantation. This is because it is difficult to achieve an ion implantation depth of more than 1 μm in the silicon carbide process. In conventional technology, the necessary doped area is generally formed within the formed epitaxial layer by etching and ion implantation, and then two P-type epitaxial layers with a specific structure are formed. As a result, the manufacturing process is complex and the manufacturing cost is high. [Overview of the project] [Problems that the invention aims to solve]

[0009] In view of this, this application provides a silicon carbide MOSFET device and a method for manufacturing the same, and the solution is as follows. [Means for solving the problem]

[0010] A silicon carbide MOSFET device, A carbide epitaxial layer comprising a first surface and a second surface facing each other, wherein there is an embedded layer between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region, A first trench located in the gate region, a trench gate located within the first trench, wherein the first trench is located on the side of the buried layer away from the second surface and has a gap between it and the buried layer, A second trench located within the source region, a trench source located within the second trench, A first pressure-resistant shield structure is located within the silicon carbide epitaxial layer at the bottom of the first trench and is spaced apart from the buried layer, The present invention includes a second pressure-resistant shield structure located within the silicon carbide epitaxial layer on the surface of the second trench and in contact with the buried layer.

[0011] Preferably, in the silicon carbide MOSFET device described above, the embedded layer includes a first ion implantation area formed based on the first trench, the first ion implantation area penetrates the embedded layer and is spaced apart from the first withstand-voltage shield structure.

[0012] Preferably, in the silicon carbide MOSFET device described above, the first trench is a single-stage trench, and the width of the first ion implantation area is smaller than the width of the single-stage trench. The width of the first pressure-resistant shield structure is smaller than the width of the single-stage trench.

[0013] Preferably, in the silicon carbide MOSFET device, the depth of the first trench is smaller than the depth of the second trench. There is a well area between the first trench and the second pressure-resistant shield structure, and the depth of the well area is less than the depth of the first trench. The silicon carbide epitaxial layer on the side of the well area that is separated from the second surface is a second ion implantation area that is opposite to the doping type of the well area.

[0014] Preferably, in the silicon carbide MOSFET device described above, the second trench is a multi-stage trench. The second pressure-resistant shield structure is a third ion implantation area formed based on the multi-stage trench, and this third ion implantation area is located within the silicon carbide epitaxial layer of the bottom of the multi-stage trench, the side walls of each trench, and the steps between adjacent two-stage trenches.

[0015] Preferably, in the silicon carbide MOSFET device, the bottom of the second trench is located on the side of the embedded layer away from the second surface and has a gap between it and the embedded layer. At least a portion of the second pressure-resistant shield structure is located within the buried layer.

[0016] Preferably, in the silicon carbide MOSFET device described above, at least a portion of the second trench is located within the buried layer.

[0017] Preferably, in the silicon carbide MOSFET device described above, the trench gate includes polysilicon filled in the first trench, and a metal gate is provided on the surface of the polysilicon. The trench source comprises polysilicon filled in the second trench, and a metal source is provided on the surface of the polysilicon. There is an insulating dielectric layer between the first trench and the polysilicon filled therein, and between the second trench and the polysilicon filled therein. The insulating dielectric layer further covers the first surface, The insulating dielectric layer covering the first surface has an opening that exposes a part of the first surface and is used for arranging an ohmic contact layer, and the metal source covers the ohmic contact layer.

[0018] Preferably, in the above silicon carbide MOSFET device, a silicon carbide base is provided opposite to the second surface, and a metal drain is provided on a side of the silicon carbide base away from the silicon carbide epitaxial layer.

[0019] This application further provides a method for manufacturing the silicon carbide MOSFET device according to any one of the above items, A step of providing an epitaxial wafer, wherein the epitaxial wafer includes a silicon carbide epitaxial layer having opposite first and second surfaces, and there is a buried layer between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region, A step of forming a first trench in the gate region and a second trench in the source region, wherein the first trench is located on a side of the buried layer away from the second surface and has a spacing from the buried layer, A step of forming the first breakdown voltage shield structure in the silicon carbide epitaxial layer based on the first trench and forming the second breakdown voltage shield structure in the silicon carbide epitaxial layer based on the second trench, wherein the first breakdown voltage shield structure and the buried layer have a spacing, and the second breakdown voltage shield structure and the buried layer are in contact, A step of forming a trench gate in the first trench and a trench source in the second trench, are included.

[0020] Preferably, in the above manufacturing method, before forming the first breakdown voltage shield structure and the second breakdown voltage shield structure, Further comprising the step of performing ion implantation on the buried layer based on the first trench to form a first ion implantation area in a region of the buried layer corresponding to the first trench, The first ion implantation area penetrates through the buried layer and has a spacing from the first breakdown voltage shield structure.

[0021] Preferably, in the above manufacturing method, the step of forming a first trench in the gate region and a second trench in the source region includes: In the first etching, forming a first-stage trench in the source region; In the second etching, forming a single-stage trench in the gate region and forming a second-stage trench based on the first-stage trench, including: The etching window of the second etching is larger than the etching window of the first etching, increasing the depth of the first-stage trench, and forming a second-stage trench based on the first trench. The first trench includes the single-stage trench, the second trench is a two-stage stepped trench, and includes the first-stage trench and the second-stage trench.

[0022] Preferably, in the above manufacturing method, Further comprising the step of forming a well area and a second ion implantation area having a doping type opposite to that of the well area within the first surface, The well area is located between the first trench and the second breakdown voltage shield structure, and the depth of the well area is smaller than the depth of the first trench.

[0023] Preferably, in the above manufacturing method, the first surface includes an electric field buffer area surrounding the second trench, The step of forming the first breakdown voltage shield structure in the silicon carbide epitaxial layer based on the first trench and forming the second breakdown voltage shield structure in the silicon carbide epitaxial layer based on the second trench includes: Forming a mask layer covering the first surface and the sidewalls of the first trench, The step includes performing ion implantation based on the mask layer to form the first pressure-resistant shield structure in the silicon carbide mask layer at the bottom of the first trench, and forming the second pressure-resistant shield structure on the side walls and bottom of the second trench. The electric field buffer area surrounds the second voltage-resistant shield structure.

[0024] Preferably, in the above manufacturing method, the step of forming a trench gate in the first trench and a trench source in the second trench is: The steps include forming an insulating dielectric layer covering the first surface, the surface of the first trench, and the surface of the second trench, The step of filling the first trench and the second trench with polysilicon, wherein the trench gate contains the polysilicon filled in the first trench and a metal gate is provided on the surface of the polysilicon, and the trench source contains the polysilicon filled in the second trench and a metal source is provided on the surface of the polysilicon. [Effects of the Invention]

[0025] As can be seen from the above description, the silicon carbide MOSFET device and its manufacturing method provided by the present invention include a first and second breakdown shield structure in the silicon carbide MOSFET, improving the breakdown performance of the device, avoiding the problem of gate insulating dielectric layer breakdown, improving the device's resistance to electrostatic effects in harsh environments and high voltage spikes in circuits, and enhancing the device's surge voltage resistance and overvoltage protection capabilities. Furthermore, the first breakdown shield structure is formed by implanting ions based on the first trench, and the second breakdown shield structure is formed by implanting ions through the second trench, enabling the realization of a deep ion implantation area within the silicon carbide epitaxial layer without requiring high-dose, high-energy ion implantation, resulting in a simple manufacturing process and low manufacturing costs.

[0026] To more clearly explain the embodiments of this application or the technical concepts in related technologies, the following is a brief introduction of the necessary drawings describing the embodiments or prior art. The drawings described below are merely embodiments of this application, and those skilled in the art can obtain other drawings based on the provided drawings, provided they do not perform work commensurate with inventive step. The structures, proportions, dimensions, etc., depicted in the drawings herein are not intended to be used as limitations on the implementable conditions of this application, but are merely for the understanding and viewing of those skilled in the art in accordance with the disclosures of the specification. Therefore, any modifications to the structure, changes in proportions, and adjustments to dimensions that do not have any substantive technical meaning do not affect the implementable effects and achievable objectives of this application, and all fall within the scope covered by the technical content disclosed herein. [Brief explanation of the drawing]

[0027] [Figure 1] This is a schematic diagram of the DMOSFET structure. [Figure 2] This is a schematic diagram of the UMOSFET structure. [Figure 3] This is a waveform diagram showing the voltage overshoot and oscillation phenomena at the switching moment of a MOSFET. [Figure 4] This is a schematic diagram of the structure of a silicon carbide MOSFET device provided by an embodiment of this application. [Figure 5] This is a schematic diagram of the structure of another silicon carbide MOSFET device provided by the embodiments of this application. [Figure 6] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 7] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 8] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 9] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 10]This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 11] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 12] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 13] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 14] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 15] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 16] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 17] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 18] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 19] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 20] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 21] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 22] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 23] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 24] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 25] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 26] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Figure 27] This is a process flowchart of the manufacturing method for a silicon carbide MOSFET device provided in the embodiments of this application. [Modes for carrying out the invention]

[0028] The embodiments of this application are described below in a clear and complete manner by combining the drawings of the embodiments of this application, and the embodiments described are not all embodiments but only a selection of embodiments of this application. All other embodiments obtained based on the embodiments of this application, provided that a person skilled in the art does not perform work worthy of inventive step, are all within the scope of protection of this application.

[0029] To make the above-mentioned objectives, features, and advantages of this application clearer, the application will be described in more detail below, combining drawings and specific embodiments.

[0030] As shown in Figure 4, Figure 4 is a schematic diagram of the structure of a silicon carbide MOSFET device provided by an embodiment of this application, and the silicon carbide MOSFET device is A carbide epitaxial layer 11 comprising a first surface and a second surface facing each other, wherein a buried layer 12 is located between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region. A first trench 13 located in the gate region, a trench gate g located within the first trench 13, wherein the first trench 13 is located on the side of the buried layer 12 away from the second surface and has a gap between the buried layer 12 and the first trench 13, trench gate g, A second trench 14 located within the source region, a trench source s located within the second trench 14, A first pressure-resistant shield structure 15 is located within the silicon carbide epitaxial layer 11 at the bottom of the first trench 13 and is spaced apart from the buried layer 12, The structure includes a second pressure-resistant shield structure 16 located within the silicon carbide epitaxial layer 11 on the surface of the second trench 14 and in contact with the buried layer 12.

[0031] An insulating dielectric layer 17 is located between the trench gate g and the first trench 13. The first withstand voltage shield structure 15 is located within the surface of the bottom of the first trench 13, with no gap between it and the bottom of the first trench 13, thereby effectively providing protection to the insulating dielectric layer 17 on the surface of the first trench 13.

[0032] The silicon carbide MOSFET is equipped with a first withstand voltage shield structure 15 and a second withstand voltage shield structure 16, improving the device's withstand voltage performance, avoiding the problem of gate insulating dielectric layer 17 breakdown, improving the device's resistance to electrostatic effects in harsh environments and high-voltage spikes in the circuit, and enhancing the device's surge voltage resistance and overvoltage protection capabilities. Furthermore, the first withstand voltage shield structure 15 is formed by implanting ions based on the first trench 13, and the second withstand voltage shield structure 16 is formed by implanting ions through the second trench 14, enabling deep ion implantation areas within the silicon carbide epitaxial layer without requiring high-dose, high-energy ion implantation, resulting in a simple manufacturing process and low manufacturing costs.

[0033] The carbonized epitaxial layer 11 includes a first epitaxial layer 111 and a second epitaxial layer 112 that are arranged opposite each other, and the embedded layer 12 is located between the first epitaxial layer 111 and the second epitaxial layer 112. The surface of the first epitaxial layer 111 that is separated from the second epitaxial layer 112 is the second surface. The surface of the second epitaxial layer 112 that is separated from the first epitaxial layer 111 is the first surface.

[0034] The silicon carbide MOSFET device comprises a silicon carbide base 10 positioned opposite the second surface, and a metal drain D is provided on the side of the silicon carbide base 10 that is separated from the carbide epitaxial layer 11.

[0035] The buried layer 12 includes a first ion implantation area 21 formed based on the first trench 13, and the first ion implantation area 21 penetrates the buried layer 12 and is spaced apart from the first pressure-resistant shield structure 15.

[0036] In the silicon carbide MOSFET device described above, a first ion implantation area 21 is formed in the embedded layer 12, and there is a gap between the first ion implantation area 21 and the first withstand voltage shield structure 15 below the trench gate g. The first ion implantation area 21 penetrates the entire embedded layer 12 and constitutes the main current path of the device. This introduces a JFET structure into the drain current path of the device, and the on-characteristics of the JFET structure are optimized based on the pattern design, ion implantation concentration, and pattern contour of the first ion implantation area 21, resulting in flexible design and process and excellent manufacturability.

[0037] In the silicon carbide MOSFET device, by making the depth of the first trench 13 smaller than the depth of the second trench 14, a second withstand voltage shield structure 16 with deep ion implantation is realized, and the second withstand voltage shield structure 16 and the embedded layer 12 are connected to jointly form reverse withstand voltage protection at the bottom of the trench gate and the trench corners, thereby realizing a highly reliable trench-type MOSFET device. A well area W is located between the first trench 13 and the second withstand voltage shield structure 16, the depth of the well area W is smaller than the depth of the first trench 13, and the silicon carbide epitaxial layer 11 on the side of the well area W away from the second surface is a second ion implantation area 18 opposite to the doping type of the well area W. The well area W is located on both sides of the first trench 13 and is in contact with the side walls of the first trench 13.

[0038] In the embodiments of this application, an N+-doped silicon carbide base is used for the silicon carbide base 10, the silicon carbide epitaxial layer 11 is an N-doped epitaxial layer, that is, both the first epitaxial layer 111 and the second epitaxial layer 112 are N-doped epitaxial layers, both the first pressure-resistant shield structure 15 and the second pressure-resistant shield structure 16 are P+ / - doped ion implantation areas, the well area W is a P-doped ion implantation area, and the second ion implantation area 18 is an N+-doped ion implantation area. Hereinafter, in the embodiments of this application, the doping type of each region of the device is not limited to the description in the embodiments, and the doping type can be set according to the needs to form a PMOS or NMOS structure.

[0039] The first trench 13 is a single-stage trench, the width of the first ion implantation area 21 is smaller than the width of the single-stage trench, and the width of the first pressure-resistant shield structure 15 is smaller than the width of the single-stage trench. By providing the first pressure-resistant shield structure 15 between the trench gate and the buried layer 12, and by providing a pitch between the first pressure-resistant shield structure 15 and the buried layer 12, a JFET structure is formed in the silicon carbide MOSFET device. Therefore, it is not necessary to increase the implantation depth of the first pressure-resistant shield structure 15, and by using a shallow single-stage trench as the first trench 13, the need for the implantation depth of the first pressure-resistant shield structure 15 can be met, the manufacturing process is simple, and the manufacturing cost is low.

[0040] The second trench 14 is a multi-stage trench, and the second pressure-resistant shield structure 16 is a third ion implantation area formed based on the multi-stage trench, the third ion implantation area being located within the silicon carbide epitaxial layer at the bottom of the multi-stage trench, the side walls of each trench, and the steps between adjacent two-stage trenches. A deep second pressure-resistant shield structure 16 is required to connect the second pressure-resistant shield structure 16 with the buried layer 12. If the second trench 14 is a multi-stage trench, this can be achieved without requiring high-dose, high-energy ion implantation, that is, a deep second pressure-resistant shield structure 16 can be manufactured within the silicon carbide epitaxial layer 11.

[0041] Preferably, the multi-stage trench is a two-stage trench. Generally, for a silicon carbide epitaxial wafer containing a silicon carbide base 10 and a silicon carbide epitaxial layer 11, the depth of the embedded layer 12 is generally about 2 μm, and the depth of the first trench 12 for manufacturing the trench gate is generally about 1 μm. If the second trench 14 is a two-stage trench, the need for ion implantation depth of the second pressure-resistant shield structure 16 can be met without requiring high-dose, high-energy ion implantation, and without damaging the silicon carbide lattice structure.

[0042] In the configuration shown in Figure 4, the bottom of the second trench 14 is located on the side of the buried layer 12 away from the second surface, and is spaced apart from the buried layer 12. At least a portion of the second pressure-resistant shield structure 16 is located within the buried layer 12, thereby connecting the second pressure-resistant shield structure 16 to the buried layer and providing good protection for the trench gate. In this case, as shown in Figure 4, the bottom of the second pressure-resistant shield structure 16 is located within the buried layer 12 or below the buried layer 12.

[0043] As shown in Figure 5, Figure 5 is a schematic diagram of the structure of another silicon carbide MOSFET device provided by an embodiment of this application, and the differences from the device shown in Figure 4 are as follows: In the embodiment shown in Figure 5, at least a portion of the second trench 14 is located within the buried layer 12. In this case, as shown in Figure 5, the bottom of the second withstand-voltage shield structure 16 is located within the buried layer 12.

[0044] Ions are implanted based on the second trench 14 to form the second pressure-resistant shield structure 16, and the bottom of the second pressure-resistant shield structure 16 may be located within the buried layer 12, as shown in Figure 4, or below the buried layer 12, as shown in Figure 5. Depending on the needs, the depth of the bottom of the second trench 14 relative to the buried layer 12 may be set, and the bottom of the second trench 14 may be positioned above the buried layer 12, as shown in Figure 4, or within the buried layer 12, as shown in Figure 5, or in other embodiments, the bottom of the second trench 14 may be positioned below the buried layer 12.

[0045] In the silicon carbide MOSFET device described in the embodiment of this application, the trench gate g includes polysilicon filled in the first trench 13, and a metal gate G is provided on the surface of the polysilicon; the trench source s includes polysilicon filled in the second trench 14, and a metal source S is provided on the surface of the polysilicon; an insulating dielectric layer 17 is provided between the first trench 13 and the filled polysilicon, and between the second trench 14 and the filled polysilicon; the insulating dielectric layer 17 further covers the first surface, and the insulating dielectric layer 17 covering the first surface has an opening that exposes a part of the first surface and is used for arranging the ohmic contact layer 20; and the metal source S covers the ohmic contact layer 20.

[0046] An electric field buffer area 19 is provided within the first surface, and the electric field buffer area 19 surrounds the second trench 14. The doping type and concentration doping of the electric field buffer area 19 and the second withstand voltage shield structure 16 may both be, for example, P+ doped regions. The electric field buffer area 19 solves the problem of leakage and destruction of the second trench 14 that would otherwise occur due to the thinness of the second withstand voltage shield structure 16 at the opening, thereby enhancing the manufacturability and reliability of the device.

[0047] As can be seen from the above description, in the silicon carbide MOSFET device provided in the embodiment of this application, trench sources s are formed on both sides of the trench gate g by process design, synchronously integrating them. A two-stage trench source is formed by making the second trench 14 a two-stage stepped trench. A second withstand voltage shield structure 16 is formed in the silicon carbide epitaxial layer 11 at the bottom of the two-stage stepped trench, the side walls of each stepped trench, and the steps of adjacent two-stage trenches by ion implantation. The bottom of the second pressure-resistant shield structure 16 is located within the buried layer 12, or the second pressure-resistant shield structure 16 penetrates the buried layer 12, that is, the bottom of the second pressure-resistant shield structure 16 is positioned below the buried layer 12, so that the second pressure-resistant shield structure 16 is in contact with the buried layer 12, and furthermore, the second pressure-resistant shield structure 16 is grounded (communicated with the source), and a JFET structure is introduced into the drain current path of the device, so that the second pressure-resistant shield structure 16 forming the JFET structure is not floating and is in full communication with the source, so that it exhibits better field shielding against the bottom of the trench gate and enhances the surge self-suppression capability.

[0048] Furthermore, a first withstand voltage shield structure 15 is formed based on the first trench 13, and a second withstand voltage shield structure 16 is formed based on the second trench 14. This makes it difficult to form a deep P+ shield structure in the silicon carbide material, solving the problems of damage and reliability due to high-dose, high-energy P+ ion implantation, while simultaneously providing good shielding and protection for the trench gate g. If high-energy, high-dose ions are simply implanted into the second withstand voltage shield structure 16 to a depth of 1 μm to 2 μm or more, it may cause severe ion implantation damage to the silicon carbide material, potentially leading to problems with the reliability of subsequent devices operating over long periods. In the embodiment of this application, the second withstand voltage shield structure 16 is formed based on the second trench 14, making it easy to implant a P+ field shield structure with a depth of 1 μm to 2 μm or more. This forms the second withstand voltage shield structure 16, providing good shielding and protection for the sidewalls and bottom of the trench gate g, thereby enhancing the reliability of the gate of the silicon carbide trench type MOSFET device.

[0049] The silicon carbide MOSFET device utilizes a design in which a first ion implantation area 21 is formed in the embedded layer 12 of the epitaxial wafer. A JFET structure is specially introduced into the drain current path of the device, grounding a two-stage trench that is implanted and modulated by the first ion implantation area 21. This automatically expands the depletion areas on both sides with large surge voltages, increasing the on-resistance of the JFET area, and the buffer circuit structure itself effectively suppresses surge spikes. Furthermore, if the surge voltage is too large, the depletion areas on both sides continue to expand and overlap each other, exhibiting a sealing effect to protect the insulating dielectric layer 17 in the internal trench gate, achieving overvoltage protection against certain spike voltages. After introducing the JFET, the on-resistance increases to a certain extent, but it has switching buffer and surge voltage self-suppression effects, improving the device's self-suppression resistance to surge voltage and overvoltage. This avoids device damage and reduced reliability due to overvoltage and overcurrent protection circuits caused by actual operational time delays. Furthermore, it provides a buffering effect against spikes during the circuit switching process, reducing switching losses, decreasing the number of buffer circuits / buffer circuit structures in the circuit design, reducing discrete elements, lowering costs, and ultimately reducing the actual module volume while enhancing reliability.

[0050] Based on the above embodiments, other embodiments of this application further provide a method for manufacturing a silicon carbide MOSFET device as described in the above embodiments, and for the manufacturing method, refer to Figures 6 to 27.

[0051] Referring to Figures 6 to 27, Figures 6 to 27 are process flowcharts of a method for manufacturing a silicon carbide MOSFET device provided in the embodiments of this application, the manufacturing method comprising the following steps: Step S11: Provide an epitaxial wafer as shown in Figure 6.

[0052] The epitaxial wafer includes a carbide epitaxial layer 11 having a first surface and a second surface facing each other, with an embedded layer 12 between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region.

[0053] In embodiments of this application, a SiC epitaxial wafer having an N-type epitaxial layer is used, and specifically, the epitaxial wafer further includes a silicon carbide base 10 disposed opposite the second surface. The carbide epitaxial layer 11 includes a first epitaxial layer 111 and a second epitaxial layer 112 disposed opposite each other, and the embedded layer 12 is located between the first epitaxial layer 111 and the second epitaxial layer 112. The surface of the first epitaxial layer 111 that is separated from the second epitaxial layer 112 is the second surface. The surface of the second epitaxial layer 112 that is separated from the first epitaxial layer 111 is the first surface.

[0054] Step S12: As shown in Figures 7 to 12, a first trench 13 is formed in the gate region and a second trench 14 is formed in the source region, the first trench 14 being located on the side of the buried layer 12 away from the second surface and spaced apart from the buried layer 12.

[0055] The first trench 13 and the second trench 14 are formed by etching using a plasma dry etching process, such as RIE or ICP etching. For the etching principle for silicon carbide material, please refer to Figures 7 to 9. First, as shown in Figure 7, SiO2 is deposited on the silicon carbide material as a mask layer in a deposition process such as CVD, a photoresist PR is spin-coated onto the surface of the mask layer, and the photoresist PR with the required pattern is formed by exposure and phenotype. Then, as shown in Figure 8, the mask layer is etched based on the patterned photoresist PR to form a patterned mask layer, and finally, as shown in Figure 9, the silicon carbide material is etched based on the patterned mask layer to form trenches on its surface. Subsequent general semiconductor process steps such as photolithography and etching are not described in detail.

[0056] Step S12, which involves forming a first trench in the gate region and a second trench in the source region, includes the following steps: Step S121: As shown in Figure 10, the first etching process forms the first trench 41 in the source region.

[0057] The first surface may be etched based on the mask layer 36 on the first surface to form the first trench 41. After entering the process production line, alignment marks are manufactured on the epitaxial wafer for use in subsequent photolithography processes. In the proposed technology of this application, the alignment marks and the first trench 41 are manufactured together, eliminating the need to individually increase the etching process. The first trench 41 is manufactured using the etching process for the alignment marks, thereby reducing manufacturing costs.

[0058] As a mask layer 36, silicon dioxide is deposited by CVD, and using an F-containing gas such as CF4 or SF6, or a Cl-containing gas such as chlorine gas, and a mixed gas of Ar and oxygen, the SiC material at the bottom of the epitaxial wafer is etched in the region where the alignment marks need to be etched and in the source region to form the alignment marks (Figure 10 does not show the alignment marks) and the first trench 14. The depth of the first trench 41 is 200 nm to 2 μm, and is determined according to the type of photoetching machine and the type of alignment marks, preferably the depth of the first trench 41 is 800 nm.

[0059] Step S122: As shown in Figures 11 and 12, a single trench is formed in the gate region during the second etching, and a second trench is formed based on the first trench.

[0060] The etching window of the second etching is larger than the etching window of the first etching, increasing the depth of the first trench, and forming a second trench based on the first trench. The first trench 13 includes the single-stage trench, and the second trench 14 is a two-stage trench, including the first trench and the second trench.

[0061] Prior to the second etching, the process further includes forming a well area W and a second ion implantation area 18 opposite to the doping type of the well area W within the first surface. The second ion implantation area 18 is located on the side of the well area W facing the first surface. Ion implantation further forms an electric field buffer area 19 surrounding the second trench 14 within the first surface. The well area W is located between the first trench 13 and the second pressure-resistant shield structure 16, and the depth of the well area W is less than the depth of the first trench 13.

[0062] In step S122, first, as shown in Figure 11, the mask layer 36 is removed and ion implantation is performed on the first surface to form the required field buffer area 19, second ion implantation area 18, and well area W. High-temperature ion implantation equipment at 500°C to 600°C is generally used for SiC materials to reduce damage to the silicon carbide lattice structure during ion implantation. Then, as shown in Figure 12, a second etching is performed based on the mask layer 25.

[0063] For the second etching, silicon dioxide is deposited as an etching mask 35 by CVD, and the SiC material at the bottom of the gate region and the source regions on both sides is etched using a plasma etching instrument ICP or RIE with an F-containing gas such as CF4 or SF6, or a Cl-containing gas such as chlorine gas, and a mixed gas of Ar and oxygen to form the first trench 13 and the second trench 14 shown in Figure 12. As the first trench 13, a single-stage trench is formed in the gate region, and the depth of the first trench 13 is 300 nm to 2 μm, preferably 800 nm to 1 μm.

[0064] The etching mask 35 has a region corresponding to the first trench 13, which has a first opening for forming the first trench 13, thereby etching the gate region based on the first opening to form the first trench 13. The etching mask 35 has a region corresponding to the second trench, which has a second opening for forming the second trench, thereby etching the source region based on the second opening to form a second trench based on the first trench, and further forming a second trench 14.

[0065] When etching is performed a second time, the second opening in the source region is made larger than the opening of the first trench 41 to form a two-stage trench as the second trench 14. During this process, the bottom of the first trench 41 is continuously etched downwards, and the total depth formed is approximately equal to the sum of the depths of the two etchings. Because the size of the second opening has been increased, one end of the first trench 41 facing the first surface forms a two-stage trench.

[0066] In one embodiment, as shown in Figure 12, the silicon carbide MOSFET device shown in Figure 4 is manufactured by making the sum of the etching depths of two etchings in the source region smaller than the distance between the embedded layer 12 and the first surface. The distance d1 < 600 nm between the bottom of the second trench 14 and the embedded layer 12 is such that the distance d1 < 600 nm. In this embodiment, when the second breakdown voltage shield structure 16 is subsequently formed by ion implantation, it is necessary to inject energy and dose so that they sufficiently reach the embedded layer 12, thereby connecting the second breakdown voltage shield structure 16 and the embedded layer 12. This embodiment is for manufacturing the silicon carbide MOSFET device shown in Figure 4, and when the device operates in the reverse direction, the electric field region with the highest intensity is distributed relatively uniformly in the embedded layer 12, resulting in good reverse breakdown voltage performance of the device.

[0067] In another embodiment, as shown in Figure 13, the silicon carbide MOSFET device shown in Figure 5 is manufactured by making the sum of the etching depths of two etchings in the source region greater than the distance between the bottom surface of the embedded layer 12 and the first surface. Silicon dioxide is deposited by CVD as the etching mask 35, and the SiC material in the gate region and the source regions on both sides is etched using plasma etching equipment ICP or RIE with an F-containing gas such as CF4 or SF6, or a Cl-containing gas such as chlorine gas, and a mixed gas of Ar and oxygen to form the structure shown in Figure 13. A single-stage trench is formed in the gate region as the first trench 13, and the depth of the first trench 13 is 300 nm to 2 μm, preferably 800 nm to 1 μm. In this case, the second trench 14 passes through the embedded layer 12. The distance d2 between the bottom of the second trench 14 and the embedded layer 12 is 600 nm. In this configuration, when the second withstand voltage shield structure 16 is formed by subsequent ion implantation, the second trench 16 penetrates the buried layer 12. Therefore, compared to the configuration in Figure 12, the second withstand voltage shield structure 16 and the buried layer 12 can be connected with a lower injection dose and injection energy. This configuration is for manufacturing the silicon carbide MOSFET device shown in Figure 5. When the device operates in the reverse direction, the region with the highest electric field strength is located in the second withstand voltage shield structure 16 at the bottom of the second trench 14. The area of ​​the region receiving the highest electric field is determined by the width of the bottom of the second trench 14, and the reverse withstand voltage performance is lower compared to the configuration in Figure 4.

[0068] Step S13: As shown in Figures 14 to 19, the first pressure-resistant shield structure 15 is formed in the silicon carbide epitaxial layer 11 based on the first trench, and the second pressure-resistant shield structure 16 is formed in the silicon carbide epitaxial layer 11 based on the second trench, with a gap between the first pressure-resistant shield structure 15 and the buried layer 12, and the second pressure-resistant shield structure 16 and the buried layer 12 in contact.

[0069] Before forming the first pressure-resistant shield structure 15 and the second pressure-resistant shield structure 16, the process further includes the step of ion implanting the buried layer 12 based on the first trench 13, as shown in Figure 14, to form a first ion implantation area 21 in the region of the buried layer 12 corresponding to the first trench 13, the first ion implantation area 21 penetrating the buried layer 12, and there being a gap between the first ion implantation area 21 and the first pressure-resistant shield structure 15 after the subsequent formation of the first pressure-resistant shield structure 15. The first trench 13 is exposed by a mask plate 34, shielding other areas of the first surface. The first ion implantation area 21 is formed by implantation using a nitrogen ion source.

[0070] Ion implantation is performed using a photoresist mask or a silicon dioxide-assisted hard mask. When using a photoresist mask, the photoresist is directly spin-coated onto the first surface, and photolithography is performed on the bottom of the first trench 13 using the mask plate 34 shown in Figure 14. Regarding the layout design of the mask plate 34, the opening of the mask plate 34 corresponding to the first trench 13 is smaller than the first trench 13.

[0071] The first surface comprises an electric field buffer area 19 surrounding the second trench, and the steps of forming the first pressure-resistant shield structure 15 within the silicon carbide epitaxial layer 11 based on the first trench 13 and the second pressure-resistant seal 16 within the silicon carbide epitaxial layer 11 based on the second trench 14 include the following steps.

[0072] Step S131: As shown in Figures 15 to 17, a mask layer 32 is formed to cover the first surface and the side walls of the first trench.

[0073] In step S131, first, as shown in Figure 15, a mask layer 32 is formed to cover the first surface and fill the first trench 13 and the second trench 14, and SiO2 is deposited as the mask layer 32 by CVD. Also, as shown in Figure 16, a photolithography mask layer 33 is placed, and the opening 331 of the photolithography mask layer 33 corresponding to the first trench 13 is smaller than the opening of the first trench 13, and the opening 332 corresponding to the second trench 14 is larger than the opening of the second trench 14. Then, as shown in Figure 17, photolithography is performed based on the photolithography mask layer 33, and the mask layer 32 is etched using dry etching with an etching gas having a high selectivity for SiO2:SiC.

[0074] Since the opening 331 is smaller than the opening of the first trench 13, when a portion of the mask layer 32 is retained on the side wall of the first trench 13 and subsequent ion implantation is performed to form the first pressure-resistant shield structure 15, by retaining a portion of the mask layer 32 on the side wall of the first trench 13, ion implantation at the side wall of the first trench 13 is avoided due to ion scattering during ion implantation. Furthermore, by positioning the first pressure-resistant shield structure 15 below the well area W, contact between the first pressure-resistant shield structure 15 and the well area W is avoided, and the problem of abnormal channel opening in the semiconductor device caused by this is avoided, thereby ensuring the normal operation of the device.

[0075] Since the opening 332 is larger than the opening of the second trench 14, a portion of the first surface around the opening of the second trench 14 is exposed. When subsequent ion implantation is performed to form the second pressure-resistant shield structure 16, the ion implantation area can cover the entire second trench 16. Furthermore, ion implantation can be performed in the bottom of the second trench 14, the side walls of each step trench, and within the silicon carbide epitaxial layer 11 of the steps between adjacent two-step trenches, forming the necessary second pressure-resistant shield structure 16. This ensures that when the final formed device operates in the reverse direction, the second pressure-resistant shield structure 16 can completely shield and protect the trench source, preventing large reverse leakage currents.

[0076] Step S132: As shown in Figure 18, on-injection is performed based on the mask layer 32 to form the first pressure-resistant shield structure 15 in the silicon carbide mask layer 11 at the bottom of the first trench 13, and the second pressure-resistant shield structure 16 is formed on the side walls and bottom of the second trench 14. Then, as shown in Figure 19, the mask layer 32 may be removed using the buffered HF wet method.

[0077] The electric field buffer area 19 surrounds the second pressure-resistant shield structure 16, and both are similarly doped and connected as a single unit. P+ type ion implantation is performed using a high-temperature ion implanter at 500°C to 600°C to form the first pressure-resistant shield structure 15 and the second pressure-resistant shield structure 16. When performing P+ type ion implantation, the implanted ions are Al ions. Preferably, the ion implantation energy is several hundred keV, and the dose is 1E12cm². -2 ~1E16cm -2 The injection depth is 100nm to 500nm.

[0078] As shown in Figure 20, Figure 20 is an SEM drawing after the first pressure-resistant shield structure 15 and the second pressure-resistant shield structure 16 have been formed by the manufacturing method of the embodiment of this application. The embedded layer 12 is a silicon carbide P-type embedded layer, and the region corresponding to the first trench is provided with an N-enrich (N-type doped) ion implantation area as the first ion implantation area 21, and SiO2 as a mask layer 32 is provided on the first surface of the epitaxial wafer, and the second pressure-resistant shield structure 16 and the embedded layer 12 are connected by an overlay portion.

[0079] As shown in Figure 21, Figure 21 is an SEM drawing of the source region before and after implantation of P+ ions using the manufacturing method of the embodiment of this application. As an example, the second trench 14 is a two-step trench, the left figure is an SEM drawing of the region corresponding to the second trench 14 before implantation of P+ ions, and the right figure is an SEM drawing of the region corresponding to the second trench 14 after implantation of P+ ions. In the right figure, the areas with small grayscale are SEM slice images formed after implantation of Al ions.

[0080] Step S14: As shown in Figures 22 to 26, a trench gate g is formed in the first trench 13 and a trench source s is formed in the second trench 14.

[0081] Step S14, which involves forming a trench gate g in the first trench 13 and a trench source s in the second trench 14, includes the following steps: Step S141: As shown in Figure 22, an insulating dielectric layer 17 is formed covering the first surface, the surface of the first trench 13, and the surface of the second trench 14.

[0082] In a high-temperature furnace tube, a trench gate oxide layer is grown as an insulating dielectric layer 17. At 1100°C to 1350°C, oxygen is introduced into the high-temperature furnace tube to perform surface oxidation and grow SiO2, with a thickness of 40 nm to 70 nm.

[0083] Step S142: As shown in Figure 23, polysilicon 31 is filled into the first trench 13 and the second trench 14, the trench gate g contains the polysilicon 31 filled into the first trench 13 and a metal gate G is provided on the surface of the polysilicon 31, the trench source s contains the polysilicon 31 filled into the second trench 14 and a metal source S is provided on the surface of the polysilicon 31.

[0084] A polysilicon layer may be deposited in the LPCVD process and filled into the first trench 13 and the second trench 14. Specifically, at 540°C to 800°C, silane or DCS gas, Ar, and doping gases containing phosphorus or boron, such as phosphane or borane, are introduced into the LPCVD furnace tube, and after a chemical decomposition reaction, polysilicon is produced with a thickness of 400 nm to several μm. To facilitate the subsequent placement of metal electrodes, the following steps are further included: Step S143: As shown in Figure 24, the polysilicon 31 is etched to remove the polysilicon 31 from the surface of the insulating dielectric layer 17 outside the first trench 13 and the second trench 14, thereby lowering the polysilicon filling the first trench 13 to slightly below the opening of the first trench 13, and lowering the polysilicon filling the second trench 14 to slightly below the second trench 14, thereby forming the subsequent metal source S and metal gate G. Polysilicon may be etched using HBr, or a mixed gas of chlorine gas and oxygen. Step S144: As shown in Figure 25, openings are formed in the insulating dielectric layer 17 outside the first trench 13 and the second trench 14. The insulating dielectric layer 17 is etched using F gas such as CHF3 or CF4, or chlorine gas containing Cl, to form the openings, thereby manufacturing the ohmic contact layer 20 in a subsequent step. Step S145: As shown in Figure 26, an ohmic contact layer 20 is formed at the openings of the insulating dielectric layer 17. Specifically, PVD deposition is performed at the openings of the insulating dielectric layer 17, in which a single layer of Ni or Ti / Ni / Al is laminated, the metal excluding the openings is peeled off or etched, and then rapid thermal annealing is performed at 900°C to 1100°C for an annealing time of 30 seconds to 5 minutes to form the ohmic contact layer 20.

[0085] Finally, a metal gate G is formed on the surface of the trench gate g, a metal source S is formed on the surface of the trench source s, and a metal drain D is formed on the surface of the silicon carbide base 10 that is separated from the silicon carbide epitaxial layer 11, thereby forming the silicon carbide MOSFET device shown in Figure 4. The source metal S is located on the surface of the polysilicon that fills the second trench 14, covering and connecting the ohmic contact layer 20. The metal drain D may be a laminated structure formed from one or more of Ni, Ti, Al, and Ag.

[0086] The subsequent metal processes such as the gate and source, the inactivation layer and polyimide PI adhesive, and the metal processes for the back drain are all standard process methods, so no further explanation is needed.

[0087] As shown in Figure 27, Figure 27 is a layout of the trench design and doped area ion implantation area of ​​a silicon carbide MOSFET device provided by an embodiment of the present application, wherein the implantation window of the first ion implantation area 21 is located within the first trench 13, and the passage characteristics of the JFET structure are adjusted according to the pattern design, ion implantation concentration and pattern contour design of the first ion implantation area 21. The area of ​​the implantation window of the first ion implantation area 21 is less than or equal to the area of ​​the first trench 13.

[0088] The above process flow will be explained using the manufacturing of the silicon carbide MOSFET device shown in Figure 4 as an example. Based on this embodiment, in other embodiments, by setting the etching depth of the second trench 14 twice as described above, its bottom is located within the buried layer 12, or passes through the buried layer 12, thereby enabling the manufacturing of the silicon carbide MOSFET device shown in Figure 5. In this way, by utilizing low-energy P-type ion implantation, the second breakdown shield structure 16 is connected to the buried layer 12, thereby achieving a modulation effect on the parasitic JFET structure on the current path, and further reducing the requirements for device parameter design and process manufacturing.

[0089] Thus, in the invention described in the embodiment of this application, a clever process integration design forms a second withstand voltage shield structure 16 based on the second trench 14, connects the second withstand voltage shield structure 16 to the embedded layer 12, and grounds the second withstand voltage shield structure 16. By combining the structural design of the epitaxial wafer and the first ion implantation area 21, the shielding of the gate insulating dielectric layer 17 in the silicon carbide trench type MOSFET device and the problems of the P-type deep implantation process in silicon carbide material are solved. Furthermore, a JFET structure is introduced into the drain current path of the device to form a JFET structure that grounds the two-stage trench implanted and modulated by the first ion implantation area 21, thereby automatically adjusting the on-resistance and self-locking protection effect of the device while maintaining a small device cell size.

[0090] According to the manufacturing method described in the embodiments of this application, P+ ion implantation is performed at a low energy of less than 1 MeV, and the implantation depth does not exceed 1 μm, but the embedded layer 12, whose depth from the bottom to the first surface exceeds 1 μm, may be connected to the source and grounded. The technical proposal of this application uses a sophisticated process integration configuration for grounding a two-stage trench double-embedded structure, and by designing a first ion implantation area 21 to be formed in the embedded layer 12 of the epitaxial wafer, the problems of shielding the gate insulating dielectric layer in SiC trench type MOSFETs and the P-type deep implantation process in silicon carbide materials are solved. Furthermore, a JFET structure that grounds the two-stage trench implanted and modulated by the first ion implantation area 21 is specially introduced into the drain current path of the device, which automatically adjusts the on-resistance and self-locking protection effect of the device and maintains a small device cell size.

[0091] Each example in this specification is described in a progressive, parallel, or combined manner, and each example mainly describes the differences from other examples, with similar or identical parts between examples referring to one another.

[0092] Herein, the drawings and embodiments described in this application are not intended to limit, but are used for illustrative purposes. Similar reference numerals that run through the embodiments in the specification indicate the same structure. Also, for ease of understanding and description, the thickness of some layers, films, panels, regions, etc., may be exaggerated in the drawings. Furthermore, for example, when an element of a layer, film, region, or substrate is described as being "located" "on" another element, the element may be located directly on the other element, or an intermediate element may exist. Also, "located on..." means that the element is located on or below another element, but not essentially located above the other element according to the direction of gravity.

[0093] The orientations or positional relationships indicated by terms such as “up,” “down,” “top,” “bottom,” “inside,” and “outside” are those shown in the drawings and do not indicate or imply that the pointed-to device or element must have a specific orientation, or must be constructed and operated in a specific orientation, but are merely for describing and simplifying the description of this application and therefore do not limit it. Where one unit is considered to be “connected” to another unit, it may be directly connected to the other unit, or there may be units located in between.

[0094] Furthermore, in this specification, relational terms such as "first" and "second," etc., are merely for distinguishing one entity or operation from another, and do not necessarily require or imply that there is an actual relationship or order between these entities or operations. Also, the terms "include," "incorporate," or any other variation are intended to include non-exclusive inclusion, so that an article or apparatus containing a set of elements not only includes those elements but also other elements not explicitly listed, or even elements inherent to such article or apparatus. Unless otherwise specified, an element limited by the phrase "includes one XX" does not preclude an article or apparatus containing the aforementioned element from having other identical elements.

[0095] The above description of the disclosed embodiments will enable those skilled in the art to implement or use this application. Several amendments to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Accordingly, this application is not limited to these embodiments described herein and will cover the broadest scope that is consistent with the principles and novel features disclosed herein.

Claims

1. A silicon carbide MOSFET device having a PMOS or NMOS structure, A silicon carbide epitaxial layer comprising a first surface and a second surface facing each other, wherein a buried layer is provided between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region. A first trench located in the gate region, a trench gate located within the first trench, wherein the first trench is located on the side of the buried layer away from the second surface and has a gap between it and the buried layer, A second trench located within the source region, a trench source located within the second trench, A first pressure-resistant shield structure is located within the silicon carbide epitaxial layer at the bottom of the first trench, has a gap between it and the buried layer, and has no gap with the bottom of the first trench, The present invention includes a second pressure-resistant shield structure located within the silicon carbide epitaxial layer on the surface of the second trench and in contact with the buried layer, A silicon carbide MOSFET device characterized in that the embedded layer comprises a first ion implantation area formed based on the first trench, the first ion implantation area penetrates the embedded layer and is spaced apart from the first pressure-resistant shield structure.

2. The first trench is a single-stage trench, and the width of the first ion implantation area is smaller than the width of the single-stage trench. The silicon carbide MOSFET device according to claim 1, characterized in that the width of the first pressure-resistant shield structure is smaller than the width of the single-stage trench.

3. The depth of the first trench is less than the depth of the second trench. There is a well area between the first trench and the second pressure-resistant shield structure, and the depth of the well area is less than the depth of the first trench. The silicon carbide MOSFET device according to claim 1, characterized in that the silicon carbide epitaxial layer on the side of the well area away from the second surface is a second ion implantation area opposite to the doping type of the well area.

4. The second trench is a multi-stage trench, The silicon carbide MOSFET device according to claim 1, characterized in that the second pressure-resistant shield structure is a third ion implantation area formed based on the multi-stage stepped trench, and the third ion implantation area is located within the silicon carbide epitaxial layer of the bottom of the multi-stage stepped trench, the side walls of each stepped trench, and the steps between adjacent two-stage trenches.

5. The bottom of the second trench is located on the side of the buried layer that is away from the second surface, and is spaced apart from the buried layer. The silicon carbide MOSFET device according to claim 1, characterized in that at least a portion of the second pressure-resistant shield structure is located within the buried layer.

6. The silicon carbide MOSFET device according to claim 1, characterized in that at least a portion of the second trench is located within the buried layer.

7. The trench gate contains polysilicon that is filled into the first trench, and a metal gate is provided on the surface of the polysilicon. The trench source comprises polysilicon filled in the second trench, and a metal source is provided on the surface of the polysilicon. There is an insulating dielectric layer between the first trench and the polysilicon filling it, and between the second trench and the polysilicon filling it, and the insulating dielectric layer further covers the first surface, The silicon carbide MOSFET device according to claim 1, wherein the insulating dielectric layer covering the first surface has an opening that exposes a part of the first surface and is used for arranging the ohmic contact layer, and the metal source covers the ohmic contact layer.

8. The silicon carbide MOSFET device according to claim 1, comprising a silicon carbide base disposed opposite to the second surface, wherein a metal drain is provided on the side of the silicon carbide base that is separated from the silicon carbide epitaxial layer.

9. A method for manufacturing a silicon carbide MOSFET device according to any one of claims 1 to 8, A step of providing an epitaxial wafer, wherein the epitaxial wafer includes a silicon carbide epitaxial layer having a first surface and a second surface facing each other, with a buried layer between the first surface and the second surface, and the first surface includes a gate region and source regions located on both sides of the gate region. A step of forming a first trench in the gate region and a second trench in the source region, wherein the first trench is located on the side of the buried layer away from the second surface and is spaced apart from the buried layer. The steps include forming the first pressure-resistant shield structure within the silicon carbide epitaxial layer based on the first trench, and forming the second pressure-resistant shield structure within the silicon carbide epitaxial layer based on the second trench, wherein there is a gap between the first pressure-resistant shield structure and the buried layer, there is no gap between the bottom of the first trench and the first pressure-resistant shield structure, and the second pressure-resistant shield structure and the buried layer are in contact, The step of forming a trench gate in the first trench and forming a trench source in the second trench, Before forming the first pressure-resistant shield structure and the second pressure-resistant shield structure, The process further includes the step of performing ion implantation on the buried layer based on the first trench to form a first ion implantation area in the region of the buried layer corresponding to the first trench, A manufacturing method characterized in that the first ion implantation area penetrates the buried layer and is spaced apart from the first pressure-resistant shield structure.

10. The steps of forming a first trench in the gate region and a second trench in the source region are: The first etching step involves forming a first trench in the source region, The process includes the steps of: forming a single trench in the gate region in a second etching, and forming a second trench based on the first trench; The manufacturing method according to claim 9, characterized in that the etching window of the second etching is larger than the etching window of the first etching, the depth of the first trench is increased, and a second trench is formed based on the first trench, the first trench includes the single trench, and the second trench is a two-stage trench, including the first trench and the second trench.

11. The process further includes the step of forming a well area and a second ion implantation area opposite to the doping type of the well area within the first surface, The manufacturing method according to claim 9, characterized in that the well area is located between the first trench and the second pressure-resistant shield structure, and the depth of the well area is less than the depth of the first trench.

12. The first surface includes an electric field buffer area surrounding the second trench, The steps of forming the first pressure-resistant shield structure in the silicon carbide epitaxial layer based on the first trench, and forming the second pressure-resistant shield structure in the silicon carbide epitaxial layer based on the second trench, The steps include forming a mask layer that covers the first surface and the side walls of the first trench, The steps include: performing ion implantation based on the mask layer to form a first pressure-resistant shield structure in the silicon carbide epitaxial layer at the bottom of the first trench, and forming a second pressure-resistant shield structure on the side walls and bottom of the second trench; The manufacturing method according to claim 9, characterized in that the electric field buffer area surrounds the second pressure-resistant shield structure.

13. The step of forming a trench gate in the first trench and a trench source in the second trench is: The steps include forming an insulating dielectric layer that covers the first surface, the surface of the first trench, and the surface of the second trench, The manufacturing method according to claim 9, comprising the step of filling the first trench and the second trench with polysilicon, wherein the trench gate contains the polysilicon filled in the first trench and a metal gate is provided on the surface of the polysilicon, and the trench source contains the polysilicon filled in the second trench and a metal source is provided on the surface of the polysilicon.

Images