Electronic components and half-bridge circuits

Abstract

To provide electronic components which are configured such that reliability and / or performance are improved as compared to conventional ones while reducing the complexity and cost of an assembly process.SOLUTION: There is provided an electronic component in which a drain electrode of a depletion-mode transistor is electrically connected to a drain lead of a package, a gate electrode of an enhancement-mode transistor is electrically connected to a gate lead of the package, a source electrode of the enhancement-mode transistor is electrically connected to a conductive structural package base, a gate electrode of the depletion-mode transistor directly contacts and is electrically connected to a conductive substrate, the conductive substrate directly contacts and is electrically connected to the conductive structural package base, and the conductive structural package base is electrically connected to a source lead of the package.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosed technology relates to semiconductor electronic devices designed to achieve improved performance and reliability.

[0002] [background] Currently, typical power semiconductors (including devices such as transistors, diodes, power MOSFETs, and insulated-gate bipolar transistors (IGBTs)) are fabricated from silicon (Si) semiconductor materials. More recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their superior properties. Group III nitride or III-N semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates for carrying large currents, supporting high voltages, and providing ultra-low on-resistance with fast switching times.

[0003] Most conventional III-N high electron mobility transistors (HEMTs) and related transistor devices are normally-on (i.e., have a negative threshold voltage), meaning they can conduct at zero gate voltage. These devices with negative threshold voltages are known as depletion-mode (D-mode) devices. In power electronics, it is preferable to have normally-off devices (i.e., devices with a positive threshold voltage) that do not conduct current at zero gate voltage, in order to prevent accidental turn-on of the device and thus avoid damage to the device or other circuit components. Normally-off devices are generally called enhancement-mode (E-mode) devices.

[0004] To date, the reliable manufacturing and fabrication of high-voltage III-N E-mode transistors has proven to be extremely difficult. One alternative to a single high-voltage E-mode transistor is to form a hybrid device by combining a high-voltage D-mode III-N transistor with a low-voltage E-mode transistor (e.g., a low-voltage silicon FET) in a cascaded circuit configuration as shown in the schematic diagram in Figure 1. This can be operated in the same way as a single high-voltage E-mode III-N transistor and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode III-N transistor. The hybrid device in Figure 1 includes a high-voltage D-mode III-N transistor 23 and a low-voltage E-mode transistor 22, both of which can be optionally cased in a single package 10, the package including a source lead 11, a gate lead 12, and a drain lead 13. The source electrode 31 of the low-voltage E-mode transistor 22 and the gate electrode 35 of the high-voltage D-mode III-N transistor 23 are electrically connected to the source lead 11. The gate electrode 32 of the low-voltage E-mode transistor 22 is electrically connected to the gate lead 12. The drain electrode 36 of the high-voltage D-mode III-N transistor 23 is electrically connected to the drain lead 13. The source electrode 34 of the high-voltage D-mode III-N transistor 23 is electrically connected to the drain electrode 33 of the low-voltage E-mode transistor 22. The low-voltage E-mode transistor 22 includes an internal body diode 37 that extends antiparallel to the channel of the transistor 22.

[0005] [Summary] This specification describes an integrated design for III-N devices, in which a low-voltage enhancement-mode device and a high-voltage depletion-mode III-N device are integrated into a single electronic component package to form a hybrid device. This device can operate in the same manner as a single high-voltage E-mode III-N transistor and / or has the same output characteristics. The term “device” is generally used for any transistor, switch, or diode when there is no need to distinguish between them.

[0006] In a first aspect, semiconductor devices are described. The semiconductor devices include III-N devices and field-effect transistors (FETs). The III-N device comprises a substrate on a first side of the III-N material structure, a first gate, a first source, and a first drain on the side of the III-N material structure opposite to the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, wherein the second source is on the side of the second semiconductor material structure opposite to the second drain. The second drain of the FET is electrically connected to the first source of each III-N device by direct contact, a via hole is formed through a portion of the III-N material structure, exposing a portion of the upper surface of the substrate, and the first gate is formed at least partially within the via hole and electrically connected to the substrate.

[0007] In a second embodiment, an electronic component is described. The electronic component comprises an enhancement-mode transistor. The electronic component further comprises a depletion-mode transistor. The depletion-mode transistor comprises a substrate. The electronic component further comprises a package. The package comprises a conductive structural package base, and the package encloses both the enhancement-mode transistor and the depletion-mode transistor. The drain electrode of the depletion-mode transistor is electrically connected to the drain lead of the package, the gate electrode of the enhancement-mode transistor is electrically connected to the gate lead of the package, and the source electrode of the enhancement-mode transistor is electrically connected to the conductive structural package base. The gate electrode of the depletion-mode transistor is electrically connected in direct contact with the conductive substrate, the conductive substrate is electrically connected in direct contact with the conductive structural package base, and the conductive structural package base is electrically connected to the source lead of the package.

[0008] In a third aspect, a half-bridge circuit is described. The half-bridge circuit comprises a high-side switch connected to a high-voltage node, a low-side switch connected to a ground node, and an inductor connected to a node between the high-side switch and the low-side switch. The low-side switch comprises a low-voltage enhancement-mode transistor and a high-voltage depletion-mode transistor. The half-bridge circuit is configured such that in a first operating mode, while the high-side switch is biased to ON and the low-side switch is biased to OFF, current flows through the high-side switch in a first direction and through the inductor. In a second operating mode, while the high-side switch is biased to OFF and the low-side switch is biased to OFF, current flows through the low-side switch in a second direction and through the inductor. In a third operating mode, while the high-side switch is biased to OFF and the low-side switch is biased to ON, current flows through the low-side switch in a second direction and through the inductor. During the second operating mode, the reverse DC current through the low-side switch is greater than 50A, and during the third operating mode, the increase in the on-resistance of the III-N depletion mode transistor is less than 5%.

[0009] In a fourth aspect, an electronic component is described that is cased within a package. The electronic component comprises a hybrid III-N device. The hybrid III-N device comprises a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a cascaded configuration. The packaged electronic component can block 600V in the forward direction and withstand a current greater than 50A in the reverse direction while the gate of the component package is biased to off, and the resistance of the electronic component while the gate is biased to on is less than 5% after withstanding the said reverse current while the gate of the electronic component is biased to off.

[0010] Each of the devices and transistors described herein may include one or more of the following features: The substrate is 1 × 10 19Hole / cm 3 It can be a doped p-type with a higher hole concentration. The substrate may be electrically coupled to the circuit ground. The III-N buffer layer may have a thickness greater than 4 μm and may be capable of blocking voltages greater than 600 V. The drain of the FET may be electrically connected to the source of the III-N device by solder, solder paste, or conductive epoxy. The gate electrode metal may contain Ti / Al or Ni / Au. The III-N material structure may be oriented in Ga polar orientation or N polar orientation. The drain electrode of the enhancement-mode transistor is in direct contact with and electrically connected to the source electrode of the depletion-mode transistor. The source electrode of the enhancement-mode transistor is coupled to the gate electrode of the depletion-mode transistor through a conductive substrate. The enhancement-mode transistor has a lower breakdown voltage than the depletion-mode transistor. The gate electrode of the III-N depletion-mode transistor may be electrically connected to a silicon substrate. The silicon substrate may be in direct contact with and electrically connected to a conductive structural package base. The structural package base is configured to be connected to the circuit ground. The enhancement mode transistor may also be a silicon MOSFET.

[0011] As used herein, a "hybrid enhancement mode electronic device or component" (or simply "hybrid device or component") is an electronic device or component formed from a depletion mode transistor and an enhancement mode transistor, where the depletion mode transistor is capable of a higher operating voltage and / or breakdown voltage compared to the enhancement mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement mode transistor having a breakdown voltage and / or operating voltage approximately as high as that of the depletion mode transistor. That is, a hybrid enhancement mode device or component includes at least three nodes having the following characteristics. When the first node (source node) and the second node (gate node) are maintained at the same voltage, the hybrid enhancement mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that an enhancement mode transistor can block) applied to the third node (drain node) with respect to the source node. When the gate node is maintained at a sufficient positive voltage (i.e., a voltage greater than the threshold voltage of the enhancement mode transistor) with respect to the source node, current passes from the source node to the drain node, or when a sufficient positive voltage with respect to the source node is applied to the drain node, current passes from the drain node to the source node. If the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid component can operate similarly to a single high voltage enhancement mode transistor. The depletion mode transistor may have a breakdown voltage and / or maximum operating voltage that is at least 2 times, at least 3 times, at least 5 times, at least 10 times, or at least 20 times that of the breakdown voltage and / or maximum operating voltage of the enhancement mode transistor.

[0012] As used herein, the terms group-III nitride or III-N material, layer, device, etc. refer to a material or device composed of a semiconductor composite material that follows the stoichiometric formula B w Al x In y Ga z N, where w + x + y + z is approximately 1, and 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. The III-N material, layer, or device can be formed or provided by directly growing it on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growing it on a suitable substrate, separating it from the original substrate, and bonding it to another substrate.

[0013] As used herein, when two or more contacts or other elements (such as conductive channels or components) are "electrically connected," it means that they are connected by a material with sufficient conductivity to ensure that, under any bias condition, the potentials of the respective contacts or elements are always made the same (e.g., approximately the same).

[0014] As used herein, "blocking a voltage" refers to the ability of a transistor, device, or component to prevent a substantial current (e.g., a current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied to the transistor, device, or component. In other words, while the transistor, device, or component is blocking the voltage applied to it, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices with an off-state current greater than this value exhibit high losses and low efficiency and are typically not suitable for many applications (especially power switching applications).

[0015] As used herein, a "high voltage device" (e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS)) is an electronic device optimized for high voltage applications. That is, when the device is off, it can block a high voltage (e.g., about 300V or more, about 600V or more, or about 1200V or more), and when the device is on, it has a sufficiently low on-resistance (R ON ) (e.g., the conduction loss experienced when a substantial current passes through the device is sufficiently low). A high voltage device can at least block a voltage equal to the high voltage supply or the maximum voltage in the circuit in which it is used. A high voltage device may be able to block 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device can block all voltages from 0V to V max up to, provided that V max is the maximum voltage that can be supplied by the circuit or power supply, and V max may be, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. For a bidirectional switch or four quadrant switch, when the switch is off, the voltage blocked may be of any polarity less than a specific maximum value (±300V or ±600V, ±1200V, etc., of ±V max ), and when the switch is on, the current may be in either direction.

[0016] In this specification, “III-N device” refers to a device based on a III-N heterostructure. A III-N device can be designed to operate as a transistor or a switch (where the state of the device is controlled by a gate terminal, or as a two-terminal device that blocks the flow of current in one direction and conducts in the other without a gate terminal). A III-N device may also be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (e.g., the gate voltage relative to the source is below the device threshold voltage), the device can at least support all source-drain voltages below the high voltage of the application in which the device is used (e.g., 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher). When the high-voltage device is biased on (e.g., the gate voltage relative to the source or associated power terminal is above the device threshold voltage), the device can conduct substantial current at low on-voltages (i.e., low voltages between source and drain or between both power terminals). The maximum acceptable voltage is the maximum on-state voltage that can be maintained in the application in which the device is used.

[0017] In this specification, the terms “over,” “under,” “between,” and “on” refer to the relative position of one layer to another. Therefore, for example, a layer positioned above or below another layer may be in direct contact with that other layer, or one or more layers may be interposed between them. Furthermore, a layer positioned between two layers may be in direct contact with those two layers, or one or more layers may be interposed between them. In contrast, the first layer “on” the second layer is in contact with the second layer. Moreover, the relative positions of each layer are provided assuming that operations are performed on the substrate, without considering the absolute orientation of the substrate.

[0018] In typical power switching applications using high-voltage switching transistors, the transistor is in one of two states for most of the time. In the first state (commonly called the "on state"), the voltage of the gate electrode relative to the source electrode is greater than the transistor threshold voltage, and substantial current flows through the transistor. In this state, the source-drain voltage difference is typically low, usually less than a few volts (e.g., about 0.1 to 5 volts). In the second state (commonly called the "off state"), the voltage of the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and substantial current does not flow through the transistor (except for off-state leakage current). In this second state, the source-drain voltage difference can vary arbitrarily from about 0V to the value of the circuit's high-voltage supply (in some cases 100V, 300V, 600V, 1200V, 1700V or higher, but can be lower than the transistor's breakdown voltage). In some applications, inductive elements in the circuit may cause the source-drain voltage to be even higher than the circuit's high-voltage supply. In addition, immediately after the gate is switched on or off, there is a short period of time during which the transistor is in a transition mode between the two states described above. When a transistor is in the off state, it is said to be “blocking the voltage” between its source and drain. In this specification, “blocking the voltage” means the ability of a transistor, device, or component to prevent substantial current (for example, a current greater than 0.001 times the average operating current during normal on-state conduction) from flowing through the transistor, device, or component when a voltage is applied to the transistor, device, or component. In other words, while a transistor, device, or component is blocking the voltage applied to it, the total current flowing through the transistor, device, or component will not be greater than 0.001 times the average operating current during normal on-state conduction.

[0019] When the hybrid enhancement mode device shown in Figure 1 is used in place of a conventional high-voltage E-mode transistor, the hybrid device operates as follows: When the hybrid device is ON, current flows through both the channels of the E-mode transistor and the D-mode transistor, and the voltages across each of these two transistors can be kept low, typically to a few volts or less. When the hybrid device is OFF, the voltage blocked by the hybrid device is divided between the E-mode transistor and the D-mode transistor. The E-mode transistor is approximately |V th,D | and V br,E Blocks the voltage between |V th,D | is the absolute value of the threshold voltage of a D-mode transistor, V br,E This is the breakdown voltage of the E-mode transistor. The remaining voltage across the hybrid device is blocked by the high-voltage D-mode transistor.

[0020] The accompanying drawings and the following description reveal details of one or more disclosed implementations of the subject matter described herein. Additional features and variations may also be included in the implementations. Other features, embodiments, and advantages will be evident from the description, drawings, and claims. [Brief explanation of the drawing]

[0021] [Figure 1] A schematic diagram of a conventional electronic component. [Figure 2A] Cross-sectional view of a hybrid III-N device. [Figure 2B] Figure 2A is a plan view of the hybrid III-N device. [Figure 2C] Figure 2A shows a cross-sectional view of the hybrid III-N device. [Figure 3] Perspective view of a packaged electronic component device. [Figure 4] A schematic diagram of an electronic component. [Figure 5A]A schematic diagram of the current path through a half-bridge buck converter circuit. [Figure 5B] A schematic diagram of the current path through a half-bridge buck converter circuit. [Figure 5C] A schematic diagram of the current path through a half-bridge buck converter circuit. [Figure 6A] Schematic diagram of the current path through the low-side switch of a half-bridge buck converter in various operating modes. [Figure 6B] Schematic diagram of the current path through the low-side switch of a half-bridge buck converter in various operating modes. [Figure 7A] A schematic diagram of the current path through a half-bridge boost converter circuit. [Figure 7B] A schematic diagram of the current path through a half-bridge boost converter circuit. [Figure 7C] A schematic diagram of the current path through a half-bridge boost converter circuit. [Figure 8] Cross-sectional view of another configuration of the hybrid III-N device. [Figure 9] Cross-sectional view of another configuration of the hybrid III-N device. [Figure 10] Cross-sectional view of another configuration of the hybrid III-N device.

[0022] The same symbols in each figure indicate the same elements. [Modes for carrying out the invention]

[0023] [Detailed explanation] This specification describes hybrid enhancement-mode electronic components, including depletion-mode transistors and enhancement-mode transistors assembled within a single electronic component package. The depletion-mode transistors (which may be high-voltage III-N devices) and enhancement-mode transistors (which may be low-voltage silicon FET devices) are arranged in a cascaded circuit configuration to form a hybrid device that can operate in the same manner as a single high-voltage E-mode III-N transistor and, in many cases, achieve identical or similar output characteristics. The depletion-mode transistor has a greater breakdown voltage than the enhancement-mode transistor (e.g., at least three times greater). The maximum blocking voltage when these hybrid electronic components are biased to the off state is at least the same magnitude as the maximum blocking voltage or breakdown voltage of the depletion-mode transistor. The hybrid electronic components described herein are configured to improve reliability and / or performance while reducing complexity and assembly costs compared to conventional hybrid devices in a package.

[0024] Figure 2A shows a cross-sectional view of an electronic device including a low-voltage E-mode device 122 (e.g., a silicon FET device) electrically connected to a high-voltage D-mode III-N device 123 (e.g., a GaN HEMT device) to form a single high-voltage hybrid III-N device 100. The E-mode device 122 includes a semiconductor body layer 25, an FET source electrode 131 and an FET gate electrode 132 on the first side of the semiconductor body layer 25, and an FET drain electrode 133 on the side of the semiconductor body layer 25 opposite to the FET source electrode 131.

[0025] The D-mode III-N device 123 in Figure 2A includes a III-N material structure 24 (e.g., a combination of GaN and AlGaN) grown on a suitable conductive substrate 14. This may be a conductive semiconductor (e.g., silicon (e.g., p-type or n-type Si), GaN, or any other sufficiently conductive substrate). For example, the substrate may be 1 × 10⁻⁶ 19 Hole / cm 3 It may also be a doped p-type with a higher hole concentration, 1 × 10 19 electron / cm 3 The substrate may be a doped n-type with a higher electron concentration. The substrate may have high or low thermal conductivity, and in the case of a substrate with low thermal conductivity, the substrate may be thinned to improve heat dissipation. The substrate may have a lattice constant and / or coefficient of thermal expansion similar to or different from any of the material layers of the III-N material structure 24. A back metal layer 42 (e.g., Ti / Ni / Ag) may be formed on the back side of the substrate opposite to the III-N material structure 24. The back metal layer 42 can be used as an adhesive layer to enable the substrate to be attached to a device package base (e.g., a lead frame) by solder, solder paste, conductive epoxy, conductive tape or other suitable mounting method (that enables a high-quality mechanical, thermal, and electrical connection of the device substrate 14 to the device package base).

[0026] The III-N material structure 24 may include a III-N buffer layer 15 (e.g., GaN or AlGaN) grown on the substrate 14. The buffer layer 15 may be manufactured to be insulating or substantially free of unintended n-type mobile carriers by including dislocations or point defects within the layer, or by doping the layer with compensatory elements (e.g., Fe, C, and / or Mg, etc.). The buffer layer may have a substantially uniform composition throughout, or its composition may vary. For example, depending on the packaging, the buffer layer may be compositionally graded by grading the aluminum component of the buffer layer (e.g., the substrate is Al x G 1-xN is the maximum voltage (where x varies through the substrate). The thickness and composition of the buffer layer 15 may be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the maximum voltage or high-voltage supply in the circuit in which it is used. For example, the buffer layer 15 may be able to block voltages greater than 600V or greater than 900V. The thickness of the buffer layer 15 can be greater than 4μm, and for example, a III-N buffer layer may have a thickness between 5μm and 8μm.

[0027] The III-N material structure may further include a III-N channel layer 16 (e.g., GaN) above the III-N buffer layer 15, and a III-N barrier layer 17 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 16. The band gap of the III-N barrier layer 17 is greater than the band gap of the III-N channel layer 16. The III-N channel layer 16 has a different composition from the III-N barrier layer 17, and the thickness of the composition of the III-N barrier layer 17 is selected so that a two-dimensional electron gas (2DEG) channel 19 (shown by a dashed line in Figure 2A) is induced in the III-N channel layer 16 adjacent to the interface between layers 17 and 16.

[0028] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) or other techniques in a reactor. As shown in Figure 2A, the III-N material structure may be grown in a group III polarity (e.g., Ga polarity) orientation (e.g., [0 0 0 1] (C-plane) orientation). That is, the source, gate, and drain contacts of the HEMT are formed above the group III plane (e.g., [0 0 0 1] plane) of the III-N material structure, which is typically on the opposite side of the III-N material structure from the substrate on which the III-N layer is formed. Alternatively, III-N HEMTs may be formed on III-N material structures grown in an N polarity (i.e., N-plane) orientation (e.g., [0 0 0 -1] orientation (not shown), etc.). In this case, the source, gate, and drain contacts of the HEMT are formed above the N-plane (e.g., the [0 0 0 -1] plane) of the III-N material structure. Here, the III-N material structure may include a II-N barrier layer above a III-N buffer layer and a III-N channel layer 16 above the III-N barrier layer 17. The band gap of the III-N barrier layer 17 is greater than the band gap of the III-N channel layer 16, and the thickness and composition of the III-N barrier layer 17 are selected so that a two-dimensional electron gas (2DEG) channel 19 is induced in the III-N channel layer 16, adjacent to the interface between the III-N channel layer 16 and the III-N barrier layer 17. N-polar III-N materials have a polarization field opposite to that of Group III polar III-N materials and thus can enable the implementation of III-N devices that cannot be fabricated using Group III polar structures.

[0029] The insulating layer 18 (e.g., dielectric layer) is grown or deposited on the upper surface of the III-N material structure. The insulator 18 is, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al 1-x Six The insulator may be formed from or include ON or any other wide-bandgap insulator. Although the insulator 18 is illustrated as a single layer, it may alternatively be formed from several layers deposited between various processing steps to form a single composite insulating layer. The insulating layer 18 may be entirely constant or may be formed from insulating materials of varying types. For example, the insulating layer may have a first portion formed from MOCVD SiN (e.g., SiN deposited by MOCVD) and a second portion formed from PECVD SiN (e.g., SiN deposited by PECVD).

[0030] The source electrode 134 and drain electrode 136 are formed on the side of the device 100 opposite to the substrate, so that the device 100 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 134 and drain 136). The source electrode 134 and drain electrode 136 are in ohmic contact and are electrically connected to the device 2DEG channel 19 formed within layer 16. The source and drain electrodes 134,136 (e.g., source and drain contacts) may be formed by a metal stack. Recesses may be formed within the III-N barrier layer 17 to improve the ohmic contact from the source and drain electrodes 134,136 to the 2DEG channel 19. The metal stack may be Ti / Al / Ni / Au, Ti / Al, or other suitable metals. The source and drain contacts 134,136 may be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact treatments, including sputtering and dry etching, may also be used.

[0031] The device 100 further includes a gate electrode 135 (e.g., a gate contact). The gate electrode 135 may be formed such that at least a partially insulating layer 18 exists between the gate electrode and the III-N material structure 24, as shown in Figure 2A, or alternatively, the gate electrode 135 may be formed to contact the III-N material structure 24 (not shown). The gate electrode 135 may be formed from a suitable conductive metal such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)) and may be deposited by metal vapor deposition or sputtering or chemical vapor deposition or various atomic layer deposition (ALD) methods. Alternatively, the gate electrode 135 may be another conductive material or material stack containing one or more materials with a large work function, such as a semiconductor material with a large work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0032] The gate electrode 135 is electrically connected to the substrate 14 by a via hole 38 that is formed through a portion of the III-N material structure 24, exposing a portion of the upper surface of the substrate 14, as shown in the dashed area of ​​Figure 2A (e.g., through-epi-via or TEV). The metal of the gate electrode 135 is formed, at least partially, within the via hole 38 so that the gate electrode 135 of the III-N device 23 is electrically connected to the substrate 14. The dashed area of ​​Figure 2A shows a via hole 38 that penetrates the 2DEG channel 19, but as further shown in Figures 2B and 2C, the via hole 38 is formed in such a way that the 2DEG channel 19 is continuous between the source electrode 134 and the drain electrode 136 (e.g., the via hole is formed in a region outside the active region of the device).

[0033] Figures 2B and 2C show a plan view and a cross-sectional view of the III-N device 123 of Figure 2A, respectively, and the cross-sectional view of Figure 2C is indicated by the dashed line 27 in Figure 2B. The active region of the device is indicated by the dashed region 26. Outside the active region, the semiconductor material is typically etched or otherwise treated (e.g., by ion embedding) so that no conductive channels are present, thereby preventing short circuits between parts of the device that are designed to be insulated from one another. As shown in Figures 2B and 2C, via holes 38 and 38' are formed outside the active region 26 and extend through the III-N material structure 24, exposing a portion of the upper surface of the substrate 14. The gate electrode metal is formed at least partially within the via holes 38 and 38' so that the gate electrode 135 is electrically connected to the substrate 14. As used herein, the “active region” of the transistor refers to the source and drain regions (i.e., region 26) along the region containing the device channel between the source and drain electrodes 134, 136 in Figures 2B and 2C.

[0034] Now returning to Figure 2A, the low-voltage E-mode device 122 is electrically connected to the high-voltage D-mode III-N device 123 to form a hybrid III-N device 100. Here, the drain electrode 133 of the E-mode device 122 is electrically connected to the source electrode 134 of the III-N device 123 by direct contact (for example, mounted on it) through a portion of the source contact, which is shown as a source pad 137 formed above a portion of the insulating layer 18. The source pad 137 may extend above the active region of the D-mode device 123, as shown in Figure 2A, so that the E-mode device 122 is directly mounted above the active region of the D-mode device 123. Alternatively, the insulating layer 18 may extend outside the active region of the D-mode device 123, and the source pad 137 may extend above the insulating layer 18 outside the active region of the D-mode device 123, and the E-mode device 122 may be mounted on the source pad 137 outside the active region of the D-mode device 123. The drain 133 of the E-mode device 122 may be connected to the source pad 137 of the D-mode device 123 by, for example, solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method that allows for a high-quality mechanical, thermal, and electrical connection between the source pad 137 of the source electrode 134 and the FET drain electrode 133. Conventional hybrid devices assembled in a single package typically require common packing side-by-side on a ceramic insulating substrate (e.g., AlN shims) and an external wire connector providing the connection from the FET drain to the HEMT source. However, as shown in Figure 2A, directly mounting the E-mode device 122 on the D-mode device 123 eliminates the need for an external wire connector and ceramic substrate. This drastically reduces the parasitic inductance of the circuit, enabling higher current ratings and faster switching speeds.

[0035] Figure 3 is a perspective view of a hybrid III-N device 100 integrated within an electronic component package 200. The package 200 is a three-terminal package comprising a conductive structural package base 310 (e.g., aluminum, copper, or nickel lead frame), a gate lead 312 (i.e., first terminal), a source lead 311 (i.e., second terminal), and a drain lead 313 (i.e., third terminal), where the gate lead 312 and drain lead 313 are electrically isolated from the conductive structural package base 310, and the source lead 311 is electrically connected to the conductive structural package base 310. Optionally, mounting holes 29 may be included. In addition, the package 200 may include a plastic or metal case (not shown) surrounding the device. The substrate 14 of the hybrid device is directly mounted and electrically connected to the conductive structural package base 310. The substrate 14 may be mounted to the package base by, for example, solder, conductive epoxy, conductive tape, or other suitable mounting method that allows for high-quality mechanical, thermal, and electrical connections of the substrate 14 to the structural package base 310. Typically, conventional hybrid device packaging methods use a ceramic or insulating substrate (e.g., an AlN shim) between the device substrate 14 and the package base 310 to electrically insulate the substrate from the package. The package base 310 can be directly attached to a heat sink (not shown), thereby creating electrical and thermal contact between the package base 310 and the heat sink, i.e., they are electrically connected, allowing heat generated by the hybrid device to be dissipated through the heat sink. The heat sink may be the circuit ground, or electrically connected to the circuit ground, in which case the package base 310, the substrate 14, and the gate 135 of the III-N device are each electrically connected to the circuit ground.

[0036] The gate lead 312 of package 200 is coupled (e.g., electrically connected) to the gate electrode 132 of E-mode device 122 by connector 41. The drain lead 313 of package 200 is coupled (e.g., electrically connected) to the drain electrode 136 of III-N device 123 by connector 43. The conductive structural package base 310 is coupled (e.g., electrically connected) to the source electrode 131 of E-mode device 122 by connector 42. The gate electrode 135 of III-N device 123 is coupled (e.g., electrically connected) to the conductive structural package base 310 through the conductive substrate 14 and via holes 38 / 38'. Connectors 41, 42, and 43 may each comprise a single wire bond (illustrated), or multiple parallel wire bonds, ribbons, conductive metal clips, or other connectors comprising a conductive material such as aluminum (Al), gold (Au), copper (Cu), or other suitable material.

[0037] As shown in Figure 3, the gate contact 135 of the D-mode III-N device 123 is electrically connected to the substrate 14 by via holes 38 / 38' formed through the III-N material structure 24. As described above, the substrate 14 is directly mounted to the conductive structural package base 310 so as to be electrically connected to it. This configuration allows the gate electrode 135 of the III-N device to be electrically coupled (e.g., electrically connected) to the source lead 311 of the package device 200 without the use of external wire connectors required in conventional methods. This configuration also allows the gate electrode 135 to be electrically coupled (e.g., electrically connected) to the source electrode 131 of the E-mode device 122. The gate electrode 135 may include a contact pad area exposed on the upper surface of the D-mode device 123 (which may be practical for device testing (e.g., device probing)) (as shown in Figure 3), but it may be preferable to completely encapsulate the upper surface of the gate electrode 135 with a dielectric material (e.g., a dielectric layer 18) so that there is no area of ​​the gate electrode 135 exposed on the upper surface of the D-mode device 123. In addition, conventional hybrid device assembly techniques typically use ceramic or insulating shims (e.g., AlN shims) between the device substrate 14 and the package base 310 to electrically isolate the substrate from the package source leads 311. This requires the use of additional wire connectors to connect the gate electrode 135 to the package source leads 311. When insulating shims are included between the package base 310 and the D-mode device substrate 14, the substrate 14 is not maintained at a fixed potential but at a floating potential (e.g., somewhere between the potential of the D-mode device gate 135 and the potential of the D-mode device drain 136), which consequently results in the voltage difference between the D-mode device drain 136 and the D-mode device substrate 14 being substantially smaller than the voltage difference between the D-mode device drain 136 and the D-mode device gate 135.By removing the ceramic shim and connecting the substrate 14 to the package base 310, the substrate voltage is fixed at 0V (i.e., ground potential), and the entire gate-drain voltage is applied to the III-N buffer layer 15. Thus, careful design considerations are required with respect to the III-N buffer layer 15 in order to maintain sufficient device breakdown voltage characteristics (for example, the buffer layer 15 can be made thicker to prevent leakage and / or dielectric breakdown caused by the increased potential across the buffer layer). In this way, the hybrid III-N device 100 does not include a ceramic shim and can be assembled in a component package 200 with three or fewer connectors, whereas conventional assembly methods (which require a ceramic shim or are assembled without via holes 38) require four or more connectors. This reduces the number of components required in the package (e.g., bill of materials or BOM), thereby reducing the overall assembly cost. The component package 200 in Figure 3 shows a led package such as TO-220 or TO-247. However, alternative embodiments with leadless packages such as quad flat no-lead (QFN), surface-mount devices (SMD), or loss-free packages (LFPAK) can also be used. In addition, the components of package 200 can be oriented or arranged in a manner that best suits the needs of the designer and package type.

[0038] Figure 4 shows a schematic circuit of the hybrid device in Figure 1, and also shows the various parasitic inductances and capacitances inherent in the device. Parasitic gate-drain capacitance (C) of D-mode device 23 GDThe ) is represented as capacitor 57. The built-in body diode of the E-mode device 22 is represented by diode 37. The parasitic inductance of the source connection of the E-mode device 22 is represented as inductor 54, and the parasitic inductance of the gate connection of the D-mode device 23 is represented as inductor 53. If the circuit in Figure 4 is implemented in a component package similar to the package 200 in Figure 3, inductor 54 represents the inductance of the wire (e.g., wire 42 in Figure 3) connecting the source 131 of the E-mode device 122 to the package base 310, and the area enclosed by the dashed line 56 in Figure 4 represents the package base 310 in Figure 3. The package source lead 311 may be connected to the circuit ground 55. An external gate wire connector is used to connect the gate electrode 35 of the D-mode device 23 to the package source lead 11 (or package base) so that the gate electrode 35 of the D-mode device 23 connects to the source electrode 31 of the E-mode device 22. This gate wire connector creates a substantial inductance (represented by inductor 53) between the gate electrode 35 of the D-mode device 23 and the package source lead 11 (or package base). Parasitic inductances 53 and 54 can slow down the device's turn-on and turn-off times, increase switching losses, and degrade the device's performance.

[0039] In the hybrid device 100 shown in Figure 2A, the gate electrode 135 of the D-mode device 123 is electrically connected to the substrate 14 via a via hole 38. Therefore, when the device 100 is mounted in a package as shown in Figure 3, the gate 135 is electrically connected to the conductive substrate 14, and the conductive substrate 14 is directly mounted (and thus electrically connected) to the package base 310, so an external wire connector between the gate 135 of the D-mode device 123 and the package base 310 is unnecessary. Furthermore, the parasitic inductance of the gate connection to the substrate 14 through the via hole 38 is substantially reduced compared to the parasitic inductance 53 corresponding to the external connection required for the device in Figure 1. As a result, the device 100, cased in the component package 200, exhibits substantial improvements in switching characteristics, reduced degradation of on-resistance, and substantially lower packaging costs compared to the device in Figure 1, also cased in the package 100. Some of the improvements in switching characteristics are described in more detail below.

[0040] Figures 5A, 5B, and 5C show three different modes for operating the half-bridge buck converter circuit. The half-bridge circuit includes a high-side switch 82 connected to a high-voltage node 91 and a low-side switch 83 connected to a ground node 92. Inductor 93 is connected to node 94 (between the low-side switch 83 and the high-side switch 8) and the output node V of the circuit. OUT It is connected between the two. The first capacitor 86 is connected between the high-voltage node 91 and the DC ground 92. The second capacitor 87 is connected between the output node V of the circuit. OUT It is connected between and DC ground 92. The low-side switch 83 is selected to have characteristics that improve the efficiency of the step-down converter circuit. Specifically, switch 83 has a low on-resistance (R DS(ON)) and should have low switching losses. Switch 83 may be, for example, the hybrid device shown in Figure 1. Alternatively, switch 83 may be implemented as the hybrid device 100 shown in Figures 2A-2C, assembled within the component package 200 shown in Figure 3.

[0041] The step-down converter half-bridges in Figures 5A and 5C can be operated as follows: Referring to Figure 5A, in the first operating mode, the gate of the high-side switch 82 is biased to ON (i.e., V GS82 >V TH ), the gate of the low-side switch 83 is biased to off (i.e., V GS83 <V TH ). Current 97 flows forward from the high-voltage node 91 through the high-side switch 83 to node 94. This current is blocked by the low-side switch 83 and flows through the inductor 93 as indicated by the current path 97. While the device is operating in the first operating mode, the gate-source voltage of the high-side switch 82 is switched to low or off (i.e., V GS82 <V TH ), when both gates of switches 82 and 83 are biased to the off position, the buck converter switches to the second operating mode shown in Figure 5B. Current must continue to flow through inductor 93.

[0042] Figure 6A shows the current path through the low-side switch 83 during the transition time T1 between the first operating mode and the second operating mode shown in Figures 5A and 5B. During the transition time T1, the voltage at node 94 (shown in Figures 5A to 5C) drops to a negative value, and the current path I in Figure 6A ACAs shown, a displacement current flows through the parasitic gate-drain capacitor 57 of the D-mode device 23. When the voltage at node 94 becomes sufficiently negative, the built-in body diode 37 of the E-mode device 22 switches on, and switch 83 becomes reverse-conducting. This is called the reverse-conducting mode (i.e., freewheeling diode mode). At the end of transition time T1, switch 83 transitions from off to reverse-conducting, and the current changes from the displacement current through the gate-drain capacitor 57 of the D-mode device 22 to the reverse DC current flowing through the built-in body diode 37 of the E-mode device 22 and the channel of the D-mode device 23 (current path I in Figure 6B). DC The transition is abrupt to (as shown by). When the operating current through the inductor 93 is high, the current path transition may cause a voltage spike across the gate of the D-mode device 23, resulting in ringing. This voltage spike injects charge into the gate dielectric 18 of the D-mode device 23, causing the on-resistance (R) of the D-mode device to change sharply. ON This leads to an increase in the on-resistance of the hybrid device. Since the current in inductor 93 must be continuous, the circuit in Figure 5B requires reverse conduction of switch 83 even when the gate of switch 83 is biased to off.

[0043] Returning to Figure 5C, as shown in Figure 5B, after the gate of the high-position 82 switches off, the low-position switch 83 switches on (i.e., V GS83 >V TH ), the step-down converter is operated in the third operating mode, and the current continues to flow through the low-side switch 83 in the same direction (reverse direction) as in the second mode, except that the low-side switch 83 is biased to ON. By biasing the low-side switch to ON during the third operating mode, the reverse voltage drop across the E-mode device 22 is reduced compared to the second operating mode, enabling higher efficiency compared to the second operating mode. To prevent the high-voltage rail from accidentally short-circuiting to ground, a sufficient dead time is required between the time the high-side switch 82 is turned OFF and the time the low-side switch 83 is turned ON.

[0044] The design of the device and associated package can be a critical factor in determining the performance of the low-side switch 83 in reverse conduction mode. By implementing device 100 as the low-side device 83 within package 200, and thereby eliminating the need for an external gate wire connection between the D-mode device 23 and the package base (since the D-mode device gate is connected to the package base through via holes 38), parasitic inductance within the packaged device (indicated by inductor 53) is reduced. This reduces voltage spikes and ringing experienced by the gate of the D-mode device 23 during current path transitions between the first and second operating modes. Surprisingly, it was shown that the degradation (i.e., increase) of the device's on-resistance is substantially reduced compared to conventional packages with external gate wires, even when operating with very high reverse DC currents. This result was unexpected. When device 100 is implemented as a low-side switch 83 within package 200, switch 83 can operate with reverse DC currents greater than 50A (or even greater than 70A) during the second and third operating modes with little increase in on-resistance. For example, the increase in on-resistance may be less than 5%. Conventional packages with external gate wire connections may typically exhibit an increase in on-resistance greater than 30% (or even greater) even while operating with reverse DC currents of 30A or less. The low-side switch 83 can block voltages greater than 600V during the first operating mode. In addition, the high-side switch 82 may be the same type of switch as the low-side switch 83, but does not undergo the same abrupt current transition conditions and therefore does not need to be designed to such stringent requirements.

[0045] Figures 7A, 7B, and 7C show three different modes of operation for the half-bridge boost converter circuit, respectively. The half-bridge circuit includes a high-side switch 84 connected to a high-voltage node 91 and a low-side switch 85 connected to a ground node 92. An inductor 101 is connected between node 102 (between the low-side switch 85 and the high-side switch 84) and the input node VIN of the circuit. A first capacitor 88 is connected between the input node VIN and DC ground 92. A second capacitor 87 is connected between the high-voltage node 91 and DC ground 92. Here, unlike a buck converter, the high-side switch 84 must be carefully selected to improve the efficiency of the boost converter circuit. In particular, switch 84 should have a low on-resistance (R DS(ON) ) and should have low switching losses. Switch 85 may be, for example, the hybrid device shown in Figure 1. Alternatively, switch 85 may be implemented as the hybrid device 100 shown in Figures 2A-2C, assembled within the component package 200 shown in Figure 3.

[0046] The boost converter half-bridges in Figures 7A and 7C can operate as follows: Referring to Figure 7A, in the first operating mode, the gate of the high-side switch 84 is biased to off (i.e., V GS84 <V TH ), the gate of the low-side switch 85 is biased to ON (i.e., V GS85 <V TH The current flows through the inductor 101 to node 102, as shown by the current path 103, and also through the low-side switch 85 in the forward direction to ground 92. While the device is operating in the first operating mode, the gate-source voltage of the low-side switch 85 is at the off low (i.e., V) GS85 <V TH When the switch is flipped and the gates of both switches 84 and 85 are biased to the off position, the boost converter switches to the second operating mode shown in Figure 7B. Current must continue to flow through inductor 101.

[0047] The current path through the high-side switch 84 during the transition between the first and second operating modes may be similar to the current path described in Figures 6A and 6B. During the transition, the voltage at node 102 rises, and a displacement current flows through the parasitic gate-drain capacitor of the D-mode device used in switch 84. When the voltage at node 102 becomes sufficiently higher than the high-voltage node 91, the built-in body diode of the E-mode device used in switch 84 switches on, and switch 84 becomes reverse-conducting. The behavior and effects of the high-side switch 84 during the transition from off to reverse conduction are similar to those described for the buck converter in Figures 5A-5C and the low-side switch 83 in Figures 6A and 6B.

[0048] Returning to Figure 7C, as shown in Figure 7B, after the gate of the low-side switch 85 is switched off, the gate of the high-side switch 84 is switched on (i.e., V GS84 >V TH ), the boost converter is operated in the third operating mode, and the current continues to flow through the high-side switch 84 in the same direction as in the second mode. By biasing the high-side switch to the ON position during the third operating mode, the reverse voltage drop across the E-mode device of switch 84 is reduced, enabling higher efficiency compared to the second operating mode. To prevent the high-voltage rail from accidentally short-circuiting to ground, a sufficient dead time is required between the time when the low-side switch 85 is turned OFF and the time when the high-side switch 84 is turned ON. When the hybrid package component 200 is used as the high-side switch 84, the boost converter circuit in Figures 7A to 7C can support similar performance characteristics to those described for the low-side switch 83 in Figures 5A to 5C. In addition, the low-side switch 85 may be the same type of switch as the high-side switch 84, but does not undergo the same abrupt current transition conditions and therefore does not need to be designed with such stringent requirements.

[0049] Referring to Figure 8, another configuration of the hybrid III-N device is shown. Device 800 in Figure 8 is similar to device 100 in Figure 2A, except that the III-N material structure 24 is manufactured on an insulating substrate 814 (e.g., a sapphire substrate) or a semi-insulating substrate (resistivity ≥ 1E5Ω·cm; e.g., a silicon carbide substrate) instead of a conductive silicon substrate (shown in Figure 2A). As described above for the packaged device 100 in Figure 2A, the conductive substrate 14 is grounded to 0V, and as a result, the entire gate-drain voltage is applied to the buffer layer 15. This requires careful design of the III-N buffer layer 15, which limits the high breakdown voltage of device 100. By using a sapphire (or other insulating or semi-insulating) substrate within device 800, the breakdown voltage of device 800 can be substantially higher than that of device 100. For example, the breakdown voltage of device 800 can be greater than 1200V and greater than 2400V, and greater than 10kV under certain design implementations. A typical sapphire substrate has a nominal thickness of ~700μm. However, substrate 814 can be made thinner to improve the thermal performance of the substrate. For example, insulating substrate 814 may have a thickness of less than 200μm.

[0050] In device 800, the gate via hole 838 extends through the entire thickness of the III-N material structure 24 and the entire thickness of the insulating substrate 814, allowing the gate 135 of the D-mode device 123 to be electrically connected to the back metal layer 842. The back metal layer 842 may have similar properties (e.g., conductivity) to the back metal layer 42 of device 100, or alternatively, layer 842 may be different. For example, the back metal layer 842 may be a plated material such as a Ni or Cu layer with a thickness greater than 6 μm. The gate via hole 838 may be formed in the same region as the gate via hole 38 in the device (e.g., outside the active region of the device). The gate via hole 838 can be produced using several different manufacturing techniques. For example, the gate via hole 838 may be formed through the III-N material structure 24 and the substrate 814 by etching (e.g., dry etching or wet etching) or laser ablation (or a combination of both), forming a hole through the substrate on the side opposite to the material structure 24.

[0051] Alternatively, the gate via holes 838 may be formed by etching through the entire thickness of the III-N material structure 24 and partially etching through the substrate 814 (e.g., etching 200 μm within a 700 μm substrate). The gate via holes 838 may then be filled with a metal stack (e.g., Al, Ni, or Cu, etc.) by sputter deposition or plating. Following the metal deposition process, the substrate 838 may be thinned to a thickness of less than 200 μm by polishing the side of the substrate opposite to the III-N material stack, exposing the metal stack on the back surface of the substrate. After substrate thinning, a back metal layer 842 may be deposited at locations where electrical connections to the gate metal stack formed in the gate via holes are to be formed.

[0052] Before or after the formation of the gate via holes 838, a back metal layer 842 may be formed on the substrate, on the side opposite to the III-N material layer 24. After etching the gate via holes 838, a metal deposition process may follow (forming a metal stack on the back surface of the substrate 814 and at least partially into the gate via holes 838 from the back side, in a position where the metal stack contacts the gate metal 135 of the III-N device 123).

[0053] The front and back sides of the device can be simultaneously double-sided Cu plated, such that the gate via hole 838 is plated from the front side of the device and the back metal layer 842 is plated from the back side of the device in a single processing step. The plated Cu layer may have a thickness of 10 μm or more on both sides of the device. The via hole 838 (extending through the entire thickness of the insulating substrate 814) allows the device 800 to be mounted in a package similar to the package of device 200 in Figure 3, and the gate 135 of the D-mode III-N device 123 can be electrically connected to the package base 310 without the use of an external gate wire connector.

[0054] Referring to Figure 9, another embodiment of the hybrid III-N device is shown. Device 900 in Figure 9 is similar to device 100 in Figure 2A, except that, in contrast to the “dion die” configuration of device 100, the low-voltage E-mode device 122 and the high-voltage D-mode III-N device 123 are packaged within device 900 in a “side-by-side” configuration. As described above for the “dion die” (e.g., device 100 in Figure 2A), the E-mode device 122 is mounted directly on the source pad 137 of the D-mode device 123, eliminating the need for an external wire connector to connect the source electrode 134 of the D-mode device to the FET drain electrode 133 of the E-mode device. However, depending on the application, the D-mode III-N device 123 may be too small, resulting in insufficient area to directly mount the E-mode FET 122 to the source pad 137 on the top side of the D-mode device. For applications with these size limitations, the hybrid device may be arranged in a “side-by-side” configuration as shown in Figure 9.

[0055] A shim 291 is mounted between the E-mode device 122 and the package base 310. The shim includes a ceramic or insulating layer 297 (e.g., AlN) and may have metal layers 298 and 299 on either side of the insulating layer 297. The metal layer 299 acts as an adhesive layer, thereby allowing the shim to be mounted to the device package base 310 by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method (that enables a high-quality mechanical and thermal connection of the shim 291 to the device package base 310). The drain electrode 133 of the device 122 is mounted to the metal layer 298 on the upper side of the insulating shim 291 by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method. The source electrode 134 of the III-N device 123 is electrically connected to the drain electrode 133 of the E-mode device 122 by a wire connector 44 extending from the source electrode 134 to the upper metallized surface 298 of the insulating shim 291. This electrically connects the source electrode 134 and the FET drain electrode 133. Other wire connections and configurations of device 900 may be similar to those of device 100 in Figure 2A. Device 900 may have advantages over device 100 in that it may allow the use of smaller / less expensive III-N HEMTs. However, device 900 may also require increased packaging complexity compared to device 100.

[0056] Figure 10 shows another hybrid III-N device 1000. Device 1000 in Figure 10 is similar to device 900 in Figure 9, except that an alternative design is implemented for the low-voltage E-mode device, which allows the E-mode and D-mode devices to be packaged in a "side-by-side" configuration without the use of ceramic shims. A typical silicon MOSFET (e.g., FET 122 in device 900) is a vertical device manufactured so that the FET drain 133 is on the bottom side of the semiconductor body 25 and the FET gate 132 and FET source 131 are on the top side of the semiconductor body 25. However, device 1000 is implemented using a silicon MOSFET with an alternative semiconductor body 125, where the FET source electrode 231 is on one side (e.g., the bottom) of the semiconductor body 125, and both the FET gate electrode 232 and the FET drain electrode 233 are on the same side (e.g., the top) of the semiconductor body 125, opposite to the FET source electrode 231, forming an inverted E-mode FET 124. In this way, the FET 124 can be implemented within device 1000 to eliminate the need for the insulating shim 291 and source connector 42 included in device 900.

[0057] As shown in Figure 10, the source electrode 231 of the inverted E-mode FET 124 can be directly attached to and electrically connected to the conductive structural package base 310 by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method (which allows for a high-quality mechanical, thermal, and electrical connection between the FET 124 and the package base 310). The source electrode 134 of the III-N device 123 is connected to the drain electrode 233 of the E-mode FET 124 by a wire connector 144. Device 1000 may have advantages over device 900 in that it reduces packaging complexity and cost by eliminating the need for several packaging components (including the insulating shim 291 and source connector 42) shown in Figure 9.

[0058] Several embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the technology and devices described herein. Therefore, other implementations are also within the scope of the appended claims.

Claims

1. It is an electronic component, Enhancement mode transistors and A depletion-mode transistor equipped with a conductive substrate, A package comprising a conductive structural package base, wherein the package encloses both the enhancement mode transistor and the depletion mode transistor, Equipped with, The drain electrode of the depletion-mode transistor is electrically connected to the drain lead of the package. The gate electrode of the enhancement mode transistor is electrically connected to the gate lead of the package. The source electrode of the enhancement mode transistor is electrically connected to the conductive structural package base. The gate electrode of the depletion mode transistor is electrically connected to the conductive substrate by direct contact. The conductive substrate is electrically connected to the conductive structural package base by direct contact. The conductive structural package base is an electronic component electrically connected to the source leads of the package.

2. In claim 1, An electronic component in which the gate electrode of the depletion-mode transistor is electrically connected to the source lead of the package without an external gate wire connector.

3. In claim 1, The depletion mode transistor is an electronic component having a III-N material structure on the conductive substrate.

4. In claim 3, The gate electrode of the depletion-mode transistor is located on the side of the III-N material structure opposite to the conductive substrate. The III-N material structure includes vias extending to the conductive substrate. The gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate through the via, forming an electronic component.

5. In claim 4, The via is an electronic component located outside the active region of the depletion-mode transistor.

6. In claim 1, The drain electrode of the enhancement mode transistor is electrically connected to the source electrode of the depletion mode transistor by direct contact. The enhancement mode transistor is an electronic component located at least partially above the active region of the depletion mode transistor.

7. In claim 6, An electronic component in which the source electrode of the enhancement mode transistor is coupled to the gate electrode of the depletion mode transistor through the conductive substrate.

8. In claim 6, The enhancement-mode transistor is an electronic component having a lower breakdown voltage than the depletion-mode transistor.

9. In claim 3, The III-N material structure comprises a III-N buffer layer, a III-N channel layer, and a III-N barrier layer. The III-N buffer layer is an electronic component doped with iron, magnesium, or carbon.

10. The electronic component according to claim 9, wherein a lateral 2DEG channel is induced in the III-N channel layer due to a compositional difference between the III-N barrier layer and the III-N channel layer.

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