General-purpose logic memory cell

Abstract

SOLUTION: In a universal logic memory cell 300, a first network element 310 and a second network element 311 are composed of a first parallel connection part to which a common drain region is connected and a second parallel connection part to which a common source region is connected between a first serial connection part in which drain regions and source regions of two triple-gate silicon elements of four triple-gate silicon elements 301 are connected in series and a second serial connection part in which drain regions and source regions of the remaining two triple-gate silicon elements are connected in series. The triple-gate silicon elements aligned in respective positions are selectively driven in either one of a first channel mode and a second channel mode.EFFECT: A universal logic memory cell can be embodied that provides a ternary logic operation function and a memory function using triple-gate silicon elements driven by a positive feedback loop.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] [Cross-reference with related applications] This application claims priority under Korean Patent Application No. 10-2023-0191705 dated December 26, 2023, and all content disclosed in the said Korean Patent Application is incorporated herein by reference.

[0002] The present invention relates to a general-purpose logic memory cell composed of a triple-gate silicon element, and more specifically, to a technology for realizing a general-purpose logic memory cell that provides ternary logic operation and memory functions using a triple-gate silicon element driven by a positive feedback loop. [Background technology]

[0003] In conventional von Neumann-based computer systems, the processor and memory are separated, and data is transmitted via a bus.

[0004] However, with the increase in computing power, bottlenecks are beginning to occur due to the difference in data processing speed between the processor and memory, and the processing of large amounts of data is starting to show its limitations.

[0005] In other words, while the von Neumann-based system, a revolutionary development in the semiconductor industry, improved the integration density and performance of modern computers, it has the drawback of consuming a lot of energy and resulting in long data transmission and latency due to the physical separation between the processor and memory hierarchy.

[0006] In the post-Fourth Industrial Revolution era, considering the increase in data-intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI), a new computing paradigm is essential to meet the demands of large-scale data processing.

[0007] To address the aforementioned problems, research into logic memory technology, which integrates computing and memory functions, is being intensified and accelerated.

[0008] Logic memory technology allows the processor's arithmetic functions and the memory's storage functions to be performed in the same space, thereby reducing delay time and power consumption during data transmission and significantly improving the system's integration density.

[0009] Conventional logic memory technology has been actively researched based on volatile memory elements such as SRAM (static random access memory) and DRAM (dynamic RAM), and non-volatile memory elements such as ReRAM (resistive RAM), MRAM (magnetoresistive RAM), and PCRAM (phase-change RAM).

[0010] In the case of volatile memory element-based logic memory technology, a large number of transistors are required for stable operation, resulting in limitations such as a large overall area and high power consumption.

[0011] Furthermore, in the case of logic memory technology based on non-volatile memory elements, complex manufacturing processes are required because non-silicon materials are used, and practical application is difficult due to low element uniformity and stability.

[0012] Furthermore, existing logic memory technologies cannot implement all basic CMOS logic operations in a single cell, and require individual circuits and wiring for each logic operation, resulting in a low level of integration.

[0013] Therefore, there is a need to develop a general-purpose logic memory cell technology that can be manufactured using silicon-based CMOS processes, perform all basic logic operations within a single cell, and store the resulting values.

[0014] Conventional logic memory technology has been studied using various types of memory, including volatile memory elements such as DRAM (dynamic random access memory) and SRAM (static RAM), and non-volatile memory elements such as PRAM (phase-change RAM), ReRAM (resistive RAM), and MRAM (magnetoresistive RAM).

[0015] However, these methods have difficulty being applied to existing CMOS logic operations because they cannot define n-channel and p-channel configurations.

[0016] In particular, non-volatile memory element-based logic memory technology requires novel process steps that are almost entirely different from silicon-based CMOS processes, and its low element uniformity and reliability make it difficult to implement in practice.

[0017] Furthermore, in order to overcome the information density limitations of existing CMOS binary logic systems, multi-valued logic systems with more than two logic states are being studied using various elements. However, because they commonly utilize leakage current flowing through the elements, they suffer from the problem of consuming high power.

[0018] In particular, devices using tunneling principle-based negative differential resistors (NDRs), negative differential transconductances (NDTs), and quantum dots (QDs) present difficulties in applying them to multi-valued logic systems due to limitations in reliability and operating temperature.

[0019] This means that conventional binary logic arithmetic methods have limitations in relatively improving integration and information density. [Overview of the Initiative] [Problems that the invention aims to solve]

[0020] The present invention aims to realize a general-purpose logic memory cell that provides ternary logic operation and memory functions using a triple-gate silicon element driven by a positive feedback loop.

[0021] The present invention aims to realize a general-purpose logic memory cell that uses a triple-gate silicon element to perform all basic ternary logic operations in a single structure and store the results of those operations.

[0022] The present invention aims to realize a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element that applies an existing CMOS process.

[0023] The present invention aims to improve the limitations of processing speed and integration caused by data bottlenecks by integrating logical operations and storage functions.

[0024] The present invention aims to improve standby power efficiency with excellent memory characteristics that maintain logical values ​​without structural changes or external biases, using channel mode reconfiguration characteristics. [Means for solving the problem]

[0025] A general-purpose logic memory cell according to one embodiment of the present invention includes a first network element and a second network element using a plurality of triple-gate silicon elements, each of the plurality of triple-gate silicon elements including a drain region, a channel region and a source region, to which a supply voltage is applied, and to which a gate region is formed on the channel region, wherein a first and second programming gate electrode and a control gate electrode are formed, and a program voltage V is applied via the first and second programming gate electrodes. PGDepending on the level, in the channel region, the channel region under the first and second programming gate electrodes operates in either the first channel mode or the second channel mode, and the control voltage V applied through the control gate electrode CG Based on the level, it is determined to be either an on state or an off state, and the first network element and the second network element output the voltage V at either a positive level, a zero level, or a negative level depending on either one of the states in either one of the performed channel modes OUT By determining the level, a ternary logic operation function and a memory function can be performed.

[0026] The first network element and the second network element include a first series connection portion in which the drain regions and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second series connection portion in which the drain regions and source regions of the remaining two triple-gate silicon elements are connected in series. The first parallel connection portion to which the common drain region between them is connected, and the second parallel connection portion to which the common source region is connected. The drain voltage V among the common voltages is applied through the first parallel connection portion of the first network element DD is applied, the source voltage V among the common voltages is applied through the second parallel connection portion of the second network element SS is applied, and the output voltage V can be measured as either one at the portion where the second parallel connection portion of the first network element and the first parallel connection portion of the second network element are connected. OUT can be measured.

[0027] When the first network element operates in the second channel mode and the second network element operates in the first channel mode, when the level of the control voltage V CG is a negative level, the level of the output voltage V OUT is determined to be a positive level, and the control voltage V CGWhen the level is positive, the output voltage V OUT The level is determined to be negative, and the control voltage V CG When the level is zero, the output voltage V OUT The ternary logic operation function can be performed to determine the level as zero.

[0028] When the first network element operates in the first channel mode and the second network element operates in the second channel mode, the control voltage V CG When the level is negative, the output voltage V OUT The level is determined to be negative, and the control voltage V CG When the level is positive, the output voltage V OUT The level is determined to be a positive level, and the control voltage V CG When the level is zero, the output voltage V OUT The ternary logic operation function can be performed to determine the level as zero.

[0029] The first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the control voltage V CG Of these, the first control voltage V IN1 The control voltage V is applied to the left side of the first network element and above the second network element. CG Of these, the second control voltage V IN2 The first control voltage V is applied to the right side of the first network element and below the second network element. IN1 and the second control voltage V IN2 If any one of the levels is negative, the output voltage V OUT The level is determined to be a positive level, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are at a positive level, the output voltage V OUT The level is determined to be negative, and the first control voltage VIN1 and the second control voltage V IN2 The output voltage V is when both levels are at zero, or when one level is at zero and the other level is at a positive level. OUT The ternary logic operation function can be performed to determine the level as zero.

[0030] The first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the control voltage V CG Of these, the first control voltage V IN1 The control voltage V is applied to the upper side of the first network element and the left side of the second network element. CG Of these, the second control voltage V IN2 The first control voltage V is applied to the lower side of the first network element and the right side of the second network element. IN1 and the second control voltage V IN2 If any one of the levels is a positive level, the output voltage V OUT The level is determined to be negative, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are at a negative level, the output voltage V OUT The level is determined to be positive, and the first control voltage V IN1 and the second control voltage V IN2 The output voltage V is considered to be at zero level when both levels are at zero level, or when one level is at zero level and the other level is at a negative level. OUT The ternary logic operation function can be performed to determine the level as zero.

[0031] The first network element operates in the first channel mode, the second network element operates in the second channel mode, and the control voltage V CG Of these, the first control voltage V IN1The control voltage V is applied to the upper side of the first network element and the left side of the second network element. CG Of these, the second control voltage V IN2 The first control voltage V is applied to the lower side of the first network element and the right side of the second network element. IN1 and the second control voltage V IN2 If any one of the levels is negative, the output voltage V OUT The level is determined to be negative, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are at a positive level, the output voltage V OUT The level is determined to be a positive level, and the first control voltage V IN1 and the second control voltage V IN2 The output voltage V is when both levels are at zero, or when one level is at zero and the other level is at a positive level. OUT The ternary logic operation function can be performed to determine the level as zero.

[0032] The first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the control voltage V CG Of these, the first control voltage V IN1 The control voltage V is applied to the left side of the first network element and above the second network element. CG Of these, the second control voltage V IN2 The first control voltage V is applied to the right side of the first network element and below the second network element. IN1 and the second control voltage V IN2 If any one of the levels is a positive level, the output voltage V OUT The level is determined to be a positive level, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are at a negative level, the output voltage VOUT The level is determined to be negative, and the first control voltage V IN1 and the second control voltage V IN2 The output voltage V is considered to be at zero when both levels are at zero, or when one level is at zero and the other level is at a negative level. OUT The ternary logic operation function can be performed to determine the level as zero.

[0033] The left side of the first network element operates in the first channel mode, the right side of the first network element operates in the second channel mode, the upper left side of the second network element operates in the second channel mode, the upper right side of the second network element operates in the first channel mode, the lower left side of the second network element operates in the first channel mode, and the lower right side of the second network element operates in the second channel mode, with the control voltage V CG Of these, the first control voltage V IN1 The control voltage V is applied to the upper side of the first network element and the second network element. CG Of these, the second control voltage V IN2 The first control voltage V is applied to the lower side of the first network element and the second network element. IN1 and the second control voltage V IN2 When the levels of are the same negative or positive level, the output voltage V OUT The level is determined to be positive, and the first control voltage V IN1 and the second control voltage V IN2 When the levels of are inversely negative or positive, the output voltage V OUT The level is determined to be negative, and the first control voltage V IN1 and the second control voltage V IN2 If any one of the levels is at the zero level, the output voltage V OUT The ternary logic operation function can be performed to determine the level as zero.

[0034] The upper left side of the first network element operates in the second channel mode, the upper right side of the first network element operates in the first channel mode, the lower left side of the first network element operates in the first channel mode, the lower right side of the first network element operates in the second channel mode, the left side of the second network element operates in the first channel mode, the right side of the second network element operates in the second channel mode, and the control voltage V CG Among them, the first control voltage V IN1 is applied to the upper sides of the first network element and the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied to the lower sides of the first network element and the second network element. When both the levels of the first control voltage V IN1 and the second control voltage V IN2 are positive levels, the level of the output voltage V OUT is determined to be a negative level. When both the levels of the first control voltage V IN1 and the second control voltage V IN2 and the second control voltage V < IN2 is applied to the lower sides of the first network element and the second network element. When both the levels of the first control voltage V<00088> and the second control voltage V IN2 are positive levels, the level of the output voltage V OUT is determined to be a negative level. When both the levels of the first control voltage V IN1 and the second control voltage V IN2 are negative levels, the level of the output voltage V OUT is determined to be a negative level. When the levels of the first control voltage V IN1 and the second control voltage V IN2 are opposite, i.e., one is a negative level and the other is a positive level, the level of the output voltage V OUT is output as a positive level. When either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is a zero level, the level of the output voltage V OUT is determined to be a zero level, and the ternary logic operation function can be performed.

[0035] The drain region is p-doped, the source region is n-doped, the channel region is intrinsic, and in the channel region, the channel region below the first and second programming gate electrodes is the program voltage V PG When the level of is positive, it operates as an n-channel corresponding to the first channel mode, and the program voltage V PG When the level is negative, it can operate as a p-channel corresponding to the second channel mode.

[0036] The drain voltage V applied to the drain region DD , source voltage V applied to the source region SS , the aforementioned program voltage V PG and the control voltage V CG When applied at zero level, the output voltage V OUT The memory function can be performed while maintaining the level.

[0037] Each of the plurality of triple-gate silicon elements operates in the first channel mode when the channel region below the first and second programming gate electrodes is in the first channel mode, and the applied control gate voltage V CG The ON state is determined when the level is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and the applied control gate voltage V CG The state can be determined to be off if the level is lower than the latch-up voltage.

[0038] Each of the plurality of triple-gate silicon elements operates in the first channel mode when the channel region below the first and second programming gate electrodes is in the first channel mode, and the applied control voltage V CGWhen the level increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the second programming gate electrode adjacent to the source region decreases, and the lowered potential barrier generates a first positive feedback loop into which electrons are injected from the source region, potentially leading to the ON state in which current flows.

[0039] Each of the plurality of triple-gate silicon elements operates in the second channel mode when the channel region below the first and second programming gate electrodes is in the second channel mode, and the applied control gate voltage V CG The state is determined to be off when the level is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and the applied control gate voltage V CG The ON state can be determined when the level is lower than the latch-up voltage.

[0040] Each of the plurality of triple-gate silicon elements operates in the second channel mode when the channel region below the first and second programming gate electrodes is operated in the second channel mode, and the applied control voltage V CG When the level decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the first programming gate electrode adjacent to the drain region decreases, and the lowered potential barrier generates a second positive feedback loop into which holes are injected from the drain region, potentially resulting in the ON state in which current flows. [Effects of the Invention]

[0041] This invention can realize a general-purpose logic memory cell that provides ternary logic operation and memory functions using a triple-gate silicon element driven by a positive feedback loop.

[0042] This invention enables the realization of a general-purpose logic memory cell that uses a triple-gate silicon element to perform all basic ternary logic operations in a single structure and store the results of those operations.

[0043] This invention enables the realization of a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element to which an existing CMOS process is applied.

[0044] This invention can improve the limitations of processing speed and integration caused by data bottlenecks by integrating logical operations and storage functions.

[0045] This invention can improve standby power efficiency with excellent memory characteristics that maintain logical values ​​without structural changes or external biases, by utilizing channel mode reconfiguration characteristics. [Brief explanation of the drawing]

[0046] [Figure 1A] This figure illustrates a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 1B] This figure illustrates a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 2A] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 2B] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 2C] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 3]This figure illustrates a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4A] This figure illustrates the operation of the TNOT gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4B] This figure illustrates the operation of the TYES gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 5A] This figure illustrates the operation of a TNAND gate in a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 5B] This figure illustrates the operation of a TNOR gate in a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 6A] This figure illustrates the operation of the TAND gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 6B] This figure illustrates the operation of the TOR gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 7A] This figure illustrates the operation of the TXNOR gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 7B] This figure illustrates the operation of the TXOR gate of a general-purpose logic memory cell according to one embodiment of the present invention. [Modes for carrying out the invention]

[0047] Various embodiments of this document are described below with reference to the attached drawings.

[0048] The examples and the terminology used herein are not intended to limit the technology described herein to any particular embodiment, but should be understood to include various modifications, equivalents, and / or substitutions of such embodiments.

[0049] In describing various embodiments below, if it is determined that a specific description of a relevant known function or configuration may obscure the gist of the invention, such detailed description will be omitted.

[0050] Furthermore, the terms described later are defined considering the functions in various embodiments, and these may change depending on the intent or conventions of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0051] In relation to the description of the drawings, similar reference numerals may be used for similar components.

[0052] A singular expression can contain multiple expressions unless the context clearly indicates a different meaning.

[0053] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0054] Expressions such as "first," "second," "first," or "second" can modify the constituent elements regardless of their order or importance, and are used only to distinguish one constituent element from others, without limiting it to that constituent element.

[0055] When it is said that one component (e.g., component 1) is "connected" or "linked" to another component (e.g., component 2), that component may be directly connected to the other component or connected via another component (e.g., component 3).

[0056] In this specification, “configured to” may be used interchangeably with, depending on the context, “suitable for,” “capable of,” “modified to,” “made to,” “capable of,” or “designed to,” either in hardware or software.

[0057] In some situations, the expression "a device configured to do ~" may mean that the device "can do ~" together with other devices or components.

[0058] For example, the phrase "a processor configured (or set up) to perform A, B, and C" can mean a dedicated processor for performing those operations (e.g., an embedded processor), or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0059] Furthermore, the term "or" here refers to inclusive OR rather than exclusive OR.

[0060] In other words, unless otherwise stated or made clear from the context, the expression "x uses a or b" means one of the natural inclusive permutations.

[0061] The terms "...part" and "...device" used below refer to a unit that processes at least one function or operation, which can be embodied in hardware, software, or a combination of hardware and software.

[0062] Figures 1A and 1B illustrate a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention.

[0063] Figure 1A illustrates the structure of a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention.

[0064] Referring to Figure 1A, a triple-gate silicon element 100 according to one embodiment of the present invention includes a drain region 101, a channel region 102, a source region 103, and a gate region, the gate region including first and second programming gate electrodes 106 and a control gate electrode 105 formed on a gate insulating film 104.

[0065] For example, a drain electrode may be connected to the drain region 101 to apply a drain voltage, and a source electrode may be connected to the source region 103 to apply a source voltage.

[0066] According to one embodiment of the present invention, the triple-gate silicon element 100 includes a drain region 101, a channel region 102, and a source region 103, which are pin nanostructures.

[0067] For example, the drain region 101 may be in a p-doped state, the source region 103 in an n-doped state, and the channel region 102 in an intrinsic state.

[0068] In channel region 102, the channel region below the first and second programming gate electrodes 106 is the program voltage V PG When the level is positive, it operates as an n-channel corresponding to the first channel mode, and the program voltage V PG When the level is negative, it can operate as a p-channel corresponding to the second channel mode.

[0069] Multiple triple-gate silicon elements 100 can be combined to form a general-purpose logic memory cell.

[0070] In other words, the triple-gate silicon element 100 is composed of multiple elements to form a general-purpose logic memory cell, but some of the elements may be composed of a first network element and some may be composed of a second network element.

[0071] The triple-gate silicon element 100 is programmed by a program voltage V applied via the first and second programming gate electrodes 106. PG Depending on the level, the channel region below the first and second programming gate electrodes 106 in the channel region can operate in either the first channel mode or the second channel mode.

[0072] Furthermore, the triple-gate silicon element 100 is subjected to a control voltage V applied via the control gate electrode. CG Based on the level, it can be determined to be in either an on state or an off state.

[0073] Therefore, the general-purpose logic memory cell has an output voltage V which changes depending on one state in any of the channel modes already performed. OUT Logical operations and memory functions can be performed based on the level.

[0074] In other words, the first network element and the second network element have an output voltage V at one of the following levels: positive, zero, or negative, depending on one of the states in any of the channel modes already performed. OUT By determining the level, ternary logical operation and memory functions can be performed.

[0075] For example, since the first and second programming gate electrodes 106 are electrically connected, the same programming voltage V is applied at the same time. PG It may be applied.

[0076] Figure 1B illustrates the operating state of a general-purpose logic memory cell according to one embodiment of the present invention and the associated circuit symbols.

[0077] Referring to Figure 1B, circuit symbol 111 according to one embodiment of the present invention illustrates a circuit symbol when the channel region of a triple-gate silicon element operates in first channel mode and operates as an n-channel element.

[0078] As an example, circuit symbol 110 illustrates the circuit symbol when the channel region of a triple-gate silicon element operates in second-channel mode and operates as a p-channel.

[0079] Circuit symbols 110 and 111 show a nanostructure including a drain region, a channel region, a source region, and a gate region, in which a first and second programming gate electrode and a control gate electrode are formed in the gate region and connected to the programming gate terminal PG and the control gate terminal CG, a drain electrode is formed in the drain region and connected to the drain terminal D, and a source electrode is formed in the source region and connected to the source terminal S.

[0080] Circuit symbol 111 indicates that the triple-gate silicon element is in the first channel mode state through the channel mode state region.

[0081] In other words, circuit symbol 111 can indicate that the triple-gate silicon element is operating as an n-channel by showing the channel mode state region in solid form.

[0082] Circuit symbol 110 indicates that the triple-gate silicon element is in the second channel mode state through the channel mode state region.

[0083] Circuit symbol 110 indicates that the triple-gate silicon element is operating as a p-channel by showing the channel mode state region in an empty form.

[0084] For example, a triple-gate silicon element can be called a triple-gate feedback field-effect element.

[0085] Figures 2A to 2C illustrate the operating principle of a triple-gate silicon element according to one embodiment of the present invention.

[0086] Figure 2A illustrates the operating principle when a triple-gate silicon element according to one embodiment of the present invention operates as a p-channel.

[0087] Referring to Figure 2A, in one embodiment of the present invention, when a positive voltage is applied through the drain terminal and a negative voltage corresponding to a negative level of the program voltage is applied from the programming gate terminal, the channel region below the programming gate electrode PG in the channel region is programmed to be a p-channel and operates as a p-channel.

[0088] When the triple-gate silicon element 200 according to one embodiment of the present invention operates as a p-channel, the operating state is determined to be off when the level of the control voltage applied via the control gate terminal is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and on when the level of the applied control voltage is lower than the latch-up voltage.

[0089] For example, a triple-gate silicon element is determined to be on or off based on the level of a control voltage applied through the control gate terminal.

[0090] The on and off operating states of the triple-gate silicon element can be further described through energy band 201, which corresponds to the off state, and energy band 202, which corresponds to the on state.

[0091] When a triple-gate silicon element according to one embodiment of the present invention operates as a p-channel, the energy band 202 when it is on and the energy band 201 when it is off can be determined based on the level of the control voltage.

[0092] According to energy bands 201 and 202, when the channel region below the first and second programming gate electrodes operates in the second channel mode, which corresponds to the p-channel mode, the control voltage V CG When the level decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the first programming gate electrode adjacent to the drain region decreases. This lowered potential barrier creates a second positive feedback loop in which holes are injected from the drain region, resulting in an ON state where current flows.

[0093] In other words, the triple-gate silicon element generates a second positive feedback loop, allowing it to switch from energy band 201 to energy band 202.

[0094] We can confirm that the repeated injection and accumulation of charge creates a positive feedback loop, switching to an ON state where current flows.

[0095] For example, a second positive feedback loop could be a positive feedback loop in which holes become the majority carriers in the channel region.

[0096] Figure 2B illustrates the operating principle when a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel element.

[0097] Referring to Figure 2B, in one embodiment of the present invention, when a negative voltage is applied through the source terminal and a positive voltage corresponding to the level of the program voltage is applied from the programming gate terminal, the channel region below the programming gate electrode PG in the channel region is programmed to be an n-channel and operates as an n-channel.

[0098] For example, a triple-gate silicon element is determined to be on or off based on the level of a control voltage applied through the control gate terminal.

[0099] When the triple-gate silicon element 210 according to one embodiment of the present invention operates as an n-channel, the operating state is determined to be ON when the level of the control voltage applied via the control gate terminal is higher than the latch-up voltage, which is the voltage when the current increases rapidly. CG The state can be determined to be off if the level is lower than the latch-up voltage.

[0100] When a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel, the energy band 211 when it is in the off state and the energy band 212 when it is in the on state are illustrated based on the level of the control voltage.

[0101] Referring to energy bands 211 and 212, when the channel region below the first and second programming gate electrodes operates in the first channel mode corresponding to the n-channel mode, the control voltage V CG When the level increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the second programming gate electrode adjacent to the source region decreases. This lowered potential barrier creates a first positive feedback loop in which electrons are injected from the source region, resulting in an ON state where current flows.

[0102] In other words, the triple-gate silicon element generates a first positive feedback loop, causing a switch from energy band 211 to energy band 212.

[0103] We can confirm that the repeated injection and accumulation of charge creates a positive feedback loop, switching to an ON state where current flows.

[0104] For example, the first positive feedback loop could be a positive feedback loop in which electrons become majority carriers in the channel region.

[0105] Figure 2C illustrates the operation of the first and second positive feedback loops and related functions when a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel and a p-channel.

[0106] Referring to Figure 2C, Graph 220 shows the operating characteristics of the n-channel mode of the triple-gate silicon device, and Graph 221 shows the operating characteristics of the p-channel mode of the triple-gate silicon device.

[0107] Graph 220 shows that a triple-gate silicon device operating in n-channel mode has an on-state and an off-state depending on the voltage applied to the control gate electrode. When the control gate voltage is lower than the latch-up voltage, which is the voltage at which the current rapidly increases, the flow of electrons and holes is blocked by the potential barrier, resulting in an off-state. It also shows that as the control gate voltage increases and becomes greater than the latch-up voltage, electrons from the source region are injected into the channel across the potential barrier and accumulate in the drain region and adjacent potential wells, reducing the height of the potential barrier.

[0108] As a result, holes in the drain region are injected into the channel and accumulate in the source region and adjacent potential wells, lowering the height of the potential barrier.

[0109] The repeated injection and accumulation of charge creates a positive feedback loop, resulting in an ON state where current flows.

[0110] Graph 221 shows that in the case of a triple-gate silicon device operating in p-channel mode, when the control gate voltage is greater than the latch-up voltage, the flow of electrons and holes is blocked by the potential barrier and the device enters an off state. When the control gate voltage decreases and becomes less than the latch-up voltage, holes in the drain region are injected into the channel over the potential barrier and accumulate in the source region and adjacent potential wells, resulting in a decrease in the height of the potential barrier.

[0111] According to one embodiment of the present invention, a triple-gate silicon element may be an element in which a first positive feedback loop or a second positive feedback loop is formed depending on the level of a control voltage applied to the gate region, and together with this, the on or off state is variably controlled in the first channel mode and the second channel mode. Here, the first channel mode is an n-channel mode, and the second channel mode is a p-channel mode.

[0112] Furthermore, triple-gate silicon elements are turned on while charge carriers accumulate in the potential well of the channel region, forming a positive feedback loop. This can be utilized as a memory function for storing data in the channel region.

[0113] Therefore, the present invention can realize a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element to which an existing CMOS process is applied.

[0114] Figure 3 is a diagram illustrating a general-purpose logic memory cell according to one embodiment of the present invention.

[0115] Figure 3 illustrates a circuit diagram of a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements according to one embodiment of the present invention.

[0116] Referring to Figure 3, a general-purpose logic memory cell 300 according to one embodiment of the present invention is composed of a first network element 310 and a second network element 311, and the first network element 310 and the second network element 311 consist of a plurality of triple-gate silicon elements 301.

[0117] More specifically, the first network element 310 and the second network element 311 are composed of a first series connection section in which the drain regions and source regions of two of the four triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain regions and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected.

[0118] The first network element 310 can be called a pull-up network element, and the second network element 311 can be called a pull-down network element.

[0119] According to one embodiment of the present invention, the general-purpose logic memory cell 300 can perform ternary logic operations and memory functions.

[0120] As an example, the general-purpose logic memory cell 300 performs ternary logic operations with positive, zero, and negative level outputs based on positive, zero, and negative level inputs, and controls the supply voltage, the voltage applied via the program gate electrode, and the input voltage applied via the control gate electrode to "0" to maintain the previously set voltage state.

[0121] According to one embodiment of the present invention, each of the first network element 310 and the second network element 311 is composed of four triple-gate silicon elements, which can be divided into two triple-gate silicon elements as upper, lower, left, and right sides, or into one triple-gate silicon element as upper left, upper right, lower left, and lower right sides.

[0122] The triple-gate silicon elements arranged at each position can be selectively driven in either the first channel mode or the second channel mode.

[0123] The configuration described above can be modified by the arrangement of network elements and may be referred to differently depending on the modified connection configuration.

[0124] The first network element 310, via the first parallel connection section of the first network element 310, receives the drain voltage V of the common voltage. DD It is applied.

[0125] The second network element 311, via its second parallel connection section, transmits the source voltage V of the common voltage. SS It is applied.

[0126] In one embodiment of the present invention, the general-purpose logic memory cell 300 has an output voltage V at the point where the second parallel connection portion of the first network element 310 and the first parallel connection portion of the second network element 311 are connected. OUT This can be measured.

[0127] The general-purpose logic memory cell 300 is composed of a first network element 310 and a second network element 311, and the drain voltage V depends on the operating state of the triple-gate silicon element 301. DD and source voltage V SS Output voltage V OUT It implements logical operations based on the content measured by [the system / method].

[0128] A general-purpose logic memory cell 300 according to one embodiment of the present invention uses a plurality of triple-gate silicon elements.

[0129] Each of the multiple triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and to which a gate region is formed on the channel region, with first and second programming gate electrodes and a control gate electrode.

[0130] Furthermore, each of the multiple triple-gate silicon elements has a program voltage V applied to it via the first and second programming gate electrodes. PG Depending on the level, the channel region below the first and second programming gate electrodes operates in either the first channel mode or the second channel mode, and the control voltage V applied via the control gate electrode operates in either channel mode or the first channel mode. CG Based on the level, it can be determined to be in either an on state or an off state.

[0131] The first network element 310 and the second network element 311 set the output voltage V to one of the following levels: positive, zero, or negative, depending on one of the states already determined in one of the channel modes that has already been performed. OUT By determining the level, ternary logical operation and memory functions can be performed.

[0132] The ternary logic operations are the logic operations associated with the TNOT, TYES, TNAND, TNOR, TAND, TOR, TXNOR, and TXOR gates.

[0133] Therefore, the present invention can embody a general-purpose logic memory cell that provides ternary logic operation and memory functions using a triple-gate silicon element driven by a positive feedback loop.

[0134] Furthermore, the present invention can realize a general-purpose logic memory cell that performs all basic ternary logic operations in a single structure using a triple-gate silicon element and stores the results of those operations.

[0135] Figure 4A is a diagram illustrating the operation of a TNOT gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0136] Figure 4A illustrates a circuit diagram and timing diagram related to the operation of a TNOT gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0137] Referring to Figure 4A, in one embodiment of the present invention, the general-purpose logic memory cell 400 operates in a second channel mode, and the triple-gate silicon elements constituting the first network element operate in the first channel mode, based on a programming voltage applied via the programming gate terminal PG.

[0138] At this time, the general-purpose logic memory cell 400 has a control voltage V which is the input voltage IN applied via the control gate terminal CG. CG When the level is negative, the output voltage V measured via the output terminal OUT The level is positive, and the control voltage V CG When the level is positive, the output voltage V OUT It can perform logical operations corresponding to the operation of a TNOT gate whose level is negative.

[0139] Furthermore, the general-purpose logic memory cell 400 has a control voltage V CG When the level is zero, the output voltage V OUT This allows for a logical operation function that corresponds to the operation of a TNOT gate, which determines the level to be zero.

[0140] Timing diagram 401 shows the input voltage V at a negative level corresponding to "-1".IN When applied, the output voltage V corresponds to a positive level of "1". OUT This illustrates how a logical operation is performed and the result is output.

[0141] Furthermore, timing diagram 401 shows the positive level input voltage V corresponding to "1". IN When applied, the output voltage V corresponds to a negative level of "-1". OUT This illustrates how a logical operation is performed and the result is output.

[0142] Furthermore, timing diagram 401 shows the zero-level input voltage V corresponding to "0". IN When applied, the zero-level output voltage V corresponds to "0". OUT This illustrates how a logical operation is performed and the result is output.

[0143] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0144] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0145] Figure 4B is a diagram illustrating the operation of the TYES gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0146] Figure 4B illustrates a circuit diagram and timing diagram related to the operation of the TYES gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0147] Referring to Figure 4B, in one embodiment of the present invention, the general-purpose logic memory cell 410 operates in a first channel mode, and the triple-gate silicon elements constituting the first network element operate in a second channel mode, based on a programming voltage applied via the programming gate terminal PG.

[0148] At this time, the general-purpose logic memory cell 410 has a control voltage V which is the input voltage IN applied via the control gate terminal CG. CG When the level is positive, the output voltage V measured via the output terminal is OUT The level is positive, and the control voltage V CG When the level is negative, the output voltage V OUT It can perform logical operations corresponding to the operation of a TYES gate where the level is negative.

[0149] Furthermore, the general-purpose logic memory cell 410 has a control voltage V CG When the level is zero, the output voltage V OUT This allows for a logical operation function that corresponds to the operation of a TYES gate, which determines the level to be zero.

[0150] Timing diagram 411 shows the input voltage V at a negative level corresponding to "-1". IN When applied, the output voltage V corresponds to a negative level of "-1". OUT This illustrates how a logical operation is performed and the result is output.

[0151] Furthermore, timing diagram 411 shows the positive level input voltage V corresponding to "1". IN When applied, the output voltage V corresponds to a positive level of "1". OUT This illustrates how a logical operation is performed and the result is output.

[0152] Furthermore, timing diagram 411 shows the zero-level input voltage V corresponding to "0". IN When applied, the zero-level output voltage V corresponds to "0".OUT This illustrates how a logical operation is performed and the result is output.

[0153] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0154] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0155] Figure 5A is a diagram illustrating the operation of a TNAND gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0156] Figure 5A illustrates a circuit diagram and timing diagram related to the operation of a TNAND gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0157] Referring to Figure 5A, in one embodiment of the present invention, the general-purpose logic memory cell 500 operates in a second channel mode, and the triple-gate silicon elements constituting the first network element operate in the first channel mode, based on a programming voltage applied via the programming gate terminal PG.

[0158] Furthermore, the general-purpose logic memory cell 500 has a control voltage V CG Of these, the first control voltage IN1 is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Of these, the second control voltage IN2 is applied to the right side of the first network element and below the second network element.

[0159] As a result, the general-purpose logic memory cell 500 will output voltage V when either the level of the first control voltage IN1 or the second control voltage IN2 is at a negative level. OUT The level is determined to be the positive level.

[0160] Furthermore, the general-purpose logic memory cell 500 outputs an output voltage V when both the levels of the first control voltage IN1 and the second control voltage IN2 are at a positive level. OUT The logic operation function of a TNAND gate can be performed to determine the level as a negative level.

[0161] Furthermore, the general-purpose logic memory cell 500 outputs an output voltage V when both the levels of the first control voltage IN1 and the second control voltage IN2 are at zero, or when one level is at zero and the other level is at a positive level. OUT By performing a TNAND gate logic operation that determines the level to zero, a ternary logic operation can be performed.

[0162] Timing diagram 501 shows two input voltages V IN1 ,V IN2 When an input corresponding to the combination of "-1", "0", and "1" is applied to it, the output voltage V OUT This demonstrates that ternary logical operations are performed by calculating values ​​corresponding to "-1", "0", and "1".

[0163] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0164] For example, supply voltage V SUP The drain voltage V DD and source voltage V SSIt consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0165] Figure 5B is a diagram illustrating the operation of a TNOR gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0166] Figure 5B illustrates a circuit diagram and timing diagram related to the operation of a TNOR gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0167] Referring to Figure 5B, in one embodiment of the present invention, the general-purpose logic memory cell 510 operates in a second channel mode, and the triple-gate silicon elements constituting the first network element operate in the first channel mode, based on a programming voltage applied via the programming gate terminal PG.

[0168] Furthermore, the general-purpose logic memory cell 510 has a control voltage V CG Of these, the first control voltage IN1 is applied to the upper side of the first network element and the left side of the second network element, and the control voltage V CG Of these, the second control voltage IN2 is applied to the lower side of the first network element and to the right side of the second network element.

[0169] As a result, the general-purpose logic memory cell 510 controls the first control voltage V IN1 and second control voltage V IN2 If any one of the levels is positive, the output voltage V OUT The level is determined to be a negative level.

[0170] Furthermore, the general-purpose logic memory cell 510 has a first control voltage V IN1 and second control voltage V IN2When both levels are negative levels, the output voltage V OUT is determined to be a positive level.

[0171] Also, the general-purpose logic memory cell 510 performs the TNOR operation of the ternary logic operation function that determines the level of the output voltage V IN1 to be a zero level when both levels of the first control voltage V IN2 and the second control voltage V OUT are zero levels, or when one of the levels is a zero level and the other level is a negative level.

[0172] The timing diagram 511 shows that the ternary logic operation function is performed by calculating values corresponding to "-1", "0", and "1" for the output voltage V IN1 , V IN2 when inputs corresponding to combinations of "-1", "0", and "1" are applied to the two input voltages V OUT .

[0173] Also, it shows that a memory function of maintaining (holding) the calculated logical value is performed even when the supply voltage V SUP , the program voltage V PG , and the input voltages V IN1 , V IN2 are removed.

[0174] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel and the program voltage V PG P corresponding to the p-channel.

[0175] FIG. 6A is a diagram for explaining the operation of the TAND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0176] FIG. 6A illustrates a circuit diagram and a timing diagram in relation to the operation of the TAND gate of a general-purpose logic memory cell according to an embodiment of the present invention.

[0177] Referring to FIG. 6A, in a general-purpose logic memory cell 600 according to an embodiment of the present invention, based on a programming voltage applied through a programming gate terminal PG, a triple-gate silicon element constituting a first network element operates in a first channel mode, and a triple-gate silicon element constituting a second network element operates in a second channel mode.

[0178] Also, in the general-purpose logic memory cell 600, a first control voltage IN1 among control voltages V CG is applied to the upper side of the first network element and the left side of the second network element, and a second control voltage IN2 among control voltages V CG is applied to the lower side of the first network element and the right side of the second network element.

[0179] Thus, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is a negative level, the general-purpose logic memory cell 600 performs a logical operation to determine the level of an output voltage V OUT as a negative level.

[0180] Also, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are positive levels, the general-purpose logic memory cell 600 determines the level of an output voltage V OUT as a positive level.

[0181] Also, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are zero levels, or when one of the levels is a zero level and the other level is a positive level, an output voltage V OUTPerforms a ternary logic operation that determines the level to be zero.

[0182] In other words, the general-purpose logic memory cell 600 performs the operation of a TAND gate.

[0183] Timing diagram 601 shows two input voltages V IN1 ,V IN2 When an input corresponding to the combination of "-1", "0", and "1" is applied to it, the output voltage V OUT This demonstrates that ternary logical operations are performed by calculating values ​​corresponding to "-1", "0", and "1".

[0184] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0185] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0186] Figure 6B is a diagram illustrating the operation of the TOR gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0187] Figure 6B illustrates a circuit diagram and timing diagram related to the operation of the TOR gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0188] Referring to Figure 6B, in one embodiment of the present invention, the general-purpose logic memory cell 610 operates in a first channel mode, and the triple-gate silicon elements constituting the first network element operate in a second channel mode, based on a programming voltage applied via the programming gate terminal PG.

[0189] Furthermore, the general-purpose logic memory cell 610 has a control voltage V CG Of these, the first control voltage IN1 is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Of these, the second control voltage IN2 is applied to the right side of the first network element and to the bottom side of the second network element.

[0190] As a result, the general-purpose logic memory cell 610 controls the first control voltage V IN1 and second control voltage V IN2 If any one of the levels is positive, the output voltage V OUT The level is determined to be the positive level.

[0191] Furthermore, the general-purpose logic memory cell 610 has a first control voltage V IN1 and second control voltage V IN2 When both levels are at a negative level, the output voltage V OUT The level is determined to be a negative level.

[0192] Furthermore, the general-purpose logic memory cell 610 has a first control voltage V IN1 and second control voltage V IN2 The output voltage V is generated when both levels are at zero, or when one level is at zero and the other is at a negative level. OUT Performs a ternary logic operation that determines the level to be zero.

[0193] Timing diagram 611 shows two input voltages V IN1 ,V IN2When an input corresponding to a combination of “-1”, “0”, and “1” is applied, the output voltage V OUT performs a TOR logic operation in relation to a ternary logic operation function by calculating values corresponding to “-1”, “0”, and “1”.

[0194] Also, it shows that it performs a memory function of maintaining (holding) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , the input voltage V IN1 , V IN2 are removed.

[0195] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0196] FIG. 7A is a diagram for explaining the operation of the TXNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0197] FIG. 7A illustrates a circuit diagram and a timing diagram in relation to the operation of the TXNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0198] Referring to FIG. 7A, in the general-purpose logic memory cell 700 according to an embodiment of the present invention, the left side of the triple-gate silicon element constituting the first network element operates in the first channel mode, the right side operates in the second channel mode, the upper left side of the triple-gate silicon element constituting the second network element operates in the second channel mode, the upper right side operates in the first channel mode, the lower left side operates in the first channel mode, and the lower right side operates in the second channel mode.

[0199] A general-purpose logic memory cell 700 according to one embodiment of the present invention has a control voltage V CG Of these, the first control voltage V IN1 However, a control voltage V is applied to the upper side of the first network element and the second network element. CG Of these, the second control voltage V IN2 However, this is applied to the underside of the first network element and the second network element.

[0200] According to one embodiment of the present invention, the general-purpose logic memory cell 700 has a first control voltage V IN1 and second control voltage V IN2 If both levels are negative, the output voltage V OUT Output the level as a positive level.

[0201] The general-purpose logic memory cell 700 has a first control voltage V IN1 and second control voltage V IN2 When both levels are at a positive level, the output voltage V OUT Output the level as a positive level.

[0202] Furthermore, the general-purpose logic memory cell 700 has a first control voltage V IN1 and second control voltage V IN2 If any one of the levels is at zero, the output voltage V OUT Output the level as a negative level.

[0203] Furthermore, the general-purpose logic memory cell 700 has a first control voltage V IN1 and second control voltage V IN2 If any one of the levels is at zero, the output voltage V OUT It is possible to perform a ternary logic operation that determines the level to be zero.

[0204] Timing diagram 701 shows two input voltages V IN1 ,V IN2When an input corresponding to the combination of "-1", "0", and "1" is applied to it, the output voltage V OUT This demonstrates that by performing calculations on values ​​corresponding to "-1", "0", and "1", a TXNOR logical operation is performed in conjunction with the ternary logical operation function.

[0205] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0206] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0207] Figure 7B is a diagram illustrating the operation of the TXOR gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0208] Figure 7B illustrates a circuit diagram and timing diagram related to the operation of a TXOR gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0209] Referring to Figure 7B, in one embodiment of the present invention, the general-purpose logic memory cell 710 has the following configurations: the upper left triple-gate silicon element constituting the first network element operates in second channel mode, the upper right triple-gate silicon element operates in first channel mode, the lower left triple-gate silicon element operates in first channel mode, and the lower right triple-gate silicon element constituting the second network element operates in first channel mode and the lower right triple-gate silicon element operates in second channel mode.

[0210] A general-purpose logic memory cell 710 according to one embodiment of the present invention has a control voltage V CG Of these, the first control voltage V IN1 However, a control voltage V is applied to the upper side of the first network element and the second network element. CG Of these, the second control voltage V IN2 However, this is applied to the underside of the first network element and the second network element.

[0211] Furthermore, the general-purpose logic memory cell 710 has a first control voltage V IN1 and second control voltage V IN2 When both levels are negative or positive, the output voltage V OUT The level is determined to be a negative level.

[0212] Furthermore, the general-purpose logic memory cell 710 has a first control voltage V IN1 and second control voltage V IN2 When the levels are inversely negative or positive, the output voltage V OUT Output the level as a positive level.

[0213] Furthermore, the general-purpose logic memory cell 710 has a first control voltage V IN1 and second control voltage V IN2 If any one of the levels is at zero, the output voltage V OUT It is possible to perform a ternary logic operation that determines the level to be zero.

[0214] Timing diagram 711 shows two input voltages V IN1 ,V IN2 When an input corresponding to the combination of "-1", "0", and "1" is applied to it, the output voltage V OUT This demonstrates that by performing calculations on values ​​corresponding to "-1", "0", and "1", a TXOR logical operation is performed in conjunction with the ternary logical operation function.

[0215] Also, the supply voltage V SUP , program voltage VPG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0216] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0217] Therefore, the present invention can improve the limitations of processing speed and integration caused by data bottlenecks through the integration of logical operations and storage functions.

[0218] Furthermore, the present invention can improve standby power efficiency with excellent memory characteristics that maintain logical values ​​without structural changes or external biases by using channel mode reconfiguration characteristics.

[0219] In the specific embodiments described above, the components included in the invention are expressed singly or plurally by the specific embodiments presented.

[0220] However, the singular or plural representations are chosen to suit the situation presented for the sake of explanation, and the embodiments described above are not limited to singular or plural components. A plural component may consist of a singular component, and a singular component may consist of a plural component.

[0221] On the other hand, while specific embodiments have been described in the description of the invention, it goes without saying that various modifications are possible as long as they do not deviate from the scope of the technical idea encompassed by the various embodiments.

[0222] Therefore, the scope of the present invention should not be limited to the embodiments described, but should be defined not only by the claims described below, but also by claims equivalent to those described below.

Claims

1. It includes a first network element and a second network element using multiple triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and to which a gate region is formed on the channel region, with first and second programming gate electrodes and a control gate electrode formed thereon, and a program voltage (V) is applied through the first and second programming gate electrodes. ＰＧ Depending on the level of the control voltage (V), the channel region below the first and second programming gate electrodes operates in one of the first channel mode and the second channel mode, and the control voltage (V) applied through the control gate electrode operates in one of the channel modes. ＣＧ Based on the level of ), it is determined to be in one of two states: on state or off state. The first network element and the second network element output an output voltage (V) to one of the following levels: positive, zero, or negative, depending on the state in any of the channel modes performed. ＯＵＴ By determining the level of ), ternary logical operation and memory functions are performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. When the first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the first control voltage (V IN1) of the control voltage (V CG) is applied to the left side of the first network element and the upper side of the second network element, and the second control voltage (V IN2) of the control voltage (V CG) is applied to the right side of the first network element and the lower side of the second network element, and if either the level of the first control voltage (V IN1) or the second control voltage (V IN2) is a negative level, the level of the output voltage (V OUT) is determined to be a positive level, and if both the levels of the first control voltage (V IN1) and the second control voltage (V IN2) are positive levels, the level of the output voltage (V OUT) is determined to be a negative level, and the first control voltage (V IN1) and the second control voltage (V IN2) A general-purpose logic memory cell characterized by performing the ternary logic operation function, which determines the level of the output voltage (V OUT) to be zero when both levels of ) are at zero, or when one level is at zero and the other level is at a positive level.

2. When the first network element operates in the second channel mode and the second network element operates in the first channel mode, when the level of the control voltage (V ＣＧ ), the level of the output voltage (V ＯＵＴ ) is determined to be a positive level, and when the level of the control voltage (V ＣＧ ) is a positive level, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level, and when the level of the control voltage (V ＣＧ ) is a zero level, the level of the output voltage (V ＯＵＴ ) is determined to be a zero level, performing the ternary logic operation function as described above. The general-purpose logic memory cell according to claim 1, characterized in that.

3. When the first network element operates in the first channel mode and the second network element operates in the second channel mode, the control voltage (V ＣＧ When the level of the output voltage (V) is at a negative level, ＯＵＴ The level of the control voltage (V) is determined to be negative, and the control voltage (V) is determined to be negative. ＣＧ When the level of the output voltage (V) is at a positive level ＯＵＴ The level of the control voltage (V) is determined to be positive, and the control voltage (V) is determined to be positive. ＣＧ When the level of the output voltage (V) is at zero level ＯＵＴ The general-purpose logic memory cell according to claim 1, characterized in that it performs the ternary logic operation function that determines the level of ) to zero level.

4. A first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, wherein, depending on the level of the program voltage (V PG) applied via the first and second programming gate electrodes, the channel region below the first and second programming gate electrodes operates in either a first channel mode or a second channel mode, and is determined to be in either an on state or an off state based on the level of the control voltage (V CG) applied via the control gate electrode. The first network element and the second network element perform ternary logic operations and memory functions by determining the level of the output voltage (V OUT) to one of positive, zero, or negative levels depending on the state in any one of the channel modes performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. The first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the control voltage (V ＣＧ ) of which the first control voltage (V ＩＮ１ The control voltage (V) is applied to the upper side of the first network element and the left side of the second network element. ＣＧ ) of which the second control voltage (V ＩＮ２ A first control voltage (V) is applied to the lower side of the first network element and the right side of the second network element. ＩＮ１ ) and the second control voltage (V ＩＮ２ If any one of the levels of ) is at a positive level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) is determined to be negative. ＩＮ１ ) and the second control voltage (V ＩＮ２ When both levels of ) are at a negative level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be a positive level, and the level of the first control voltage (V) is determined to be a positive level. ＩＮ１ ) and the second control voltage (V ＩＮ２ If both of the levels are at zero, or if one level is at zero and the other level is at a negative level, the output voltage (V ＯＵＴ A general-purpose logic memory cell characterized by performing the ternary logic operation function that determines the level of ) to zero level.

5. A first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, wherein, depending on the level of the program voltage (V PG) applied via the first and second programming gate electrodes, the channel region below the first and second programming gate electrodes operates in either a first channel mode or a second channel mode, and is determined to be in either an on state or an off state based on the level of the control voltage (V CG) applied via the control gate electrode. The first network element and the second network element perform ternary logic operations and memory functions by determining the level of the output voltage (V OUT) to one of positive, zero, or negative levels depending on the state in any one of the channel modes performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. The first network element operates in the first channel mode, the second network element operates in the second channel mode, and the control voltage (V ＣＧ ) of which the first control voltage (V ＩＮ１ The control voltage (V) is applied to the upper side of the first network element and the left side of the second network element. ＣＧ ) of which the second control voltage (V ＩＮ２ A first control voltage (V) is applied to the lower side of the first network element and the right side of the second network element. ＩＮ１ ) and the second control voltage (V ＩＮ２ If any one of the levels of ) is a negative level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) is determined to be negative. ＩＮ１ ) and the second control voltage (V ＩＮ２ When both levels of ) are at a positive level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be a positive level, and the level of the first control voltage (V) is determined to be a positive level. ＩＮ１ ) and the second control voltage (V ＩＮ２ If both levels of ) are at zero, or if one level is at zero and the other level is at a positive level, then the output voltage (V ＯＵＴ A general-purpose logic memory cell characterized by performing the ternary logic operation function that determines the level of ) to zero level.

6. A first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, wherein, depending on the level of the program voltage (V PG) applied via the first and second programming gate electrodes, the channel region below the first and second programming gate electrodes operates in either a first channel mode or a second channel mode, and is determined to be in either an on state or an off state based on the level of the control voltage (V CG) applied via the control gate electrode. The first network element and the second network element perform ternary logic operations and memory functions by determining the level of the output voltage (V OUT) to one of positive, zero, or negative levels depending on the state in any one of the channel modes performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. The first network element operates in the second channel mode, and the second network element operates in the first channel mode, and the control voltage (V ＣＧ ) of which the first control voltage (V ＩＮ１ The control voltage (V) is applied to the left side of the first network element and the upper side of the second network element. ＣＧ ) of which the second control voltage (V ＩＮ２ The first control voltage (V) is applied to the right side of the first network element and below the second network element, and the first control voltage (V) is applied to the right side of the first network element and below the second network element. ＩＮ１ ) and the second control voltage (V ＩＮ２ If any one of the levels of ) is at a positive level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be a positive level, and the level of the first control voltage (V) is determined to be a positive level. ＩＮ１ ) and the second control voltage (V ＩＮ２ When both levels of ) are at a negative level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) is determined to be negative. ＩＮ１ ) and the second control voltage (V ＩＮ２ If both levels of ) are at zero, or if one level is at zero and the other level is at a negative level, then the output voltage (V ＯＵＴ A general-purpose logic memory cell characterized by performing the ternary logic operation function that determines the level of ) to zero level.

7. A first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, wherein, depending on the level of the program voltage (V PG) applied via the first and second programming gate electrodes, the channel region below the first and second programming gate electrodes operates in either a first channel mode or a second channel mode, and is determined to be in either an on state or an off state based on the level of the control voltage (V CG) applied via the control gate electrode. The first network element and the second network element perform ternary logic operations and memory functions by determining the level of the output voltage (V OUT) to one of positive, zero, or negative levels depending on the state in any one of the channel modes performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. The left side of the first network element operates in the first channel mode, the right side of the first network element operates in the second channel mode, the upper left side of the second network element operates in the second channel mode, the upper right side of the second network element operates in the first channel mode, the lower left side of the second network element operates in the first channel mode, and the lower right side of the second network element operates in the second channel mode, and the control voltage (V ＣＧ ) of which the first control voltage (V ＩＮ１ ) is applied to the upper side of the first network element and the second network element, and the control voltage (V ＣＧ ) of which the second control voltage (V ＩＮ２ The first control voltage (V) is applied to the lower side of the first network element and the second network element. ＩＮ１ ) and the second control voltage (V ＩＮ２ When the levels of the output voltage (V) are the same negative or positive level, ＯＵＴ The level of the first control voltage (V) is determined to be a positive level, and the level of the first control voltage (V) is determined to be a positive level. ＩＮ１ ) and the second control voltage (V ＩＮ２ If the levels of the output voltage (V) are inversely negative or positive, ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) ＩＮ１ ) and the second control voltage (V ＩＮ２ If any one of the levels of ) is at the zero level, the output voltage (V ＯＵＴ A general-purpose logic memory cell characterized by performing the ternary logic operation function that determines the level of ) to zero level.

8. A first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, wherein, depending on the level of the program voltage (V PG) applied via the first and second programming gate electrodes, the channel region below the first and second programming gate electrodes operates in either a first channel mode or a second channel mode, and is determined to be in either an on state or an off state based on the level of the control voltage (V CG) applied via the control gate electrode. The first network element and the second network element perform ternary logic operations and memory functions by determining the level of the output voltage (V OUT) to one of positive, zero, or negative levels depending on the state in any one of the channel modes performed. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected. The drain voltage (VDD) of the common voltage is applied via the first parallel connection section of the first network element, and the source voltage (VSS) of the common voltage is applied via the second parallel connection section of the second network element. The output voltage (VOUT) is measured as one of the portions where the second parallel connection section of the first network element and the first parallel connection section of the second network element are connected. The upper left side of the first network element operates in the second channel mode, the upper right side of the first network element operates in the first channel mode, the lower left side of the first network element operates in the first channel mode, the lower right side of the first network element operates in the second channel mode, the left side of the second network element operates in the first channel mode, and the right side of the second network element operates in the second channel mode, and the control voltage (V ＣＧ ) of which the first control voltage (V ＩＮ１ ) is applied to the upper side of the first network element and the second network element, and the control voltage (V ＣＧ ) of which the second control voltage (V ＩＮ２ The first control voltage (V) is applied to the lower side of the first network element and the second network element. ＩＮ１ ) and the second control voltage (V ＩＮ２ When both levels of ) are at a positive level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) is determined to be negative. ＩＮ１ ) and the second control voltage (V ＩＮ２ When both levels of ) are at a negative level, the output voltage (V ＯＵＴ The level of the first control voltage (V) is determined to be negative, and the first control voltage (V) is determined to be negative. ＩＮ１ ) and the second control voltage (V ＩＮ２ If the levels of the output voltage (V) are inversely negative or positive, ＯＵＴ The level of the first control voltage (V) is determined to be a positive level, and the first control voltage (V) is determined to be a positive level. ＩＮ１ ) and the second control voltage (V ＩＮ２ If any one of the levels of ) is at zero, then the output voltage (V ＯＵＴ A general-purpose logic memory cell characterized by performing the ternary logic operation function that determines the level of ) to zero level.

9. The drain region is in a p-doped state. The aforementioned source region is in an n-doped state, The channel region is intrinsic. In the channel region, the channel region below the first and second programming gate electrodes is the program voltage (V ＰＧ When the level of the program voltage (V) is at a positive level, it operates as an n-channel corresponding to the first channel mode, and the program voltage (V) ＰＧ The general-purpose logic memory cell according to claim 1, characterized in that it operates as a p-channel corresponding to the second channel mode when the level of ) is at a negative level.

10. The drain voltage (V ＤＤ ), the source voltage (V ＳＳ ), the program voltage (V ＰＧ ), and the control voltage (V ＣＧ ) are applied at zero level, and the memory function is performed while maintaining the level of the output voltage (V ＯＵＴ ). The general-purpose logic memory cell according to claim 9, characterized in that.

11. Each of the plurality of triple-gate silicon elements operates in the first channel mode, and the channel region below the first and second programming gate electrodes in the channel region is such that the applied control gate voltage (V ＣＧ The ON state is determined when the level of the applied control gate voltage (V) is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and the applied control gate voltage (V) is higher than the latch-up voltage, which is the voltage when the current increases rapidly. ＣＧ The general-purpose logic memory cell according to claim 1, characterized in that it is determined to be in an off state when the level of ) is lower than the latch-up voltage.

12. Each of the plurality of triple-gate silicon elements operates in the first channel mode, and the channel region below the first and second programming gate electrodes in the channel region is controlled by the applied control voltage (V ＣＧ The general-purpose logic memory cell according to claim 11, characterized in that when the level of increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the second programming gate electrode adjacent to the source region decreases, and the reduced potential barrier generates a first positive feedback loop into which electrons are injected from the source region, resulting in the ON state in which current flows.

13. Each of the plurality of triple-gate silicon elements operates in the second channel mode when the channel region below the first and second programming gate electrodes is the channel region of the plurality of triple-gate silicon elements, and the applied control gate voltage (V ＣＧ The state is determined to be off when the level of the applied control gate voltage (V) is higher than the latch-up voltage, which is the voltage when the current increases rapidly. ＣＧ The general-purpose logic memory cell according to claim 1, characterized in that it is determined to be in an ON state when the level of ) is lower than the latch-up voltage.

14. Each of the plurality of triple-gate silicon elements operates in the second channel mode, and the channel region below the first and second programming gate electrodes in the channel region is controlled by the applied control voltage (V ＣＧ The general-purpose logic memory cell according to claim 13, characterized in that when the level of ) decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the first programming gate electrode adjacent to the drain region decreases, and the reduced potential barrier generates a second positive feedback loop into which holes are injected from the drain region, resulting in the ON state in which current flows.

Images