Laminated structure, method for manufacturing a laminated structure, and semiconductor device

Abstract

The present invention includes: an amorphous substrate having an insulating surface; an alignment pattern formed on the amorphous substrate; an insulating layer that is in contact with a side surface of the alignment pattern and that surrounds a peripheral edge section of the alignment pattern; and a gallium nitride-containing semiconductor pattern formed on the alignment pattern. The insulating layer has a first region that overlaps with the semiconductor pattern, and a second region that does not overlap with the semiconductor pattern. An upper surface of the second region is located below an upper surface of the first region. The insulating layer has, in the second region, a side surface that is continuous with the upper surface of the first region.

Description

Technical Field

[0001] One embodiment of the present invention relates to a stacked structure including a semiconductor layer containing gallium nitride formed on an amorphous substrate, a method for manufacturing the stacked structure, and a semiconductor device using the stacked structure.

Background Art

[0002] In recent years, the development of semiconductor devices using a semiconductor layer containing gallium nitride (hereinafter referred to as a "gallium nitride-based semiconductor layer") has been progressing. As semiconductor devices using a gallium nitride-based semiconductor layer, for example, transistor elements such as HEMT (High Electron Mobility Transistor) and light-emitting elements such as LED (Light Emitting Diode) are known. In particular, the demand for a light-emitting device using a light-emitting diode (LED) for each pixel is high, and the development of a technique for forming a highly crystalline gallium nitride-based semiconductor layer on a substrate other than a silicon substrate is urgent. For example, Patent Document 1 discloses a technique for forming a buffer layer on an insulating substrate such as a sapphire substrate or a quartz glass substrate, forming an insulating pattern on the buffer layer, and forming a gallium nitride-based semiconductor layer on the buffer layer and the insulating pattern.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As with the conventional technology described above, a gallium nitride-based semiconductor layer is generally formed by epitaxial growth at temperatures exceeding 1000°C using a sapphire substrate or quartz glass substrate with heat resistance of 1000°C or higher. However, when considering applications in light-emitting devices, the use of expensive sapphire substrates or quartz glass substrates hinders the creation of larger display screens. Furthermore, processing at temperatures exceeding 1000°C involves time-consuming heating at the start and cooling at the end of processing, resulting in reduced throughput.

[0005] One embodiment of the present invention aims to form a multilayer structure using a highly crystalline gallium nitride-based semiconductor layer on an inexpensive amorphous substrate. [Means for solving the problem]

[0006] A laminated structure in one embodiment of the present invention includes an amorphous substrate having an insulating surface, an orientation pattern on the amorphous substrate, an insulating layer in contact with the side surface of the orientation pattern and surrounding the peripheral edge of the orientation pattern, and a semiconductor pattern containing gallium nitride on the orientation pattern, wherein the insulating layer has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

[0007] A method for manufacturing a laminated structure according to one embodiment of the present invention includes an amorphous substrate having an insulating surface, an orientation pattern on the amorphous substrate, an insulating layer in contact with the outer peripheral surface of the orientation pattern but not in contact with the upper surface of the orientation pattern, and a semiconductor pattern containing gallium nitride on the orientation pattern, wherein the orientation pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

[0008] A method for manufacturing a laminated structure according to one embodiment of the present invention includes forming an orientation layer on an amorphous substrate having an insulating surface, forming an orientation pattern on the insulating surface by etching the orientation layer, depositing an insulating layer on the insulating surface and the orientation pattern, forming the insulating layer so as to be in contact with the side surface of the orientation pattern and surrounding the peripheral edge of the orientation pattern by etching the insulating layer, depositing a semiconductor layer containing gallium nitride on the insulating layer and the orientation pattern, and forming a semiconductor pattern on the upper surface of the orientation layer by etching the semiconductor layer containing gallium nitride, wherein the insulating layer surrounding the peripheral edge of the orientation pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

[0009] A method for manufacturing a laminated structure according to one embodiment of the present invention includes forming an orientation layer on an amorphous substrate having an insulating surface, forming an orientation pattern on the insulating surface by etching the orientation layer, depositing an insulating layer on the insulating surface and the orientation pattern, forming a semiconductor layer on the insulating layer that is in contact with the outer peripheral surface of the orientation pattern but not in contact with the upper surface of the orientation pattern by etching the insulating layer, depositing a semiconductor layer containing gallium nitride on the insulating layer and the orientation pattern, and forming a semiconductor pattern on the upper surface of the orientation layer by etching the semiconductor layer containing gallium nitride, wherein the orientation pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern. [Brief explanation of the drawing]

[0010] [Figure 1] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 2] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 3] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 4] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 5]This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 6] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 7] This is a plan view showing a laminated structure according to one embodiment of the present invention. [Figure 8] This is an end view showing a laminated structure according to one embodiment of the present invention. [Figure 9] This is an end view showing a laminated structure according to one embodiment of the present invention. [Figure 10] This is an end view showing a method for manufacturing a laminated structure according to one embodiment of the present invention. [Figure 11] This is an end view showing a semiconductor device using a stacked structure according to one embodiment of the present invention. [Figure 12] This is a plan view showing a light-emitting device using a semiconductor device with a stacked structure according to one embodiment of the present invention. [Figure 13] This is an end view showing a semiconductor device using a stacked structure according to one embodiment of the present invention. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its essence. The present invention is not to be interpreted as being limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0012] When describing embodiments of the present invention, the direction from the substrate toward the semiconductor layer is defined as "upward", and the opposite direction is defined as "downward". However, the expressions "upward" or "downward" merely explain the vertical relationship of each element. Further, the expressions "upward" or "downward" include not only the case where a third element is interposed between the first element and the second element, but also the case where no such element is interposed. Additionally, the expressions "upward" or "downward" include not only the case where the elements overlap in a plan view, but also the case where they do not overlap.

[0013] When describing embodiments of the present invention, for elements having the same function as those already described, the same reference numerals or the same reference numerals with symbols such as letters may be attached, and the description may be omitted. Further, when it is necessary to separately describe a part of an element, symbols such as letters may be attached to the reference numeral indicating the element for distinction. However, when there is no particular need to distinguish each part of the element, the description is made using only the reference numeral indicating the element.

[0014] When describing embodiments of the present invention, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C, unless otherwise specified. Further, these expressions do not exclude the case where α includes other elements.

[0015] <First Embodiment> FIGS. 1 to 8 are end views showing a method for manufacturing a stacked structure including a semiconductor pattern containing gallium nitride in the first embodiment. In particular, FIGS. 1 to 6 show an example of forming a semiconductor pattern containing gallium nitride on an amorphous substrate. FIG. 7 is a plan view when the stacked structure is viewed in a plan view, and FIG. 8 is a cross-sectional view when the stacked structure shown in FIG. 7 is cut along the line A1 - A2. Note that FIGS. 1 to 8 show an example of forming a single semiconductor pattern, but in actuality, a plurality of semiconductor patterns are formed on the substrate.

[0016] First, as shown in Figure 1, a base layer 102 is formed on the amorphous substrate 101. For example, a glass substrate can be used as the amorphous substrate 101. It is preferable that the glass substrate has a low alkali content, a low coefficient of thermal expansion, a high strain point, and high surface flatness. For example, it is preferable that the alkali metal (such as sodium) content is 0.1% or less and the coefficient of thermal expansion is 50 × 10⁻⁶. -7 The temperature is preferably lower than / ℃ and the strain point is 600℃ or higher. As will be described later, in this embodiment, since the gallium nitride semiconductor layer is formed by sputtering, a glass substrate with lower heat resistance compared to a sapphire substrate or a quartz substrate can be used. Such a glass substrate is less expensive than a sapphire substrate or a quartz substrate and is also suitable for increasing the area of ​​the mother glass. However, the amorphous substrate 101 in this embodiment is not limited to a glass substrate, but may also be a resin substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate.

[0017] When growing gallium nitride, for example, on an amorphous substrate 101 such as amorphous glass, the crystallinity of the gallium nitride is affected by the surface condition of the amorphous substrate 101. In particular, surface irregularities of the amorphous substrate 101 cause the generation of random crystal nuclei. As a result, gallium nitride crystal growth occurs in random directions, and adjacent crystals interfere with each other, inhibiting crystal growth. Therefore, a base layer 102 is provided on the amorphous substrate 101. By providing the base layer 102, the surface irregularities of the amorphous substrate 101 can be mitigated. The material of the base layer 102 also affects the crystallinity of the gallium nitride that is formed later.

[0018] The underlayer 102 serves as a protective layer to prevent contamination from the amorphous substrate 101. The underlayer 102 is composed of one or more insulating layers selected from, for example, a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer, and an aluminum oxide layer. In this embodiment, an aluminum nitride layer is used as the underlayer 102. The thickness of the underlayer 102 is 5 nm to 50 nm. For example, the underlayer 102 is formed by sputtering, CVD, vacuum deposition, electron beam deposition, or ALD (Atomic Layer Deposition). Planarization treatment may be performed to improve the flatness of the surface of the underlayer 102. Planarization treatment refers to, for example, reverse sputtering or etching.

[0019] An orientation layer 103 is formed on top of the underlayer 102. The orientation layer 103 has the function of improving the crystal orientation of the semiconductor layer 108 (see Figure 2), which contains gallium nitride and will be described later, when forming the semiconductor layer 108.

[0020] The orientation layer 103 may be conductive or insulating, but it is preferable that it has crystallinity oriented along a specific axis (e.g., the c-axis). The orientation layer 103 is preferably a crystal with rotational symmetry. For example, it is preferable that its crystal surface has 6-fold rotational symmetry. Furthermore, the orientation layer 103 is preferably a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto. Here, a hexagonal close-packed structure or a structure similar thereto includes a crystal structure in which the c-axis is not at a 90-degree angle to the a-axis and b-axis. An orientation layer 103 having a hexagonal close-packed structure or a structure similar thereto is preferably oriented in the (0001) direction, i.e., in the c-axis direction, with respect to the amorphous substrate 101. An orientation layer 103 having a face-centered cubic structure or a structure similar thereto is preferably oriented in the (111) direction with respect to the amorphous substrate 101.

[0021] As the orientation layer 103 described above, for example, a conductive orientation layer can be made of titanium (Ti), titanium nitride (TiNx), titanium oxide (TiOx), graphene, zinc oxide (ZnO), magnesium diboride (MgB2), aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), etc. In particular, it is preferable to use titanium, graphene, or zinc oxide as the conductive orientation layer 103. In this embodiment, a titanium layer is used as the orientation layer 103.

[0022] Furthermore, the orientation layer 103 described above can be, for example, an insulating orientation layer, such as aluminum nitride (AlN), aluminum oxide (Al2O3), lithium niobate (LiNbO), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO, PMnN-PZT, or bioapatite (BAp). In particular, it is preferable to use aluminum nitride or aluminum oxide as the insulating orientation layer. In this embodiment, it is preferable to use an aluminum nitride layer as the insulating orientation layer.

[0023] In this specification, the orientation layer 103 may be a conductive orientation layer or an insulating orientation layer. When there is no need to distinguish between a conductive orientation layer and an insulating orientation layer, it is referred to as the orientation layer 103.

[0024] The surface state of the alignment layer 103 affects the crystallinity of the semiconductor layer 108, which will be described later. Therefore, it is desirable that the surface of the alignment layer 103 be flat. For example, it is preferable that the arithmetic mean roughness (Ra) of the surface of the alignment layer 103 is less than 2.3 nm. By having a surface roughness of less than 2.3 nm of the alignment layer 103, it is possible to form a semiconductor layer 108 having c-axis orientation. In addition, in order to improve the flatness of the alignment layer 103, the surface of the alignment layer 103 may also be subjected to the planarization treatment described in the underlayer 102 before forming the semiconductor layer 108.

[0025] In this embodiment, an aluminum nitride layer is used as the base layer 102, and a titanium layer is used as the orientation layer 103. By using an aluminum nitride layer as the base layer 102, the flatness of the surface of the base layer 102 can be improved. Furthermore, the titanium layer is formed as the orientation layer 103 on top of the base layer 102 which has a flat surface. This improves the flatness of the surface of the orientation layer 103. Therefore, this is preferable because it increases the crystallinity of the semiconductor layer 108 that is formed later.

[0026] The thickness of the orientation layer 103 is, for example, 50 nm or more (preferably 50 nm to 100 nm). The orientation layer 103 may be formed by any method. For example, the orientation layer 103 may be formed by sputtering, CVD, vacuum deposition, electron beam deposition, or ALD.

[0027] Next, as shown in Figure 2, a resist mask 104 is formed on the orientation layer 103, and the orientation pattern 105 is formed by etching the orientation layer 103 using the resist mask. After that, the resist mask 104 is removed. The orientation pattern 105 has a gradient (hereinafter referred to as "taper") where the angle of the side surface with respect to the bottom surface is θ1. By using a dry etching method for etching the orientation layer 103, it is easier to increase the taper, and under certain conditions, the taper angle θ1 of the orientation pattern 105 can be made 60° or more. Alternatively, by using a wet etching method for etching the orientation layer 103, the taper angle θ1 of the orientation pattern 105 can be made 20° to 50° (preferably 30° to 40°). In this embodiment, the taper angle θ1 of the orientation pattern 105 is made 60° or more by etching the orientation layer 103 using a dry etching method.

[0028] Next, as shown in Figure 3, an insulating layer 106 is formed to cover the orientation pattern 105. An inorganic insulating material such as silicon oxide or silicon nitride is used as the insulating layer 106. In this embodiment, silicon nitride is formed as the insulating layer 106 by CVD. When an inorganic insulating material is used as the insulating layer 106, the shape of the insulating layer 106 will have irregularities that reflect the shape of the orientation pattern 105. If the material of the base layer 102 and the insulating layer 106 are the same, the sealing performance can be improved. If the material of the base layer 102 and the insulating layer 106 are different, a material that does not affect the orientation pattern 105 can be selected.

[0029] Next, as shown in Figure 4, a resist mask 107 is formed on the insulating layer 106, and the insulating layer 106 is etched using the resist mask 107 to form an opening 106a that exposes the upper surface 105a of the orientation pattern 105. As a result, the insulating layer 106 is in contact with the side surface 105b of the orientation pattern 105 and surrounds the peripheral edge of the orientation pattern 105. The peripheral edge of the orientation pattern 105 refers to the portion that includes the side surface 105b and a part of the upper surface 105a of the orientation pattern. The thickness of the insulating layer 106 is, for example, in the range of 50 nm to 100 nm. It is preferable that the thickness of the insulating layer 106 is about the same as that of the orientation pattern 105. It is also preferable that the thickness of the insulating layer 106 is thicker than that of the orientation pattern 105, but it is preferable that it is twice or less the thickness of the orientation pattern 105. If the thickness of the insulating layer 106 exceeds, for example, twice the thickness of the orientation pattern 105, a step will be created between the upper surface 105a of the orientation pattern 105 and the upper surface of the insulating layer 106. This step caused by the insulating layer 106 may reduce the crystallinity of the semiconductor layer formed later. Also, if the thickness of the insulating layer 106 is less than the thickness of the orientation pattern 105, the insulating layer 106 on top of the orientation pattern 105 may disappear when the insulating layer 106 is etched. By making the thickness of the insulating layer 106 provided on top of the orientation pattern 105 substantially the same as the thickness of the orientation pattern, the side surface 105b of the orientation pattern 105 can be covered and the upper surface 105a of the orientation pattern 105 can be protected. After etching, the orientation pattern 105 can be obtained by removing the resist mask 107.

[0030] The crystal orientation axis of the semiconductor layer 108, which is deposited later, is influenced by the surface of the insulating layer 106 and the surface of the orientation pattern 105. Therefore, it is preferable that the surfaces of the insulating layer 106 and the orientation pattern have flat surfaces. For example, the thickness of the insulating layer 106 may be made greater than the thickness of the orientation pattern 105, and a planarization treatment may be performed on the surface of the insulating layer 106 before forming the resist mask 107 so that the surface of the orientation pattern 105 is not exposed. For example, a polishing treatment may be performed on the surface of the insulating layer 106. In other words, a treatment may be performed on the insulating layer 106 so that the thickness of the region overlapping with the orientation pattern 105 is smaller than the thickness of the region not overlapping with the orientation pattern 105. This makes it possible to form a flat surface with reduced irregularities on the surface of the insulating layer 106.

[0031] Next, as shown in Figure 5, a semiconductor layer 108 is formed on the orientation pattern 105. In this embodiment, gallium nitride is formed as the semiconductor layer 108 by sputtering. Specifically, gallium nitride is formed by sputtering while an amorphous substrate 101 having an insulating surface (here, an amorphous substrate 101 provided with an underlayer 102) is heated to 25°C to 600°C, preferably 25°C to 400°C. In other words, the gallium nitride is formed at a temperature below the strain point of the amorphous substrate 101. Gallium nitride is usually formed by the MOCVD method (metal-organic chemical vapor deposition), but the MOCVD method has a high process temperature, which is not suitable considering the heat resistance of the amorphous substrate 101.

[0032] In contrast, in this embodiment, by using the sputtering method, a semiconductor layer 108 can be formed on an inexpensive amorphous substrate 101 at a lower temperature than the MOCVD method. Furthermore, the semiconductor layer 108 is formed on an orientation pattern 105 having crystallinity oriented along a specific axis (for example, the c-axis). In addition, the surface irregularities of the amorphous substrate 101 are mitigated by the underlayer 102, thereby mitigating the surface irregularities of the orientation pattern 105 formed on the underlayer 102. As a result, even when the semiconductor layer 108 is formed at a lower temperature than the MOCVD method, a highly crystalline semiconductor layer 108 can be formed. Moreover, since the amorphous substrate 101 can be made larger in area than a sapphire substrate, a large-area laminated structure 100 can be formed.

[0033] The semiconductor layer 108 is formed, for example, by sputtering a sintered gallium nitride body as a sputtering target and using argon (Ar) or a mixed gas of argon (Ar) and nitrogen (N2) as the sputtering gas. Examples of sputtering methods that can be applied include two-electrode sputtering, magnetron sputtering, dual magnetron sputtering, opposing target sputtering, ion beam sputtering, and inductively coupled plasma (ICP) sputtering.

[0034] The conductivity type of the semiconductor layer 108 may be substantially intrinsic, or it may have n-type or p-type conductivity. The n-type conductive semiconductor layer 108 may not contain a dopant for valence control, or it may be doped with silicon (Si) or germanium (Ge) as the n-type dopant. The p-type conductive semiconductor layer 108 may be doped with one element selected from magnesium (Mg), zinc (Zn), cadmium (Cd), and beryllium (Be) as the p-type dopant. When an n-type dopant is added to the semiconductor layer 108, the carrier concentration should be 1 × 10⁻⁶. 18 / cm 3 It is preferable to keep the values ​​above. When adding a p-type dopant to the semiconductor layer 108, the carrier concentration should be 5 × 1016 / cm 3 The above is preferable. Furthermore, if the semiconductor layer 108 is made substantially intrinsic, zinc (Zn) may be included as a dopant.

[0035] Furthermore, the semiconductor layer 108 may contain one or more elements selected from indium (In), aluminum (Al), and arsenic (As). These elements can be used to adjust the band gap of the semiconductor layer 108.

[0036] As described above, in this embodiment, a semiconductor layer 108 containing gallium nitride is formed on an amorphous substrate 101 on which an orientation pattern 105 is formed. The crystallinity of the semiconductor layer 108 formed on the orientation pattern 105 is influenced by the orientation axis of the orientation pattern 105. For example, if the orientation pattern 105 has rotational symmetry or c-axis orientation crystallinity, the semiconductor layer 108 also has c-axis orientation or (111) orientation crystallinity. The crystallinity of the semiconductor layer 108 is preferably single crystal, but it may also be polycrystalline, microcrystalline, or nanocrystalline. The crystal structure of the semiconductor layer 108 may have a wurtzite structure. The orientation of the semiconductor layer 108 is preferably c-axis orientation or (111) orientation. The semiconductor layer 108 may contain an amorphous structure near the interface in contact with the orientation pattern 105, but it is preferable that it has crystalline properties in bulk.

[0037] The thickness of the semiconductor layer 108 is between 100 nm and 1 μm. However, there are no limitations on the thickness of the semiconductor layer 108, and it can be set appropriately according to the device structure. The semiconductor layer 108 may be a single layer or a multilayer structure including multiple layers with different conductivity types and / or compositions.

[0038] Next, as shown in Figure 6, a resist mask 109 is formed on the semiconductor layer 108. Then, a semiconductor pattern 111 is formed by etching the semiconductor layer 108 using the resist mask 109. In this embodiment, a dry etching method using a halogenated gas is used as the method for etching the semiconductor layer 108. The halogenated gas is not particularly limited as long as it contains one or more halogen atoms such as chlorine atoms, fluorine atoms, and bromine atoms and is in a gaseous state at room temperature, but examples include CF4, C2F6, C3F8, C2F4, C4F8, C4F6, C5F8, CHF3, CCl4, CClF3, AlF3, AlCl3, etc. Multiple halogenated gases may also be mixed and used. It is preferable to use chlorine-based gases such as CCl4, CClF3, AlF3, AlCl3 as the halogenated gas. Therefore, the taper angle θ2 of the semiconductor pattern 111 can be 60° or more. However, the semiconductor pattern 111 may be formed using a wet etching method, as shown in Figure 6. The semiconductor pattern 111 has a gradient (hereinafter referred to as "taper") where the angle of the side surface to the bottom surface is θ2. Therefore, when using a wet etching method, the taper angle θ2 of the semiconductor pattern 111 can be set to 20° or more and 50° or less (preferably 30° or more and 40° or less). After etching, the resist mask 109 is removed to obtain a semiconductor pattern 111 containing gallium nitride.

[0039] In this case, the insulating layer 106 has a first region 110 (see Figure 8) that overlaps with the semiconductor pattern 111 and a second region 120 (see Figure 8) that does not overlap with the semiconductor pattern 111. Furthermore, the upper surface of the second region 120 in the insulating layer 106 is located below the upper surface of the first region 110. In other words, the first region 110 of the insulating layer 106 is the region that overlaps with the orientation pattern 105, and the second region 120 is the region that does not overlap with the orientation pattern 105. In addition, the film thickness in the second region 120 of the insulating layer 106 is thicker than the film thickness in the first region 110. Furthermore, the insulating layer 106 has a side surface in the second region 120 that is continuous with the upper surface of the first region 110.

[0040] Figure 7 is a plan view of a laminated structure 100 having a semiconductor pattern 111 containing gallium nitride. Figure 8 is an end view of the laminated structure 100 when it is cut along the line A1-A2.

[0041] The laminated structure 100 according to this embodiment includes forming an orientation layer 103 on an amorphous substrate 101 having an insulating surface, forming an orientation pattern 105 on the insulating surface by etching the orientation layer 103, depositing an insulating layer 106 on the insulating surface and the orientation pattern 105, and etching the insulating layer 106 to form the insulating layer 106 so that it is in contact with the side surface 105b of the orientation pattern 105 and surrounds the peripheral edge of the orientation pattern 105, depositing a semiconductor layer 108 containing gallium nitride on the insulating layer 106 and the orientation pattern 105, and etching the semiconductor layer 108 containing gallium nitride to form a semiconductor pattern 111 on the upper surface 105a of the orientation pattern 105. Furthermore, the insulating layer 106 surrounding the peripheral edge of the orientation pattern 105 has a first region 110 that overlaps with the semiconductor pattern 111 and a second region 120 that does not overlap with the semiconductor pattern 111.

[0042] In one embodiment of the present invention, the laminated structure 100 includes a semiconductor pattern 111 that has high crystallinity and c-axis orientation. The laminated structure 100 also includes an amorphous substrate 101 that can be made to a large area. Therefore, by using the laminated structure 100, the productivity of LEDs containing gallium nitride can be increased, or a backplane on which a transistor containing gallium nitride is formed can be fabricated.

[0043] The semiconductor pattern 111 of this embodiment has crystallinity aligned along a specific orientation axis, reflecting the orientation of the orientation pattern 105 and the insulating layer 106. Therefore, by processing the semiconductor pattern 111 of this embodiment and using it in a semiconductor device, a semiconductor device with excellent properties can be realized.

[0044] Furthermore, by patterning the orientation layer 103 to form an orientation pattern 105, a high-resolution semiconductor device can be formed compared to the case where the orientation layer is not patterned. In addition, by using a conductive material as the orientation pattern 105, the orientation pattern 105 can be used as wiring and electrodes.

[0045] When depositing the semiconductor layer 108, if the insulating layer 106 creates irregularities, these irregularities may affect the crystallinity of the semiconductor layer 108. Therefore, the insulating layer 106 may be processed to make the film thickness of the first region 110, which overlaps with the orientation pattern 105, smaller than the film thickness of the second region 120, which does not overlap with the orientation pattern 105. By performing such processing, the irregularities of the insulating layer 106 can be reduced when depositing the semiconductor layer 108 on the orientation pattern 105 and the insulating layer 106. Since the semiconductor layer 108 can be deposited on a surface that is as flat as possible, the crystallinity of the semiconductor layer 108 can be improved.

[0046] When dry etching is used to etch the orientation layer 103, the taper angle θ1 of the orientation pattern 105 tends to become large, and under certain conditions, the taper angle θ1 can exceed 60°. For example, when a gallium nitride layer is deposited immediately after the formation of the orientation pattern 105 and the gallium nitride layer is etched, etching residue (residue of the gallium nitride layer) may be generated near the lower end of the tapered portion (near the boundary between the base layer 102 and the orientation pattern 105). When forming high-resolution semiconductor devices, adjacent orientation patterns 105 are also in close proximity. Therefore, if gallium nitride residue is generated, there is a risk that adjacent orientation patterns 105 may become electrically conductive due to the etching residue.

[0047] In this embodiment, an insulating layer 106 is provided so as to surround the peripheral edge of the orientation pattern 105. The semiconductor layer 108 is deposited on the orientation pattern 105 and the insulating layer 106, and etched on the insulating layer 106. Therefore, regardless of the taper angle θ1 of the orientation pattern 105, it is possible to suppress the occurrence of etching residue of the semiconductor layer 108 near the lower end of the tapered portion of the orientation pattern 105. This makes it possible to suppress electrical conductivity caused by etching residue.

[0048] <Second Embodiment> In this embodiment, a laminated structure 100A having a structure that differs in part from the laminated structure 100 in the first embodiment will be described with reference to Figures 9 and 10. In the laminated structure 100A, the shape of the insulating layer 106 in contact with the orientation pattern 105 is different from the shape of the insulating layer 106 in the laminated structure 100.

[0049] The manufacturing method for the laminated structure 100A in this embodiment is the same as the manufacturing method for the laminated structure 100, as shown in Figures 1 to 5. The laminated structure 100A differs from the manufacturing method for the laminated structure 100 in that the region in which the resist mask 112 is formed on the deposited semiconductor layer 108 is located.

[0050] As shown in Figure 9, the resist mask 112 is formed inside the opening 106a of the insulating layer 106. Next, the semiconductor pattern 111 is formed by etching the insulating layer 106 using the resist mask 112. In this embodiment, a dry etching method using a halogenated gas is used as the method for etching the semiconductor layer 108. For the taper angle θ2, please refer to the description in Figure 6.

[0051] In this embodiment, the resist mask 112 is provided inside the opening 106a of the insulating layer 106. Therefore, when the semiconductor pattern 111 is formed by etching, the upper surface of the insulating layer 106 and the upper surface 105a of the orientation pattern 105 are removed. At this time, the insulating layer 106 is in contact with the side surface 105b (also called the outer peripheral side surface) of the orientation pattern 105, but not with the upper surface 105a of the orientation pattern 105. The orientation pattern 105 has a first region 130 that overlaps with the semiconductor pattern 111 and a second region 140 that does not overlap with the semiconductor pattern 111. The orientation pattern 105 also has a groove 105c near the lower end of the semiconductor pattern 111 in the second region 140.

[0052] As shown in Figure 10, the semiconductor pattern 111 does not overlap with the insulating layer 106. Therefore, even if there are regions with low crystallinity in the region that overlaps with the insulating layer 106 when the semiconductor layer 108 is deposited, these can be removed during the formation of the semiconductor pattern 111. This makes it possible to manufacture semiconductor devices using semiconductor patterns with high crystallinity.

[0053] <Third Embodiment> In this embodiment, a semiconductor device 500 using the stacked structure 100 in the first embodiment will be described with reference to Figures 11 to 12.

[0054] Figure 11 is an end view showing a semiconductor device 500 including the laminated structure 100 in the first embodiment. Specifically, the semiconductor device 500 shown in Figure 11 is an example of an LED element manufactured using the semiconductor pattern 111 shown in Figure 4. In the drawings, elements that are the same as those in the laminated structure 100 shown in the first embodiment are denoted by the same reference numerals, and redundant explanations are omitted.

[0055] As shown in Figure 11, the semiconductor device 500 includes a stacked structure 100 in the first embodiment, an n-type gallium nitride layer 501 provided on the semiconductor pattern of the stacked structure 100, an n-type electrode 504 provided on the n-type gallium nitride layer 501, a light-emitting layer 502 provided spaced apart from the n-type electrode 504 and provided on the n-type gallium nitride layer 501, a p-type gallium nitride layer 503 provided on the light-emitting layer 502, and a p-type electrode 505 provided on the p-type gallium nitride layer 503.

[0056] The semiconductor device 500 is formed by the process described below. After forming the semiconductor pattern 111 shown in Figure 4, an n-type gallium nitride layer 501, an emissive layer 502, and a p-type gallium nitride layer 503 are sequentially grown on the semiconductor pattern 111. Subsequently, a portion of the n-type gallium nitride layer 501, the emissive layer 502, and the p-type gallium nitride layer 503 is removed so that the n-type gallium nitride layer 501 is exposed. Finally, an n-type electrode 504 and a p-type electrode 505 are formed to contact the n-type gallium nitride layer 501 and the p-type gallium nitride layer 503, respectively. For the method of forming the n-type gallium nitride layer 501 and the p-type gallium nitride layer 503, refer to the description of the n-type conductive semiconductor layer 108 and the p-type conductive semiconductor layer 108 in the first embodiment.

[0057] Through the above process, the semiconductor device 500 shown in Figure 11 is completed. The semiconductor device 500 of this embodiment is formed using a highly crystalline semiconductor pattern 111 formed on an amorphous substrate 101. Therefore, according to this embodiment, the semiconductor device 500 can be manufactured on an inexpensive amorphous substrate 101. Furthermore, since the semiconductor device 500 can be manufactured on a large-area amorphous substrate 101, productivity is improved. In addition, according to this embodiment, since a highly crystalline gallium nitride layer can be formed by sputtering, the semiconductor device 500 is not exposed to high temperatures throughout the entire process, and the semiconductor device 500 can be manufactured with high throughput. Moreover, according to this embodiment, a high-resolution semiconductor device can be formed by using a laminated structure 100 having a fine semiconductor pattern 111.

[0058] The semiconductor device 500 shown in Figure 11 is merely one example of an LED element, and other LED elements with different structures may also be used. For example, the light-emitting layer 502 may be a quantum well structure in which gallium nitride layers and indium gallium nitride layers are alternately stacked.

[0059] In this embodiment, an example of manufacturing a semiconductor device 500 using a stacked structure 100 has been described, but the semiconductor device 500 may also be manufactured using a stacked structure 100A.

[0060] Figure 12 is a plan view showing a light-emitting device 600 using a semiconductor device 500 including a stacked structure 100 in the first embodiment. As shown in Figure 12, a display unit 601 and a peripheral circuit unit 602 are provided on the amorphous substrate 101. A terminal unit 603 for inputting various signals (video signals and control signals) to the light-emitting device 600 is provided in a part of the peripheral circuit unit 602. Multiple pixels 604 are arranged in a matrix inside the display unit 601. The semiconductor device 500 shown in Figure 11 is placed in each pixel 604. Although not shown, each pixel 604 may be provided with a semiconductor chip for controlling the light emission and non-light emission of the semiconductor device 500.

[0061] <Fourth Embodiment> This embodiment describes an example in which a semiconductor device with a different structure from that of the second embodiment is formed. Specifically, this embodiment describes an example in which a HEMT (High Electron Mobility Transistor) is formed as the semiconductor device. In the drawings, the same reference numerals are used for elements that are the same as those in the laminated structure 100 shown in the first embodiment, and redundant descriptions are omitted.

[0062] Figure 13 is an end view showing a semiconductor device 700 including a gallium nitride-based semiconductor layer in the fourth embodiment. Specifically, the semiconductor device 700 shown in Figure 13 is an example of a HEMT manufactured using the semiconductor pattern 111 shown in Figure 4 in the first embodiment.

[0063] As shown in Figure 13, the semiconductor device 700 includes a stacked structure 100 in the first embodiment, an n-type aluminum gallium nitride layer 701 provided on the semiconductor pattern of the stacked structure, an n-type gallium nitride layer 702 provided on the n-type aluminum gallium nitride layer 701, a source electrode 703 provided in contact with the n-type gallium nitride layer 702, a drain electrode 704 provided spaced apart from the source electrode 703 and in contact with the n-type aluminum gallium nitride layer 701, and a gate electrode 705 provided on the n-type aluminum gallium nitride layer 701, sandwiched between the source electrode 703 and the drain electrode 704. The semiconductor device 700 may also have silicon nitride provided as a protective layer on the source electrode 703, the drain electrode 704, and the gate electrode 705.

[0064] The semiconductor device 700 is formed by the process described below. An n-type aluminum gallium nitride layer 701 and an n-type gallium nitride layer 702 are sequentially formed on a semiconductor pattern 111 composed of gallium nitride-based semiconductor layers. Sputtering can be used to form these gallium nitride-based semiconductor layers. A trench reaching the n-type aluminum gallium nitride layer 701 is provided in the n-type aluminum gallium nitride layer 702, and a source electrode 703 and a drain electrode 704 are placed inside it. A gate electrode 705, which is in contact with the n-type gallium nitride layer 702, is placed between the source electrode 703 and the drain electrode 704. Finally, a silicon nitride layer 706 is formed as a protective layer, completing the HEMT shown in Figure 13.

[0065] The semiconductor device 700 of this embodiment is formed using a highly crystalline gallium nitride layer (semiconductor pattern 111) formed on an amorphous substrate 101. Therefore, according to this embodiment, the semiconductor device 700 can be manufactured on an inexpensive amorphous substrate 101. Furthermore, productivity is improved because the semiconductor device 500 can be manufactured on a large-area amorphous substrate 101. In addition, according to this embodiment, since multiple gallium nitride-based semiconductor layers are formed by sputtering, the semiconductor device 700 is not exposed to high temperatures throughout the entire process, and the semiconductor device 700 can be manufactured with high throughput. Moreover, according to this embodiment, a high-resolution semiconductor device can be formed by using a laminated structure 100 having a fine semiconductor pattern 111. Note that the semiconductor device 700 shown in Figure 13 is merely one example of a HEMT, and other HEMT structures may also be used.

[0066] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Based on these embodiments, any additions, deletions, or design changes made by those skilled in the art, or additions, omissions, or changes in processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0067] Furthermore, any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0068] 100, 100A...Laminated structure, 101...Amorphous substrate, 102...Underlayer, 103...Orientation layer, 104...Resist mask, 105...Orientation pattern, 105a...Top surface, 105b...Side surface, 105c...Groove, 106...Insulating layer, 106a...Opening, 107...Resist mask, 108...Semiconductor layer, 109...Resist mask, 110...First region, 111...Semiconductor pattern, 112...Resist mask, 120...Second region, 130...First region, 140...Second region Region, 500... Semiconductor device, 501... n-type gallium nitride layer, 502... Light-emitting layer, 503... p-type gallium nitride layer, 504... n-type electrode, 505... p-type electrode, 600... Light-emitting device, 601... Display unit, 602... Peripheral circuit unit, 603... Terminal unit, 604... Pixel, 700... Semiconductor device, 701... n-type aluminum gallium nitride layer, 702... n-type gallium nitride layer, 703... Source electrode, 704... Drain electrode, 705... Gate electrode, 706... Silicon nitride layer

Claims

1. An amorphous substrate having an insulating surface, The orientation pattern on the amorphous substrate, An insulating layer in contact with the side surface of the orientation pattern and surrounding the peripheral edge of the orientation pattern, A semiconductor pattern including gallium nitride on the orientation pattern, The insulating layer is a laminated structure having a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

2. The laminated structure according to claim 1, wherein the upper surface of the second region is located below the upper surface of the first region.

3. The laminated structure according to claim 2, wherein the insulating layer has a side surface in the second region that is continuous with the upper surface of the first region.

4. An amorphous substrate having an insulating surface, The orientation pattern on the amorphous substrate, An insulating layer that is in contact with the outer peripheral surface of the orientation pattern and not in contact with the upper surface of the orientation pattern, A semiconductor pattern including gallium nitride on the orientation pattern, The orientation pattern comprises a first region overlapping with the semiconductor pattern and a second region not overlapping with the semiconductor pattern, forming a laminated structure.

5. The laminated structure according to claim 4, wherein the orientation pattern has grooves near the lower end of the semiconductor pattern in the second region.

6. The laminated structure according to claim 1, wherein the orientation pattern is composed of a conductive material or insulating material having c-axis orientation.

7. The laminated structure according to claim 1, wherein the amorphous substrate is an amorphous glass substrate or a resin substrate.

8. An orientation layer is formed on an amorphous substrate having an insulating surface. By etching the orientation layer, an orientation pattern is formed on the insulating surface. An insulating layer is formed on the insulating surface and the orientation pattern. By etching the insulating layer, the insulating layer is formed to be in contact with the side surface of the orientation pattern and to surround the peripheral edge of the orientation pattern. A semiconductor layer containing gallium nitride is formed on the insulating layer and the orientation pattern. This includes etching the gallium nitride-containing semiconductor layer to form a semiconductor pattern on the upper surface of the orientation layer, A method for manufacturing a laminated structure, wherein the insulating layer surrounding the peripheral edge of the orientation pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

9. Forming the aforementioned insulating layer is The method for manufacturing a laminated structure according to claim 8, comprising forming the insulating layer such that the thickness of the insulating layer is substantially the same as the thickness of the orientation pattern.

10. Etching the aforementioned semiconductor layer is A method for manufacturing a laminated structure according to claim 8, comprising etching the upper surface of the second region in the orientation layer so that it is located below the upper surface of the first region.

11. Etching the aforementioned semiconductor layer is A method for manufacturing a laminated structure according to claim 8, comprising etching the insulating layer surrounding the peripheral edge of the orientation pattern such that a side surface continuous with the upper surface of the second region is formed in the second region.

12. An orientation layer is formed on an amorphous substrate having an insulating surface. By etching the orientation layer, an orientation pattern is formed on the insulating surface. An insulating layer is formed on the insulating surface and the orientation pattern. By etching the insulating layer, a surface is formed on the insulating layer that is in contact with the outer peripheral surface of the orientation pattern but not in contact with the upper surface of the orientation pattern. A semiconductor layer containing gallium nitride is formed on the insulating layer and the orientation pattern. This includes etching the gallium nitride-containing semiconductor layer to form a semiconductor pattern on the upper surface of the orientation layer, A method for manufacturing a laminated structure, wherein the orientation pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.

13. Forming the aforementioned insulating layer is The method for manufacturing a laminated structure according to claim 12, comprising forming the insulating layer such that the thickness of the insulating layer is substantially the same as the thickness of the orientation pattern.

14. Etching the aforementioned semiconductor layer is The method for manufacturing a laminated structure according to claim 12, wherein the orientation pattern is etched in the second region to form grooves near the lower end of the semiconductor pattern.

15. The method for manufacturing a laminated structure according to claim 8, wherein the orientation layer is formed of a conductive material or insulating material having c-axis orientation.

16. The method for manufacturing a laminated structure according to claim 8, wherein the amorphous substrate is an amorphous glass substrate or a resin substrate.

17. The method for manufacturing a laminated structure according to claim 8, wherein the semiconductor layer containing gallium nitride is formed by sputtering.

18. A semiconductor device using a laminated structure according to any one of claims 1 to 7.

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