Delay calibration device and delay calibration method

Abstract

The present disclosure provides a delay calibration apparatus including a delay calibration module, the delay calibration module including a coarse delay calibration unit and a fine delay calibration unit, the coarse delay calibration unit configured to receive an air interface pulse signal and perform delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal, the fine delay calibration unit including a fine delay calibration subunit and a phase calibration subunit, the fine delay calibration subunit configured to perform delay compensation on the channel associated pulse signal in an analog clock domain, and the phase calibration subunit configured to calibrate the phase of the clock domain. The present disclosure further provides a delay calibration method.

Description

[Technical Field]

[0001] [Cross-reference of related applications] This disclosure claims priority to the Chinese patent application filed with the China National Intellectual Property Administration on 31 August 2022, publication number CN202211058378.8, with the title of the invention "Delay Calibration Apparatus and Delay Calibration Method," all of which are incorporated herein by reference. [Technical field] The embodiments of this disclosure relate to, but are not limited to, the technology of communications, and more specifically to delay calibration devices and delay calibration methods. [Background technology]

[0002] In recent years, 5G communication has developed rapidly, and technologies such as Massive MIMO (Major-intensive Antenna Monetary Optics) and GPS 1PPS (Global Positioning System Pulse Per Second) time reporting have improved system capacity and clock accuracy. Consequently, the demand for higher accuracy in the digital link delay of radio frequency transceiver systems has also increased. However, limitations such as asynchronous processing of the clock domain crossing of the digital link, differences in reset path length, and changes in integrated circuit process characteristics (e.g., process corners, power supply voltage, and temperature, collectively referred to as PVT) result in differences in digital link delay between initial power-on and operation. These differences are represented by multi-antenna configurations in products, requiring data alignment processing.

[0003] Currently, the methods used for this type of processing involve constructing special excitation data, sampling two points of digital link data, analyzing it based on a correlation algorithm, obtaining the transmission delay of the data link, and then calibrating and aligning the data. However, the accuracy of delay calibration for two-point sampling links is limited, the entire algorithmic analysis process is complex and cumbersome, and the cost is high. [Overview of the project] [Problems that the invention aims to solve]

[0004] This disclosure provides a delay calibration device and a delay calibration method. [Means for solving the problem]

[0005] According to a first aspect, an embodiment of the present disclosure provides a delay calibration apparatus including a delay calibration module, the delay calibration module including a coarse delay calibration unit and a fine delay calibration unit. The coarse delay calibration unit is configured to receive an air interface pulse signal and to perform delay compensation for a channel linkage pulse signal in the digital clock domain based on the air interface pulse signal. The fine delay calibration unit includes a fine delay calibration subunit and a phase calibration subunit. The fine delay calibration subunit is configured to perform delay compensation for the channel linkage pulse signal in the analog clock domain after the coarse delay calibration unit has performed delay compensation for the channel linkage pulse signal in the digital clock domain based on the air interface pulse signal, and the phase calibration subunit is configured to calibrate the phase of the clock domain after the fine delay calibration subunit has performed delay compensation for the channel linkage pulse signal in the analog clock domain.

[0006] In another aspect, embodiments of the present disclosure further provide a delay calibration method applicable to the delay calibration apparatus described above, the method comprising the steps of receiving an air interface pulse signal and performing delay compensation for a channel coupling pulse signal in a digital clock domain based on the air interface pulse signal, and performing delay compensation for the channel coupling pulse signal in an analog clock domain and calibrating the phase of the clock domain. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram of the delay calibration module in the delay calibration device according to an embodiment of the present disclosure. [Figure 2] This is a schematic diagram of the overall configuration of the delay calibration device according to an embodiment of the present disclosure. [Figure 3] This is a schematic diagram of the second delay calibration module according to an embodiment of the present disclosure. [Figure 4] This is a schematic diagram of the RX link delay calibration sequence according to an embodiment of the present disclosure. [Figure 5] This is a schematic diagram of the first delay calibration module according to an embodiment of the present disclosure. [Figure 6] This is a schematic diagram of the TX link delay calibration sequence according to an embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the gate_pluse differential circuit according to an embodiment of the present disclosure. [Figure 8] This is a schematic diagram of the gate_pluse differential circuit sequence according to an embodiment of the present disclosure. [Figure 9] This is a flowchart of the delayed calibration method according to an embodiment of the present disclosure. [Figure 10] This is a flowchart illustrating delay compensation for channel-coordinated pulse signals in a transmission link according to an embodiment of the present disclosure. [Figure 11]A flowchart for performing delay compensation on a channel cooperation pulse signal in a reception link according to an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described more fully with reference to the drawings. However, the exemplary embodiments may be embodied in different forms and are not limited to the embodiments described herein. Conversely, the purpose of providing these embodiments is to make the present disclosure clear and complete, and enable those skilled in the art to fully understand the scope of the present disclosure.

[0009] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0010] The terms used herein are only for the purpose of describing specific embodiments and do not limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Further understood, when the terms "comprising" and / or "manufactured from..." are used herein, it specifies the presence of the above characteristics, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other characteristics, wholes, steps, operations, elements, components and / or groups thereof.

[0011] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations can be changed based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the illustrated embodiments and include changes in the configurations formed based on manufacturing steps. Therefore, the illustrated exemplary regions have exemplary attributes, and the shapes of the illustrated regions show the specific shapes of the regions of the elements, but are not intended to be limiting.

[0012] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art. Furthermore, unless expressly limited herein, such terms, as limited to, for example, their general dictionaries, should be construed to have meanings consistent with their meanings in the context of the relevant art and this disclosure, and not to have ideal or excessive formal meanings.

[0013] In related technologies, performing delay calibration by taking two-point samples from digital link data has the following drawbacks:

[0014] 1. Link delay calibration has limitations in terms of accuracy. Conventional two-point synchronous sampling methods have one uncertainty in the clock cycle accuracy of each clock domain for each clock domain crossing in the link, and because sampling is performed in the digital clock domain, the clock frequency is low and there is a time difference of one clock cycle.

[0015] 2. The entire algorithm analysis process is complex, cumbersome, and costly. First, it is necessary to construct and process corresponding excitation data for different data processing methods in different scenes of digital links of different systems. Second, offline analysis cannot enable immediate product application, and online analysis consumes a large amount of software and hardware resources, significantly increasing power consumption. Finally, both initialization correction during power-on and recorrection during normal operation take a long time overall, which is detrimental to quickly completing high-precision time reporting of the system.

[0016] To solve the above problems, an embodiment of the present disclosure provides a delay calibration device, the delay calibration device including a delay calibration module. Figure 1 is a schematic diagram of the delay calibration module in the delay calibration device according to an embodiment of the present disclosure. As shown in Figure 1, the delay calibration module includes a coarse delay calibration unit 10 and a precision delay calibration unit 20, the coarse delay calibration unit 10 is configured to receive an air interface pulse signal (ref_pluse) and to perform delay compensation for a channel linkage pulse signal (data_pluse) in the digital clock domain based on the air interface pulse signal (ref_pluse).

[0017] The precision delay calibration unit 20 includes a precision delay calibration subunit 21 and a phase calibration subunit 22, wherein the precision delay calibration subunit 21 is configured to perform delay compensation on the channel coupling pulse signal in the analog clock domain after the coarse delay calibration unit 22 has performed delay compensation on the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal.

[0018] The phase calibration subunit 22 is configured to calibrate the phase of the clock domain after the precision delay calibration subunit 21 has performed delay compensation on the channel-coupling pulse signal in the analog clock domain.

[0019] The air interface pulse signal (ref_pluse) is generated by dividing the GPS 1PPS signal, and is generally an integer multiple of the T period, maintaining a high level for a certain period of time. The period of the channel coupling pulse signal (data_pluse) is the same as the period of the air interface pulse signal, maintaining a high level for one period of the clock domain in which it is located.

[0020] The delay calibration device according to the embodiment of this disclosure can improve delay calibration accuracy to two high-frequency clock cycles by performing delay compensation in the digital clock domain and phase calibration in the analog high-frequency clock domain, using the air interface pulse signal as a reference. Instead of algorithmic analysis after conventional two-point synchronous sampling, the calibration process is simplified by adjusting the channel-coordinated pulse signal delay and digital clock phase in the digital clock domain, reducing the computational load of the algorithm and achieving high-speed, high-precision time reporting of the link. Furthermore, the overall structure of the delay calibration device is simple and can be adapted to multi-channel, multi-mode, and multiple operating scenes.

[0021] Figure 2 is a schematic diagram of the overall configuration of a delay calibration device according to an embodiment of the present disclosure. As shown in Figure 2, the delay calibration device includes a transmit link (TX link), the delay calibration module includes a first delay calibration module (DAC calibration) 100, the first delay calibration module is located on the transmit link, the coarse delay calibration unit 10 is the first coarse delay calibration unit 101, the precision delay calibration unit 20 is the first precision delay calibration unit 201, and the channel linkage pulse signal is the transmit channel linkage pulse signal.

[0022] The transmission link (TX link) further includes a transmission channel linkage pulse generation module 110 and a transmission link channel linkage pulse transmission module 120. The transmission channel linkage pulse generation module 110 is configured to receive an air interface pulse signal and generate a transmission channel linkage pulse signal based on the air interface pulse signal.

[0023] The transmit link channel coordinated pulse transmission module 120 is configured to align and transmit the transmit channel coordinated pulse signal and link data within the multi-clock domain of the transmit link using the data enable signal, and transmit them to the first coarse delay calibration unit 101 of the first delay calibration module 100.

[0024] The transmit channel coordination pulse signal is generated in the transmit channel coordination pulse signal generation module 110, passes through each clock domain of the TX link, and reaches the first delay calibration module (DAC calibration) 100 where it is calibrated. When transmitting a signal, the transmit channel coordination pulse signal and link data pass together through the multi-clock domain of the TX link and are transmitted after being aligned with the link data using the data enable signal. Therefore, the transmit channel coordination pulse signal can represent the delay status of link data transmission.

[0025] As shown in Figure 2, the delay calibration device further includes a receiving link (RX link), the delay calibration module includes a second delay calibration module (ADC calibration) 200, the second delay calibration module 200 is located on the receiving link, the channel coupling pulse signal is a received channel coupling pulse signal, the precision delay calibration unit 20 is a second precision delay calibration unit 202, the coarse delay calibration unit 10 is a second coarse delay calibration unit 102, the second coarse delay calibration unit 102 further generates a received channel coupling pulse signal (rx_data_pluse) based on the air interface pulse signal after receiving the air interface pulse signal.

[0026] The receive link (RX link) further includes a receive channel coordinating pulse calibration module 210 and a receive link channel coordinating pulse transmission module 220. The receive link channel coordinating pulse transmission module 220 is configured to align and transmit receive channel coordinating pulse signals and link data within the multi-clock domain of the receive link, using a data enable signal, and transmit them to the receive channel coordinating pulse calibration module 210.

[0027] The receiving channel coordinating pulse calibration module 210 is configured to perform delay compensation on the channel coordinating pulse signal received in the digital clock domain based on the air interface pulse signal.

[0028] The received channel coordination pulse signal is generated in the second delay calibration module (ADC calibration) 200, passes through each clock domain of the RX link, and reaches the received channel coordination pulse calibration module 210 for calibration. When transmitting signals, the received channel coordination pulse signal and link data pass together through the multi-clock domain of the RX link and are transmitted after being aligned with the link data using the data enable signal. Therefore, the received channel coordination pulse signal can represent the delay status of link data transmission.

[0029] Figure 3 is a schematic diagram of a second delay calibration module according to an embodiment of the present disclosure. As shown in Figure 3, the second delay calibration module 200 includes a second coarse delay calibration unit (GEN_PLUSE) 102 and a second fine delay calibration unit (ADC_FT_PLUSE) 202.

[0030] The second coarse delay calibration unit 102 includes a second air interface pulse processing subunit (posedge0), a second channel linked pulse signal regeneration subunit (regen2), a second delay subunit (delay2), and a second coarse delay calibration subunit (ct_g). The second air interface pulse processing subunit (posedge0) is configured to generate a single-period air interface pulse signal based on the rising edge of the air interface pulse signal (ref_pluse).

[0031] The second channel linkage pulse signal regeneration subunit (regen) is connected to the second air interface pulse processing subunit (posedge0) and the second delay subunit (delay2), respectively. It is configured to generate a regenerated received channel linkage pulse signal by reducing a single-period air interface pulse signal transmitted from the second air interface pulse processing subunit (posedge0) by a predetermined multiple at the same ratio period, and then transmit the regenerated received channel linkage pulse signal to the second delay subunit (delay2). The period T and predetermined multiple N of the air interface pulse signal are set in advance in the second channel linkage pulse signal regeneration subunit (regen), and the loop regenerated received channel linkage pulse signal is generated according to the period T and predetermined multiple N of the air interface pulse signal.

[0032] The second delay subunit (delay2) is configured to remove the delay between the regenerated received channel linkage pulse signal and the next air interface pulse signal to acquire the second signal, which is the regenerated received channel linkage pulse signal from which the delay has been removed. The second delay subunit (delay2) sets a delay close to the period T of the air interface pulse signal, and then performs successive comparisons by increasing the delay by 1 beat each time. Figure 4 is a schematic diagram of the RX link delay calibration sequence according to an embodiment of the present disclosure. As shown in Figure 4, in this case, the delay difference Rd1 between the received channel linkage pulse signal (i.e., the second signal) and the next air interface pulse signal is the asynchronous sampling uncertainty delay.

[0033] The second coarse delay calibration subunit (ct_g) is configured to perform a logical AND operation on the second signal and the single-period air interface pulse signal. If the result of the operation is not 1, it performs coarse delay calibration, stops the operation until the result is 1, and generates a second instruction signal (gen_int_flag). The second instruction signal (gen_int_flag) instructs the second precision delay calibration unit 202 to perform precision delay calibration. Each time, the second coarse delay calibration subunit (ct_g) triggers a coarse delay calibration interrupt on the rising edge of the air interface pulse signal, generates ct_int_flag until the logical AND result of the channel linkage pulse signal and the air interface pulse signal is 1, and indicates that the coarse delay calibration is complete.

[0034] In some embodiments, as shown in Figure 3, the second coarse delay calibration unit 102 further includes a second expansion subunit (expand2), which is connected to a second delay subunit (delay2) and a second coarse delay calibration subunit (ct_g). The second expansion subunit (expand2) expands the high-level length of the second signal according to one clock cycle and transmits the expanded signal to the second coarse delay calibration subunit (ct_g), so that the second coarse delay calibration subunit (ct_g) performs a logical AND operation on the expanded signal and the single-period air interface pulse signal. The second expansion subunit (expand2) eliminates the effects of uncertainty due to asynchronous sampling delay differences by expanding the high-level length of the channel coupling pulse signal (i.e., the second signal) according to one clock cycle, and ensures that the channel coupling pulse signal is faster than the air interface pulse signal.

[0035] As shown in FIGS. 2 and 4, the second delay calibration module 200 transmits a received channel cooperation pulse signal, and the received channel cooperation pulse signal sequentially passes through a plurality of clock domains of the received link channel cooperation pulse transmission module 220, ensuring that the received channel cooperation pulse signal holds a high level for one clock cycle, is transmitted to the next-stage circuit in synchronization with data, and when reaching the received channel cooperation pulse calibration module 210, the difference between the received channel cooperation pulse signal and the air interface pulse signal is R d3 -R d2 and R d2 is the delay between the received channel cooperation pulse signal and the next air interface pulse signal, and R d3 is the sum of the link fixed delay R d31 and the uncertain delay R d32 of the clock domain crossing. Coarse delay calibration is performed within the received channel cooperation pulse calibration module 210, and the coarse delay calibration process is the same as the coarse delay calibration process of the first delay calibration module 100. The final delay accuracy is R d5 =R d2 +R d51 where R d51 is the clock cycle R1 of one RX interface clock domain, and R d2 is the sum of the clock cycles T adc_ana of two ADC analog clock domains.

[0036] FIG. 5 is a schematic configuration diagram of the first delay calibration module according to an embodiment of the present disclosure. As shown in FIG. 5, the first delay calibration module 100 includes a first coarse delay calibration unit (CT_PLUSE) 101 in the digital domain and a first precision delay calibration unit (DAC_FT_PLUSE) 201 in the analog domain.

[0037] The first coarse delay calibration unit 101 includes a first air interface pulse processing subunit (posedge0), a first delay subunit (delay1), and a first coarse delay calibration subunit (ct_f).

[0038] The first air interface pulse processing subunit (posedge0) is configured to generate a single-period air interface pulse signal based on the rising edge of the air interface pulse signal.

[0039] The first delay subunit (delay1) is configured to remove the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit 101 and the next air interface pulse signal to obtain the first signal (ct_data_pluse). The transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit 101 is the signal (dac_data_pluse) transmitted from the transmit link channel linkage pulse transmission module 120 to the first coarse delay calibration unit 101.

[0040] The first coarse delay calibration subunit (ct_f) performs a logical AND operation on the first signal (ct_data_pluse) and the single-period air interface pulse signal. If the result of the operation is not 1, it performs coarse delay calibration and stops the operation until the result is 1. It then generates a first instruction signal (ct_int_flag), which instructs the first precision delay calibration unit 201 to perform precision delay calibration. Each time, the first coarse delay calibration subunit (ct_f) triggers a coarse delay calibration interrupt by the rising edge of the channel linkage pulse signal. It generates ct_int_flag until the logical AND result of the channel linkage pulse signal and the air interface pulse signal is 1, indicating that the coarse delay calibration is complete.

[0041] Figure 6 is a schematic diagram of the TX link delay calibration sequence according to an embodiment of the present disclosure. As shown in Figure 6, after performing coarse delay calibration, in this case the delay difference between the transmit channel coupling pulse signal and the next air interface pulse signal is T d4 =T d1 +T d22 +T d31 And, T d1 This is the asynchronous sampling delay between the transmit channel linkage pulse signal and the air interface pulse signal, and T d22 This is the uncertainty delay of the clock domain crossing, and T d31 This is the sampling delay of the air interface pulse signal in the DAC digital clock domain.

[0042] In some embodiments, as shown in Figure 5, the first coarse delay calibration unit 101 further includes a comparison subunit (counter0) configured to calculate the time difference between a single-period air interface pulse signal and a transmit channel coupling pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101, and to set the delay between the transmit channel coupling pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit and the next air interface pulse signal based on the time difference. After obtaining the time difference between the single-period air interface pulse signal and the transmit channel coupling pulse signal (dac_data_pluse), the comparison subunit (counter0) performs a successive comparison by increasing the beat delay by 1 each time.

[0043] In some embodiments, as shown in Figure 5, the first coarse delay calibration unit 101 further includes a first air interface pulse signal regeneration subunit (regen_1) and a first channel linkage pulse signal regeneration subunit (regen_0).

[0044] The first air interface pulse signal regeneration subunit (regen_1) is connected to the first air interface pulse processing subunit (posedge0) and the first coarse delay calibration subunit (ct_f). It is configured to generate a regenerated air interface pulse signal by reducing the air interface pulse signal (ref_pluse) by a predetermined multiple at the same ratio period, and to transmit the regenerated air interface pulse signal to the first coarse delay calibration subunit (ct_f). The period T and predetermined multiple N of the air interface pulse signal (ref_pluse) are set in advance in the first air interface pulse signal regeneration subunit (regen_1), and the loop regenerated air interface pulse signal is generated according to the period T and predetermined multiple N of the air interface pulse signal (ref_pluse).

[0045] The first channel linkage pulse signal regeneration subunit (regen_0) is connected to the first delay subunit (delay1) and generates a regenerated transmit channel linkage pulse signal by reducing the transmit channel linkage pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101 by a predetermined multiple at the same ratio period. The first delay subunit (delay1) then transmits the regenerated transmit channel linkage pulse signal to the first delay subunit (delay1), thereby eliminating the delay between the regenerated transmit channel linkage pulse signal and the next air interface pulse signal. The period T and predetermined multiple N of the transmit channel linkage pulse signal (dac_data_pluse) are set in advance in the first channel linkage pulse signal regeneration subunit (regen_0), and the loop regenerated transmit channel linkage pulse signal is generated according to the period T and predetermined multiple N of the transmit channel linkage pulse signal (dac_data_pluse).

[0046] By reducing the transmit channel linkage pulse signal (dac_data_pluse) and the air interface pulse signal (ref_pluse) by N times with the same ratio period and looping them back up, it is possible to perform N coarse delay calibration processes within a single air interface pulse signal period, significantly accelerating the speed of coarse delay calibration.

[0047] In some embodiments, as shown in Figure 5, the first coarse delay calibration unit 101 further includes a first expansion subunit (expand1), which is connected to a first delay subunit (delay1) and a first coarse delay calibration subunit (ct_f). The first expansion subunit (expand1) expands the high-level length of a first signal (ct_data_pluse) according to one clock cycle and transmits the expanded signal to the first coarse delay calibration subunit (ct_f), so that the first coarse delay calibration subunit (ct_f) performs a logical AND operation on the expanded signal and the single-period air interface pulse signal. The first expansion subunit (expand1) expands the high-level length of the channel linkage pulse signal (i.e., the first signal) according to one clock cycle, thereby avoiding uncertainty in the delay difference due to two asynchronous samplings and clock domain crossings, and ensuring that the channel linkage pulse signal is faster than the air interface pulse signal.

[0048] As shown in Figures 2 and 6, the transmit channel coordinating pulse generation module 110 receives the air interface pulse signal (ref_pluse) and then synchronously generates the channel coordinating pulse signal (data_pluse). Here, the channel coordinating pulse signal (data_pluse) refers to the transmit channel coordinating pulse signal. In this case, since the clock samples the air interface pulse signal (ref_pluse) asynchronously, there is a possibility of a metastable state scene, and the delay difference between the channel coordinating pulse signal (data_pluse) and the air interface pulse signal (ref_pluse) is one T1 clock domain period Td1. The channel linkage pulse signal (data_pluse) passes sequentially through multiple clock domains of the transmit link channel linkage pulse transmission module 120, is controlled by the data enable signal, and is processed according to different operating scenes or modes. For example, by multiplicative expansion of different extraction filters or non-power-saving processing in TDD (Time Division Duplexing) scenes, the channel linkage pulse signal is sampled by the next stage circuit and maintains a high level for only one clock cycle, ensuring that it is transmitted to the next stage circuit in synchronization with the data. However, due to power-on each time or long-term clock fluctuations, the clock phase relationship on both sides of the clock domain crossing is not determined, so there is an uncertainty of one clock cycle in each clock domain crossing transmission. When it reaches the DAC digital clock domain, the difference between the channel linkage pulse signal (data_pluse) and the air interface pulse signal (ref_pluse) that generates it is Td1 + Td2, where Td2 is the sum of the link fixed delay Td21 and the uncertainty delay Td22 of the clock domain crossing.

[0049] In the embodiments of this disclosure, the structures of the first precision delay calibration unit 201 and the second precision delay calibration unit 202 are basically the same. As shown in Figures 3 and 5, both the first precision delay calibration unit 201 and the second precision delay calibration unit 202 include a channel linkage pulse processing subunit (posedge), a decision subunit (count), an air interface pulse synchronization subunit (sync1), a channel linkage pulse synchronization subunit (sync0), a precision delay calibration subunit (not shown), and a precision delay calibration interrupt subunit (ft_int_gen).

[0050] The channel coordinating pulse processing subunit (posedge) is configured to receive a channel coordinating pulse signal transmitted from a coarse delay calibration unit in the delay calibration module in which it exists, generate a single-period channel coordinating pulse signal based on the rising edge of the channel coordinating pulse signal, and transmit the single-period channel coordinating pulse signal to the first precision delay calibration interrupt subunit. In the first precision delay calibration unit 201, the channel coordinating pulse signal is the first signal transmitted from the first coarse delay calibration unit 101, and in the second precision delay calibration unit 202, the channel coordinating pulse signal is the second signal transmitted from the second coarse delay calibration unit 102.

[0051] The air interface pulse synchronization subunit (sync1) is configured to synchronize the air interface pulse signal to its existing clock domain and to send the synchronized air interface pulse signal to the decision subunit (count).

[0052] The channel linkage pulse synchronization subunit (sync0) is configured to synchronize the channel linkage pulse signal to its existing clock domain and to send the synchronized channel linkage pulse signal to the decision subunit (count).

[0053] The decision subunit (count) is configured to perform a logical AND operation on the synchronized air interface pulse signal and the synchronized channel linkage pulse signal.

[0054] The precision delay calibration subunit performs precision delay calibration if the calculation result calculated by the decision subunit (count) is 0. The precision delay calibration subunit may also be a functional module implemented by software.

[0055] The precision delay calibration interrupt subunit (ft_int_gen) is configured to trigger and generate an interrupt signal to stop precision delay calibration based on a single-period channel coordinating pulse signal.

[0056] In some embodiments, the precision delay calibration subunit of the first precision delay calibration unit 201 is configured to adjust the delay of the transmit channel coupling pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101 by incrementing the read address of the first-in, first-out memory (FIFO) of the clock domain crossing in the transmit link by one.

[0057] In some embodiments, the precision delay calibration subunit of the second precision delay calibration unit 202 is configured to adjust the delay between the regenerated received channel coupling pulse signal and the next air interface pulse signal.

[0058] As shown in Figures 3 and 5, the first precision delay calibration unit 201 of the first delay calibration module 100 includes a phase calibration subunit, and the second precision delay calibration unit 202 of the second delay calibration module 200 includes a phase calibration subunit. The phase calibration subunit includes a differential pulse gating subunit (gate_pluse) and a clock division subunit (clk_div), the differential pulse gating subunit (gate_pluse) being configured to adjust the initial phase of the analog domain clock signal based on a gating signal, and the clock division subunit (clk_div) being configured to adjust the initial phase of the digital domain clock signal based on the initial phase of the analog domain clock signal.

[0059] After the coarse delay calibration is complete, the precise delay calibration is performed. The precise delay calibration includes precise delay compensation and phase calibration. The synchronized air interface pulse signal and the synchronized channel linkage pulse signal are subjected to a logical AND operation in the decision subunit (count). If the calculation result (adc_ft_counter) is 0, the precise delay calibration subunit is instructed to perform precise delay compensation until the calculation result is not 0, indicating that the uncertain delays of the two asynchronously sampled air interface pulses and clock domain crossing have been eliminated. In this case, the delay difference is equal to one clock cycle T of the DAC digital clock domain. dac_dig and 1 clock cycle T of the DAC analog clock domain dac_ana It is the sum of.

[0060] Figure 7 is a schematic diagram of the gate_pluse differential circuit according to an embodiment of the present disclosure, and Figure 8 is a schematic diagram of the gate_pluse differential circuit sequence according to an embodiment of the present disclosure. As shown in Figures 5, 6, 7, and 8, taking the first precision delay calibration unit 201 as an example, the differential pulse gating subunit (gate_pluse) can turn off the clock for one clock cycle each time the gating enable is activated, and together with the clock division subunit (clk_div), the digital clock clk_dac_dig of the DAC can adjust the initial phase division of the analog clock clk_dac_ana of one DAC each time. In this way, when the calculation result reaches its maximum, the phase calibration is completed, and as shown in Figure 6, after precision delay calibration, the delay accuracy between the transmit channel coupling pulse signal and the next air interface pulse signal is T d5 Therefore, the clock cycle of the two DAC analog clock domains is T dac_ana That is the case.

[0061] Furthermore, in the second delay calibration module 200, after the second coarse delay calibration unit 102 completes the coarse delay calibration, the second precise delay calibration unit 202 performs the precise delay calibration. This precise delay calibration process is the same as the process performed by the first precise delay calibration unit 201, but with the following differences.

[0062] 1. Precision delay compensation uses a different method for adjusting the delay. The second precision delay calibration unit 202 adjusts the delay between the regenerated receive channel linkage pulse signal and the next air interface pulse signal, while the first precision delay calibration unit 201 adjusts the delay of the transmit channel linkage pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit by increasing the FIFO read address of the clock domain crossing in the transmit link by one.

[0063] 2. The trigger signals for the precision delay calibration interrupt are different. In the second precision delay calibration unit 202, the precision delay calibration interrupt is triggered by the rising edge of the air interface pulse signal (ref_pluse), while in the first precision delay calibration unit 201, the precision delay calibration interrupt is triggered by the rising edge of the channel coordinating pulse signal (data_pluse).

[0064] As shown in Figure 4, after precise delay calibration, the delay accuracy between the received channel coupling pulse signal and the next air interface pulse signal is R d2 Therefore, the clock cycle of the two ADC analog clock domains is T adc_ana That is the case.

[0065] The delay calibration device according to the embodiment of this disclosure can improve the accuracy of delay calibration to two high-frequency clock cycles by using the synchronous transmissionability after alignment of the channel coordinating pulse signal and link data with respect to the air interface pulse signal, performing delay compensation in the digital clock domain, and performing phase calibration in the analog ADDA high-frequency clock domain. Instead of algorithmic analysis after conventional two-point synchronous sampling, the calibration process is greatly simplified by adjusting the channel coordinating pulse signal delay and digital clock phase of the first / last level digital clock domain by software, avoiding a large amount of algorithmic calculations, and enabling rapid, high-precision link time reporting, even during the initial power-up process or normal operation. The entire delay calibration device according to the embodiment of this disclosure has a simple structure and can be adapted to multi-channel, multi-mode, and multiple operating scenes.

[0066] The embodiments of this disclosure are applicable to radio frequency transceiver systems of terminals or base stations and can support high-precision delay calibration in multilink, multiclock domain, and multioperating modes. They support TX and RX multilink extensions and can merge and generate multilink channel coordinating pulse signals in a transmit channel coordinating pulse signal generator module 110 and a receive channel coordinating pulse signal calibration module 210 within a digital interface for calibration. The embodiments of this disclosure support multi-system docking of the entire device and can transfer the transmit channel coordinating pulse signal generator module 110 and the receive channel coordinating pulse signal calibration module 210 within the digital interface to the link source / end of the upstream chip system, thus enabling high-precision calibration of the delay across the entire link.

[0067] The embodiments of this disclosure are applicable to transceiver systems with high latency requirements and clock domain crossing or asynchronous clock domains, and can be broadly applied to radio frequency chips, terminal chips, and baseband chips having corresponding needs.

[0068] Embodiments of the present disclosure further provide a delay calibration method applicable to the delay calibration apparatus described above, the method comprising the following steps S11 to S12, as shown in Figure 9.

[0069] In step S11, the air interface pulse signal is received, and based on the air interface pulse signal, delay compensation is performed on the channel coupling pulse signal in the digital clock domain.

[0070] In this step, the coarse delay calibration unit 10 performs delay compensation on the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal.

[0071] In step S12, delay compensation is performed on the channel-coupling pulse signal in the analog clock domain, and the phase of the clock domain is calibrated.

[0072] In this step, the precision delay calibration subunit 21 of the precision delay calibration unit 20 performs delay compensation for the channel-coupling pulse signal in the analog clock domain, and the phase calibration subunit of the precision delay calibration unit 20 calibrates the phase of the clock domain.

[0073] The delay calibration method according to the embodiment of this disclosure improves the delay calibration accuracy to two high-frequency clock cycles by performing delay compensation in the digital clock domain and phase calibration in the analog high-frequency clock domain, using the air interface pulse signal as a reference. Instead of the conventional algorithmic analysis after two-point synchronous sampling, the calibration process is simplified by adjusting the channel-coordinated pulse signal delay and digital clock phase in the digital clock domain, reducing the computational load of the algorithm, achieving high-speed and high-precision time reporting of the link, and the overall structure of the delay calibration device is simple and can be adapted to multi-channel, multi-mode and multiple operating scenes.

[0074] In some embodiments, as shown in Figure 10, the step of performing delay compensation for the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal in the transmit link (i.e., step S11) is: Step S111 generates a transmit channel linkage pulse signal based on the air interface pulse signal, Step S112 involves aligning and transmitting a transmission channel coordination pulse signal and link data within the multi-clock domain of the transmission link using a data enable signal. The process includes step S113, which performs delay compensation for the transmit channel coupling pulse signal in the digital clock domain based on the air interface pulse signal.

[0075] In some embodiments, as shown in Figure 11, the step of performing delay compensation for the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal in the receiving link (i.e., step S11) is: Step S111' generates a received channel linkage pulse signal based on the air interface pulse signal, Step S112' involves aligning and transmitting the received channel coordination pulse signal and link data within the multi-clock domain of the receiving link using the data enable signal, The process includes step S113', which performs delay compensation on a received channel coupling pulse signal that has been aligned and transmitted in the digital clock domain, based on an air interface pulse signal.

[0076] In some embodiments, the step of generating a received channel linkage pulse signal based on an air interface pulse signal (i.e., step S111') includes generating a single-period air interface pulse signal based on the rising edge of the air interface pulse signal, and generating a regenerated received channel linkage pulse signal by reducing the single-period air interface pulse signal by a predetermined multiple at the same ratio period.

[0077] The step of performing delay compensation for the received channel coupling pulse signal that has been aligned and transmitted in the digital clock domain based on the air interface pulse signal (i.e., step S113') is, The process includes the steps of: obtaining a second signal by removing the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal; performing a logical AND operation on the second signal and the single-period air interface pulse signal; performing a coarse delay calibration if the result of the operation is not 1; stopping the operation until the result of the operation is 1; and generating a second instruction signal.

[0078] In some embodiments, after acquiring the second signal, and before performing a logical AND operation on the second signal and the single-period air interface pulse signal, the method further includes the step of extending the high-level length of the second signal according to one clock cycle and performing a logical AND operation on the extended signal and the single-period air interface pulse signal.

[0079] In some embodiments, the step of performing delay compensation for the transmit channel coupling pulse signal in the digital clock domain based on the air interface pulse signal (i.e., step S113) is: The method includes the steps of: generating a single-period air interface pulse signal based on the rising edge of an air interface pulse signal; obtaining a first signal by removing the delay between a transmit channel coupling pulse signal transmitted to a first coarse delay calibration unit and the next air interface pulse signal; and performing a logical AND operation on the first signal and the single-period air interface pulse signal, and if the result of the operation is not 1, performing a coarse delay calibration, stopping the operation until the result of the operation is 1, and generating a first instruction signal.

[0080] In some embodiments, before removing the delay between the transmit channel coordinating pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method further includes the step of calculating the time difference between the single-period air interface pulse signal and the transmit channel coordinating pulse signal transmitted to the first coarse delay calibration unit, and setting the delay between the transmit channel coordinating pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal based on the time difference.

[0081] In some embodiments, before removing the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method further includes the steps of generating a regenerated air interface pulse signal by reducing the air interface pulse signal by a predetermined multiple at the same ratio period, and removing the delay between the regenerated transmit channel linkage pulse signal and the next air interface pulse signal by generating a regenerated transmit channel linkage pulse signal by reducing the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit by a predetermined multiple at the same ratio period.

[0082] In some embodiments, before performing a logical AND operation on the first signal and the single-period air interface pulse signal, the method further includes the step of extending the high-level length of the first signal according to one clock cycle, and then performing a logical AND operation on the extended signal and the single-period air interface pulse signal.

[0083] In some embodiments, after performing coarse delay calibration, the method is performed A step of receiving a channel linkage pulse signal and generating a single-period channel linkage pulse signal based on the rising edge of the channel linkage pulse signal, wherein the channel linkage pulse signal is a first signal or a second signal. The steps include synchronizing the air interface pulse signal to the clock domain in which it resides, and synchronizing the channel interoperability pulse signal to the clock domain in which it resides, A step of performing a logical AND operation on the synchronized air interface pulse signal and the synchronized channel linkage pulse signal, and if the result of the operation is 0, performing a precise delay calibration, further comprising the step of triggering and generating an interrupt signal to stop the precise delay calibration based on the single-period channel linkage pulse signal.

[0084] In some embodiments, the step of performing the precise delay calibration is, A step of adjusting the delay of the transmit channel coupling pulse signal transmitted to the first coarse delay calibration unit by increasing the read address of the first-in, first-out memory of the clock domain crossing in the transmit link by one, or The process includes adjusting the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal.

[0085] In some embodiments, the step of calibrating the phase of the clock domain is: A step of adjusting the initial phase of the analog domain clock signal based on the gating signal, The method includes the step of adjusting the initial phase of a clock signal in the digital domain based on the initial phase of a clock signal in the analog domain.

[0086] To clearly explain the technical means of the embodiments of this disclosure, the delayed calibration process according to the embodiments of this disclosure will be described in detail below with specific examples. The specific steps of the delayed calibration process are as follows:

[0087] 1. Depending on the actual chip's requirements, initiate TX and RX delay calibration after power-on.

[0088] 2. Depending on the product's application and operating scenario, the software initializes parameters such as pulse period, link settings, calibration initial values, and registers related to TX and RX channel linkage pulse generation and calibration.

[0089] 3. An air interface pulse signal is transmitted via a loop from an external source, a TX channel coupling pulse generator is used to directly generate the channel coupling pulse signal for the TX link, and an ADC calibration unit is used to generate the channel coupling pulse signal for the RX link through coarse delay calibration and fine delay calibration.

[0090] The ADC coarse delay calibration process involves the rising edge of the air interface pulse signal triggering a software ADC coarse delay calibration interrupt. The software then increments the delay by one beat each time until the logical AND result of the channel coupling pulse signal and the air interface pulse signal becomes 1, indicating that the coarse delay calibration is complete.

[0091] The ADC's precision delay calibration process involves the rising edge of the air interface pulse signal triggering a software ADC precision calibration interrupt. If the logical AND result of the channel coupling pulse signal and the air interface pulse signal is 0, the system continuously increases the beat delay by 1, performing precision delay compensation. If the count value is not 0, the software performs a process of turning clock gating off and on once, and performs phase adjustment until the count value equals a predetermined threshold, indicating that the precision delay calibration is complete.

[0092] 4. The TX and RX channel linkage pulse signals are transmitted across the link and reach the DAC calibration unit and the RX channel linkage pulse signal calibrator, respectively.

[0093] 5. Coarse delay calibration and precise delay calibration are performed sequentially within the DAC calibration unit, and coarse delay calibration is performed within the RX channel linked pulse calibrator.

[0094] The DAC coarse delay calibration process involves the rising edge of the channel co-operation pulse signal triggering a software DAC coarse delay calibration interrupt. After reading the counter value of the comparison module, a close delay value is set. Subsequently, the software increases the delay by 1 beat each time until the logical AND result of the channel co-operation pulse signal and the air interface pulse signal becomes 1, indicating that the coarse delay calibration is complete.

[0095] The DAC's precision delay calibration process involves the rising edge of the channel co-operation pulse signal triggering a software DAC precision delay calibration interrupt. If the logical AND result of the channel co-operation pulse signal and the air interface pulse signal is 0, the read address of the DAC clock domain crossing FIFO is incremented by 1 to adjust the channel co-operation pulse delay and perform precision delay compensation. If the count value is not 0, the software performs a process of turning clock gating off and on once, and performs phase adjustment until the count value equals a predetermined threshold, indicating that the precision delay calibration is complete. The coarse delay calibration within the RX channel co-operation pulse calibrator is the same as the DAC's coarse delay calibration process.

[0096] 6. Complete the delay calibration process, wait for the TX and RX links to perform delay detection calibration during the next normal operation process, and repeat steps 2-5.

[0097] This disclosure provides exemplary embodiments and uses specific terms, which are to be used and interpreted only in a general illustrative sense and not for limiting purposes. In some embodiments, as will be apparent to those skilled in the art, unless otherwise specified, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Thus, as will be understood to those skilled in the art, various forms and modifications of detail are possible without deviating from the scope of the invention as revealed by the appended claims.

Claims

1. A delay calibration apparatus including a delay calibration module, wherein the delay calibration module includes a coarse delay calibration unit and a precise delay calibration unit. The coarse delay calibration unit is configured to receive an air interface pulse signal and, based on the air interface pulse signal, perform delay compensation for the channel coupling pulse signal in the digital clock domain. The precision delay calibration unit includes a precision delay calibration subunit and a phase calibration subunit. The precision delay calibration subunit is configured such that, after the coarse delay calibration unit performs delay compensation on the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal, it then performs delay compensation on the channel coupling pulse signal in the analog clock domain. A delay calibration device in which the phase calibration subunit is configured to calibrate the phase of the clock domain after the precision delay calibration subunit has performed delay compensation on the channel coupling pulse signal in the analog clock domain.

2. The transmission link is further included, and the delay calibration module includes a first delay calibration module, the first delay calibration module is located on the transmission link, The coarse delay calibration unit is a first coarse delay calibration unit, the precise delay calibration unit is a first precise delay calibration unit, and the channel linkage pulse signal is a transmitted channel linkage pulse signal. The transmission link further includes a transmission channel linked pulse generation module and a transmission link channel linked pulse transmission module. The transmission channel linkage pulse generation module is configured to receive an air interface pulse signal and generate the transmission channel linkage pulse signal based on the air interface pulse signal. The transmit link channel coordinating pulse transmission module is configured to align and transmit the transmit channel coordinating pulse signal and link data within the multi-clock domain of the transmit link using a data enable signal, and / or transmit them to the first coarse delay calibration unit of the first delay calibration module, and / or The receiving link is further included, and the delay calibration module includes a second delay calibration module, the second delay calibration module is located in the receiving link, The channel linkage pulse signal is a received channel linkage pulse signal, the precision delay calibration unit is a second precision delay calibration unit, the coarse delay calibration unit is a second coarse delay calibration unit, and the second coarse delay calibration unit is further configured to generate the received channel linkage pulse signal based on the air interface pulse signal after receiving the air interface pulse signal. The receiving link further includes a receiving channel linked pulse calibration module and a receiving link channel linked pulse transmission module. The receiving link channel coordinating pulse transmission module is configured to align and transmit the receiving channel coordinating pulse signal and link data within the multi-clock domain of the receiving link using a data enable signal, and to transmit them to the receiving channel coordinating pulse calibration module. The delay calibration device according to claim 1, wherein the receiving channel coordinating pulse calibration module is configured to perform delay compensation on the channel coordinating pulse signal received in the digital clock domain based on the air interface pulse signal.

3. The second coarse delay calibration unit includes a second air interface pulse processing subunit, a second channel linked pulse signal regeneration subunit, a second delay subunit, and a second coarse delay calibration subunit. The second air interface pulse processing subunit is configured to generate a single-period air interface pulse signal based on the rising edge of the air interface pulse signal. The second channel linkage pulse signal regeneration subunit is connected to the second air interface pulse processing subunit and the second delay subunit, respectively, and is configured to generate a regenerated received channel linkage pulse signal by reducing the single-period air interface pulse signal transmitted from the second air interface pulse processing subunit by a predetermined multiple at the same ratio period, and to transmit the regenerated received channel linkage pulse signal to the second delay subunit. The second delay subunit is configured to remove the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal to acquire the second signal. The delay calibration device according to claim 2, wherein the second coarse delay calibration subunit is configured to perform a logical AND operation on the second signal and the single-period air interface pulse signal, and if the result of the operation is not 1, to perform coarse delay calibration, to stop the operation until the result of the operation is 1, and to generate a second instruction signal.

4. The second coarse delay calibration unit further includes a second extension subunit, The delay calibration apparatus according to claim 3, wherein the second extension subunit is connected to the second delay subunit and the second coarse delay calibration subunit, and is configured to extend the high-level length of the second signal according to one clock cycle and transmit the extended signal to the second coarse delay calibration subunit so that the second coarse delay calibration subunit performs a logical AND operation on the extended signal and the single-period air interface pulse signal.

5. The first coarse delay calibration unit includes a first air interface pulse processing subunit, a first delay subunit, and a first coarse delay calibration subunit. The first air interface pulse processing subunit is configured to generate a single-period air interface pulse signal based on the rising edge of the air interface pulse signal. The first delay subunit is configured to remove the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal to acquire the first signal. The delay calibration device according to claim 3, wherein the first coarse delay calibration subunit is configured to perform a logical AND operation on the first signal and the single-period air interface pulse signal, and if the result of the operation is not 1, to perform coarse delay calibration, to stop the operation until the result of the operation is 1, and to generate a first instruction signal.

6. The first coarse delay calibration unit further includes a comparison subunit, The comparison subunit is configured to calculate the time difference between the single-period air interface pulse signal and the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit, and to set the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal based on the time difference, or The first coarse delay calibration unit further includes a first air interface pulse signal regeneration subunit and a first channel linked pulse signal regeneration subunit, The first air interface pulse signal regeneration subunit is connected to the first air interface pulse processing subunit and the first coarse delay calibration subunit, and is configured to generate a regenerated air interface pulse signal by reducing the air interface pulse signal by a predetermined multiple at the same ratio period, and to transmit the regenerated air interface pulse signal to the first coarse delay calibration subunit. The first channel linkage pulse signal regeneration subunit is connected to the first delay subunit and is configured to generate a regenerated transmit channel linkage pulse signal by reducing the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit by a predetermined multiple at the same ratio period, and to transmit the regenerated transmit channel linkage pulse signal to the first delay subunit, thereby eliminating the delay between the regenerated transmit channel linkage pulse signal and the next air interface pulse signal, or The first coarse delay calibration unit further includes a first extension subunit, The delay calibration apparatus according to claim 5, wherein the first extension subunit is connected to the first delay subunit and the first coarse delay calibration subunit, and is configured to extend the high-level length of the first signal according to one clock cycle and transmit the extended signal to the first coarse delay calibration subunit so that the first coarse delay calibration subunit performs a logical AND operation on the extended signal and the single-period air interface pulse signal.

7. The first precision delay calibration unit and the second precision delay calibration unit each include a channel linkage pulse processing subunit, a decision subunit, an air interface pulse synchronization subunit, a channel linkage pulse synchronization subunit, a precision delay calibration subunit, and a precision delay calibration interrupt subunit. The channel coordinating pulse processing subunit is configured to receive a channel coordinating pulse signal transmitted from a coarse delay calibration unit in the delay calibration module in which it exists, generate a single-period channel coordinating pulse signal based on the rising edge of the channel coordinating pulse signal, and transmit the single-period channel coordinating pulse signal to the precision delay calibration interrupt subunit, wherein in the first precision delay calibration unit, the channel coordinating pulse signal is the first signal, and in the second precision delay calibration unit, the channel coordinating pulse signal is the second signal. The air interface pulse synchronization subunit is configured to synchronize the air interface pulse signal with the clock domain in which it resides, and to transmit the synchronized air interface pulse signal to the determination subunit. The channel linkage pulse synchronization subunit is configured to synchronize the channel linkage pulse signal with the clock domain in which it exists, and to transmit the synchronized channel linkage pulse signal to the decision subunit. The judgment subunit is configured to perform a logical AND operation on the synchronized air interface pulse signal and the synchronized channel linkage pulse signal. The precision delay calibration subunit is configured to perform precision delay calibration if the calculation result calculated by the decision subunit is 0. The delay calibration apparatus according to claim 5, wherein the precision delay calibration interrupt subunit is configured to trigger and generate an interrupt signal for stopping the precision delay calibration based on the single-period channel linkage pulse signal.

8. The precision delay calibration subunit of the first precision delay calibration unit is configured to adjust the delay of the transmission channel coupling pulse signal transmitted to the first coarse delay calibration unit by increasing the read address of the first-in, first-out memory of the clock domain crossing in the transmission link by one, or The delay calibration apparatus according to claim 7, wherein the precision delay calibration subunit of the second precision delay calibration unit is configured to adjust the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal.

9. The phase calibration subunit includes a differential pulse gating subunit and a clock frequency divider subunit. The differential pulse gating subunit is configured to adjust the initial phase of the analog domain clock signal based on the gating signal. The delay calibration apparatus according to any one of claims 1 to 8, wherein the clock frequency divider subunit is configured to adjust the initial phase of the clock signal in the digital domain based on the initial phase of the clock signal in the analog domain.

10. A delay calibration method applicable to the delay calibration apparatus according to any one of claims 1 to 8, The steps include receiving an air interface pulse signal and performing delay compensation for a channel linkage pulse signal in the digital clock domain based on the air interface pulse signal, A delay calibration method comprising the steps of performing delay compensation on the channel-coupling pulse signal in the analog clock domain and calibrating the phase of the clock domain.

11. In the transmission link, the step of performing delay compensation for the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal is: The steps include generating a transmit channel linkage pulse signal based on the aforementioned air interface pulse signal, Within the multi-clock domain of the transmission link, the steps include aligning and transmitting the transmission channel coordination pulse signal and link data using the data enable signal, The steps include and / or, performing delay compensation in the digital clock domain for the transmit channel coupling pulse signal based on the air interface pulse signal, In the receiving link, the step of performing delay compensation for the channel coupling pulse signal in the digital clock domain based on the air interface pulse signal is: The steps include generating a received channel linkage pulse signal based on the aforementioned air interface pulse signal, Within the multi-clock domain of the receiving link, the steps include aligning and transmitting the receiving channel coordination pulse signal and link data using the data enable signal, The delay calibration method according to claim 10, comprising the step of performing delay compensation on a received channel coordinating pulse signal that has been aligned and transmitted in the digital clock domain based on the air interface pulse signal.

12. The delay calibration apparatus described in claim 3, wherein the step of generating a received channel linkage pulse signal based on the air interface pulse signal is: The steps include: generating a single-period air interface pulse signal based on the rising edge of the air interface pulse signal, and generating a regenerated receiving channel linkage pulse signal by reducing the single-period air interface pulse signal by a predetermined multiple at the same ratio period; The step of performing delay compensation on a received channel-coordinated pulse signal that has been aligned and transmitted in the digital clock domain based on the aforementioned air interface pulse signal is: The steps include: removing the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal to obtain a second signal; The method according to claim 11, comprising the steps of performing a logical AND operation on the second signal and the single-period air interface pulse signal, performing a coarse delay calibration if the result of the operation is not 1, stopping the operation until the result of the operation is 1, and generating a second instruction signal.

13. Applicable to the delay calibration apparatus described in claim 4, after acquiring the second signal, and before performing a logical AND operation on the second signal and the single-period air interface pulse signal, the method is: The method according to claim 12, further comprising the steps of extending the high-level length of the second signal according to one clock cycle and performing a logical AND operation on the extended signal and the single-period air interface pulse signal; or, The delay calibration apparatus described in claim 5, which includes the step of performing delay compensation for a transmit channel coupling pulse signal in the digital clock domain based on the air interface pulse signal, The steps include generating a single-period air interface pulse signal based on the rising edge of the aforementioned air interface pulse signal, The steps include: obtaining a first signal by removing the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal; The method according to claim 12, comprising the steps of performing a logical AND operation on the first signal and the single-period air interface pulse signal, performing a coarse delay calibration if the result of the operation is not 1, stopping the operation until the result of the operation is 1, and generating a first instruction signal.

14. The delay calibration apparatus described in claim 6 is applied, and before removing the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method is: The method according to claim 13, further comprising the steps of calculating the time difference between the single-period air interface pulse signal and the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit, and setting the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal based on the time difference; or, The delay calibration apparatus described in claim 6 is applied, and before removing the delay between the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method is: The steps include generating a regenerated air interface pulse signal by reducing the aforementioned air interface pulse signal by a predetermined multiple with the same ratio period, The method according to claim 13, comprising the step of reducing the transmit channel linkage pulse signal transmitted to the first coarse delay calibration unit by a predetermined multiple at the same ratio period to generate a regenerated transmit channel linkage pulse signal, thereby eliminating the delay between the regenerated transmit channel linkage pulse signal and the next air interface pulse signal; or, The delay calibration apparatus described in claim 6 is applied, and before performing a logical AND operation on the first signal and the single-period air interface pulse signal, the method is: The method according to claim 13, further comprising the steps of extending the high-level length of the first signal according to one clock cycle and performing a logical AND operation on the extended signal and the single-period air interface pulse signal; or, The method is applied to the delay calibration apparatus described in claim 7, and after performing coarse delay calibration, A step of receiving a channel linkage pulse signal and generating a single-period channel linkage pulse signal based on the rising edge of the channel linkage pulse signal, wherein the channel linkage pulse signal is the first signal or the second signal. The steps include synchronizing the air interface pulse signal with the clock domain in which it resides, and synchronizing the channel linkage pulse signal with the clock domain in which it resides, The method according to claim 13, comprising the steps of performing a logical AND operation on the synchronized air interface pulse signal and the synchronized channel linkage pulse signal, and if the result of the operation is 0, performing a precise delay calibration, the step of triggering and generating an interrupt signal to stop the precise delay calibration based on the single-period channel linkage pulse signal.

15. The step of performing the aforementioned precise delay calibration is: The steps include: adjusting the delay of the transmission channel linkage pulse signal transmitted to the first coarse delay calibration unit by increasing the read address of the first-in, first-out memory of the clock domain crossing in the transmission link by one; The method according to claim 14, comprising the step of adjusting the delay between the regenerated receiving channel linkage pulse signal and the next air interface pulse signal.

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