Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device having a size that can be reduced, and a method for manufacturing such a semiconductor device.SOLUTION: A semiconductor device includes: a first nitride semiconductor layer having a first surface, and a first recess formed in the first surface; a second nitride semiconductor layer provided inside the first recess; a first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer, and having a first opening that is formed therein and exposes at least a portion of the second nitride semiconductor layer; and a wiring layer making ohmic contact with the second nitride semiconductor layer through the first opening. The second nitride semiconductor layer has a second surface opposing the wiring layer. A second recess that is continuous with the first opening is formed in the second surface. The wiring layer makes direct contact with the second nitride semiconductor layer at an inner surface of the second recess.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device including a high electron mobility transistor (HEMT) in which openings are formed in a barrier layer and a channel layer, and a gallium nitride (n-GaN) layer containing a high concentration of n-type impurities is provided in the openings is known. An electrode layer for ensuring ohmic contact is provided between the n-GaN layer and the wiring layer. The electrode layer has a laminate of a titanium (Ti) layer or a tantalum (Ta) layer and an aluminum (Al) layer. + GaN) layer is provided in the opening is known. An electrode layer for ensuring ohmic contact is provided between the n-GaN layer and the wiring layer. The electrode layer has a laminate of a titanium (Ti) layer or a tantalum (Ta) layer and an aluminum (Al) layer. + An electrode layer for ensuring ohmic contact is provided between the n-GaN layer and the wiring layer. The electrode layer has a laminate of a titanium (Ti) layer or a tantalum (Ta) layer and an aluminum (Al) layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for further miniaturization of semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device that can be miniaturized and a method of manufacturing the semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure includes a first nitride semiconductor layer having a first surface and having a first recess formed on the first surface, a second nitride semiconductor layer provided in the first recess, a first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer and having a first opening formed therein through which a part of the second nitride semiconductor layer is exposed, and a wiring layer making ohmic contact with the second nitride semiconductor layer through the first opening, wherein the second nitride semiconductor layer has a second surface facing the wiring layer, and a second recess connected to the first opening is formed on the second surface, and the wiring layer is in direct contact with the second nitride semiconductor layer on the inner surface of the second recess. [Effects of the Invention]

[0007] According to this disclosure, semiconductor devices can be miniaturized. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the layout of electrodes and pads in a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a semiconductor device according to the embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a semiconductor device according to the embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view (No. 6) showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 11] FIG. 11 is a cross-sectional view (No. 7) showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view (No. 8) showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 13] FIG. 13 is a cross-sectional view (No. 9) showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 14] FIG. 14 is a diagram showing a layout of electrodes and pads in a semiconductor device according to a reference example. [Figure 15] FIG. 15 is a cross-sectional view showing a semiconductor device according to a reference example.

Mode for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure][[ID=2�]] First, embodiments of the present disclosure will be listed and described.

[0010] 〔1〕 A semiconductor device according to one aspect of the present disclosure has a first surface, a first nitride semiconductor layer having a first recess formed in the first surface, a second nitride semiconductor layer provided in the first recess, a first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer and having a first opening formed therein through which a part of the second nitride semiconductor layer is exposed, and a wiring layer that makes an ohmic contact with the second nitride semiconductor layer through the first opening. The second nitride semiconductor layer has a second surface facing the wiring layer, and a second recess continuous with the first opening is formed in the second surface. The wiring layer directly contacts the second nitride semiconductor layer on the inner surface of the second recess.

[0011] When the first insulating film is formed with the first opening, local damage occurs in the second nitride semiconductor layer, but the damaged portion is removed as the second recess is formed. Therefore, a good ohmic contact can be obtained between the wiring layer and the second nitride semiconductor layer. Also, since no electrode layer or the like for ensuring ohmic contact is required between the second nitride semiconductor layer and the wiring layer, the margin can be reduced and the size can be miniaturized.

[0012] 〔2〕 In 〔1〕, the wiring layer may include a first metal layer that directly contacts the second nitride semiconductor layer on the side surface and the bottom surface of the second recess, and a second metal layer that is laminated on the first metal layer and has a lower electrical resistance than the first metal layer. In this case, while obtaining good adhesion between the wiring layer and the first insulating film, it is easy to obtain good conductivity for the wiring layer.

[0013] 〔3〕 In 〔2〕, the second metal layer may be a gold layer. In this case, it is particularly easy to obtain good conductivity.

[0014] 〔4〕 In 〔2〕 or 〔3〕, it has a passivation film that covers the wiring layer and in which a second opening is formed through which a part of the wiring layer is exposed, and the wiring layer may have the first metal layer and the second metal layer in a region overlapping the second opening in a plan view perpendicular to the first surface. In this case, it is easy to reduce the margin.

[0015] 〔5〕 In any one of 〔1〕 to 〔4〕, it may have a second insulating film provided between the first nitride semiconductor layer and the first insulating film and in which a third opening is formed through which the first recess is exposed. In this case, it is easy to protect the first nitride semiconductor layer with the second insulating film.

[0016] 〔6〕 In any one of 〔1〕 to 〔5〕, the carrier density in the second nitride semiconductor layer may be higher than the carrier density in the first nitride semiconductor layer. In this case, it is easy to reduce the electrical resistance.

[0017] [7] In any of [1] to [6], a gate electrode may be provided between the first nitride semiconductor layer and the first insulating film. In this case, the potential of the channel region included in the first nitride semiconductor layer can be controlled by the gate electrode.

[0018] [8] In any of [1] to [7], the depth of the second recess may be 5 nm or more and 50 nm or less. In this case, it is easier to remove the damaged portion and to shorten the processing time for forming the second recess.

[0019] [9] A method for manufacturing a semiconductor device according to another aspect of the present disclosure comprises the steps of: forming a first recess on the first surface of a first nitride semiconductor layer having a first surface; forming a second nitride semiconductor layer in the first recess; forming a first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer; forming a first opening in the first insulating film through which a part of the second nitride semiconductor layer is exposed; and forming a wiring layer that makes ohmic contact with the second nitride semiconductor layer through the first opening, wherein the second nitride semiconductor layer has a second surface facing the wiring layer, and between the step of forming the first opening and the step of forming the wiring layer, there is a step of forming a second recess on the second surface that is connected to the first opening, and the wiring layer is in direct contact with the second nitride semiconductor layer on the side and bottom surfaces of the second recess.

[0020] When the first aperture is formed in the first insulating film, localized damage occurs in the second nitride semiconductor layer, but the damaged portion is removed as the second recess is formed. As a result, good ohmic contact is obtained between the wiring layer and the second nitride semiconductor layer. Furthermore, since an electrode layer or the like is not required to ensure ohmic contact between the second nitride semiconductor layer and the wiring layer, the margin can be reduced and the device can be miniaturized.

[0021]

[10] In [9], the step of forming the second recess may include the steps of forming an oxide layer on the portion of the second surface exposed from the first opening and removing the oxide layer. In this case, the damaged portion is easier to remove.

[0022] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In the following description, the XYZ Cartesian coordinate system will be used, but this coordinate system is defined for illustrative purposes only and is not limited to the orientation of the semiconductor device. Also, from any point, the +Z side may be referred to as up, upper, or top, and the -Z side may be referred to as down, lower, or bottom.

[0023] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a diagram showing the layout of electrodes and pads in the semiconductor device according to the embodiment. Figures 2 to 4 are cross-sectional views showing the semiconductor device according to the embodiment. Figure 2 corresponds to a cross-sectional view along line II-II in Figure 1, Figure 3 corresponds to a cross-sectional view along line III-III in Figure 1, and Figure 4 corresponds to a cross-sectional view along line IV-IV in Figure 1.

[0024] As shown in Figures 1 to 4, the semiconductor device 100 according to the embodiment includes a substrate 10 and a laminated structure 21. The substrate 10 is, for example, a silicon carbide (SiC) substrate having a (0001) plane, and the stacking direction of the laminated structure 21 is, for example, the

[0001] direction. The laminated structure 21 is provided on the substrate 10. The laminated structure 21 includes a nucleation layer 11, a channel layer 12, a barrier layer 13, and a cap layer 14. The laminated structure 21 is an example of a first nitride semiconductor layer.

[0025] The nucleation layer 11 is formed on the substrate 10. For example, the nucleation layer 11 is an aluminum nitride (AlN) layer, and its thickness is between 5 nm and 20 nm. The nucleation layer 11 functions as a seed layer for the channel layer 12.

[0026] The channel layer 12 is formed on the nucleation layer 11 by epitaxial growth. For example, the channel layer 12 is an undoped gallium nitride (GaN) layer, and its thickness is 500 nm. The channel layer 12 functions as an electron transport layer.

[0027] The barrier layer 13 is formed on the channel layer 12 by epitaxial growth. For example, the barrier layer 13 is an aluminum gallium nitride (AlGaN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer. The thickness of the barrier layer 13 is, for example, 5 nm to 30 nm. The band gap of the barrier layer 13 is larger than the band gap of the channel layer 12. If the barrier layer 13 is an AlGaN layer, the Al composition of the barrier layer 13 is, for example, 0.15 to 0.35. The conductivity type of the barrier layer 13 is n-type or undoped. The barrier layer 13 and the channel layer 12 may be in contact with each other, or a spacer layer (not shown) may be interposed between the barrier layer 13 and the channel layer 12. Distortion occurs between the barrier layer 13 and the channel layer 12 due to the difference in their lattice constants. Therefore, a two-dimensional electron gas (2DEG) 15 originating from piezoelectric charge is generated in the vicinity of the interface between the barrier layer 13 and the channel layer 12, in the region on the channel layer 12 side, and a channel region is formed. The barrier layer 13 functions as an electron supply layer.

[0028] The cap layer 14 is formed on the barrier layer 13 by epitaxial growth. For example, the cap layer 14 is a GaN layer, and its thickness is 5 nm. For example, the conductivity type of the cap layer 14 is n-type.

[0029] The laminated structure 21 has a first surface 1. The first surface 1 is the top surface of the laminated structure 21. The cap layer 14 constitutes the first surface 1. A plurality of recesses 41S and a plurality of recesses 41D are formed on the first surface 1. The recesses 41S and 41D extend parallel to the Y-axis direction and are arranged alternately in the X-axis direction. The recesses 41S and 41D penetrate the cap layer 14 and the barrier layer 13 and reach the channel layer 12. The bottom surfaces of the recesses 41S and 41D are in the channel layer 12. The bottom surfaces of the recesses 41S and 41D are located deeper than 2DEG15. The recesses 41S and 41D are examples of first recesses.

[0030] The semiconductor device 100 has an insulating film 32. The insulating film 32 covers the laminated structure 21. For example, the insulating film 32 is a nitride film such as a silicon nitride (SiN) film, and the thickness of the insulating film 32 is 10 nm or more and 100 nm or less. Multiple openings 53S, multiple openings 53D, and multiple openings 53G are formed in the insulating film 32. The openings 53S, 53D, and 53G extend parallel to the Y-axis direction. The openings 53S and 53D are connected to the recesses 41S and 53D, respectively. The opening 53G is provided between adjacent openings 53S and 53D in the X-axis direction. The insulating film 32 is an example of a second insulating film. The openings 53S and 53D are examples of a third opening.

[0031] The semiconductor device 100 has semiconductor layers 22S and 22D. Semiconductor layer 22S is provided in recess 41S, and semiconductor layer 22D is provided in recess 41D. Part of semiconductor layer 22S may be inside the opening 53S, and part of semiconductor layer 22D may be inside the opening 53D. For example, semiconductor layers 22S and 22D are n-type GaN layers. Semiconductor layers 22S and 22D contain n-type impurities at a higher concentration than the barrier layer 13. The carrier density in semiconductor layers 22S and 22D is higher than the carrier density in the stacked structure 21. The carrier density in semiconductor layers 22S and 22D is 2 × 10⁻⁶ 20 cm -3 The carrier's mobility is 20cm. 2 The value is greater than or equal to / Vs. Semiconductor layers 22S and 22D are examples of second nitride semiconductor layers.

[0032] The semiconductor layer 22S has a second surface 2S. The second surface 2S is the upper surface of the semiconductor layer 22S. A recess 42S is formed on the second surface 2S. The recess 42S is formed inside the opening 53S. The depth of the recess 42S is, for example, 5 nm to 50 nm. The semiconductor layer 22D has a second surface 2D. The second surface 2D is the upper surface of the semiconductor layer 22D. A recess 42D is formed on the second surface 2D. The recess 42D is formed inside the opening 53D. The depth of the recess 42D is, for example, 5 nm to 50 nm. Recesses 42S and 42D are examples of second recesses.

[0033] The semiconductor device 100 has a gate electrode 61G. The gate electrode 61G covers an opening 53G in the insulating film 32 and is in Schottky contact with the cap layer 14 through the opening 53G. The gate electrode 61G has, for example, nickel (Ni) layers, palladium (Pd) layers and gold (Au) layers stacked in order from upward.

[0034] The semiconductor device 100 has an insulating film 31. The insulating film 31 covers the gate electrode 61G, the insulating film 32, the semiconductor layer 22S, and the semiconductor layer 22D. The insulating film 31 covers the laminated structure 21 from above the gate electrode 61G and the insulating film 32. For example, the insulating film 31 is a nitride film such as a SiN film, and the thickness of the insulating film 31 is 10 nm or more and 50 nm or less. Multiple openings 51S and multiple openings 51D are formed in the insulating film 31. The openings 51S and 51D extend parallel to the Y axis. The openings 51S reach the semiconductor layer 22S, and the openings 51D reach the semiconductor layer 22D. In a plan view perpendicular to the first surface 1, the openings 51S are inside the openings 53S, and the openings 51D are inside the openings 53D. The recesses 42S and 42D are connected to the openings 51S and 51D, respectively. A portion of the semiconductor layer 22S is exposed through the opening 51S, and a portion of the semiconductor layer 22D is exposed through the opening 51D. The insulating film 31 is an example of the first insulating film. The openings 51S and 51D are examples of the first openings.

[0035] The semiconductor device 100 has a wiring layer 60S, a wiring layer 60D, and a wiring layer 60G.

[0036] As shown in Figure 1, the wiring layer 60S has a plurality of local wiring regions 71S, a global wiring region 72S, and a pad region 73S. The local wiring regions 71S extend parallel to the Y-axis direction. The local wiring regions 71S make ohmic contact with the semiconductor layer 22S through the opening 51S. The global wiring region 72S extends in the X-axis direction. The global wiring region 72S is connected to the +Y side end of each local wiring region 71S. The pad region 73S extends in the Y-axis direction. The pad region 73S is connected to the -X side end of the global wiring region 72S.

[0037] The wiring layer 60S has a seed layer 61S and a plating layer 62S in each of the multiple local wiring regions 71S, global wiring regions 72S, and pad regions 73S. For example, the seed layer 61S has a titanium (Ti) layer, and the thickness of the seed layer 61S is 50 nm to 300 nm. For example, the plating layer 62S has a gold (Au) layer, and the thickness of the plating layer 62S is 1000 nm to 9000 nm. The electrical resistance of the plating layer 62S is lower than that of the seed layer 61S. The second surface 2S of the semiconductor layer 22S faces the local wiring region 71S. The local wiring region 71S is in direct contact with the semiconductor layer 22S on the inner surface of the recess 42S, that is, on the side and bottom surfaces of the recess 42S. The seed layer 61S is in direct contact with the inner surface of the recess 42S, the inner surface of the opening 51S, and the upper surface of the insulating film 31. The plating layer 62S is provided on top of the seed layer 61S. The seed layer 61S is an example of a first metal layer, and the plating layer 62S is an example of a second metal layer. The types of metal layers included in the local wiring region 71S, the global wiring region 72S, and the pad region 73S may all be the same.

[0038] As shown in Figure 1, the wiring layer 60D has a plurality of local wiring regions 71D and pad regions 73D. The local wiring regions 71D extend parallel to the Y-axis direction. The local wiring regions 71D make ohmic contact with the semiconductor layer 22D through the opening 51D. The pad regions 73D extend in the X-axis direction. The pad regions 73D are connected to the -Y-side end of each local wiring region 71D.

[0039] The wiring layer 60D has a seed layer 61D and a plating layer 62D in each of the multiple local wiring regions 71D and pad regions 73D. For example, the seed layer 61D has a Ti layer, and the thickness of the seed layer 61D is 50 nm to 300 nm. For example, the plating layer 62D has an Au layer, and the thickness of the plating layer 62D is 1000 nm to 9000 nm. The electrical resistance of the plating layer 62D is lower than that of the seed layer 61D. The second surface 2D of the semiconductor layer 22D faces the local wiring region 71D. The local wiring region 71D is in direct contact with the semiconductor layer 22D on the inner surface of the recess 42D, that is, on the side and bottom surfaces of the recess 42D. The seed layer 61D is in direct contact with the inner surface of the recess 42D, the inner surface of the opening 51D, and the upper surface of the insulating film 31. The plating layer 62D is provided on top of the seed layer 61D. The seed layer 61D is an example of a first metal layer, and the plating layer 62D is an example of a second metal layer. The type of metal layer included in the local wiring area 71D and the type of metal layer included in the pad area 73D may be the same.

[0040] As shown in Figure 1, the wiring layer 60G extends in the X-axis direction. The wiring layer 60G is located on the +Y side of the global wiring region 72S of the wiring layer 60S. Like the wiring layers 60S and 60D, the wiring layer 60G has a seed layer and a plating layer (not shown). An opening (not shown) is formed in the insulating film 31 above the +Y side end of the gate electrode 61G, and the wiring layer 60G directly contacts the gate electrode 61G through this opening.

[0041] The semiconductor device 100 has a passivation film 33. The passivation film 33 covers the wiring layers 60S, 60D, and 60G and the insulating film 31. As shown in Figure 3, an opening 52S is formed in the passivation film 33 that exposes a portion of the pad region 73S of the wiring layer 60S. A bonding wire 74S is connected to the portion of the pad region 73S exposed from the opening 52S. As shown in Figure 4, an opening 52D is formed in the passivation film 33 that exposes a portion of the pad region 73D of the wiring layer 60D. A bonding wire 74D is connected to the portion of the pad region 73D exposed from the opening 52D. An opening (not shown) is formed in the passivation film 33 that exposes a portion of the wiring layer 60G. A bonding wire (not shown) is connected to the portion of the wiring layer 60G exposed from the opening. The wiring layer 60G can function as a pad region. Openings 52S and 52D are examples of second openings.

[0042] The wiring layer 60S has a seed layer 61S and a plating layer 62S in the region that overlaps with the opening 52S in a plan view perpendicular to the first surface 1. The wiring layer 60S also has a seed layer 61S and a plating layer 62S in the region that overlaps with the recess 42S in a plan view perpendicular to the first surface 1. The wiring layer 60D has a seed layer 61D and a plating layer 62D in the region that overlaps with the opening 52D in a plan view perpendicular to the first surface 1. The wiring layer 60D also has a seed layer 61D and a plating layer 62D in the region that overlaps with the recess 42D in a plan view perpendicular to the first surface 1.

[0043] Next, a method for manufacturing the semiconductor device 100 according to the embodiment will be described. Figures 5 to 13 are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment. Figures 5 to 13 show the changes in the cross-section shown in Figure 2.

[0044] First, as shown in Figure 5, a laminated structure 21 containing multiple nitride semiconductor layers is formed on a substrate 10 using metal-organic chemical vapor deposition (MOCVD). Specifically, first, a nucleation layer 11 is grown on the substrate 10. If the nucleation layer 11 is an AlN layer, the source gases are, for example, TMA (trimethylaluminum) and NH3 (ammonia). Next, a channel layer 12 is grown on the nucleation layer 11. If the channel layer 12 is a GaN layer, the source gases are, for example, TMG (trimethylgallium) and NH3. Subsequently, a barrier layer 13 is grown on the channel layer 12. If the barrier layer 13 is an AlGaN layer, the source gases are, for example, TMA, TMG, and NH3. Subsequently, a cap layer 14 is grown on the barrier layer 13. If the cap layer 14 is a GaN layer, the source gases are, for example, TMG and NH3.

[0045] Next, an insulating film 32 is formed that is in contact with the first surface 1 of the laminated structure 21. The insulating film 32 is formed, for example, by a reduced-pressure CVD method or a plasma CVD method.

[0046] Next, as shown in Figure 6, openings 53S and 53D are formed in the insulating film 32, and recesses 41S and 41D are formed in the laminated structure 21. For the formation of the openings 53S and 53D, reactive ion etching (RIE) of the insulating film 32 is performed, for example, using a resist pattern as a mask. For the RIE of the insulating film 32, a reactive gas containing fluorine (F), for example, is used. For the formation of the recesses 41S and 41D, RIE of the laminated structure 21 is performed, using the resist pattern used to form the openings 53S and 53D as a mask. For the RIE of the laminated structure 21, a reactive gas containing chlorine (Cl), for example, is used.

[0047] Next, as shown in Figure 7, a semiconductor layer 22S is formed in the recess 41S and a semiconductor layer 22D is formed in the recess 41D. For the formation of semiconductor layers 22S and 22D, for example, crystal growth of the semiconductor layer is performed using MOCVD, molecular beam epitaxy (MBE), or sputtering with a growth mask, and then the growth mask is removed.

[0048] Next, as shown in Figure 8, an opening 53G is formed in the insulating film 32. For the formation of the opening 53G, for example, RIE is performed using a resist pattern as a mask. For etching the insulating film 32, for example, a reactive gas containing F is used. Next, a gate electrode 61G is formed on the insulating film 32. The gate electrode 61G can be formed, for example, by evaporation and lift-off. The gate electrode 61G makes Schottky contact with the cap layer 14 through the opening 53G. Next, an insulating film 31 is formed to cover the gate electrode 61G, the insulating film 32, the semiconductor layer 22S, and the semiconductor layer 22D. The insulating film 31 can be formed, for example, by plasma CVD.

[0049] Next, as shown in Figure 9, a resist pattern 90 is formed on the insulating film 31. Openings 91S and 91D are formed in the resist pattern 90. The region forming the opening 51S of the insulating film 31 is exposed from the opening 91S, and the region forming the opening 51D of the insulating film 31 is exposed from the opening 91D. Next, RIE is performed on the insulating film 31 using the resist pattern 90 as a mask. For the RIE of the insulating film 31, a reactive gas containing F, such as carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6), is used. At this time, inevitably, a damaged layer 81S is formed in the portion of the semiconductor layer 22S exposed from the opening 51S due to RIE damage, and a damaged layer 81D is formed in the portion of the semiconductor layer 22D exposed from the opening 51D due to RIE damage.

[0050] Next, as shown in Figure 10, the resist pattern 90 is removed. Then, the portion of the semiconductor layer 22S containing the damaged layer 81S is oxidized to form an oxide layer 82S, and the portion of the semiconductor layer 22D containing the damaged layer 81D is oxidized to form an oxide layer 82D. For the formation of oxide layers 82S and 82D, for example, strong ashing is performed using an oxygen plasma with an output of about 1000W. Because the crystal structure is disordered within the damaged layers 81S and 81D, the damaged layers 81S and 81D are more easily oxidized than the rest of the semiconductor layers 22S and 22D. Note that the removal of the resist pattern 90 may be performed after the formation of oxide layers 82S and 82D.

[0051] Next, as shown in Figure 11, the oxide layers 82S and 82D are removed. The oxide layers 82S and 82D can be removed, for example, by wet etching using an alkaline etchant. The wet etching time is, for example, 1 to 5 minutes. As the alkaline etchant, for example, a solution containing potassium hydroxide (KOH) or ammonium hydroxide (ammonia water, NH4OH) can be used. The oxide layers 82S and 82D may also be removed by wet etching using an acidic etchant. After the removal of the oxide layers 82S and 82D, when the semiconductor layers 22S and 22D are exposed to the atmosphere, a native oxide film 83S may be formed on the surface of semiconductor layer 22S, and a native oxide film 83D may be formed on the surface of semiconductor layer 22D. The thickness of the native oxide films 83S and 83D is about 1 nm to several nm. The native oxide films 83S and 83D contain, for example, gallium oxide.

[0052] Next, as shown in Figure 12, the native oxide films 83S and 83D are removed to form the wiring layers 60S and 60D. The native oxide films 83S and 83D are removed by milling, such as argon (Ar) milling, or by wet etching using an acidic solution such as dilute hydrochloric acid. Both milling and wet etching may be performed. The wiring layers 60S and 60D can be formed, for example, by a semi-additive method as described below. That is, a seed layer is formed to cover the surfaces of the semiconductor layer 22S, the semiconductor layer 22D, and the insulating film 31, a resist mask having openings in the region where the plating layers 62S and 62D are to be formed is formed, and the plating layers are formed. The seed layer can be formed, for example, by vapor deposition or sputtering. The plating layer can be formed, for example, by electroplating. After the formation of the plating layers, the resist mask is removed, and the seed layer that was covered by the resist mask is removed. In this way, a wiring layer 60S having a seed layer 61S and a plating layer 62S, and a wiring layer 60D having a seed layer 61D and a plating layer 62D are formed.

[0053] In addition, an opening that exposes the gate electrode 61G may be formed in the insulating film 31 simultaneously with the openings 51S and 51D, or a wiring layer 60G that is in contact with the gate electrode 61G may be formed simultaneously with the wiring layer 60S and wiring layer 60D (see Figure 1).

[0054] Next, as shown in Figure 13, a passivation film 33 is formed to cover the wiring layers 60S, 60D, and 60G and the insulating film 31. The passivation film 33 can be formed, for example, by plasma CVD. Next, an opening 52S (see Figure 3) that exposes a part of the pad region 73S of the wiring layer 60S, an opening 52D (see Figure 4) that exposes a part of the pad region 73D of the wiring layer 60D, and an opening (not shown) that exposes a part of the wiring layer 60G are formed in the passivation film 33.

[0055] In this way, the semiconductor device 100 according to the embodiment can be manufactured.

[0056] In the semiconductor device 100, when an opening 51S is formed in the insulating film 31, a localized damage layer 81S is formed in the semiconductor layer 22S. However, the damage layer 81S is removed, and a recess 41S is formed in the semiconductor layer 22S. As a result, good ohmic contact is obtained between the wiring layer 60S and the semiconductor layer 22S. Also, when an opening 51D is formed in the insulating film 31, a localized damage layer 81D is formed in the semiconductor layer 22D. However, the damage layer 81D is removed, and a recess 41D is formed in the semiconductor layer 22D. As a result, good ohmic contact is obtained between the wiring layer 60D and the semiconductor layer 22D.

[0057] Furthermore, since good ohmic contact is obtained between the wiring layers 60S and 60D and the semiconductor layers 22S and 22D, the margin between the semiconductor layers 22S and 22D and the wiring layers 60S and 60D can be reduced compared to the reference example below.

[0058] Here, a reference example for comparison with the embodiment will be described. Figure 14 is a diagram showing the layout of electrodes and pads in a semiconductor device according to the reference example. Figure 15 is a cross-sectional view showing the semiconductor device according to the reference example. Figure 15 corresponds to a cross-sectional view along the line XV-XV in Figure 14. Note that Figures 14 and 15 are diagrams showing reference examples and not diagrams showing prior art.

[0059] As shown in Figures 14 and 15, the semiconductor device 100X according to the reference example has, in addition to the configuration of the semiconductor device 100, electrode layers 66S and 66D and barrier metal layers 67S and 67D.

[0060] In the semiconductor layer 22S, no recess 41S is formed on the second surface 2S, an electrode layer 66S is provided on the second surface 2S, and a barrier metal layer 67S is provided on the electrode layer 66S. In a plan view perpendicular to the first surface 1, the edge of the electrode layer 66S is inside the edge of the semiconductor layer 22S, and the edge of the barrier metal layer 67S is inside the edge of the electrode layer 66S. In the semiconductor layer 22D, no recess 41D is formed on the second surface 2D, an electrode layer 66D is provided on the second surface 2D, and a barrier metal layer 67D is provided on the electrode layer 66D. In a plan view perpendicular to the first surface 1, the edge of the electrode layer 66D is inside the edge of the semiconductor layer 22D, and the edge of the barrier metal layer 67D is inside the edge of the electrode layer 66D. The electrode layers 66S and 66D have a laminated film of a titanium (Ti) layer or a tantalum (Ta) layer and an aluminum (Al) layer. The barrier metal layers 67S and 67D have a titanium (Ti) layer, a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, or a titanium tungsten nitride (TiWN) layer.

[0061] The insulating film 31 covers not only the gate electrode 61G, the insulating film 32, the semiconductor layer 22S, and the semiconductor layer 22D, but also the electrode layer 66S, the electrode layer 66D, the barrier metal layer 67S, and the barrier metal layer 67D. The opening 51S reaches the barrier metal layer 67S, and the opening 51D reaches the barrier metal layer 67D.

[0062] Thus, in the semiconductor device 100X according to the reference example, there is an electrode layer 66S and a barrier metal layer 67S between the semiconductor layer 22S and the wiring layer 60S, and there is an electrode layer 66D and a barrier metal layer 67D between the semiconductor layer 22D and the wiring layer 60D. For this reason, a margin is required between the semiconductor layer 22S and the electrode layer 66S, a margin is required between the electrode layer 66S and the barrier metal layer 67S, and a margin is required between the barrier metal layer 67S and the wiring layer 60S. Similarly, a margin is required between the semiconductor layer 22D and the wiring layer 60D, a margin is required between the semiconductor layer 22D and the electrode layer 66D, a margin is required between the electrode layer 66D and the barrier metal layer 67D, and a margin is required between the barrier metal layer 67D and the wiring layer 60D.

[0063] According to the semiconductor device 100 of this embodiment, the margin between the semiconductor layers 22S and 22D and the wiring layers 60S and 60D can be reduced compared to the semiconductor device 100X of the reference example. As a result, the spacing between adjacent gate electrodes 61G in the X-axis direction can be reduced, enabling miniaturization. Furthermore, since the semiconductor device 100 does not include electrode layers 66S and 66D, barrier metal layers 67S and 67D, the contact resistance between dissimilar materials can be reduced.

[0064] Furthermore, in the manufacturing process of semiconductor device 100X, heat treatment is performed at a temperature of 500°C to 800°C after the formation of electrode layers 66S and 66D in order to ensure ohmic contact between electrode layer 66S and semiconductor layer 22S, and between electrode layer 66D and semiconductor layer 22D. During this heat treatment, the Schottky properties of the gate electrode 61G may change. In contrast, in the manufacturing process of semiconductor device 100, no heat treatment is performed that may change the Schottky properties of the gate electrode 61G. Therefore, with semiconductor device 100, stable properties are more easily obtained.

[0065] The wiring layer 60S has a seed layer 61S and a plating layer 62S, and the wiring layer 60D has a seed layer 61D and a plating layer 62D. The seed layers 61S and 61D provide good adhesion between the wiring layers 60S and 60D and the insulating film 31. In addition, since the electrical resistance of the plating layers 62S and 62D is lower than that of the seed layers 61S and 61D, good conductivity is easily obtained in the wiring layers 60S and 60D. When the plating layers 62S and 62D are Au layers, particularly good conductivity is easily obtained.

[0066] In the region where the wiring layer 60S overlaps with the opening 52S in a plan view perpendicular to the first surface 1, it has a seed layer 61S and a plating layer 62S. That is, the type of metal layer included in the local wiring region 71S and the type of metal layer included in the pad region 73S are the same. Also, in the region where the wiring layer 60D overlaps with the opening 52D in a plan view perpendicular to the first surface 1, it has a seed layer 61D and a plating layer 62D. That is, the type of metal layer included in the local wiring region 71D and the type of metal layer included in the pad region 73D are the same. Therefore, it is easy to reduce the margin.

[0067] In addition to the insulating film 31, an insulating film 32 is provided, making it easier to protect the laminated structure 21 with the insulating film 32.

[0068] Because the carrier density in semiconductor layers 22S and 22D is higher than the carrier density in the multilayer structure 21, the electrical resistance of the semiconductor device 100 can be easily reduced. Specifically, the electrical resistance between wiring layer 60S and wiring layer 60D can be easily reduced. In addition, the gate electrode 61G can control the potential of the channel region included in the multilayer structure 21.

[0069] The depth of the recesses 42S and 42D is not particularly limited. The depth of the recesses 42S and 42D may be, for example, 5 nm or more and 50 nm or less, or 10 nm or more and 40 nm or less. If the depth of the recesses 42S and 42D is 5 nm or more, it is easier to eliminate the damaged layers 81S and 81D. If the depth of the recesses 42S and 42D is 10 nm or more, it is even easier to eliminate the damaged layers 81S and 81D. If the depth of the recesses 42S and 42D is 50 nm or less, it is easier to shorten the processing time for forming the recesses 42S and 42D. If the depth of the recesses 42S and 42D is 40 nm or less, it is even easier to shorten the processing time for forming the recesses 42S and 42D.

[0070] Furthermore, the seed layers 61S and 61D may include an Au layer in addition to the bottom Ti layer, provided on top of the Ti layer. Also, the seed layers 61S and 61D may include a titanium-tungsten (TiW) layer, a Ti layer, and an Au layer provided in order on top of the Ti layer, in addition to the bottom Ti layer. The plating layers 62S and 62D may have a copper (Cu) layer instead of an Au layer.

[0071] Furthermore, the second metal layer does not have to be a plating layer, and the first metal layer does not have to be a seed layer. For example, the second metal layer may be formed by a vapor deposition method.

[0072] The configuration of the semiconductor layers included in the stacked structure 21 is not limited to that of the above embodiment. For example, the barrier layer 13 may be located between the channel layer 12 and the substrate 10. In other words, a so-called inverse HEMT structure may be employed. Also, for example, the cap layer 14 may not be included.

[0073] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]

[0074] 1: Front page 2D, 2S: 2nd side 10: Circuit board 11: Nucleation layer 12: Channel Layer 13: Barrier layer 14: Cap layer 15: Two-dimensional electron gas (2DEG) 21: Laminated Structure 22D, 22S: Semiconductor layer 31, 32: Insulating film 33: Passivation membrane 41D, 41S, 42D, 42S: Recessed 51D, 51S, 52D, 52S, 53D, 53G, 53S: Opening 60D, 60G, 60S: Wiring layer 61D, 61S: Seed layer 61G: Gate stop gate 62D, 62S: Plating layer 66D, 66S: Electrode layer 67D, 67S: Barrier metal layer 71D, 71S: Local wiring area 72S: Global wiring area 73D, 73S: Pad area 74D, 74S: Bonding wires 81D, 81S: Damage Layer 82D, 82S: Oxide layer 83D, 83S: Natural oxide film 90: Resist Pattern 91D, 91S: Opening 100, 100X: Semiconductor device

Claims

1. A first nitride semiconductor layer having a first surface and having a first recess formed on the first surface, The second nitride semiconductor layer provided in the first recess, A first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer, having a first opening formed therein in which a part of the second nitride semiconductor layer is exposed, A wiring layer that makes ohmic contact with the second nitride semiconductor layer through the first opening, It has, The second nitride semiconductor layer has a second surface facing the wiring layer, The second surface has a second recess formed therein that is connected to the first opening. The wiring layer is in direct contact with the second nitride semiconductor layer on the inner surface of the second recess, in a semiconductor device.

2. The aforementioned wiring layer is A first metal layer that is in direct contact with the second nitride semiconductor layer on the side and bottom surfaces of the second recess, A second metal layer is laminated on the first metal layer and has lower electrical resistance than the first metal layer, A semiconductor device according to claim 1, having the following features.

3. The semiconductor device according to claim 2, wherein the second metal layer is a gold layer.

4. The passivation film covers the wiring layer and has a second opening formed therein in which a part of the wiring layer is exposed, The semiconductor device according to claim 2 or 3, wherein the wiring layer has the first metal layer and the second metal layer in a region that overlaps with the second opening in a plan view perpendicular to the first surface.

5. A semiconductor device according to any one of claims 1 to 3, comprising a second insulating film provided between the first nitride semiconductor layer and the first insulating film, having a third opening formed therein that exposes the first recess.

6. The semiconductor device according to any one of claims 1 to 3, wherein the carrier density in the second nitride semiconductor layer is higher than the carrier density in the first nitride semiconductor layer.

7. A semiconductor device according to any one of claims 1 to 3, having a gate electrode provided between the first nitride semiconductor layer and the first insulating film.

8. The semiconductor device according to any one of claims 1 to 3, wherein the depth of the second recess is 5 nm or more and 50 nm or less.

9. A step of forming a first recess on the first surface of a first nitride semiconductor layer having a first surface, The process involves forming a second nitride semiconductor layer in the first recess, A step of forming a first insulating film covering the first nitride semiconductor layer and the second nitride semiconductor layer, The process involves forming a first opening in the first insulating film in which a portion of the second nitride semiconductor layer is exposed, A step of forming a wiring layer that makes ohmic contact with the second nitride semiconductor layer through the first opening, It has, The second nitride semiconductor layer has a second surface facing the wiring layer, Between the step of forming the first opening and the step of forming the wiring layer, there is a step of forming a second recess on the second surface that is connected to the first opening. A method for manufacturing a semiconductor device, wherein the wiring layer is in direct contact with the second nitride semiconductor layer at the side and bottom surfaces of the second recess.

10. The process of forming the two recesses described above is: A step of forming an oxide layer on the portion of the second surface exposed from the first opening, The step of removing the aforementioned oxide layer, A method for manufacturing a semiconductor device according to claim 9, comprising:

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