Low-power clock drive

Abstract

A clock driver circuit for low power clocking can include a multi-phase divider and a buffer that supplies at least one of a plurality of phases to the multi-phase divider at a center frequency that is an integer multiple of an input frequency, where the multi-phase divider and the buffer share the same current from a power supply rail.

Description

Technical Field

[0001] The field of the present invention is data processing, and more specifically, methods, apparatuses, and products for low-power clock driving.

Background Art

[0002] The development of the EDVAC computer system in 1948 is often cited as the beginning of the computer era. Since then, computer systems have evolved into very complex devices. Today's computers are much more sophisticated than early systems such as EDVAC. Computer systems typically include combinations of hardware and software components, application programs, operating systems, processors, buses, memories, input / output devices, and the like. With the progress of semiconductor processing and computer architecture, the performance of computers has become increasingly higher, and more sophisticated computer software has evolved to utilize the high performance of hardware, and today's computer systems are much more powerful than a few years ago.

[0003] Low-power arrays are used in various devices including memory arrays, sensor arrays, quantum computing, antenna arrays, and the like. In most low-power arrays, it is necessary to simultaneously transmit a clock to each array element so that the uncorrelated jitter between the array elements is minimized. Since an array can include a large number of elements (e.g., more than 1000), a low-power clocking solution is essential to allocate most of the power consumption to signal processing.

[0004] Larger arrays require longer clock distribution paths and generally need to be driven by wide-band drivers, thus consuming several milliwatts (mW) of power. The wide-band drivers need to supply rectangular-wave pulses and, in most cases, require duty cycle correction, thus consuming a large amount of power. Such additional blocks result in a trade-off reduction in the dynamic range per mW metric. Existing solutions use an H-tree layout for clocking an array with clock receivers associated with appropriate levels for individual channels. These clock receivers increase the uncorrelated out-of-band jitter. SUMMARY OF THE INVENTION

[0005] In some embodiments, a clock driver circuit for low-power clock driving can include a multiphase divider and a buffer that supplies at least one of a plurality of phases to the multiphase divider at a center frequency that is an integer multiple of an input frequency, and the multiphase divider and the buffer share the same current from a power rail.

[0006] The above and other objects, features, and advantages of the present invention will become apparent from the following more specific description of exemplary embodiments of the present invention, in which like reference numerals generally represent like parts of the exemplary embodiments of the present invention, shown in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] [Figure 1] FIG. 19 is a circuit diagram of an exemplary clock driver circuit for low-power clock driving according to some embodiments of the present disclosure. [Figure 2] FIG. 22 is a circuit diagram of a delay cell used in an exemplary dynamic D-type flip-flop according to some embodiments of the present disclosure. [Figure 3] FIG. 25 is a circuit diagram of an exemplary clock driver circuit for low-power clock driving according to some embodiments of the present disclosure. [Figure 4]This is a schematic diagram of an exemplary clock driver circuit for low-power clock driving according to some embodiments of the present disclosure. [Figure 5] This is a schematic diagram of an exemplary clock driver circuit for low-power clock driving according to some embodiments of the present disclosure. [Figure 6] This is a block diagram of a low-power array system for low-power clock driving according to some embodiments of the present disclosure. [Figure 7] This is a diagram of an exemplary system according to some embodiments of the present disclosure. [Figure 8] This is a flowchart illustrating exemplary methods for low-power clock driving according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0008] Figure 1 shows a schematic diagram of an exemplary clock driver circuit for low-power clock driving according to several embodiments of the present disclosure. The exemplary clock driver circuit in Figure 1 includes a polyphase divider 102 and a buffer 104. The polyphase divider 102 is configured to receive a clock signal of a first frequency as input and output another clock signal of a second frequency equal to the first frequency divided by some integer value. The polyphase divider 102 can operate with both square and sinusoidal waveforms at the input and supply a square waveform at the output. For example, assuming a clock signal input of frequency N, the polyphase divider 102 outputs a clock signal of frequency N / 2, N / 4, or N divided by any other integer value. Those skilled in the art will understand that the integer value by which the polyphase divider 102 divides the input signal depends on the number of delay cells in the feedback loop. Thus, although the polyphase divider 102 in Figure 1 is shown as a 2-way divider, those skilled in the art will understand that other configurations are also contemplated within the scope of the present disclosure.

[0009] In this example, the clock signal is embodied as two complementary clock signals CLK and CLKB each having non-overlapping pulses. That is, the multiphase divider 102 receives, as an input, a two-phase clock signal. In some embodiments, the clock signals CLK and CLKB are received from a clock signal generator such as an oscillator (not shown). The multiphase divider 102 outputs complementary clock signals RF P (Radio Frequency plus) and RF M (Radio Frequency minus), where RF M is 180 degrees out of phase with RF P . The complementary clock signals CLK and CLKB are supplied to dynamic D-type flip-flops (DDFFs) 106a, 106b, 108a, 108b. Each of the DDFFs 106a, 106b and 108a, 108b may be implemented as a clock delay cell 200 as shown in FIG. 2. A divide voltage V DD-DIV is supplied to each of the DDFFs 106a, 106b and 108a, 108b. In some embodiments, the voltage terminals of each of the DDFFs 106a, 106b and 108a, 108b that receive V DD-DIV are shorted together.

[0010] The outputs RF P and RF M from the multiphase divider 102 are supplied as inputs to the buffer 104. The buffer 104 supplies the desired signal amplitude at the load and provides impedance transformation (using an inductor L and associated capacitance) to protect the inputs to the buffer 104 (the outputs RF P and RF M from the multiphase divider) from the effects of kickback noise from the output. The buffer 104 also receives the input voltage V DD which is the main supply voltage of the clock driver circuit. The plus and minus outputs of the buffer 104 are shown as BUF P and BUF M respectively, where BUF M is BUF PIt is 180 degrees out of phase. The variable capacitor C is BUF P and BUF M The bypass capacitor CBYP is coupled to the respective inductance L. As shown in the figure, buffer 104 is V DD-DIV This is supplied to the multiphase frequency divider 102.

[0011] In some embodiments, the multiphase divider 102 and buffer 104 are stacked (for example, the buffer 104 is stacked on top of the multiphase divider 102). In some embodiments, a clock signal generator, such as an oscillator, may be stacked with the multiphase divider 102, the buffer 104, or both. In some embodiments, the multiphase divider 102 and buffer 104 share a common current; that is, both the multiphase divider 102 and buffer 104 share current from the same power rail (e.g., connected in parallel). This reduces the overall power consumption of the clock driver circuit.

[0012] In some embodiments, the buffer 104 is inductively loaded to a desired harmonic of the multiphase divider 102. For example, in some embodiments, the buffer 104 is inductively loaded to the fundamental harmonic of the output of the multiphase divider 102 (for example, for a frequency f applied to the divider, the buffer 104 is inductively loaded to f / 2). In other embodiments, the buffer is inductively loaded to the odd harmonics of the multiphase divider 102 (for example, for a frequency f, the buffer 104 is inductively loaded to 3f / 2). Thus, in some embodiments, the output frequency of the clock driver circuit is F out =(M / N) * F in It is calculated as F in is the input frequency, N is the integer frequency division supplied by the multiphase frequency divider 102, and M is the frequency multiplication obtained by resonance at the output of the buffer 104, which amplifies the Mth harmonic of the signal at the output of the multiphase frequency divider 102.

[0013] Next, referring to Figure 3, a schematic diagram of another clock driver circuit for low-power clock driving according to an embodiment of the present disclosure is shown. The clock driver circuit in Figure 3 is similar to the clock driver circuit in Figure 1, in that it includes a multiphase frequency divider 102. The clock driver circuit in Figure 3 includes a buffer 304, but the buffer 304 is a switch M SW It differs from buffer 104 in Figure 1 in that it includes (for example, a shunt switch). This switch allows buffer 304 to be shut down without affecting the operation of the multiphase frequency divider 102. The size of the switch can be increased without affecting the performance of buffer 304 in the ON state. In some embodiments, the switch can be used as part of a regulator loop, where the switch is connected to the main voltage V DD and intermediate voltage V DD-DIV It is located between these two points.

[0014] Referring now to Figure 4, a schematic diagram of another clock driver circuit for low-power clock driving according to an embodiment of the present disclosure is shown. The clock driver circuit of Figure 4 differs from the clock driver circuit of Figure 1 in that it is configured to drive the orthogonal and common-mode portions of the input clock signal separately and simultaneously. The clock driver circuit of Figure 4 includes a multiphase divider 402, which includes DDFFs 406a, 406b and 408a, 408b. As shown in Figure 4, the inputs to DDFFs 408a, 408b are supplied as inputs to a first buffer 404a for driving the orthogonal portions. Such inputs are RF QP (RF Quadrature plus) (e.g., 90-degree phase) and RF QM This is expressed as (RF Quadrature minus) (270 degrees phase). Intermediate voltage V from buffer 404a DD-DIV These are supplied to DDFF406a and 406b. The orthogonal positive and negative outputs of buffer 404a are supplied to BUF, respectively. QP and BUF QM This is shown as follows: Since the current of the multiphase frequency divider 402 is shared between the two phases, each phase uses an equal current and supplies an equal amplitude.

[0015] RF IP (RF in-phase plus) (e.g., 0-degree phase) and RF IM The output of the multiphase divider 402, indicated as (RF in-phase minus) (e.g., 180-degree phase), is supplied as input to a second buffer 404b for common-phase driving. The intermediate voltage V from buffer 404b DD-DIV These are supplied to DDFF408a and 408b. The common-mode positive and negative outputs of buffer 404b are supplied to BUF, respectively. IP and BUF IM It is shown as follows.

[0016] Referring now to Figure 5, a schematic diagram of another clock driver circuit for low-power clock driving according to an embodiment of the present disclosure is shown. The clock driver circuit of Figure 5 is similar to the clock driver circuit of Figure 4 in that it is configured to drive the orthogonal and common-mode portions of the input clock signal separately and simultaneously. Thus, the clock driver circuit of Figure 5 includes a multiphase frequency divider 402 including DDFF406a, 406b and 408a, 408b. Voltage is supplied to DDFF406a, 406b and input RF QP and RF QM The buffer that receives (for example, buffer 404a in Figure 4) is omitted for clarity.

[0017] Buffer 504 is similar to buffer 404b in Figure 4, but the input to buffer 504 (for example, input RF) QP and RF QM The difference is that the ) is coupled to the operational amplifier (OPAMP) 508. The OPAMP 508 is a high-gain voltage amplifier with differential input and single-ended output. Here, the OPAMP 508 has a reference voltage V from buffer 504 as its differential input. REF and V DD-DIV It accepts. The OPAMP508 accepts voltage V DD2 It is powered by [this]. The appropriate loop gain between the OPAMP and the buffer 504 is V REFThis is adapted by adjusting the input RF. As those skilled in the art will know, in some embodiments, although not shown, the input RF QP and RF QM You will understand that the corresponding buffer receiving this signal may also have an OPAMP coupled to the input line.

[0018] Figure 6 shows an exemplary low-power array system 600, including a clock driver circuit for driving a low-power clock, according to some embodiments of the present disclosure. The exemplary low-power array system 600 in Figure 6 includes a clock signal generator 602. The clock signal generator 602 is configured to generate an electrical signal at a desired frequency. For example, the clock signal generator 602 includes a crystal oscillator circuit that generates an electrical signal using the mechanical resonance of a crystal. The electrical signal generated by the clock signal generator 602 is the clock signal 603. In some embodiments, the clock signal 603 is embodied as a two-phase clock signal comprising two complementary clock signals (e.g., “CLK” and “CLKB” in Figures 1-5) having non-overlapping pulses.

[0019] The exemplary low-power array system 600 in Figure 6 also includes a polyphase divider 604. The polyphase divider 604 may be any of the polyphase dividers shown in Figures 1, 3 to 5 (e.g., polyphase dividers 102, 402). The polyphase divider 604 receives a clock signal 603 as input and supplies a divided clock signal 605 as output. The divided clock signal 605 is a clock signal of frequency f / N, where f is the frequency of the clock signal 603 and N is an integer value corresponding to the number of delay cells in the polyphase divider 604. For example, in the case of a polyphase divider 604 with N delay cells, the polyphase divider 604 supplies N divisions of frequency division and 2N divisions of phase. The polyphase divider 604 supplies the divided clock signal 605 to one or more buffers 606.

[0020] Buffer 606 includes any of the buffers shown in Figures 1, 3 to 5 (e.g., buffers 104, 304, 404a, 404b, 504). For example, in some embodiments, buffer 606 outputs positive and negative shifted output signals (e.g., "BUF P " and "BUF M The buffer includes a single buffer configured to drive positive and negative common-mode and quadrature outputs (e.g., "BUF IP "BUF IM "BUF QP " and "BUF QM It includes multiple buffers configured to drive the multiphase divider 604 and buffers 606. In some embodiments, the multiphase divider 604 and buffers 606 share the same current from the same power rail. For example, the multiphase divider 604 and buffers 606 are coupled in parallel. In some embodiments, two or more of the clock signal generator 602, multiphase divider 604, and buffers 606 are stacked.

[0021] The output of buffer 606 is shown as a drive-divided clock signal 607 supplied to multiple array elements 608. The array elements 608 can include any of a variety of components that depend on the shared clock, including quantum computing channels, wireless transceivers (e.g., 5G transceivers), and memory modules. By sharing the same current, the multiphase divider 604 and buffer 606 allow the array elements 608 to receive a clock signal with less jitter and reduced power consumption compared to existing solutions.

[0022] Those skilled in the art will understand that the approach specified herein is not limited to clock driver circuits but is also applicable to other circuits in which multiple stacked processing blocks are stacked such that at least one intermediate state is broadband. For example, multiple signal processing blocks 702 may be stacked as shown in Figure 7. The signal processing blocks 702 may be single-ended or differential. Each of the signal processing blocks 702 can be powered up or powered down independently. One or more of the signal processing blocks 702 may be narrowband. Each of the signal processing blocks 702 may share the same power rail as described above. The outputs of such signal processing blocks 702 may be supplied to multiple array elements 706a, 706b, 706n by a distribution network 704. For example, in some embodiments, such as the clock driver circuit described above, the first signal processing block 702 at the bottom of the layer is an oscillator (narrowband), the second signal processing block 702 is a frequency divider (broadband), and the third signal processing block 702 is a buffer (narrowband). As another example, the first signal processing block 702 is an amplifier, the second signal processing block 702 is a filter / delay network (broadband), and the third signal processing block 702 is an amplifier, driving N amplifiers in the beamformer as array elements 706a~706n. As yet another example, the first signal processing block 702 is a single-ended oscillator, the second signal processing block 702 is a single-ended frequency divider, and the stage of the third signal processing block 702 is a differential buffer. Those skilled in the art will understand that a distribution network 704 may also be included in the layer having signal processing blocks 702.

[0023] For further explanation, Figure 8 is a flowchart illustrating an exemplary method for low-power clock driving according to an embodiment of the present invention, which includes receiving a clock signal 804 by a clock driver circuit 800 including a multiphase divider and buffer that share the same current 802. The clock signal 804 is received from a clock signal generator 806 configured to generate an electrical signal at a desired frequency. For example, in some embodiments, the clock signal generator 806 includes an oscillator circuit that generates the clock signal 804 based on the mechanical resonance of a crystal. In some embodiments, the clock signal 804 is embodied as a pair of complementary clock signals (e.g., "two-phase clock signals"). Complementary clock signals are two signals of non-overlapping pulses that, when combined, generate pulses at a desired frequency.

[0024] The clock driver circuit 800 is configured to receive an input clock signal 804 and, as an output, supply a divided drive clock signal 808 suitable for receiving the components described in more detail below. The clock driver circuit 800 includes a multiphase divider. The multiphase divider receives the input clock signal 804 and, as an output, supplies another clock signal of frequency f / N, where f is the frequency of the clock signal and N is an integer. For example, in some embodiments, the multiphase divider supplies complementary clock signals RF that are 180 degrees apart from each other. P and RF M In other embodiments, the multiphase divider outputs the clock signal pair RF QP / RF QM and RF IP / RF IM Outputs RF QP / RF QM This corresponds to orthogonality, RF IP / RF IM These correspond to the same phase.

[0025] In some embodiments, the multiphase frequency divider uses an intermediate voltage V supplied by the buffer. DD-DIV It includes multiple DDFFs driven by the main voltage V DDIt is driven by the multiphase divider output being fed into a buffer. For example, in some embodiments, the output RF P and RF M It is supplied to a single buffer. In other embodiments, RF QP / RF QM Output pair RF QP / RF QM and RF IP / RF IM These signals are supplied to the respective buffers; the first buffer drives the common-mode signal from the multiphase divider, and the second buffer drives the quadrature signal from the multiphase divider.

[0026] The buffer supplies the desired signal amplitude to the load and provides impedance conversion so that the input from the multiphase divider to the buffer is not affected by kickback noise from the output. As mentioned above, the buffer is V DD-DIV By supplying current to the multiphase divider, the multiphase divider and buffer share the same current. That is, the multiphase divider and buffer are supplied with current from the same power rail. In some embodiments, the multiphase divider and buffer are coupled in parallel to the same supply rail. In some embodiments, the multiphase divider and buffer are stacked. In some embodiments, the clock signal generator is stacked with the multiphase divider, buffer, or both. Therefore, in some embodiments, the clock signal generator also shares the same current as the multiphase divider and buffer. By sharing current between the multiphase divider, buffer, or clock signal generator or a combination thereof, overall power consumption is reduced.

[0027] In some embodiments, the multiphase divider 102 and buffer 104 are stacked (for example, the buffer 104 is stacked on top of the multiphase divider 102). In some embodiments, a clock signal generator, such as an oscillator, may be stacked with the multiphase divider 102, the buffer 104, or both. In some embodiments, the multiphase divider 102 and buffer 104 share a common current; that is, both the multiphase divider 102 and buffer 104 share current from the same power rail (e.g., connected in parallel). This reduces the overall power consumption of the clock driver circuit.

[0028] In some embodiments, the buffer is inductively loaded to a desired harmonic of the multiphase divider. For example, in some embodiments, the buffer is inductively loaded to the fundamental harmonic of the output of the multiphase divider (e.g., for a frequency f applied to the divider, the buffer is inductively loaded to f / 2). In other embodiments, the buffer is inductively loaded to the odd harmonics of the multiphase divider (e.g., for a frequency f, the buffer is inductively loaded to 3f / 2).

[0029] In some embodiments, the buffer includes a switch (e.g., a shunt switch). This switch allows the buffer to be shut down without affecting the operation of the multiphase frequency divider. The size of the switch can be increased without affecting the performance of the buffer in the ON state. In some embodiments, the switch can be used as part of a regulator loop. In some embodiments, the switch controls the main voltage V DD The intermediate voltage V supplied to the DDFF of the multiphase frequency divider DD-DIV It is located between the two. In embodiments including multiple buffers (for example, a buffer that drives in-phase and other buffers that drive orthogonal phases), each buffer may contain its own switch such that any of the phases are driven independently, in combination, or not at all.

[0030] In some embodiments, the buffer is coupled to an operational amplifier (OPAMP). For example, the OPAMP may be coupled to the input line from a multiphase divider. In embodiments including multiple buffers (e.g., a buffer driving in-phase and other buffers driving orthogonal), each buffer may be coupled to a corresponding OPAMP. The OPAMP is a high-gain voltage amplifier having differential inputs and a single-ended output. For example, the OPAMP takes a reference voltage V from the coupled buffer as a differential input. REF and V DD-DIV It can accept the voltage V. The OPAMP accepts the voltage V. DD2 It is powered by the OPAMP. The moderate loop gain between the OPAMP and the coupled buffer is V REF It is adapted by adjusting it.

[0031] The method in Figure 8 also includes an output 810 of a divided clock signal (e.g., a divided drive clock signal 808) driven by a clock driver circuit 800. The divided drive clock signal 808 is the output of a buffer of the clock driver circuit 800. In some embodiments, the divided drive clock signal 808 is output to multiple array elements 812. Array elements 812 are arrays of components that operate using the same synchronous clock. For example, array elements 812 may not be suitable for operating on a direct clock signal 804 from a clock signal generator 806, and instead must operate on a divided drive clock signal 808 output by the clock driver circuit 800. For example, array elements 812 may include arrays of synchronous transceivers (e.g., a 5G array), arrays of memory modules, arrays of quantum computing channels, and so on.

[0032] From the above description, readers will recognize that the advantages of low-power clock driving according to embodiments of the present invention include the following: • By using low-power clocks that reduce jitter and power consumption, the performance of computing systems is improved. By adding a switch to the buffer of the clock driver circuit, independent operation of the buffer is possible without affecting the performance of the multiphase frequency divider, thereby improving the performance of the computing system. • The number of clock phases used for distribution to the computing system array can be flexibly selected.

[0033] Exemplary embodiments of the present invention are described primarily in the context of a fully functional computer system for low-power clock driving. However, those skilled in the art will recognize that the present invention can also be embodied in a computer program product located on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or floppy disks, compact disks for optical drives, magnetic tapes, and others that those skilled in the art may conceive of. Those skilled in the art will immediately recognize that any computer system with suitable programming means can perform steps of the method of the present invention embodied in a computer program product. Furthermore, those skilled in the art will recognize that while some of the exemplary embodiments described herein are directed towards software installed and run on computer hardware, alternative embodiments implemented as firmware or hardware are nevertheless within the scope of the present invention.

[0034] The present invention may be a system, a method, a computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions for causing a processor to execute an aspect of the present invention.

[0035] A computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. A computer-readable storage medium may, for example, be an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROM, DVD, memory stick, floppy disk, punch cards or grooved raised structures, and other mechanically encoded devices on which instructions are recorded, and suitable combinations thereof. Computer-readable storage devices as used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0036] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). The network consists of copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. The network adapter card or network interface of each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on the computer-readable storage medium within each computing / processing device.

[0037] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++ and procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions are executable as a standalone software package, either entirely on the user's computer or partially on the user's computer. Alternatively, they may be executable partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by personalizing them using state information of computer-readable program instructions in order to perform aspects of the present invention.

[0038] Aspects of the present invention are described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and any combination of blocks in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0039] These computer-readable program instructions can be provided to a general-purpose computer, a special-purpose computer processor, or other programmable data processing device to generate a machine, such that instructions executed via the processor of a computer or other programmable data processing device generate means for implementing functions / operations specified in one or more blocks of a flowchart or block diagram or both. These computer-readable program instructions can also be stored in a computer-readable storage medium that can be connected to a computer, a programmable data processing device, or other device or combination of devices that function in a particular way, such that the computer-readable storage medium on which the instructions are stored constitutes one of the outputs containing instructions that implement the modes of function / operations specified in one or more blocks of a flowchart or block diagram or both.

[0040] Computer-readable program instructions, like instructions that perform a function / action specified in one or more blocks of a flowchart or block diagram or both on a computer, other programmable device, or other device, can also be loaded into a computer, other programmable data processing device, or other device and perform a series of operational steps on the computer, other programmable device, or other device to produce a computer-implemented process.

[0041] The flowcharts and block diagrams in the figures illustrate the configuration, function, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which constitutes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions shown in the blocks may differ from the order shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions they relate to. It should also be noted that each block in a block diagram or flowchart, or both, and any combination of blocks in a block diagram or flowchart, or both, can be implemented by a special-purpose hardware-based system that performs a specified function or operation, or a combination of special-purpose hardware and computer instructions.

[0042] From the above description, it will be understood that modifications and changes can be made to various embodiments of the present invention without departing from the true scope of the invention. The descriptions herein are for illustrative purposes only and should not be construed as restrictive. The scope of the present invention is limited only by the following claims.

Claims

1. A clock driver circuit for low-power clock driving, A multiphase frequency divider, A buffer that receives at least one of multiple phase-having signals output from the multiphase frequency divider, operates at a center frequency that is an integer multiple of the input frequency, and forms an intermediate voltage power supply that supplies power to the multiphase frequency divider, The multiphase frequency divider and the buffer share the same current from the power rail. Clock driver circuit.

2. The buffer further includes an operational amplifier that receives a reference voltage and the intermediate voltage power supply as inputs and adjusts the intermediate voltage power supply based on the reference voltage. The clock driver circuit according to claim 1.

3. The multiphase frequency divider and the buffer are stacked. The clock driver circuit according to claim 1.

4. The system further includes a clock signal generator coupled to the multiphase frequency divider, which generates a clock signal that is input to the multiphase frequency divider. The clock driver circuit according to claim 1.

5. Two or more of the clock signal generator, the multiphase frequency divider, and the buffer are stacked. The clock driver circuit according to claim 4.

6. The system further includes a power-down switch that controls the power supply to the buffer to power down the buffer. The clock driver circuit according to claim 1.

7. The power-down switch is connected between the main voltage power supply and the intermediate voltage power supply. The clock driver circuit according to claim 6.

8. One or more outputs from the multiphase frequency divider are directly coupled to one or more inputs of the buffer. The clock driver circuit according to claim 1.

9. The buffer is configured to resonate at a frequency that is an integer multiple of the output frequency of the multiphase frequency divider. The clock driver circuit according to claim 1.

10. The output frequency of the aforementioned clock driver circuit is F ｏｕｔ = (M / N) ＊ F ｉｎ It is calculated as, here, F ｉｎ is the input frequency, N is the integer frequency division supplied by the multiphase frequency divider, and M is the frequency multiplication obtained by resonance at the output of the buffer that amplifies the Mth harmonic of the signal at the output of the multiphase frequency divider. The clock driver circuit according to claim 9.

11. A device for driving a low-power clock, Includes a clock driver circuit, The clock driver circuit is, A multiphase frequency divider, The system includes a buffer that operates by receiving at least one of multiple phase-having signals output from the multiphase frequency divider and forms an intermediate voltage power supply that supplies power to the multiphase frequency divider, The multiphase frequency divider and the buffer share the same current from the power rail. Device.

12. The buffer further includes an operational amplifier that receives a reference voltage and the intermediate voltage power supply as inputs and adjusts the intermediate voltage power supply based on the reference voltage. The apparatus according to claim 11.

13. The multiphase frequency divider and the buffer are stacked. The apparatus according to claim 11.

14. The clock driver circuit further includes an oscillator coupled to the multiphase divider that generates a signal input to the multiphase divider. The apparatus according to claim 11.

15. Two or more of the oscillator, the multiphase frequency divider, and the buffer are stacked. The apparatus according to claim 14.

16. The clock driver circuit further includes a power-down switch connected between the main voltage power supply and the intermediate voltage power supply, which controls the power supply to the buffer and powers down the buffer. The apparatus according to claim 14.

17. One or more outputs from the multiphase frequency divider are directly coupled to one or more inputs of the buffer. The apparatus according to claim 11.

18. A method for low-power clock driving, A clock driver circuit includes a multiphase frequency divider and a buffer that operates by receiving at least one of multiple phase-having signals output from the multiphase frequency divider and forms an intermediate voltage power supply that supplies power to the multiphase frequency divider, thereby receiving a clock signal. The process includes outputting a divided clock signal, generated by dividing the clock signal by an integer using the multiphase frequency divider, by the clock driver circuit. method.

19. The multiphase frequency divider and the buffer are stacked. The method according to claim 18.

20. The divided clock signal driven by the clock driver circuit is output to a plurality of array elements. The method according to claim 18.

21. Multiple signal processing blocks, Each of the aforementioned plurality of signal processing blocks is stacked and shares the same current, The plurality of signal processing blocks are connected in series with each other and configured to process signals sequentially, and one or more intermediate signal processing blocks of the plurality of signal processing blocks include a broadband signal processing block that generates signals for driving a subsequent distribution network or a plurality of array elements. Multiple signal processing blocks, A distribution network that receives the outputs of the aforementioned plurality of signal processing blocks as inputs, Includes a plurality of array elements, each receiving an input from the distribution network, system.

22. The aforementioned plurality of signal processing blocks are: An oscillator that generates a clock signal, A multiphase frequency divider that divides the clock signal generated by the oscillator and outputs a divided clock signal having multiple phases, A buffer that receives the divided clock signal output from the multiphase divider and supplies it to the distribution network, and also forms an intermediate voltage power supply that supplies power to the multiphase divider, The system according to claim 21.

23. The aforementioned plurality of signal processing blocks are: A first amplifier that amplifies the input signal, A delay network that imparts a delay to the output signal of the first amplifier, The system includes a second amplifier that amplifies the output signal of the delay network, The aforementioned plurality of array elements are The beamformer includes a plurality of third amplifiers that receive and amplify the output signal of the second amplifier, The system according to claim 21.

24. The aforementioned plurality of signal processing blocks are: A single-ended oscillator that generates a clock signal as a single-ended signal, A single-ended frequency divider that divides the clock signal generated by the single-ended oscillator into a single-ended signal, A differential buffer that receives a single-ended divided clock signal output from the single-ended frequency divider and outputs differential signals that are out of phase with respect to each other, is included. The system according to claim 21.

25. The distribution network is stacked with the plurality of signal processing blocks. The system according to claim 21.

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