METHOD AND DEVICES FOR IMPLEMENTING DELAY LINES AND ANALOGUE / DIGITAL CONVERTERS

Abstract

An exemplary device comprises the following: a first delay buffer having a clock input, a bias input coupled to a delay control input, a reset input, and an output; a second delay buffer having a clock input coupled to the output of the first delay buffer, a bias input coupled to the delay control input, a reset input, and an output; and a counter having a clock input coupled to the output of the second delay buffer, a reset output coupled to a clear input of the first delay buffer, the clear input being coupled to the second delay buffer, and an output.

Description

TECHNICAL AREA

[0001] This description generally concerns integrated circuits and, in particular, methods and devices for implementing delay lines and analog-to-digital converters. BACKGROUND

[0002] Delay lines contain a sequence of delay circuit elements used to delay an electrical signal (e.g., a digital signal) by a specified amount. For example, a series of buffers can be connected to delay a signal. Delay lines can be used in many applications. For instance, they are used in some implementations of analog-to-digital converters. SUMMARY

[0003] For delay lines, an exemplary buffer line device includes a first delay buffer having a clock input, a bias input coupled to a delay control input, a reset input, and an output; a second delay buffer having a clock input coupled to the output of the first delay buffer, a bias input coupled to the delay control input, a reset input, and an output; and a counter having a clock input coupled to the output of the second delay buffer, a reset output coupled to a clear input of the first delay buffer (the clear input being coupled to the second delay buffer), and an output. Other examples are described.

[0004] For delay lines, an exemplary analog-to-digital converter includes an analog delay control input; a signal input; several delay buffers connected in series, with the first of the multiple delay buffers coupled to the signal input; a first counter with a clock input coupled to an output of the last of the multiple delay buffers; several flip-flops containing clock inputs, each coupled to the outputs of the delay buffers of the multiple delay buffers; a thermometer-to-binary converter coupled to the outputs of the multiple flip-flops; and binary data outputs based on an output of the first counter and the outputs of the thermometer-to-binary converter. Other examples are described.

[0005] For delay lines, an exemplary method includes a procedure for converting an analog voltage into a digital value, wherein the procedure includes: repeatedly passing a signal through a first sequence of delay buffers biased by a reference voltage; repeatedly passing the signal through a second sequence of delay buffers biased by an input voltage; after the signal has passed through the first sequence of delay buffers a specified number of times, determining the number of delay buffers in the second sequence of delay buffers through which the signal has passed and the number of loops; and outputting a binary value based on the number of delay buffers in the second sequence of delay buffers through which the signal has passed and the number of passes through the second sequence of delay buffers.Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates the delay response of a delay circuit element over an operating voltage range. Fig. Figure 2 illustrates an exemplary delay line circuit containing sixteen delay buffers connected in series and a 2-bit counter. Fig. Figure 3 illustrates an example analog-to-digital converter (ADC). Fig. Figure 4 illustrates another example ADC circuit. Fig. Figure 5 illustrates an implementation of the digital calibration circuit. Fig. Figure 6 is a flowchart illustrating an exemplary process for implementing an ADC.

[0006] The drawings are not necessarily to scale. In general, identical reference symbols in one or more drawings and in this description refer to identical or (functionally and / or structurally) similar features and / or parts. Although the drawings show areas with clear lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended, or irregular. DETAILED DESCRIPTION

[0007] When implementing delay lines, the required delay duration for a circuit can necessitate a large number of delay circuit elements. For example, an analog-to-digital converter design might use 64 delay circuit elements to provide six-bit resolution for the digital output. Such a large number of delay circuit elements can require a significant amount of physical RAM and increase the cost of a circuit.

[0008] The delay lines disclosed here use a reduced number of delay circuit elements in combination with a counter to iterate through the delay circuit elements multiple times, thus implementing the equivalent of a large number of circuit elements. The analog-to-digital converters disclosed here utilize the delay lines to provide efficient use of voltage-to-time digital conversion with a reduced number of circuit elements.

[0009] Fig. Figure 1 illustrates the delay response of a delay circuit element over an operating voltage range. As shown in Fig. As shown in Figure 1, line 100 illustrates that the delay time generally increases as the voltage level decreases. Furthermore, as shown in Box 102, the example delay circuit has a linear operating range between approximately 0.7 volts and 1.3 volts. The delay circuit elements can be used within this linear range to provide a consistent voltage-delay response. Accordingly, when designing a circuit, the number of delay circuit elements is chosen to distribute the input voltage across the appropriate number of delay circuit elements, thus keeping the voltage within the linear range of the delay circuit elements.

[0010] Fig. Figure 2 illustrates an exemplary delay line circuit 200 containing sixteen delay buffers 202 connected in series and a 2-bit counter 204. The exemplary circuit 200 can emulate 64 delay buffers, using only the sixteen delay buffers 202. While the sixteen delay buffers 202 and the 2-bit counter 204 are included in the illustrated example, other implementations could use any number of delay buffers and any bit counter.

[0011] The delay line circuit 200 includes a signal input 206 and a delay control input 208. The signal input 206 is connected to a clock input of the first of the sixteen delay buffers 202 and is delayed by each delay buffer 202 through which the signal passes. The delayed signal can be accessed at an output 210 of each delay buffer 202. The delay duration for each delay buffer 202 is controlled by the delay control input 208, which is coupled to a bias input of each delay buffer 202. According to the illustrated example, the delay duration decreases as the magnitude of the signal input 206 increases. Alternatively, other types of delay buffers can be used. For example, a circuit can use delay buffers with fixed delays, delay buffers with delays that increase as the voltage increases, and so on.

[0012] According to the exemplary delay line circuit 200, the output of the last of the delay buffers 202 is coupled to an input of the 2-bit counter 204. When the input of the 2-bit counter 204 is high (e.g., when a signal is output by the last of the delay buffers 202), the 2-bit counter 204 increments its output counter value (S0 and S1). The outputs S0 and S1 cycle through 0,0, 0,1, 1,0, 1,1, and then back to 0,0. Each time the 2-bit counter 204 is incremented, the 2-bit counter 204 outputs a reset signal 212. The reset signal 212 is coupled to a clear input terminal of each of the sixteen delay buffers 202. Accordingly, the sixteen delay buffers 202 are cleared each time the 2-bit counter 204 is incremented, restarting the delay buffering of the signal input 206. Consequently, another buffering cycle begins. When the 2-bit counter 204 has incremented four cycles (e.g.,Starting at 0,0 and continuing until the counter is incremented to 0,0; starting at 1,1 and continuing until the counter is incremented to 1,1; etc.), the signal input 206 has been delayed 64 times (four rounds with sixteen delay buffers). The signal input 206 can be read at the output 210 of the last of the sixteen delay buffers 202 after 64 delays, if the output of the 2-bit counter 204 has been incremented four times. A time of 64 delays can also be determined by monitoring the output of the 2-bit counter 204. A time of 64 delays can be determined, for example, by... B. can be determined when the 2-bit counter 204 has been incremented four times (e.g. by cyclically going from 1.1 to 0.0 to 0.1 to 1.0 and back to 1.1).

[0013] Fig. Figure 3 illustrates an exemplary analog-to-digital converter (ADC) circuit 300, which utilizes the structure of the delay line circuit 200. The exemplary ADC circuit 300 contains a reference set of sixteen delay buffers 302, a reference 2-bit counter 304, a reference set of sixteen flip-flops 306, a data set of sixteen delay buffers 308, a data 2-bit counter 310, a data set of sixteen flip-flops 312, a thermometer-to-binary converter 314, and a digital calibration circuit 316. The ADC circuit 300 outputs a 6-bit value indicating the voltage Vin applied to the clock input of the first delay buffer of the data set of sixteen delay buffers 308.

[0014] Similar to the delay line circuit 200, the reference set of sixteen delay buffers 302 is connected in series, with the output of one of the delay buffers connected to the clock input of the next delay buffer. Additionally, an output of each of the reference set of sixteen delay buffers 302 is connected to a data input of a corresponding flip-flop of the reference set of sixteen flip-flops 306. A high voltage Vmax is connected to the bias input of each of the delay buffers of the reference set of sixteen delay buffers 302. According to the example circuit 300, the high voltage is a maximum voltage that can be detected by the circuit 300 (e.g., converted from analog to digital).

[0015] An output of the last delay buffer of the reference set of sixteen delay buffers 302 is connected to a clock input of the reference 2-bit counter 304. A reset output of the reference 2-bit counter 304 is connected to a reset input of each of the reference set of delay buffers 302.

[0016] The ADC circuit 300 contains a set of sixteen delay buffers 308 connected in series, with the output of one delay buffer connected to the clock input of the next delay buffer. Additionally, an output of each set of sixteen delay buffers 308 is connected to a data input of a corresponding flip-flop in the set of sixteen flip-flops 312. An input voltage Vin is connected to the bias input of each delay buffer in the set of sixteen delay buffers 308. Vin is an analog voltage that is converted into a digital output value by the ADC circuit 300.

[0017] An output of the last delay buffer of the data set of sixteen delay buffers 308 is connected to a clock input of the data 2-bit counter 310. A reset output of the data 2-bit counter 310 is connected to a reset input of each of the data sets of delay buffers 308.

[0018] An output of the reference 2-bit counter 304 is coupled to a capture input of each of the data set of sixteen flip-flops 312 to capture the data input of each of the data set of sixteen flip-flops 312 when the output of the reference 2-bit counter 304 reaches a predetermined value (e.g., when the reference 2-bit counter 304 increments to 1,1).

[0019] The outputs of each flip-flop of the data set of sixteen flip-flops 312 are connected to the thermometer-to-binary converter 314. The thermometer-to-binary converter 314 can be implemented by any type of thermometer-to-binary converter circuit arrangement to convert a thermometer value corresponding to the outputs of the data set of sixteen flip-flops 312 into a binary value. The exemplary thermometer-to-binary converter 314 outputs a 4-bit binary value representing the 16-bit thermometer input from the sixteen flip-flops 312 (e.g., if...If the output of all sixteen flip-flops in the data set is 312 low / zero, the thermometer-to-binary converter can output 314 0000; if the output of all sixteen flip-flops in the data set is 312 high / one, the thermometer-to-binary converter can output 314 1111; if the output of the first eight flip-flops in the data set is 312 high / one and the output of the last eight flip-flops in the data set is 312 low / zero, the thermometer-to-binary converter can output 314 0111, etc.).

[0020] An output of the 2-bit data counter 310 and an output of the thermometer-to-binary converter 314 are connected to the digital calibration circuit 316. The digital calibration circuit 316 combines the outputs to produce a 6-bit digital value that indicates a voltage of the voltage input Vin. The exemplary digital calibration circuit 316 defines the two most significant bits of the 6-bit digital value as the two bits S0 and S1 output by the 2-bit data counter 310, and the four least significant bits of the 6-bit digital value as the four bits output by the thermometer-to-binary converter 314.

[0021] During operation of the ADC circuit 300, when a stage input is applied to the clock input of the first delay buffer of the reference set of delay buffers 302, the stage input is delayed by 64 delays with a shortest delay duration determined by Vmax. Simultaneously, the stage input is delayed by the data set of sixteen delay buffers 308. Since the voltage Vin is a voltage smaller than Vmax, the delay of each delay buffer in the data set of sixteen delay buffers 308 is longer than the delay of each delay buffer in the reference set of sixteen delay buffers 302.Accordingly, after four delay rounds through the delay buffers of the reference set of sixteen delay buffers 302, when the capture signal is forwarded to the data set of sixteen flip-flops 312, the stage input has not traversed as many delay buffers of the data set of sixteen delay buffers 308. Which of the flip-flops of the data set of sixteen flip-flops are set to high / one and which of the bits of the data 2-bit counter 310 are set to high / one consequently indicates the voltage of Vin compared to the voltage of Vmax.

[0022] For example, if the voltage Vin is 1 volt and Vmax is 1.3 volts, the data set of sixteen delay buffers 308 will have completed two iterations in the time required for four iterations through the reference set of sixteen delay buffers 302, with none of the delay buffers in the data set of sixteen delay buffers 308 being set to high / one. Consequently, the output of the digital calibration circuit 316 is 100000.

[0023] After the digital value has been output by the digital calibration circuit 316, the data 2-bit counter 310 is reset, with the stage input continuing to be delayed by the reference set of sixteen delay buffers 302, with the reference 2-bit counter 304 continuing to be incremented.

[0024] Fig. Figure 4 illustrates another exemplary ADC circuit 400, which contains the components of ADC circuit 300 plus additional components. To allow the structure of ADC circuit 400 to operate within the linear range of the delay buffers in the circuit, ADC circuit 400 is configured such that when Vmax is applied to the reference section of the circuit and Vin is the minimum value for the circuit, only the very first delay buffer in the set of sixteen delay buffers 308 should increase after the four passes through the reference set of sixteen delay buffers 302. The time required to pass through the reference set of sixteen delay buffers is 2 N * T dVmax Nanoseconds, where N is the number of bits in the digital result and T dVmaxThe delay of a delay buffer is when it is preloaded with Vmax. For an example delay buffer with a T dVmaxFor a 50 picosecond delay, the time required by the reference set of sixteen delay buffers is 3.2 nanoseconds. To keep the delay buffers within their linear range while the 3.2 nanosecond range between Vmin and Vmax is reached, the ADC circuit 400 additionally includes a preliminary reference set of delay buffers 420, a preliminary reference 2-bit counter 422, an AND gate 424, a flip-flop 426, a process and temperature calibration circuit 428, a preliminary data set of delay buffers 440, a preliminary data 2-bit counter 442, an AND gate 444, a flip-flop 446, and a process and temperature calibration circuit 448. The additional delay buffers 420 and 440 in the reference and data sections of the ADC circuit 400 park the delay buffers within their linear range.Due to the increase in power consumption and area required by such a large number of delay buffers, the use of loop delay buffers with a counter allows for buffer reuse (e.g., a fourfold reduction in the number of delay buffers with a 2-bit counter). Such reuse provides a reduction in the area and power required by the delay buffers compared to a circuit with a full set of delay buffers.

[0025] The preliminary reference set of delay buffers 420 and the preliminary delay buffer set 440 contain 30 delay buffers. These 30 delay buffers, operating with the preliminary reference 2-bit counter 422 and the preliminary data 2-bit counter 442 respectively, add sufficient delay to provide the equivalent of 120 delay buffers in the reference and data lines, ensuring that the delay buffers of the ADC circuit 400 continue to operate within the linear range for Vin between Vmin and Vmax. Alternatively, other numbers of delay buffers can be used in a circuit with varying time constraints, linear ranges of the delay buffers, and / or voltage ranges.

[0026] Similar to the ADC circuit 300, a reference voltage of Vmax is applied as the bias voltage to the preliminary reference set of delay buffers 420, with a step input as the clock input being applied to the preliminary set of delay buffers 420. The output of the last delay buffer of the preliminary set of delay buffers 420 and the outputs of the preliminary reference 2-bit counter 422 are coupled to the AND gate 424. When all inputs of the AND gate 424 are high / one, the AND gate 424 outputs a high / one signal to a clock input of the flip-flop 426. A voltage signal DVDD (e.g., a high digital signal) is coupled to a data input of the flip-flop 426. When the AND gate 424 outputs the high / one signal, the flip-flop 426 outputs the high / one signal to the process and temperature calibration cells 428.The process and temperature calibration cells 428 can be implemented by any circuit capable of compensating for variations in operating conditions, such as temperature. For example, the process and temperature calibration cells 428 can be implemented by sixteen series-connected delay buffers with a fixed bias, where the time it takes for a signal to pass through the sixteen delay buffers can be monitored to provide calibration for the effects of the operating conditions. After the high / one signal from the flip-flop 426 has passed through the process and temperature calibration cells 428, the high / one signal is output from the process and temperature calibration cells 428 to the first delay buffer of the reference set of sixteen delay buffers 302.

[0027] Regarding the data line, an input voltage Vin is supplied as the bias voltage to the preliminary data set of delay buffers 440, with a step input as the clock input being supplied to the preliminary data set of delay buffers 440. The output of the last delay buffer of the preliminary data set of delay buffers 440 and the outputs of the preliminary 2-bit counter 442 are coupled to the AND gate 444. When all inputs of the AND gate 444 are high / one, the AND gate 444 outputs a high / one signal to a clock input of the flip-flop 446. A voltage signal DVDD (e.g., a high digital signal) is coupled to a data input of the flip-flop 446. When the AND gate 444 outputs the high / one signal, the flip-flop 446 outputs the high / one signal to the process and temperature calibration cells 448.The process and temperature calibration cells 448 can be implemented by any circuit capable of compensating for variations in operating conditions, such as temperature. For example, the process and temperature calibration cells 448 can be implemented by sixteen series-connected delay buffers with a fixed bias, where the time it takes for a signal to pass through the sixteen delay buffers can be monitored to provide calibration for the effects of the operating conditions. After the high / one signal from the flip-flop 446 has passed through the process and temperature calibration cells 448, the high / one signal is output from the process and temperature calibration cells 448 to the first delay buffer of the reference set of sixteen delay buffers 302.

[0028] The remaining connections and functionality of the ADC circuit 400 are the same as the description of the ADC circuit 300 according to... Fig. 3. Consequently, the ADC 400 circuit provides additional improvements in the ability to keep delay buffers within their linear range by adding additional delay buffers (compared to the ADC 300 circuit, etc.), while reducing the area and power required for such a design by using delay buffers combined with a counter to provide multiple passes through the same delay buffers.

[0029] Fig. Figure 5 illustrates an implementation of the digital calibration circuit 316. According to the illustrated example, the digital calibration circuit 316 receives a 2-bit binary code 502 (from the 2-bit data counter 310) and a 4-bit binary code 504 (from the example thermometer-to-binary converter 314). A code conversion circuit 506 combines the code 502 and the code 504 to produce a 6-bit binary output. According to the illustrated example, the code conversion circuit 506 includes lines connecting the inputs to the outputs to output the 2-bit binary code 502 as the most significant bits of the 6-bit binary output and the 4-bit binary code 504 as the least significant bits of the 6-bit binary output.

[0030] While the example disclosed here includes a thermometer-to-binary converter 314, which is separate from the digital calibration module 316, these components may be combined in other examples. While the examples disclosed here illustrate an example containing six bits of a binary output, any number of bits may be implemented. While the examples combine a 2-bit counter and sixteen delay buffers, any number of bits and any number of delay buffers may be used. The number of required delays may, for example, be expressed as 2 N can be determined, where N is the number of bits desired in the output. According to such an example, the number of delay buffers can be defined as 2N2C to be determined, where C is the number of bits used in the counter.

[0031] Fig. Figure 6 is a flowchart illustrating an exemplary process for implementing an ADC, such as the ADC 300 and / or the ADC 400. The operations in Fig. 6 can be representative, for example, of exemplary machine-readable instructions and / or exemplary operations 600 that can be executed, instantiated, or performed by a programmable circuit arrangement of at least one of them to implement an ADC. The exemplary machine-readable instructions and / or the exemplary operations 600 according to Fig.The process begins at block 602, where a reference line of series-connected delay buffers is biased with a constant voltage (e.g., Vref = Vmax) greater than an expected analog voltage to be measured. A data line of series-connected delay buffers is biased with an input voltage (e.g., Vin) to be converted from an analog voltage to a digital value (block 604). Then, a step signal is applied essentially simultaneously to the reference delay buffers and the data delay buffers, and the step signal begins to flow through the delay buffers (block 606). When the signal from the last delay buffer is output in each sequence of data buffers, a counter is incremented (block 608). Each time a counter is incremented, a reset signal is sent to the delay buffers to start another round / pass of delays (block 610).When the reference buffer clock hits 1,1 (e.g., after four loops through the sequence of delay buffers), the outputs on the data line are captured in the flip-flops (Block 612). While, for example, the delay buffers on the reference line always delay by the same fixed amount, the delay of the delay buffers on the data line varies based on Vin. Because Vin is smaller than Vref, which is applied to the reference delay buffers, the relative number of delay buffers activated when the reference line has completed four loops indicates the magnitude of the voltage of Vin with respect to Vref. The output of the data line flip-flops and the data line counter is then collected and processed to produce the binary output value that indicates the voltage of Vin (Block 614).

[0032] According to some examples, some of the components of the ADC 300 and / or the ADC 400 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. All components except the delay buffers can, for example, be implemented by a logic circuit, such as a processor or a microcontroller. The operations of Flowchart 600 can be implemented by such a logic circuit.

[0033] The singular forms used here (e.g., "one," "a," "first," "second," etc.) do not exclude multiple forms. The term "one" or "an" object, as used here, refers to one or more of these objects. The terms "one" (or "a"), "one or more," and "at least one" are used synonymously here. Furthermore, multiple means, elements, or processes may be implemented by, for example, the same entity or object, even though they are listed individually. Although individual features may be included in different examples or claims, they may also potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0034] The term "above," as used here, describes the relationship of two parts with respect to the Earth, unless otherwise specified. A first part is above a second part if the second part has at least one part between the Earth and the first part. As used here, a first part is also "below" a second part if the first part is closer to the Earth than the second part. A first part may be above or below a second part with one or more of the following: other parts in between, no other parts in between, the first and second parts touching, or the first and second parts not in direct contact, as mentioned above.

[0035] Notwithstanding the foregoing, when referring to at least one component of a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an assembly of an integrated circuit (IC assembly) containing a semiconductor die, during fabrication or manufacturing, "above" does not refer to the ground, but instead refers to an underlying substrate on which relevant components are fabricated, assembled, attached, supported, or otherwise provided. Consequently, as used here, and unless otherwise specified or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is "above" a second component within the semiconductor die if, during fabrication / manufacturing, the first component is located further from a substrate (e.g., a substrate) than the second component.a semiconductor wafer) on which the two components are manufactured or otherwise provided. Similarly, unless otherwise specified or implied from the context, a first component within an IC assembly (e.g., a semiconductor die) is located "over" a second component within the IC assembly during manufacturing if the first component is located farther from a printed circuit board (PCB) on which the IC assembly is to be mounted or attached. Semiconductor devices are frequently used in a different orientation than their orientation during manufacturing. Consequently, if one or a combination of a semiconductor device (e.g.,When reference is made to a transistor), a semiconductor die containing a semiconductor device, or an assembly of an integrated circuit (IC assembly) containing a semiconductor die, the definition of "over" in the preceding paragraph (i.e., the term "over" describes the relationship of two parts with respect to the earth) is likely to be decisive based on the context of use.

[0036] As used in this patent, the indication that any part (e.g., a layer, a film, an area, a region, or a plate) is in any way located on another part (e.g., positioned, situated, arranged, or formed, etc.) means that the referenced part is either in contact with the other part or that the referenced part is located above the other part with one or more intermediate parts in between.

[0037] As connection references (e.g., attached, coupled, connected, and joined) are used here, they may include intermediate elements between the elements referenced by at least one of the connection references, or a relative movement between those elements, unless otherwise specified. As such, the connection references do not necessarily imply that two elements are directly connected or in a fixed relationship to one another. As used here, stating that any part is in "contact" with another part is defined as meaning that there is no intermediate element between the two parts.

[0038] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used here without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, or any other kind of order. They are used simply as at least one of designations or arbitrary names to distinguish elements for the ease of understanding the examples described. According to some examples, the descriptor "first" may be used to refer to an element in the detailed description, while in a claim, a different descriptor, such as "second" or "third," may refer to the same element. In such cases, these descriptors are used merely to uniquely identify these elements within the context of the discussion (e.g., within a claim), where the elements are, for example,otherwise they might share the same name.

[0039] As used here, "approximately" and "about" modify their subjects / values ​​to acknowledge the potential presence of variations that occur in real-world applications. For example, "approximately" and "about" can modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. "Approximately" and "about" can also indicate, for example, that such dimensions may fall within a tolerance range of ±10% unless otherwise specified here.

[0040] As used here, "essentially real-time" refers to an occurrence in a near-instantaneous manner, recognizing that real-world delays for processing, transmission, etc., may occur. Consequently, "essentially real-time" refers to real-time plus one second unless otherwise specified.

[0041] The term “in connection”, including its variations as used here, includes one or a combination of a direct connection or an indirect connection via one or more intermediate components and does not require a direct physical (e.g., wired) connection or permanent connection, but rather also includes a selective connection in at least one of periodic intervals, scheduled intervals, aperiodic intervals or in one-off operations.

[0042] A “programmable circuit arrangement,” as used here, is defined as containing at least one of: (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and containing one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific functions or operations and containing one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors, such as…Central processing units (CPUs) that can execute first instructions to perform one or more operations or functions; field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure or structure the FPGAs to instantiate one or more operations or functions corresponding to the first instructions; graphics processing units (GPUs) that can execute first instructions to perform one or more operations or functions; digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions; XPUs; network processing units (NPUs); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). An XPU, for example, can...be implemented by a heterogeneous computing system that includes several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any or any combinations thereof) and an orchestration technology (e.g., one or more application programming interfaces (APIs)) that can assign one or more computational tasks to whichever of the several types of programmable circuitry is suitable and available to perform the one or more computational tasks.

[0043] An integrated circuit / circuit assembly, as used here, is defined as one or more semiconductor assemblies containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. An integrated circuit can be implemented, for example, as one or more ASICs, FPGAs, chips, microchips, programmable logic devices, semiconductor substrates coupling multiple circuit elements, systems-on-a-chip (SoCs), etc.

[0044] In this description, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if a device A generates a signal to control a device B to perform an operation: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0045] A device that is "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, and / or can be configured (or reconfigured) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the design and / or arrangement of hardware components and interconnections of the device, or a combination thereof.

[0046] The terms "terminal," "node," "interconnection," "terminal pin," and "conduit," as used herein, are synonymous. Unless specifically stated otherwise, these terms are generally used to refer to an interconnection between, or an endpoint of, a device element, circuit element, integrated circuit, appliance, or other electronic or semiconductor component.

[0047] A “circuit arrangement” described in the description and claims may contain one or more circuits. A circuit or device described herein as containing certain components may instead be designed to be coupled to these components to form the described circuit arrangement or device. A structure described as containing one or more semiconductor elements (such as transistors), one or more passive elements (such as one of or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and / or current sources) may, for example, instead contain only the semiconductor elements within a single physical device (e.g., a housing).a semiconductor die and / or an integrated circuit (IC) assembly) and may be designed to be coupled to at least some of the passive elements or sources to form the described structure either at the time of manufacture or after a time of manufacture, e.g. by an end user and / or a third party.

[0048] The circuits described here are reconfigurable to include the replaced components in order to provide functionality that is at least partially similar to the functionality available before the component was replaced. Unless otherwise stated, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.These are capacitors connected in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are contained within an integrated circuit and other elements are located outside the integrated circuit, according to other exemplary embodiments, additional or fewer features may be included in the integrated circuit. Additionally, some or all of the features illustrated as being located outside the integrated circuit may be included within the integrated circuit, while some features illustrated as being located inside the integrated circuit may be included outside the integrated circuit.The term “integrated circuit”, as used herein, means one or more circuits which are at least one of the following: (i) incorporated into / over a semiconductor substrate; (ii) incorporated into a single semiconductor assembly; (iii) incorporated into the same module; or (iv) incorporated into / on the same printed circuit board.

[0049] The uses of the term "mass" in the foregoing description include at least one chassis mass, earth mass, suspended mass, virtual mass, digital mass, common mass, or any other form of ground connection applicable to or suitable for the teachings of this description. Unless otherwise specified, "about," "approximately," or "essentially" before a value means ±10 percent of the stated value or, if the value is zero, a reasonable range of values ​​around zero.

[0050] Modifications of the described embodiments are possible, and other embodiments within the scope of protection of the claims are possible.

[0051] From the foregoing, it is clear that exemplary systems, devices, manufactured articles, and methods have been described that implement delay lines (e.g., delay lines used in analog-to-digital converters) by using a counter to loop a signal multiple times through the same delay circuit elements in a manner that reduces area, power consumption, etc. The described systems, devices, manufactured articles, and methods are also directed toward one or more improvements in the operation of a machine, such as a computer or other electronic, electromechanical, or mechanical device.

Claims

[1] Buffer line device comprising the following: a first delay buffer comprising a clock input, a bias input coupled to a delay control input, a reset input and an output; a second delay buffer comprising a clock input coupled to the output of the first delay buffer, a bias input coupled to the delay control input, a reset input, and an output; and a counter having a clock input coupled to the output of the second delay buffer, a reset output coupled to a clear input of the first delay buffer, the clear input being coupled to the second delay buffer, and an output. [2] Buffer line device according to claim 1, wherein the clock input of the second delay buffer is coupled to the output of the first delay buffer. [3] Buffer line device according to claim 1, which further comprises several delay buffers coupled to the first delay buffer. [4] Buffer line device according to claim 3, wherein the multiple delay buffers comprise fourteen delay buffers. [5] Buffer line device according to claim 1, wherein the counter is a 2-bit counter. [6] Analog / digital converter device comprising the following: an analog delay control input; a signal input; several delay buffers connected in series, with a first delay buffer of the several delay buffers coupled to the signal input; a first counter having a clock input coupled to an output of a final delay buffer in the multiple delay buffers; several flip-flops containing clock inputs, each coupled to the outputs of the delay buffers of the multiple delay buffers; a thermometer-to-binary converter coupled to the outputs of several flip-flops; and Binary data outputs based on an output of the first counter and the outputs of the thermometer-to-binary converter. [7] Analog / digital converter device according to claim 6, wherein the output of the counter includes multiple outputs. [8] Analog / digital converter device according to claim 6, wherein the multiple delay buffers include Xdelay buffers, wherein X=2Y2Z is where Y is a number of bits in the binary data outputs and Z is a number of bits in the first counter. [9] Analog / digital converter device according to claim 6, further comprising: second, several delay buffers connected in series; and a second counter which has a clock input that is coupled to an output of a last buffer in the second set of multiple buffers. [10] Analog / digital converter device according to claim 9, wherein a number of the delay buffers of the multiple delay buffers is equal to a number of delay buffers in the second multiple delay buffers. [11] Analog / digital converter device according to claim 9, further comprising a logic gate coupled to the output of the last buffer in the multiple buffers and to an output of the second counter. [12] Analog / digital converter device according to claim 11, wherein the logic gate is an AND gate. [13] Analog / digital converter device according to claim 9, wherein the first counter and the second counter are 2-bit counters. [14] Analog / digital converter device according to claim 9, further comprising a flip-flop having a clock input coupled to an output of the logic gate and an output. [15] Analog / digital converter device according to claim 9, wherein an output of the second counter is coupled to the clock inputs of the flip-flops. [16] Analog / digital converter device according to claim 6, wherein the binary data outputs include an output of the first counter as the most significant bits and an output of the thermometer-to-binary converter as the least significant bits. [17] Method for converting an analog voltage into a digital value, the method comprising: Repeatedly passing a signal through a first sequence of delay buffers biased by a reference voltage; Repeatedly passing the signal through a second series of delay buffers biased by an input voltage; After the signal has passed through the first sequence of delay buffers a specified number of times, determine the number of delay buffers in the second sequence of delay buffers through which the signal has passed, and the number of loops; and Outputting a binary value based on the number of delay buffers in the second sequence of delay buffers through which the signal has passed, and the number of passes through the second sequence of delay buffers. [18] The method of claim 17, further comprising resetting the first sequence of delay buffers after each iteration through the first sequence of delay buffers. [19] The method of claim 17, further comprising counting the number of passes of the signal through the first sequence of delay buffers. [20] Method according to claim 17, wherein the output of the binary value includes generating the binary value with the most significant bits as a binary value indicating the number of iterations through the second sequence of delay buffers, and the least significant bits as the binary number indicating the number of delay buffers in the second sequence of delay buffers through which the signal has passed.

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