Phase interpolation circuit, receiving circuit, and semiconductor integrated circuit

Abstract

This invention provides a phase interpolation circuit that generates an output clock signal with suppressed phase shift relative to the phase interpolation code. [Solution] A phase interpolation circuit that generates an output clock signal having a phase corresponding to a current control code based on first and second input clock signals having a first phase difference comprises: a first generation circuit that generates a first intermediate current based on the first input clock signal according to the first current control code; a second generation circuit that generates a second intermediate current based on the second input clock signal according to the second current control code; a combining circuit that combines the first and second intermediate currents to generate an output clock signal; and a correction circuit that corrects the amount of current of at least one of the first and second intermediate currents by generating a correction current according to at least one of the first and second current control codes and a correction code set according to the amount of the first phase difference, wherein the correction code is set to a fixed value according to the amount of the first phase difference.

Description

Technical Field

[0001] The present invention relates to a phase interpolation circuit, a receiving circuit, and a semiconductor integrated circuit.

Background Art

[0002] A receiving circuit of a deserializer of a serializer / deserializer (SerDes) acquires data from a high-speed received signal based on a clock signal. In order to adjust the phase of the clock signal so that data can be appropriately acquired from the received signal, there is a phase interpolation (PI) circuit that generates an output clock signal having a desired phase from a plurality of input clock signals. The phase interpolation circuit is used as a phase adjustment circuit of a clock data recovery (CDR) circuit used in the receiving circuit.

[0003] For example, in the receiving circuit of the deserializer, as shown in FIG. 16, a comparator 1604 acquires data DT from a received signal DTIN using a first output clock signal ICKO output from a phase interpolation circuit 1601, and a comparator 1605 acquires a boundary BD from the received signal DTIN using a second output clock signal QCKO output from the phase interpolation circuit 1601. The first output clock signal ICKO and the second output clock signal QCKO have a predetermined phase difference (substantially 90 degrees).

[0004] The phase interpolation circuit 1601 generates output clock signals ICKO and QCKO having phases corresponding to an input phase interpolation (PI) code based on input clock signals ICKI and QCKI, respectively. The phase interpolation circuit 1601 includes a phase interpolation circuit 1602 that generates the first output clock signal ICKO and a phase interpolation circuit 1603 that generates the second output clock signal QCKO. The phase interpolation circuits 1602 and 1603 generate the output clock signals ICKO and QCKO, respectively, by weighting and synthesizing the input clock signals ICKI and QCKI based on the PI code.

[0005] Figure 17 shows an example configuration of conventional phase interpolation circuits 1602 and 1603 (see, for example, Patent Document 1). The drains of transistors 1711, 1722, 1731, and 1742 are connected to the power supply VDD via resistor 1701. The drains of transistors 1711, 1722, 1731, and 1742 are connected to the output terminal OUTP. In addition, the drains of transistors 1712, 1721, 1732, and 1741 are connected to the power supply VDD via resistor 1702. The drains of transistors 1712, 1721, 1732, and 1741 are connected to the output terminal OUTN.

[0006] The gates of transistors 1711 and 1721 are input to the input clock signal ICKIP, and the gates of transistors 1712 and 1722 are input to the input clock signal ICKIN, which is inverse phase to the input clock signal ICKIP. In addition, the gates of transistors 1731 and 1741 are input to the input clock signal QCKIP, which has a predetermined phase difference from the input clock signal ICKIP, and the gates of transistors 1732 and 1742 are input to the input clock signal QCKIN, which is inverse phase to the input clock signal QCKIP. The input clock signals ICKIP and ICKIN correspond to the input clock signal ICKI shown in Figure 16, and the input clock signals QCKIP and QCKIN correspond to the input clock signal QCKI shown in Figure 16.

[0007] The drain of transistor 1713 is connected to the sources of transistors 1711 and 1712, and the drain of transistor 1723 is connected to the sources of transistors 1721 and 1722. Additionally, the drain of transistor 1733 is connected to the sources of transistors 1731 and 1732, and the drain of transistor 1743 is connected to the sources of transistors 1741 and 1742. The sources of transistors 1713, 1723, 1733, and 1743 are grounded.

[0008] The gates of transistors 1713 and 1723 are subjected to gate voltages VGAP and VGAN according to the PI code, and the gates of transistors 1733 and 1743 are subjected to gate voltages VGBP and VGBN according to the PI code. Transistors 1713, 1723, 1733, and 1743 function as current sources that supply current to the corresponding transistors according to the PI code. Depending on the PI code, either transistor 1713 or 1723, and either transistor 1733 or 1743 are driven with a voltage corresponding to the PI code, thereby weighting and combining one of the input clock signals ICKIP and ICKIN with one of the input clock signals QCKIP and QCKIN to generate the output clock signal.

[0009] Here, if there is a phase difference (skew mismatch) between the input clock signals ICKI and QCKI input to the phase interpolation circuit 1601, a phase difference will also occur between the output clock signals ICKO and QCKO. The phases of the output clock signals ICKO and QCKO change linearly according to the PI code, as shown by the dashed lines in Figure 18, and it is preferable that they have a constant phase difference regardless of the PI code. However, as shown by the solid lines 1801 and 1802, they change, and a phase difference occurs depending on the PI code. When the phase difference between the output clock signals ICKO and QCKO changes according to the PI code in this way, it reduces the timing margin of the circuits that use the output clock signals ICKO and QCKO, which hinders high-speed operation.

[0010] One way to avoid this is to provide an input clock correction circuit 1901, which has the same function as the phase interpolation circuit 1601, before the phase interpolation circuit 1601, as shown in Figure 19. The internal circuits 1902 and 1903 of this circuit generate a clock signal that corrects the phase difference based on the input clock signals ICKI and QCKI, and input it to the phase interpolation circuit 1601. This method involves adding a circuit that transmits high-speed signals. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Publication No. 2014-146869 [Patent Document 2] Japanese Patent Publication No. 2016-219916 [Patent Document 3] U.S. Patent Application Publication No. 2016 / 0182216 [Overview of the project] [Problems that the invention aims to solve]

[0012] The object of the present invention is to provide a phase interpolation circuit that generates an output clock signal with suppressed phase shift relative to the phase interpolation code. [Means for solving the problem]

[0013] One embodiment of a phase interpolation circuit is a phase interpolation circuit that generates an output clock signal having a phase corresponding to a first current control code and a second current control code based on a first input clock signal and a second input clock signal having a first phase difference, the circuit comprising: a first generation circuit that generates a first intermediate current based on the first input clock signal according to the first current control code; a second generation circuit that generates a second intermediate current based on the second input clock signal according to the second current control code; a combining circuit that combines the first intermediate current and the second intermediate current to generate the output clock signal; and a correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value, wherein the correction code is set to a fixed value according to the amount of deviation of the first phase difference from a predetermined value. [Effects of the Invention]

[0014] The disclosed phase interpolation circuit can generate an output clock signal with suppressed phase shift with respect to the phase interpolation code.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a diagram showing a configuration example of a phase interpolation circuit in the first embodiment. [Figure 2A] FIG. 2A is a diagram showing a configuration example of a gate voltage control circuit of the phase interpolation circuit in the first embodiment. [Figure 2B] FIG. 2B is a diagram showing a configuration example of a gate voltage control circuit of the phase interpolation circuit in the first embodiment. [Figure 2C] FIG. 2C is a diagram showing a configuration example of a gate voltage control circuit of the phase interpolation circuit in the first embodiment. [Figure 3A] FIG. 3A is a diagram showing a circuit configuration example of the gate voltage control circuit shown in FIG. 2A. [Figure 3B] FIG. 3B is a diagram showing a circuit configuration example of the gate voltage control circuit shown in FIG. 2C. [Figure 4A] FIG. 4A is a diagram for explaining the relationship between the PI code and the current. [Figure 4B] FIG. 4B is a diagram for explaining the correction of the phase difference shift between two clocks. [Figure 5] FIG. 5 is a diagram for explaining a control example of the phase interpolation circuit in the first embodiment. [Figure 6] FIG. 6 is a diagram showing an example of the output phase of the phase interpolation circuit in the first embodiment. [Figure 7] FIG. 7 is a diagram showing a configuration example of a phase interpolation circuit including a skew correction circuit in the first embodiment. [Figure 8A] FIG. 8A is a diagram for explaining the calibration in the first embodiment. [Figure 8B] FIG. 8B is a diagram for explaining the calibration in the first embodiment. [Figure 9A] FIG. 9A is a diagram for explaining the calibration in the first embodiment. [Figure 9B] FIG. 9B is a diagram for explaining calibration in the first embodiment. [Figure 10] FIG. 10 is a diagram showing a configuration example of a phase interpolation circuit in the second embodiment. [Figure 11A] FIG. 11A is a diagram showing a configuration example of a gate voltage control circuit of a phase interpolation circuit in the second embodiment. [Figure 11B] FIG. 11B is a diagram showing a configuration example of a gate voltage control circuit of a phase interpolation circuit in the second embodiment. [Figure 12A] FIG. 12A is a diagram showing a configuration example of a gate voltage control circuit of a phase interpolation circuit in the third embodiment. [Figure 12B] FIG. 12B is a diagram showing a configuration example of a gate voltage control circuit of a phase interpolation circuit in the third embodiment. [Figure 12C] FIG. 12C is a diagram for explaining a control example of a gate voltage control circuit of a phase interpolation circuit in the third embodiment. [Figure 13A] FIG. 13A is a diagram showing a configuration example of a semiconductor integrated circuit to which the phase interpolation circuit in this embodiment is applied. [Figure 13B] FIG. 13B is a diagram showing a configuration example of a variable delay circuit. [Figure 14] FIG. 14 is a diagram showing another configuration example of a semiconductor integrated circuit to which the phase interpolation circuit in this embodiment is applied. [Figure 15] FIG. 15 is a diagram for explaining an example of data reception in this embodiment. [Figure 16] FIG. 16 is a diagram for explaining a reception circuit of a deserializator. [Figure 17] FIG. 17 is a diagram showing a configuration example of a phase interpolation circuit. [Figure 18] FIG. 18 is a diagram for explaining a phase shift in the output of the phase interpolation circuit shown in FIG. 17. [Figure 19] FIG. 19 is a diagram for explaining a reception circuit provided with an input clock correction circuit. [Figure 20] FIG. 20 is a diagram showing a configuration example of a phase interpolation circuit in the fourth embodiment. [Figure 21] Figure 21 shows an example of the configuration of a phase interpolation circuit in the fifth embodiment. [Figure 22] Figure 22 shows an example of the configuration of a phase interpolation circuit in the sixth embodiment. [Figure 23] Figure 23 shows an example of the configuration of a phase interpolation circuit in the sixth embodiment. [Modes for carrying out the invention]

[0016] Embodiments of the present invention will be described below with reference to the drawings.

[0017] (First embodiment) A first embodiment of the present invention will be described. Figure 1 shows an example of the configuration of a phase interpolation circuit in the first embodiment. The phase interpolation circuit in the first embodiment includes resistors 101 and 102, and transistors 111-113, 121-123, 131-134, and 141-144. Transistors 111-113, 121-123, 131-134, and 141-144 are, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0018] The drains of transistors 111, 122, 131, and 142 are connected to the power supply VDD via the load resistor 101. The connection points between the drains of transistors 111, 122, 131, and 142 and resistor 101 are connected to the output terminal OUTP. The drains of transistors 112, 121, 132, and 141 are connected to the power supply VDD via the load resistor 102. The connection points between the drains of transistors 112, 121, 132, and 141 and resistor 102 are connected to the output terminal OUTN.

[0019] The input clock signal ICKIP is input to the gate of transistor 111, and the input clock signal ICKIN, which is inverse phase to the input clock signal ICKIP, is input to the gate of transistor 112. The sources of transistor 111 and transistor 112 are connected in common to the drain of transistor 113. The source of transistor 113 is grounded, and a gate voltage VGAP is applied to the gate of transistor 113 according to the phase interpolation (PI) code. Transistor 113 functions as a current source, supplying current to transistors 111 and 112 according to the PI code.

[0020] The input clock signal ICKIP is input to the gate of transistor 121, and the input clock signal ICKIN is input to the gate of transistor 122. The sources of transistor 121 and transistor 122 are connected in common to the drain of transistor 123. The source of transistor 123 is grounded, and the gate voltage VGAN is applied to the gate of transistor 123 according to the PI code. Transistor 123 functions as a current source, supplying current to transistors 121 and 122 according to the PI code.

[0021] In the example shown in Figure 1, transistors 111, 112, 121, 122 and transistors 113, 123 described above are an example of a first generation circuit that generates a first intermediate current at the connection point with resistors 101, 102 based on the first input clock signals ICKIP, ICKIN according to the PI code.

[0022] Furthermore, an input clock signal QCKIP having a predetermined phase difference with the input clock signal ICKIP is input to the gate of transistor 131, and an input clock signal QCKIN, which is in the opposite phase to the input clock signal QCKIP, is input to the gate of transistor 132. The sources of transistor 131 and transistor 132 are commonly connected to the drains of transistor 133 and transistor 134. The sources of transistor 133 and transistor 134 are grounded, and a gate voltage VGBP is applied to the gate of transistor 133 according to the PI code, and a gate voltage VGCP is applied to the gate of transistor 134 according to the PI code and correction code. Transistor 133 functions as a current source that supplies current to transistors 131 and 132 according to the PI code, and transistor 134 functions as a current source that supplies current to transistors 131 and 132 according to the PI code and correction code.

[0023] The input clock signal QCKIP is input to the gate of transistor 141, and the input clock signal QCKIN is input to the gate of transistor 142. The sources of transistor 141 and transistor 142 are connected in common to the drains of transistor 143 and transistor 144. The sources of transistors 143 and 144 are grounded, and a gate voltage VGBN is applied to the gate of transistor 143 according to the PI code, and a gate voltage VGCN is applied to the gate of transistor 144 according to the PI code and correction code. Transistor 143 functions as a current source that supplies current to transistors 141 and 142 according to the PI code, and transistor 144 functions as a current source that supplies current to transistors 141 and 142 according to the PI code and correction code.

[0024] In the example shown in Figure 1, transistors 131, 132, 141, 142 and transistors 133, 143 are an example of a second generation circuit that generates a second intermediate current at the connection point with resistors 101, 102 based on the second input clock signals QCKIP, QCKIN according to the PI code.

[0025] In the example shown in Figure 1, the connection points between resistor 101 and the drains of transistors 111, 122, 131, and 142 and resistor 101, as well as the connection points between resistor 102 and the drains of transistors 112, 121, 132, and 141 and resistor 102, are examples of a combining circuit that combines the first intermediate current and the second intermediate current described above to generate an output clock signal at the output terminals OUTP and OUTN.

[0026] In the example shown in Figure 1, transistors (134, 144) that function as current sources that supply current according to the correction code are placed on the side of transistors 133, 143 that function as current sources that supply current according to the PI code (the side of the second intermediate current). However, they may also be placed on the side of transistors 113, 123 that similarly function as current sources that supply current according to the PI code (the side of the first intermediate current), or they may be placed on both sides.

[0027] Figure 2A shows an example of the configuration of a gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of transistors 113 and 123 shown in Figure 1. As shown in Figure 2A, the gate voltage control circuit includes a current DAC (digital-to-analog converter) 201, a transistor 202, and a switch 203.

[0028] The current DAC201 outputs a current corresponding to the absolute value of the code value of the input current control code PIA. The current control code PIA is set based on the PI code for the phase interpolation circuit and is a code for controlling the current flowing through transistors 113 and 123, which function as current sources related to the input clock signals ICKIP and ICKIN, in accordance with the PI code. Transistor 202 is diode-connected between the output terminal of the current DAC201 and ground. That is, the output terminal of the current DAC201 is connected to the drain and gate of transistor 202, and the source of transistor 202 is grounded.

[0029] Switch 203 is connected to the gate of transistor 202 and outputs the voltage generated by inputting the output current of DAC201 to diode-connected transistor 202 as a gate voltage VGAP or VGAN, depending on the sign of the current control code PIA. When the current control code PIA is positive, switch 203 outputs a voltage corresponding to the current control code PIA generated by the current DAC201 and diode-connected transistor 202 as a gate voltage VGAP to the gate of transistor 113. When the current control code PIA is negative, switch 203 outputs a voltage corresponding to the current control code PIA generated by the current DAC201 and diode-connected transistor 202 as a gate voltage VGAN to the gate of transistor 123.

[0030] Figure 2B shows an example configuration of a gate voltage control circuit that controls the gate voltages VGBP and VGBN applied to the gates of transistors 133 and 143 shown in Figure 1. As shown in Figure 2B, the gate voltage control circuit includes a current DAC 211, a transistor 212, and a switch 213.

[0031] The current DAC211 outputs a current corresponding to the absolute value of the code value of the input current control code PIB. The current control code PIB is set based on the PI code for the phase interpolation circuit and is a code for controlling the current flowing through transistors 133 and 143, which function as current sources related to the input clock signals QCKIP and QCKIN, in accordance with the PI code. Transistor 212 is diode-connected between the output terminal of the current DAC211 and ground. That is, the output terminal of the current DAC211 is connected to the drain and gate of transistor 212, and the source of transistor 212 is grounded.

[0032] Switch 213 is connected to the gate of transistor 212 and outputs the voltage generated by inputting the output current of DAC211 to diode-connected transistor 212 as a gate voltage VGBP or VGBN, depending on the sign of the current control code PIB. When the current control code PIB is positive, switch 213 outputs a voltage corresponding to the current control code PIB generated by the current DAC211 and diode-connected transistor 212 as a gate voltage VGBP to the gate of transistor 133. When the current control code PIB is negative, switch 213 outputs a voltage corresponding to the current control code PIB generated by the current DAC211 and diode-connected transistor 212 as a gate voltage VGBN to the gate of transistor 143.

[0033] In this specification, we describe an example where the current control code PIA and current control code PIB are integer values ​​in the range of (-16) to (+16). In this case, as the output phase of the clock signal, 32 PI codes allow for phase control within a range of 180 degrees, and 64 PI codes allow for phase control within a range of 360 degrees. This is just one example, and the present invention is not limited thereto. The number of PI codes (current control code PIA and current control code PIB) is arbitrary, and by increasing the number of codes, finer phase control is possible.

[0034] Figure 2C shows an example configuration of a gate voltage control circuit that controls the gate voltages VGCP and VGCN applied to the gates of transistors 134 and 144 shown in Figure 1. As shown in Figure 2C, the gate voltage control circuit includes a current DAC 221, transistors 222, 223, and 224, and a switch 225.

[0035] The current DAC221 outputs a current corresponding to the absolute value of the code value of the input correction code CAL. The correction code CAL is a code related to the correction current that flows to reduce the phase error of the output clock signal. The source of transistor 222 is connected to the power supply VDD, and its drain and gate are connected to the output terminal of the current DAC221. The source of transistor 223 is connected to the power supply VDD, and its gate is connected to the gate of transistor 222. Transistors 222 and 223 constitute a current mirror circuit. The mirror ratio k of the current mirror circuit composed of transistors 222 and 223 is changeable and is controlled to change in proportion to the current control code PIA. Therefore, from the drain of transistor 223, a current (|C|) is output that is k times the output current (|C0|) of the current DAC221 corresponding to the correction code CAL, according to the current control code PIA.

[0036] Transistor 224 is diode-connected between the drain of transistor 223 and ground. That is, the drain of transistor 223 is connected to the drain and gate of transistor 224, and the source of transistor 224 is grounded.

[0037] Switch 225 is connected to the gate of transistor 224 and outputs a voltage to the diode-connected transistor 224 that is input to a current k times the output current of DAC 211, as a gate voltage VGCP or VGCN depending on the sign of the multiplication value of the correction code CAL and the current control code PIA. If the multiplication value of the correction code CAL and the current control code PIA is positive, switch 225 outputs a voltage corresponding to the correction code CAL and the current control code PIA generated by the diode-connected transistor 224 as a gate voltage VGCP to the gate of transistor 134. If the multiplication value of the correction code CAL and the current control code PIA is negative, switch 225 outputs a voltage corresponding to the correction code CAL and the current control code PIA generated by the diode-connected transistor 224 as a gate voltage VGCN to the gate of transistor 144.

[0038] In the example shown in Figure 1, the transistors 134 and 144 described above and the gate voltage control circuit shown in Figure 2C are an example of a correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current based on a correction current corresponding to the correction code.

[0039] Figure 3A shows an example of the circuit configuration of the gate voltage control circuit shown in Figure 2A. The output terminal of the current DAC301, which outputs a current corresponding to the absolute value of the code value of the input current control code PIA, is connected to the drain and gate of transistor 302, and the source of transistor 302 is grounded. The gate of transistor 302 is connected to the output terminal of the gate voltage VGAP via a transfer gate composed of transistors 303 and 304. The connection point between the transfer gate composed of transistors 303 and 304 and the output terminal of the gate voltage VGAP is grounded via transistor 305. In addition, the gate of transistor 302 is connected to the output terminal of the gate voltage VGAN via a transfer gate composed of transistors 306 and 307. The connection point between the transfer gate composed of transistors 306 and 307 and the output terminal of the gate voltage VGAN is grounded via transistor 308.

[0040] The transfer gates composed of transistors 303 and 304, the transfer gate composed of transistors 305, 306 and 307, and transistor 308 are controlled to switch between conduction and non-conduction states by the signal PIAS and its inverted signal / PIAS. The signal PIAS is a signal indicating the sign of the current control code PIA. When the current control code PIA is positive, the signal PIAS is high level (the inverted signal / PIAS is low level), and when the current control code PIA is negative, the signal PIAS is low level (the inverted signal / PIAS is high level).

[0041] When the signal PIAS is at a high level (inverted signal / PIAS is at a low level), that is, when the current control code PIA is positive, the transfer gate composed of transistors 303 and 304 and transistor 308 are in a conductive state (on state), while the transfer gate composed of transistors 305 and transistors 306 and 307 is in a non-conductive state (off state). Therefore, when the sign of the current control code PIA is positive, a voltage corresponding to the current control code PIA is output as the gate voltage VGAP, and the gate voltage VGAN is at ground potential.

[0042] Furthermore, when the signal PIAS is low level (inverted signal / PIAS is high level), that is, when the current control code PIA is negative, the transfer gate composed of transistors 305 and transistors 306 and 307 is in a conductive state (on state), while the transfer gate composed of transistors 303 and 304 and transistor 308 are in a non-conductive state (off state). Therefore, when the sign of the current control code PIA is negative, a voltage corresponding to the current control code PIA is output as the gate voltage VGAN, and the gate voltage VGAP is at ground potential. The gate voltage control circuit shown in Figure 2B is configured similarly.

[0043] Figure 3B shows an example of the circuit configuration of the gate voltage control circuit shown in Figure 2C. The output terminal of the current DAC311, which outputs a current corresponding to the absolute value of the code value of the input correction code CAL, is connected to the drain and gate of transistor 312, and the source of transistor 312 is connected to the power supply VDD. The source of transistor 313-i (i is an integer from 0 to 4; the same applies below) is connected to the power supply VDD, and its gate is connected to the gate of transistor 312 via switch 314-i. When the corresponding switches 314-i are in the conducting state (on state), transistors 313-0 and 313-1 are configured to flow (1 / 16) times the Miller current, and transistor 313-2 is configured to flow (2 / 16) times the Miller current. Similarly, transistor 313-3 is configured to flow (4 / 16) times the Miller current, and transistor 313-4 is configured to flow (8 / 16) times the Miller current. Switch 314-i is switched on / off by a control signal CTL based on the current control code PIA, such that the mirror ratio of the current mirror circuit composed of transistors 312 and 313-i changes in proportion to the current control code PIA.

[0044] The drain of transistor 313-i is connected to the drain and gate of transistor 315, and the source of transistor 315 is grounded. The gate of transistor 315 is connected to the output terminal of the gate voltage VGCP via a transfer gate composed of transistors 316 and 317. The connection point between the transfer gate composed of transistors 316 and 317 and the output terminal of the gate voltage VGCP is grounded via transistor 318. In addition, the gate of transistor 315 is connected to the output terminal of the gate voltage VGCN via a transfer gate composed of transistors 319 and 320. The connection point between the transfer gate composed of transistors 319 and 320 and the output terminal of the gate voltage VGCN is grounded via transistor 321.

[0045] The transfer gates composed of transistors 316 and 317, the transfer gate composed of transistors 318, 319 and 320, and transistor 321 are controlled to switch between conduction and non-conduction states by the signal CALS and its inverted signal / CALS. The signal CALS is a signal that indicates the sign of the product of the correction code CAL and the current control code PIA. When the product of the correction code CAL and the current control code PIA is positive, the signal CALS is high level (the inverted signal / CALS is low level), and when the product of the correction code CAL and the current control code PIA is negative, the signal CALS is low level (the inverted signal / CALS is high level).

[0046] When the CALS signal is at a high level (inverted signal / CALS is at a low level), that is, when the product of the correction code CAL and the current control code PIA is positive, the transfer gate composed of transistors 316 and 317 and transistor 321 are in a conductive state (on state), while the transfer gate composed of transistors 318 and transistors 319 and 320 is in a non-conductive state (off state). Therefore, when the sign of the product of the correction code CAL and the current control code PIA is positive, a voltage corresponding to the correction code CAL and the current control code PIA is output as the gate voltage VGCP, and the gate voltage VGCN is at ground potential.

[0047] Furthermore, when the CALS signal is low level (inverted signal / CALS is high level), that is, when the product of the correction code CAL and the current control code PIA is negative, the transfer gate composed of transistors 318, 319, and 320 is in a conductive state (on state), while the transfer gate composed of transistors 316 and 317 and transistor 321 are in a non-conductive state (off state). Therefore, when the sign of the product of the correction code CAL and the current control code PIA is negative, a voltage corresponding to the correction code CAL and the current control code PIA is output as the gate voltage VGCN, and the gate voltage VGCP becomes the ground potential.

[0048] Next, the operation of the phase interpolation circuit in this embodiment will be described. The current DACs 201 and 211 of the gate voltage control circuit shown in Figures 2A and 2B output currents having the absolute values ​​of currents I_A and I_B, respectively, as shown by solid lines 401 and 402 in Figure 4A, according to the PI code. For the sake of explanation, the current DACs 201 and 211 are assumed to output a current with a relative value of 16 when the absolute values ​​of the input current control codes PIA and PIB are at their maximum (16), and to output a current with a relative value of 0 (no output current) when the absolute values ​​of the input current control codes PIA and PIB are at their minimum (0).

[0049] The current output from current DAC201 is converted to a voltage by diode-connected transistor 202, and the converted voltage is supplied to one gate of transistors 113 and 123, which function as current sources, according to the sign of the current control code PIA. Similarly, the current output from current DAC211 is converted to a voltage by diode-connected transistor 212, and the converted voltage is supplied to one gate of transistors 133 and 143, which function as current sources, according to the sign of the current control code PIB.

[0050] For example, if the PI code is 8 (output phase 45 degrees), the current control code PIA is (+8). Therefore, the current DAC201 of the gate voltage control circuit shown in Figure 2A outputs a current with a relative value of 8 corresponding to the absolute value of the current control code PIA, and since the sign of the current control code PIA is positive, the voltage corresponding to the current with a relative value of 8 is supplied to the gate of transistor 113 as the gate voltage VGAP. Also, if the PI code is 8, the current control code PIB is (+8). Therefore, the current DAC211 of the gate voltage control circuit shown in Figure 2B outputs a current with a relative value of 8 corresponding to the absolute value of the current control code PIB, and since the sign of the current control code PIB is positive, the voltage corresponding to the current with a relative value of 8 is supplied to the gate of transistor 133 as the gate voltage VGBP. At this time, the gate of transistor 123 is supplied with ground potential as the gate voltage VGAN, and the gate of transistor 143 is supplied with ground potential as the gate voltage VGBN.

[0051] Furthermore, for example, if the PI code is 16 (output phase 90 degrees), the current control code PIA is (0), so the current DAC201 of the gate voltage control circuit shown in Figure 2A outputs a current with a relative value of 0 corresponding to the absolute value of the current control code PIA (no output current), and the voltage corresponding to a current with a relative value of 0 (ground potential) is supplied to the gate of transistor 113 as the gate voltage VGAP. Also, if the PI code is 16, the current control code PIB is (+16), so the current DAC211 of the gate voltage control circuit shown in Figure 2B outputs a current with a relative value of 16 corresponding to the absolute value of the current control code PIB (16), and since the sign of the current control code PIB is positive, the voltage corresponding to a current with a relative value of 16 is supplied to the gate of transistor 133 as the gate voltage VGBP. At this time, the gate of transistor 123 is supplied with the ground potential as the gate voltage VGAN, and the gate of transistor 143 is supplied with the ground potential as the gate voltage VGBN.

[0052] Furthermore, for example, if the PI code is 32 (output phase 180 degrees), the current control code PIA is (-16). Therefore, the current DAC201 of the gate voltage control circuit shown in Figure 2A outputs a current with a relative value of 16 corresponding to the absolute value of the current control code PIA, which is 16. Since the sign of the current control code PIA is negative, the voltage corresponding to a current with a relative value of 16 is supplied to the gate of transistor 123 as the gate voltage VGAN. Also, if the PI code is 32, the current control code PIB is 0. Therefore, the current DAC211 of the gate voltage control circuit shown in Figure 2B outputs a current with a relative value of 0 corresponding to the absolute value of the current control code PIB, which is 0 (no output current). The voltage corresponding to a current with a relative value of 0 (ground potential) is supplied to the gate of transistor 133 as the gate voltage VGBP. At this time, the ground potential is supplied to the gate of transistor 113 as the gate voltage VGAP, and the ground potential is supplied to the gate of transistor 143 as the gate voltage VGBN.

[0053] Therefore, when the PI code is between 0 and 16, that is, when the current control code PIA is positive and the current control code PIB is positive, transistors 113 and 133 of the phase interpolation circuit operate as current sources that supply current based on the PI code. As a result, transistor 111 generates and outputs an intermediate current based on the input clock signal ICKIP, and transistor 112 generates and outputs an intermediate current based on the input clock signal ICKIN. Similarly, transistor 131 generates and outputs an intermediate current based on the input clock signal QCKIP, and transistor 132 generates and outputs an intermediate current based on the input clock signal QCKIN. The intermediate currents output from transistor 111 and transistor 131 are combined on the node to form a signal which is output as the output clock signal from output terminal OUTP. The intermediate currents output from transistor 112 and transistor 132 are combined on the node to form a signal which is output as the output clock signal (inverted phase output clock signal) from output terminal OUTN. In this way, the input clock signals ICKI (ICKIP, ICKIN) and QCKI (QCKIP, QCKIN) are weighted according to the phase interpolation (PI) code and combined to generate the output clock signal.

[0054] Furthermore, when the PI code is between 17 and 32, that is, when the current control code PIA is negative and the current control code PIB is positive, transistors 123 and 133 of the phase interpolation circuit operate as current sources that supply current based on the PI code. As a result, transistor 121 generates and outputs an intermediate current based on the input clock signal ICKIP, and transistor 122 generates and outputs an intermediate current based on the input clock signal ICKIN. Transistor 131 generates and outputs an intermediate current based on the input clock signal QCKIP, and transistor 132 generates and outputs an intermediate current based on the input clock signal QCKIN. The intermediate currents output from transistor 122 and transistor 131 are combined on the node to form a signal which is output as the output clock signal from output terminal OUTP. The intermediate currents output from transistor 121 and transistor 132 are combined on the node to form a signal which is output as the output clock signal (inverted phase output clock signal) from output terminal OUTN.

[0055] The same applies when the PI code is 33-48 or 49-64. That is, when the PI code is 33-48, the current control code PIA is negative and the current control code PIB is negative, so transistors 123 and 143 of the phase interpolation circuit act as current sources that supply current based on the PI code, and the output clock signal is generated in the same way. Also, when the PI code is 49-64, the current control code PIA is positive and the current control code PIB is negative, so transistors 113 and 143 of the phase interpolation circuit act as current sources that supply current based on the PI code, and the output clock signal is generated in the same way.

[0056] Furthermore, in the phase interpolation circuit of this embodiment, a correction current is applied to adjust the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees). In the phase interpolation circuit shown in Figure 1, transistors 134 and 144 function as current sources that supply the correction current. In this embodiment, as shown in Figure 4B, the phase error of the output clock signal ICKO is measured with the output clock signal QCKO as a reference, and the phase difference of the output clock signals (ICKO, QCKO) is adjusted by applying a correction current to correct the phase of the output clock signal ICKO so that the phase error becomes smaller. The amount of the correction current is determined by setting it to a predetermined PI code and measuring the phase of the output clock signal to determine the correction code for supplying the correction current, and then adjusting it by changing the mirror ratio of the current mirror circuit in the gate voltage control circuit according to the current control code PIA set based on the PI code.

[0057] For example, if the determined correction code CAL is (-8), the current DAC221 of the gate voltage control circuit shown in Figure 2C outputs a current with a relative value of 8, corresponding to the absolute value of the correction code CAL, which is 8. Therefore, the current mirror circuit composed of transistors 222 and 223 outputs a correction current I_Bcal, shown by the solid line 403 in Figure 4A, according to the PI code. The output correction current I_Bcal is converted into a voltage by the diode-connected transistor 224, and the converted voltage is supplied to one of the gates of transistors 134 and 144, which function as current sources, according to the sign of the multiplication value of the correction code CAL and the current control code PIA.

[0058] For example, when the PI code is 8, the current control code PIA is (+8). The gate voltage control circuit shown in Figure 2C generates a current of relative value 4 (=8 × 8 / 16) obtained by multiplying the absolute value of the correction code CAL (8) by a ratio corresponding to the current control code PIA, i.e., the ratio of the current absolute value of the current control code PIA (8) to its maximum value (16). Since the sign of the product of the correction code CAL and the current control code PIA is negative, the voltage corresponding to the generated current is supplied to the gate of transistor 144 as the gate voltage VGCN. Also, when the PI code is 16, the current control code PIA is (0). The gate voltage control circuit shown in Figure 2C supplies a voltage (ground potential) corresponding to a current of relative value 0 (=8 × 0 / 16) to the gate of transistor 134 as the gate voltage VGCP. Furthermore, if the PI code is 32, the current control code PIA is (-16). Therefore, the gate voltage control circuit shown in Figure 2C generates a current of relative value 8 (=8 × 16 / 16) based on the ratio of the current absolute value (16) of the current control code PIA to its maximum value (16), for example, based on the absolute value (8) of the correction code CAL. Since the sign of the product of the correction code CAL and the current control code PIA is positive, the voltage corresponding to the generated current is supplied to the gate of transistor 134 as the gate voltage VGCP.

[0059] As described above, in the phase interpolation circuit of this embodiment, control is performed according to the PI code as shown in Figure 5 as an example. As a result, the amount of intermediate current output from transistors 131, 132, 141, and 142 is corrected based on the correction code and the correction current corresponding to the PI code, and the phase of the output clock signal obtained by combining the intermediate currents is adjusted. In this way, the phase interpolation circuit of this embodiment adjusts the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees). As a result, the phases of the respective output clock signals (ICKO, QCKO) change as shown by solid lines 601 and 602 in Figure 6, for example, and the phase difference shift in the output clock signals (ICKO, QCKO) can be suppressed. Therefore, it is possible to suppress the reduction in the timing margin of the circuit using the output clock signals (ICKO, QCKO) and to achieve high-speed operation.

[0060] Next, the method for determining the correction code will be explained with reference to Figures 7 to 9B. Figure 7 is a diagram showing an example configuration of a phase interpolation circuit including a skew correction circuit in the first embodiment. In Figure 7, the phase interpolation circuit 701 generates output clock signals ICKO and QCKO, respectively, which have phases corresponding to the input PI code, based on the input clock signals ICKI and QCKI. The phase interpolation circuit 701 includes a phase interpolation circuit 702 that generates a first output clock signal ICKO and a phase interpolation circuit 703 that generates a second output clock signal QCKO. The phase interpolation circuits 702 and 703 are configured as shown in Figures 1 to 2C, and generate output clock signals ICKO and QCKO, respectively, by weighting and combining the input clock signals ICKI and QCKI based on the PI code. The input clock signals ICKI and QCKI, and the output clock signals ICKO and QCKO, are each composed of a pair of complementary signals consisting of a non-inverting signal (ICKIP, QCKIP, ICKOP, QCKOP) and an inverting signal (ICKIN, QCKIN, ICKON, QCKON).

[0061] Comparator 704 acquires data DT from the input signal using the first output clock signal ICKO (ICKOP, ICKON) output from the phase interpolation circuit 701. Comparator 705 acquires boundary BD from the input signal using the second output clock signal QCKO (QCKOP, QCKON) output from the phase interpolation circuit 701. Either the received signal DTIN or the internal data signal dataQ is input to comparators 704 and 705 via selector 708. Normally, the received signal DTIN is input to comparators 704 and 705, and when the correction code is determined (during calibration operation), the internal data signal dataQ is input to comparators 704 and 705.

[0062] The frequency divider circuit 706 divides the second output clock signal QCKO (QCKOP, QCKON) output from the phase interpolation circuit 701 by two. The variable delay circuit 707 delays the output clock signal QCKOP from the second output clock signal QCKO divided by the frequency divider circuit 706 and outputs it as an internal data signal dataQ. The internal data signal dataQ has half the frequency of the output clock signal QCKOP.

[0063] In determining the correction code, the PI code is first set to 16. This causes the phase interpolation circuit 701 to generate output clock signals ICKO and QCKO, respectively, based on the input clock signals ICKI and QCKI, each having a phase (output phase of 90 degrees) corresponding to the PI code. The selector 708 outputs the internal data signal dataQ, i.e., the divided output clock signal QCKOP via the variable delay circuit 707. The comparator 704 then performs edge detection of the internal data signal dataQ. At this time, based on the data DT acquired by the comparator 704 using the output clock signal ICKOP within the output clock signal ICKO, and the data DT acquired by the comparator 704 using the output clock signal ICKON, the CDR circuit (described later) is used to determine whether the phases of the output clock signals ICKOP and ICKON are leading or lagging the internal data signal dataQ. The delay amount of the variable delay circuit 707 is then adjusted to converge the rising edge of the output clock signal ICKOP to the edge of the internal data signal dataQ, as shown in Figure 8A. While this PI code is set to 16, the correction code is kept at 0, and no correction current is supplied.

[0064] Next, the PI code is set to 0. As a result, the phase interpolation circuit 701 generates output clock signals ICKO and QCKO, respectively, which have a phase (output phase 0 degrees) corresponding to the PI code, based on the input clock signals ICKI and QCKI. The selector 708 also outputs the internal data signal dataQ, which is the divided output clock signal QCKOP via the variable delay circuit 707. Here, the delay amount of the variable delay circuit 707 is fixed to the delay amount when the PI code is set to 16 and the rising edge of the output clock signal ICKOP converges to the edge of the internal data signal dataQ. Then, the comparator 704 is used to detect the edge of the internal data signal dataQ. At this time, based on the data DT acquired by comparator 704 using the output clock signal ICKOP from the output clock signal ICKO, and the data DT acquired by comparator 704 using the output clock signal ICKON, for example, using the CDR circuit described later, it is determined whether the phases of the output clock signals ICKOP and ICKON are leading or lagging the internal data signal dataQ, and the amount of correction current is adjusted by changing the correction code, so that the rising edge of the input clock signal ICKOP converges to the edge of the internal data signal dataQ, as shown in Figure 8B.

[0065] As shown in Figure 9A, the phase relationship between the output clock signals ICKO and QCKO in the above operation is as follows. By setting the PI code to 0 and applying half the amount of correction current when the rising edge of the input clock signal ICKOP is converged to the edge of the internal data signal dataQ, the phase difference between the corrected output clock signals ICKO and QCKO becomes 90 degrees, as shown in Figure 9B. Therefore, the correction code used in normal operation should be determined to be half the value of the correction code when the PI code is set to 0 and the rising edge of the input clock signal ICKOP is converged to the edge of the internal data signal dataQ.

[0066] (Second embodiment) Next, a second embodiment will be described. In the first embodiment, the current sources for the input clock signals ICKI (ICKIP, ICKIN) are transistors 113 and 123, and the current sources for the input clock signals QCKI (QCKIP, QCKIN) are transistors 133 and 143 in addition to transistors 134 and 144. In other words, the phase interpolation circuit in the first embodiment has a difference in circuit configuration as a differential pair.

[0067] In the second embodiment, the current corresponding to the current control code PIB is combined with the current corresponding to the correction code CAL and the current control code PIA, and a voltage corresponding to the combined current is supplied to the gate of a transistor that functions as a current source. This makes it possible to operate each with a single current source, and the differential pair in the phase interpolation circuit can be configured similarly. This reduces the layout size of the differential pair and suppresses the increase in capacitive load in the differential pair.

[0068] Figure 10 shows an example of the configuration of a phase interpolation circuit in the second embodiment. In Figure 10, components having the same function as those shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit in the second embodiment includes resistors 101 and 102, and transistors 111-113, 121-123, 131-132, 141-142, 1031, and 1041. Transistors 111-113, 121-123, 131-132, 141-142, 1031, and 1041 are, for example, N-type MOSFETs.

[0069] The sources of transistor 131 and transistor 132 are connected in common to the drain of transistor 1031. The source of transistor 1031 is grounded, and a gate voltage VGBP' is applied to its gate according to the PI code and correction code. Transistor 1031 functions as a current source, supplying current to transistors 131 and 132 according to the PI code and correction code.

[0070] The sources of transistor 141 and transistor 142 are connected in common to the drain of transistor 1041. The source of transistor 1041 is grounded, and a gate voltage VGBN' is applied to its gate according to the PI code and correction code. Transistor 1041 functions as a current source, supplying current to transistors 141 and 142 according to the PI code and correction code.

[0071] In the example shown in Figure 10, transistors 131, 132, 141, 142 and transistors 1031, 1041 described above are an example of a second generation circuit that generates a second intermediate current at the connection point with resistors 101, 102 based on the second input clock signals QCKIP, QCKIN according to the PI code.

[0072] Figure 11A shows an example of the configuration of a gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of transistors 113 and 123 shown in Figure 10. As shown in Figure 11A, the gate voltage control circuit includes a current DAC 1101, a switch 1102, and transistors 1103 and 1104.

[0073] The current DAC 1101 outputs a current corresponding to the absolute value of the code value of the input current control code PIA. The switch 1102 is controlled according to the sign of the current control code PIA; when the current control code PIA is positive, it connects the first terminal TMA1 to the second terminal TMB1, and when the current control code PIA is negative, it connects the first terminal TMA1 to the third terminal TMC1. The first terminal TMA1 of the switch 1102 is connected to the output terminal of the current DAC 1101.

[0074] Transistor 1103 is diode-connected between the second terminal TMB1 of switch 1102 and ground. That is, the drain and gate of transistor 1103 are connected to the second terminal TMB1 of switch 1102, and the source of transistor 1103 is grounded. Transistor 1104 is diode-connected between the third terminal TMC1 of switch 1102 and ground. That is, the drain and gate of transistor 1104 are connected to the third terminal TMC1 of switch 1102, and the source of transistor 1104 is grounded. The voltage generated by diode-connected transistor 1103 is output as the gate voltage VGAP, and the voltage generated by diode-connected transistor 1104 is output as the gate voltage VGAN.

[0075] Figure 11B shows an example configuration of a gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of transistors 1031 and 1041 shown in Figure 10. As shown in Figure 11B, the gate voltage control circuit includes current DACs 1111 and 1116, transistors 1112, 1113-i, 1118, and 1119, and switches 1114-i, 1115, and 1117.

[0076] The current DAC1111 outputs a current corresponding to the absolute value of the code value of the input correction code CAL. The source of transistor 1112 is connected to the power supply VDD, and its drain and gate are connected to the output terminal of the current DAC1111.

[0077] The source of transistor 1113-i is connected to the power supply VDD, and its gate is connected to the gate of transistor 1112 via switch 1114-i. When the corresponding switch 1114-i is conducting (on), transistors 1113-0 and 1113-1 are configured to flow (1 / 16) times the Miller current, and transistor 1113-2 is configured to flow (2 / 16) times the Miller current. Similarly, transistor 1113-3 is configured to flow (4 / 16) times the Miller current, and transistor 1113-4 is configured to flow (8 / 16) times the Miller current. Switch 1114-i is turned on / off by a control signal CTL based on the current control code PIA, so that the Miller ratio of the current mirror circuit composed of transistors 1112 and 1113-i changes in proportion to the current control code PIA.

[0078] Switch 1115 is controlled according to the sign of the product of the correction code CAL and the current control code PIA. If the product of the correction code CAL and the current control code PIA is positive, it connects the first terminal TMA2 and the second terminal TMB2. If the product of the correction code CAL and the current control code PIA is negative, it connects the first terminal TMA2 and the third terminal TMC2. The drain of transistor 1113-i is commonly connected to the first terminal TMA2 of switch 1115.

[0079] The current DAC 1116 outputs a current corresponding to the absolute value of the code value of the input current control code PIB. The switch 1117 is controlled according to the sign of the current control code PIB; when the current control code PIB is positive, it connects the first terminal TMA3 to the second terminal TMB3, and when the current control code PIB is negative, it connects the first terminal TMA3 to the third terminal TMC3. The first terminal TMA3 of the switch 1117 is connected to the output terminal of the current DAC 1116.

[0080] The second terminal TMB2 of switch 1115 is connected to the second terminal TMB3 of switch 1117. The third terminal TMC2 of switch 1115 is connected to the third terminal TMC3 of switch 1117.

[0081] Transistor 1118 is diode-connected between the connection point between the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117 and ground. That is, the drain and gate of transistor 1118 are connected to the connection point between the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117, and the source of transistor 1118 is grounded. Transistor 1119 is diode-connected between the connection point between the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117 and ground. That is, the drain and gate of transistor 1119 are connected to the connection point between the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117, and the source of transistor 1119 is grounded.

[0082] In this configuration, the current corresponding to the correction code CAL and the current control code PIA, and the current corresponding to the current control code PIB, are combined at the connection point between the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117. Based on the combined current, the voltage generated by the diode-connected transistor 1118 is output as the gate voltage VGBP'. Additionally, the current corresponding to the correction code CAL and the current control code PIA, and the current corresponding to the current control code PIB, are combined at the connection point between the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117. Based on the combined current, the voltage generated by the diode-connected transistor 1119 is output as the gate voltage VGBN'.

[0083] In the example shown in Figure 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in Figure 11B are an example of a correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current based on a correction current corresponding to the correction code.

[0084] In the second embodiment as well, the amount of intermediate current output from transistors 131, 132, 141, and 142 is corrected based on the correction current corresponding to the correction code and PI code, and the phase of the output clock signal obtained by combining the intermediate currents is adjusted. As a result, the phase interpolation circuit adjusts the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees), thereby suppressing the phase difference deviation in the output clock signals (ICKO, QCKO). Therefore, it is possible to suppress the reduction in the timing margin of circuits using the output clock signals (ICKO, QCKO) and to achieve high-speed operation.

[0085] (Third embodiment) Next, a third embodiment will be described. The configuration of the phase interpolation circuit in the third embodiment is the same as that of the phase interpolation circuit in the second embodiment shown in Figure 10. Also, in the third embodiment, the configuration of the gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of transistors 113 and 123 shown in Figure 10 is the same as that of the second embodiment shown in Figure 11A. In the third embodiment, the gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of transistors 1031 and 1041 shown in Figure 10 differs from that of the second embodiment described above. The gate voltage control circuit that controls the gate voltages VGBP' and VGBN' in the third embodiment will be described below.

[0086] Figure 12A shows an example configuration of a gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of transistors 1031 and 1041. As shown in Figure 12A, the gate voltage control circuit includes current DACs 1201 and 1203, switches 1202 and 1204, and transistors 1205 and 1206.

[0087] The current DAC1201 outputs a current corresponding to the absolute value of the code value of the input correction code CAL'. Here, the correction code CAL' is a code value calculated based on the correction code CAL and the current control code PIA. The correction code CAL' is obtained by multiplying the correction code CAL by a ratio corresponding to the current control code PIA, for example, the ratio of the current value of the current control code PIA corresponding to the PI code to its maximum value (corresponding to the Miller ratio in the current mirror circuit shown in Figure 11B). The correction code CAL' is, for example, the value shown as the code "Q Correction Current: CAL'" in Figure 12C. Note that the multiplication of the correction code CAL by the ratio corresponding to the current control code PIA can be performed by a logic circuit, for example, not shown. Furthermore, in this embodiment, since the correction code CAL' can take the form of a decimal value, it is preferable that the current DAC1201 is a current DAC with high resolution.

[0088] Switch 1202 is controlled according to the sign of the correction code CAL'. When the correction code CAL' is positive, it connects the first terminal TMA4 to the second terminal TMB4, and when the correction code CAL' is negative, it connects the first terminal TMA4 to the third terminal TMC4. The first terminal TMA4 of switch 1202 is connected to the output terminal of the current DAC 1201.

[0089] The current DAC1203 outputs a current corresponding to the absolute value of the code value of the input current control code PIB. The switch 1204 is controlled according to the sign of the current control code PIB; when the current control code PIB is positive, it connects the first terminal TMA5 to the second terminal TMB5, and when the current control code PIB is negative, it connects the first terminal TMA5 to the third terminal TMC5. The first terminal TMA5 of the switch 1204 is connected to the output terminal of the current DAC1203.

[0090] The second terminal TMB4 of switch 1202 is connected to the second terminal TMB5 of switch 1204. The third terminal TMC4 of switch 1202 is connected to the third terminal TMC5 of switch 1204.

[0091] Transistor 1205 is diode-connected between the connection point between the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204 and ground. That is, the drain and gate of transistor 1205 are connected to the connection point between the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204, and the source of transistor 1205 is grounded. Transistor 1206 is diode-connected between the connection point between the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204 and ground. That is, the drain and gate of transistor 1206 are connected to the connection point between the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204, and the source of transistor 1206 is grounded.

[0092] In this configuration, the current corresponding to the correction code CAL' based on the correction code CAL and current control code PIA, and the current corresponding to the current control code PIB, are combined at the connection point between the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204. Based on the combined current, the voltage generated by the diode-connected transistor 1205 is output as the gate voltage VGBP'. Additionally, the current corresponding to the correction code CAL' based on the correction code CAL and current control code PIA, and the current corresponding to the current control code PIB, are combined at the connection point between the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204. Based on the combined current, the voltage generated by the diode-connected transistor 1206 is output as the gate voltage VGBN'.

[0093] In the example shown in Figure 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in Figure 12A are an example of a correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current based on a correction current corresponding to the correction code.

[0094] Even when the gate voltage control circuit shown in Figure 12A is applied, the current amount of the intermediate current output from transistors 131, 132, 141, and 142 is corrected according to the correction code and PI code, and the phase of the output clock signal obtained by combining the intermediate currents is adjusted. As a result, the phase interpolation circuit adjusts the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees), thereby suppressing the phase difference deviation in the output clock signals (ICKO, QCKO).

[0095] Figure 12B shows another example configuration of a gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of transistors 1031 and 1041. As shown in Figure 12B, the gate voltage control circuit includes a current DAC 1211, a switch 1212, and transistors 1213 and 1214.

[0096] The current DAC1211 outputs a current corresponding to the absolute value of the code value of the input current control code PIB'. Here, the current control code PIB' is a code value obtained by adding the current control code PIB and the correction code CAL' described above. In other words, the current control code PIB' is a value obtained by adding the value of the current control code PIB to the correction code CAL, multiplying it by a ratio corresponding to the current control code PIA, for example, the ratio of the current value of the current control code PIA corresponding to the PI code to its maximum value. The current control code PIB' is, for example, the value shown as the code "Q Correction Current: PIB'" in Figure 12C. Note that the calculation of the current control code PIB' can be performed by a logic circuit, for example, not shown. Also, in this embodiment, since the current control code PIB' can take the form of a decimal value, it is preferable that the current DAC1211 is a current DAC with high resolution.

[0097] Switch 1212 is controlled according to the sign of the current control code PIB'. When the current control code PIB' is positive, it connects the first terminal TMA6 to the second terminal TMB6, and when the current control code PIB' is negative, it connects the first terminal TMA6 to the third terminal TMC6. The first terminal TMA6 of switch 1212 is connected to the output terminal of the current DAC 1211.

[0098] Transistor 1213 is diode-connected between the second terminal TMB6 of switch 1212 and ground. That is, the drain and gate of transistor 1213 are connected to the second terminal TMB6 of switch 1212, and the source of transistor 1213 is grounded. Transistor 1214 is diode-connected between the third terminal TMC6 of switch 1212 and ground. That is, the drain and gate of transistor 1214 are connected to the third terminal TMC6 of switch 1212, and the source of transistor 1214 is grounded.

[0099] With this configuration, when the current control code PIB' is positive, the voltage generated by the diode-connected transistor 1213 is output as the gate voltage VGBP' based on the current corresponding to the current control code PIB'. When the current control code PIB' is negative, the voltage generated by the diode-connected transistor 1214 is output as the gate voltage VGBN' based on the current corresponding to the current control code PIB'.

[0100] In the example shown in Figure 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in Figure 12B are an example of a correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current based on a correction current corresponding to a correction code.

[0101] Even when the gate voltage control circuit shown in Figure 12B is applied, the current amounts of the intermediate currents output from transistors 131, 132, 141, and 142 are corrected according to the correction code and PI code, and the phase of the output clock signal obtained by combining the intermediate currents is adjusted. As a result, the phase interpolation circuit adjusts the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees), thereby suppressing the phase difference deviation in the output clock signals (ICKO, QCKO).

[0102] In the first to third embodiments described above, a correction current is applied to the differential pair to which the second input clock signal QCKI (QCKIP, QCKIN) is input. However, the invention is not limited to this, and a correction current may also be applied to the differential pair to which the first input clock signal ICKI (ICKIP, ICKIN) is input.

[0103] In the phase interpolation circuits of the embodiments described above, the sum of currents corresponding to the PI codes (current control codes PIA, PIB) remains constant regardless of the PI code, as shown by the solid lines 401 and 402 in Figure 4A, I_A and I_B. However, a correction current corresponding to the correction code CAL is added, so the sum of currents changes depending on the PI code. Therefore, if the correction current becomes large, the common-mode voltage at the output terminals OUTP and OUTN of the phase interpolation circuit may shift due to the influence of the correction current.

[0104] The following describes a phase interpolation circuit that has a common-mode voltage correction circuit that suppresses fluctuations in the common-mode voltage so that the total sum of currents flowing through the phase interpolation circuit remains constant even when the correction current changes, and the common-mode voltage at the output of the phase interpolation circuit remains constant.

[0105] (Fourth embodiment) Figure 20 shows an example of the configuration of the phase interpolation circuit in the fourth embodiment. In Figure 20, components having the same function as those shown in Figures 1 and 2C are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit in the fourth embodiment shown in Figure 20 is an example in which a common-mode voltage correction circuit is provided to the phase interpolation circuit corresponding to the first embodiment described above. Note that the gate voltage control circuits that control the gate voltages VGAP and VGAN applied to the gates of transistors 113 and 123, and the gate voltage control circuits that control the gate voltages VGBP and VGBN applied to the gates of transistors 133 and 143 are not shown, but they are the same as in the first embodiment.

[0106] In the phase interpolation circuit of the fourth embodiment, the common-mode voltage correction circuit has a current source 2001 and transistors 2002 to 2008. Transistors 2002 to 2004 and 2007 to 2008 are, for example, N-type MOSFETs, and transistors 2005 and 2006 are, for example, P-type MOSFETs.

[0107] Current source 2001 is a current source that supplies a predetermined current Imax. Current Imax is, for example, the maximum value of the correction current supplied to the phase interpolation circuit, i.e., the current corresponding to the absolute value of the code value of the correction code CAL. The source of transistor 2002 is grounded, and its drain and gate are connected to current source 2001. The source of transistor 2003 is grounded, and its gate is connected to the gate of transistor 2002. Transistors 2002 and 2003 form a current mirror circuit, configured so that current Imax flows through transistor 2003.

[0108] The source of transistor 2004 is grounded, and its gate is connected to the gate of transistor 224, which is part of a gate voltage control circuit that controls gate voltages VGCP and VGCN. Transistors 2004 and 224 form a current mirror circuit, configured so that a current Ical flows through transistor 2004. In this embodiment, the current Ical is a correction current, which is a current (|C|) obtained by multiplying the current (|C0|) corresponding to the absolute value of the code value of the correction code CAL by k according to the current control code PIA.

[0109] The source of transistor 2005 is connected to the power supply VDD, and its drain and gate are connected to the drain of transistor 2004. The source of transistor 2006 is connected to the power supply VDD, and its gate is connected to the gate of transistor 2005. Transistors 2005 and 2006 form a current mirror circuit. Therefore, a current Ical flows through transistor 2006.

[0110] The sources of transistor 2007 and transistor 2008 are commonly connected to the drains of transistor 2003 and transistor 2006. The drain of transistor 2007 is connected to the output terminal OUTP, and the drain of transistor 2008 is connected to the output terminal OUTN. The voltage CMVI is applied to the gates of transistor 2007 and transistor 2008. The voltage CMVI is equal to the common-mode voltage of, for example, the input clock signals ICKI (ICKIP, ICKIN) and QCKI (QCKIP, QCKIN).

[0111] To correct the amount of intermediate current output from transistors 131, 132, 141, and 142, a correction current corresponding to the correction code and PI code flows through the gate voltage control circuit that controls the gate voltages VGCP and VGCN. A current mirror circuit composed of transistors 224 and 2004, and another current mirror circuit composed of transistors 2005 and 2006, causes a current Ical equal to the correction current corresponding to the correction code and PI code to flow through transistor 2006. Furthermore, a current mirror circuit composed of transistors 2002 and 2003 causes a current Imax to flow through transistor 2003. Therefore, a differential pair composed of transistors 2007 and 2008, whose sources are commonly connected to the drains of transistors 2003 and 2006, can supply a current of (Imax - Ical) to the phase interpolation circuit. This allows transistor 2006 to draw a current Ical equal to the correction current, making it possible to maintain a constant current at the output terminals OUTP and OUTN even when the correction current changes, thereby suppressing fluctuations in the common-mode voltage in response to the correction current.

[0112] (Fifth embodiment) Figure 21 shows an example of the configuration of a phase interpolation circuit in the fifth embodiment. In Figure 21, components having the same function as those shown in Figures 10, 11A, and 11B are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit in the fifth embodiment shown in Figure 21 is an example in which a common-mode voltage correction circuit is provided to the phase interpolation circuit corresponding to the second embodiment described above.

[0113] In the phase interpolation circuit of the fifth embodiment, the common-mode voltage correction circuit includes a current source 2101 and transistors 2102 to 2111. Transistors 2102 to 2105 and 2108 to 2111 are, for example, N-type MOSFETs, and transistors 2106 and 2107 are, for example, P-type MOSFETs.

[0114] Current source 2101 is a current source that supplies a predetermined current Imax. Current Imax is the current that flows, for example, through a phase interpolation circuit, corresponding to the sum of the maximum current value according to the current control code PIA, the maximum current value according to the current control code PIB, and the maximum correction current value. The source of transistor 2102 is grounded, and its drain and gate are connected to current source 2101. The source of transistor 2103 is grounded, and its gate is connected to the gate of transistor 2102. Transistors 2102 and 2103 form a current mirror circuit, configured so that current Imax flows through transistor 2103.

[0115] The source of transistor 2104 is grounded, and its gate is connected to the connection point between the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117, both of which are part of the gate voltage control circuit. The source of transistor 2105 is grounded, and its gate is connected to the connection point between the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117, both of which are part of the gate voltage control circuit. The source of transistor 2110 is grounded, and its gate is connected to the second terminal TMB1 of switch 1102, both of which are part of the gate voltage control circuit. The source of transistor 2111 is grounded, and its gate is connected to the third terminal TMC1 of switch 1102, both of which are part of the gate voltage control circuit.

[0116] The source of transistor 2106 is connected to the power supply VDD, and its drain and gate are connected to the drains of transistors 2104, 2105, 2110, and 2111, respectively. Therefore, a current Ical' equal to the combined current of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the correction code CAL and the current corresponding to the current control code PIA flows through transistor 2106. The source of transistor 2107 is connected to the power supply VDD, and its gate is connected to the gate of transistor 2106. Transistors 2106 and 2107 form a current mirror circuit. Therefore, a current Ical' flows through transistor 2107.

[0117] The sources of transistor 2108 and transistor 2109 are commonly connected to the drains of transistor 2103 and transistor 2107. The drain of transistor 2108 is connected to the output terminal OUTP, and the drain of transistor 2109 is connected to the output terminal OUTN. The voltage CMVI is applied to the gates of transistor 2108 and transistor 2109. The voltage CMVI is equal to the common-mode voltage of, for example, the input clock signals ICKI (ICKIP, ICKIN) and QCKI (QCKIP, QCKIN).

[0118] When a correction current corresponding to the correction code and PI code for correcting the amount of intermediate current output from transistors 131, 132, 141, and 142 flows through the gate voltage control circuit that controls the gate voltages VGBP' and VGBN', a current Ical' equal to the sum of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, the correction code CAL, and the correction current corresponding to the current control code PIA flows through transistor 2107. In addition, a current Imax flows through transistor 2103 due to the current mirror circuit composed of transistors 2102 and 2103. Therefore, a differential pair composed of transistors 2108 and 2109, whose sources are commonly connected to the drains of transistor 2103 and transistor 2107, can supply a current of (Imax - Ical') to the phase interpolation circuit. Here, the current Ical' is equal to the sum of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, the correction code CAL, and the correction current corresponding to the current control code PIA. Furthermore, the sum of the current corresponding to current control code PIA and the current corresponding to current control code PIB is constant. Therefore, by subtracting a current Ical', which contains a current equal to the correction current, using transistor 2107, it is possible to maintain a constant current amount at the output terminals OUTP and OUTN even if the correction current changes, thereby suppressing fluctuations in the common-mode voltage in response to the correction current.

[0119] (Sixth embodiment) Figure 22 shows an example of the configuration of a phase interpolation circuit in the sixth embodiment. In Figure 22, components having the same function as those shown in Figures 10, 11A, and 12A are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit in the sixth embodiment shown in Figure 22 is an example in which a common-mode voltage correction circuit is added to the phase interpolation circuit corresponding to the third embodiment to which the gate voltage control circuit shown in Figure 12A is applied.

[0120] In the phase interpolation circuit of the sixth embodiment shown in Figure 22, the common-mode voltage correction circuit includes a current source 2201 and transistors 2202 to 2211. Transistors 2202 to 2205 and 2208 to 2211 are, for example, N-type MOSFETs, and transistors 2206 and 2207 are, for example, P-type MOSFETs.

[0121] Current source 2201 is a current source that supplies a predetermined current Imax. Current Imax is the current that flows, for example, through a phase interpolation circuit, corresponding to the sum of the maximum current value according to the current control code PIA, the maximum current value according to the current control code PIB, and the maximum correction current value. The source of transistor 2202 is grounded, and its drain and gate are connected to current source 2201. The source of transistor 2203 is grounded, and its gate is connected to the gate of transistor 2202. Transistors 2202 and 2203 form a current mirror circuit, configured so that current Imax flows through transistor 2203.

[0122] The source of transistor 2204 is grounded, and its gate is connected to the connection point between the second terminal TMB4 of switch 1202 of the gate voltage control circuit and the second terminal TMB5 of switch 1204. The source of transistor 2205 is grounded, and its gate is connected to the connection point between the third terminal TMC4 of switch 1202 of the gate voltage control circuit and the third terminal TMC5 of switch 1204. The source of transistor 2210 is grounded, and its gate is connected to the second terminal TMB1 of switch 1102 of the gate voltage control circuit. The source of transistor 2211 is grounded, and its gate is connected to the third terminal TMC1 of switch 1102 of the gate voltage control circuit.

[0123] The source of transistor 2206 is connected to the power supply VDD, and its drain and gate are connected to the drains of transistors 2204, 2205, 2210, and 2211, respectively. Therefore, a current Ical' flows through transistor 2206, which is equal to the combined current of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the current corresponding to the correction code CAL'. Here, the correction code CAL' is a code value calculated based on the correction code CAL and the current control code PIA, as described above. The source of transistor 2207 is connected to the power supply VDD, and its gate is connected to the gate of transistor 2206. Transistors 2206 and 2207 form a current mirror circuit. Therefore, a current Ical' flows through transistor 2207.

[0124] The sources of transistor 2208 and transistor 2209 are commonly connected to the drains of transistor 2203 and transistor 2207. The drain of transistor 2208 is connected to the output terminal OUTP, and the drain of transistor 2209 is connected to the output terminal OUTN. The voltage CMVI is applied to the gates of transistor 2208 and transistor 2209. The voltage CMVI is equal to the common-mode voltage of, for example, the input clock signals ICKI (ICKIP, ICKIN) and QCKI (QCKIP, QCKIN).

[0125] When a correction current corresponding to the correction code CAL', which corrects the amount of intermediate current output from transistors 131, 132, 141, and 142, flows through the gate voltage control circuit that controls the gate voltages VGBP' and VGBN', a current Ical' equal to the combined current of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the correction current corresponding to the correction code CAL' flows through transistor 2207. In addition, a current Imax flows through transistor 2203 due to the current mirror circuit composed of transistors 2202 and 2203. Therefore, it is possible to supply a current of (Imax-Ical') to the phase interpolation circuit through the differential pair composed of transistors 2208 and 2209, whose sources are commonly connected to the drains of transistor 2203 and transistor 2207, respectively. Here, the current Ical' is equal to the sum of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the correction code CAL', i.e., the correction current corresponding to the correction code CAL and the current control code PIA. Furthermore, the sum of the current corresponding to current control code PIA and the current corresponding to current control code PIB is constant. Therefore, by subtracting a current Ical', which contains a current equal to the correction current, using transistor 2207, it is possible to maintain a constant current amount at the output terminals OUTP and OUTN even if the correction current changes, thereby suppressing fluctuations in the common-mode voltage in response to the correction current.

[0126] Figure 23 shows another example of the configuration of the phase interpolation circuit in the sixth embodiment. In Figure 23, components having the same function as those shown in Figures 10, 11A, and 12B are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit in the sixth embodiment shown in Figure 23 is an example in which a common-mode voltage correction circuit is added to the phase interpolation circuit corresponding to the third embodiment to which the gate voltage control circuit shown in Figure 12B is applied.

[0127] In the phase interpolation circuit of the sixth embodiment shown in Figure 23, the common-mode voltage correction circuit includes a current source 2301 and transistors 2302-2309, 2311-2312. Transistors 2302-2305, 2308-2309, and 2311-2312 are, for example, N-type MOSFETs, and transistors 2306 and 2307 are, for example, P-type MOSFETs.

[0128] Current source 2301 is a current source that supplies a predetermined current Imax. Current Imax is the maximum value of the current according to the current control code PIA and the maximum value of the current according to the current control code PIB', which are supplied to, for example, a phase interpolation circuit. Here, current control code PIB' is the code value obtained by adding the current control code PIB and the correction code CAL', as described above. The source of transistor 2302 is grounded, and its drain and gate are connected to current source 2301. The source of transistor 2303 is grounded, and its gate is connected to the gate of transistor 2302. Transistors 2302 and 2303 form a current mirror circuit, configured so that current Imax flows through transistor 2303.

[0129] The source of transistor 2304 is grounded, and its gate is connected to the second terminal TMB6 of switch 1212 of the gate voltage control circuit. The source of transistor 2305 is grounded, and its gate is connected to the third terminal TMC6 of switch 1212 of the gate voltage control circuit. The source of transistor 2311 is grounded, and its gate is connected to the second terminal TMB1 of switch 1102 of the gate voltage control circuit. The source of transistor 2312 is grounded, and its gate is connected to the third terminal TMC1 of switch 1102 of the gate voltage control circuit.

[0130] The source of transistor 2306 is connected to the power supply VDD, and its drain and gate are connected to the drains of transistors 2304, 2305, 2311, and 2312. Therefore, a current Ical' flows through transistor 2306, which is equal to the combined current of the current according to current control code PIA and the current according to current control code PIB'. The source of transistor 2307 is connected to the power supply VDD, and its gate is connected to the gate of transistor 2306. Transistors 2306 and 2307 form a current mirror circuit. Therefore, a current Ical' flows through transistor 2307.

[0131] The sources of transistor 2308 and transistor 2309 are commonly connected to the drains of transistor 2303 and transistor 2307. The drain of transistor 2308 is connected to the output terminal OUTP, and the drain of transistor 2309 is connected to the output terminal OUTN. The voltage CMVI is applied to the gates of transistor 2308 and transistor 2309. The voltage CMVI is equal to the common-mode voltage of, for example, the input clock signals ICKI (ICKIP, ICKIN) and QCKI (QCKIP, QCKIN).

[0132] When a current corresponding to the current control code PIB', which includes a correction current to correct the amount of intermediate current output from transistors 131, 132, 141, and 142, flows through the gate voltage control circuit that controls the gate voltages VGBP' and VGBN', a current Ical' equal to the combined current of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB' flows through transistor 2307. In addition, a current Imax flows through transistor 2303 due to the current mirror circuit composed of transistors 2302 and 2303. Therefore, it is possible to supply a current of (Imax-Ical') to the phase interpolation circuit through the differential pair composed of transistors 2308 and 2309, whose sources are commonly connected to the drains of transistor 2303 and transistor 2307, respectively. Here, the current Ical' is equal to the sum of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB'. Furthermore, the current control code PIB' is a code value obtained by adding the current control code PIB and the correction code CAL', and the sum of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB is constant. Therefore, by subtracting a current Ical', which contains a current equal to the correction current, using transistor 2307, it is possible to maintain a constant current amount at the output terminals OUTP and OUTN even if the correction current changes, and the common-mode voltage fluctuation in response to the correction current can be suppressed.

[0133] (Other embodiments of the present invention) Figure 13A shows an example of the configuration of a semiconductor integrated circuit in this embodiment. The semiconductor integrated circuit 1301 in this embodiment has a receiving circuit 1302 that has the function of a deserializer circuit that converts an input serial signal into a parallel signal, and an internal circuit 1321 such as a logic circuit that receives a parallel signal (data) from the receiving circuit 1302 and performs processing operations.

[0134] The receiving circuit 1302 includes a PLL (Phase Locked Loop) circuit 1303, a phase interpolation circuit 1304, an equalizer circuit (CTLE: Continuous Time Linear Equalizer) 1307, a selector 1308, comparators 1309 and 1311, demultiplexer circuits 1310 and 1312, a digital processing circuit 1313, frequency divider circuits 1318 and 1319, a variable delay circuit 1317, and a resistor 1316.

[0135] The PLL circuit 1303 generates and outputs clock signals to be supplied to each circuit in the semiconductor integrated circuit based on the input reference clock signal REFCK. For example, the PLL circuit 1303 generates and outputs a first input clock signal ICKI (ICKIP, ICKIN) and a second input clock signal QCKI (QCKIP, QCKIN) having a predetermined phase difference with the first input clock signal ICKI, based on the input reference clock signal REFCK.

[0136] The phase interpolation circuit 1304 generates and outputs output clock signals ICKO and QCKO, which have phases corresponding to the input PI codes, based on the input clock signals ICKI and QCKI. The phase interpolation circuit 1304 includes a phase interpolation circuit 1305 that generates a first output clock signal ICKO and a phase interpolation circuit 1306 that generates a second output clock signal QCKO. The phase interpolation circuits 1305 and 1306 are the phase interpolation circuits in the first to sixth embodiments described above, and generate output clock signals ICKO and QCKO, respectively, by weighting and combining the input clock signals ICKI and QCKI based on the PI codes.

[0137] The equalizer circuit 1307 receives the input serial signal Input transmitted via a transmission line or the like. The selector 1308 outputs either the input serial signal Input or the internal data signal dataQ received by the equalizer circuit 1307 to the comparators 1309 and 1311 according to the control signal SEL. Normally, the input serial signal Input received by the equalizer circuit 1307 is output from the selector 1308, and the internal data signal dataQ is output from the selector 1308 when determining the correction code (during calibration operation), etc.

[0138] The comparator 1309 acquires data DT from the input signal using the first output clock signal ICKO output from the phase interpolation circuit 1304. The demultiplexer circuit 1310 performs serial-to-parallel conversion on the output of the comparator 1309 based on the clock obtained by dividing the first output clock signal ICKO output from the phase interpolation circuit 1304 by the frequency divider circuit 1319, and outputs a parallel data signal.

[0139] Comparator 1311 obtains the boundary BD from the input signal using the second output clock signal QCKO output from the phase interpolation circuit 1304. Demultiplexer circuit 1312 performs serial-to-parallel conversion on the output of comparator 1311 based on the clock obtained by dividing the first output clock signal ICKO output from the phase interpolation circuit 1304 by the frequency divider circuit 1319, and outputs a parallel boundary signal.

[0140] Furthermore, the demultiplexer circuits 1310 and 1312 may perform serial-to-parallel conversion on the outputs of comparators 1309 and 1311 based on a clock obtained by dividing the second output clock signal QCKO, instead of a clock obtained by dividing the first output clock signal ICKO.

[0141] The digital processing circuit 1313 generates and outputs the received data signal RXOUT and the received clock signal RXCLK based on the data signal DT and boundary signal BD output from the demultiplexer circuits 1310 and 1312. The received data signal RXOUT output from the receiving circuit 1302 is taken up by the internal circuit 1321 via the flip-flop 1322, which operates with the received clock signal RXCLK, and processed thereafter.

[0142] Furthermore, the digital processing circuit 1313 includes a calibration control circuit 1314 and a CDR circuit 1315. The calibration control circuit 1314 performs control related to the calibration operation for determining the correction code.

[0143] The CDR circuit 1315 appropriately controls the phase of the output clock signals ICKO and QCKO output by the phase interpolation circuit 1304 based on the signals received from the demultiplexer circuits 1310 and 1312. As shown in Figure 15, the CDR circuit 1315 determines whether the phase of the output clock signals ICKO and QCKO output by the phase interpolation circuit 1304 is leading or lagging relative to the input serial signal DTIN, based on the data signal DT and boundary signal BD output from the demultiplexer circuits 1310 and 1312. The CDR circuit 1315 also generates and outputs a PI code to advance or delay the phase of the output clock signals ICKO and QCKO according to the determination result.

[0144] The frequency divider circuit 1318 divides the second output clock signal QCKO output from the phase interpolation circuit 1304 by two. The variable delay circuit 1317 delays the second output clock signal QCKO, which has been divided by the frequency divider circuit 1318, and outputs it as an internal data signal dataQ. The configuration of the variable delay circuit 1317 is not particularly limited, and any delay circuit that can change the amount of delay can be applied. The variable delay circuit 1317 may be configured, for example, as shown in Figure 13B, by cascading unit delay circuits 1331 (1331-1, 1331-2, 1331-3, 1331-4) consisting of an inverter circuit, a resistor, and a capacitor, and selecting one of the outputs from each unit delay circuit 1331 using a selection circuit 1332 to output.

[0145] In the receiving circuit 1302 of the semiconductor integrated circuit 1301 shown in Figure 13A, the internal data signal dataQ is generated by the frequency divider circuit 1318 and the variable delay circuit 1317 using the second output clock signal QCKO output from the phase interpolation circuit 1304. However, this is not the only option; for example, as shown in Figure 14, the internal data signal dataQ may be generated by the phase interpolation circuit 1401 and the frequency divider circuit 1402 using the second input clock signal QCKI output from the PLL circuit 1303. Alternatively, the internal data signal dataQ may be generated using a DLL circuit.

[0146] Figure 14 shows an example of the configuration of a semiconductor integrated circuit in this embodiment. In Figure 14, components having the same function as those shown in Figure 13A are denoted by the same reference numerals, and redundant explanations are omitted. The phase interpolation circuit 1401 generates and outputs a clock signal equivalent to the output clock signal QCKO, which has its output phase adjusted, i.e., its delay amount adjusted, based on the second input clock signal QCKI output from the PLL circuit 1303. The frequency divider circuit 1402 divides the clock signal output from the phase interpolation circuit 1401 by 2 and outputs it as an internal data signal dataQ.

[0147] Furthermore, the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Industrial applicability]

[0148] According to the present invention, it is possible to provide a phase interpolation circuit that generates an output clock signal with suppressed phase shift relative to the phase interpolation code.

Claims

1. A phase interpolation circuit that generates an output clock signal having a phase corresponding to a first current control code and a second current control code based on a first input clock signal and a second input clock signal having a first phase difference, A first generation circuit that generates a first intermediate current based on the first input clock signal in accordance with the first current control code, A second generation circuit that generates a second intermediate current based on the second input clock signal in accordance with the second current control code, A combining circuit that combines the first intermediate current and the second intermediate current to generate the output clock signal, A correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The phase interpolation circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation of the first phase difference from a predetermined value.

2. The first generation circuit has a first transistor that operates as a current source, to which a first gate voltage corresponding to the first current control code is supplied to the gate. The second generation circuit has a second transistor that operates as a current source, to which a second gate voltage corresponding to the second current control code is supplied to the gate. The correction circuit has a third transistor that operates as a current source, to which a third gate voltage corresponding to at least one of the first current control code and the second current control code and the correction code is supplied to the gate. The phase interpolation circuit according to feature 1.

3. The phase interpolation circuit according to claim 2, further comprising a gate voltage control circuit that generates the third gate voltage based on the correction code and at least one of the first current control code and the second current control code and supplies it to the gate of the third transistor.

4. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal in accordance with the first current control code, A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal in accordance with the second current control code, A combining circuit that combines the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal, A correction circuit that corrects the amount of current of at least one of the first differential intermediate current and the second differential intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The phase interpolation circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation of the first phase difference from a predetermined value.

5. The first generation circuit has first and fourth transistors that operate as current sources, to which first and fourth gate voltages corresponding to the first current control code are supplied to the gates, respectively. The second generation circuit has second and fifth transistors that operate as current sources, to which second and fifth gate voltages corresponding to the second current control code are supplied to the gates, respectively. The correction circuit has third and sixth transistors that operate as current sources, to which third and sixth gate voltages corresponding to at least one of the first current control code and the second current control code and the correction code are supplied to the gate. The phase interpolation circuit according to feature 4.

6. The first and fourth transistors are controlled such that when one of the first and fourth transistors is in the ON state, the other is in the OFF state. The second and fifth transistors are controlled such that when one of the second and fifth transistors is in the ON state, the other is in the OFF state. The third and sixth transistors are controlled such that when one of the third and sixth transistors is in the ON state, the other is in the OFF state. The phase interpolation circuit according to claim 5.

7. The phase interpolation circuit according to claim 5 or 6, further comprising a gate voltage control circuit that generates the third and sixth gate voltages based on the correction code and at least one of the first current control code and the second current control code, and supplies them to the gates of the third and sixth transistors, respectively.

8. The phase interpolation circuit according to any one of claims 4 to 7, further comprising a common mode voltage correction circuit that suppresses fluctuations in the common mode voltage corresponding to the correction current in the differential output clock signal.

9. The phase interpolation circuit according to claim 8, characterized in that the common-mode voltage correction circuit keeps the total sum of currents flowing through the phase interpolation circuit constant, regardless of the correction current.

10. The phase interpolation circuit according to claim 8, characterized in that the common-mode voltage correction circuit suppresses fluctuations in the common-mode voltage in accordance with at least one of the first current control code and the second current control code and the correction code.

11. A phase interpolation circuit that generates an output clock signal having a phase corresponding to a first current control code and a second current control code based on a first input clock signal and a second input clock signal having a first phase difference, A comparator that uses the output clock signal generated by the phase interpolation circuit to acquire data from the received signal, A demultiplexer circuit that converts the output signal of the comparator into a parallel signal, It has, The aforementioned phase interpolation circuit is A first generation circuit that generates a first intermediate current based on the first input clock signal in accordance with the first current control code, A second generation circuit that generates a second intermediate current based on the second input clock signal in accordance with the second current control code, A combining circuit that combines the first intermediate current and the second intermediate current to generate the output clock signal, A correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The receiving circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation from a predetermined value of the first phase difference.

12. The first generation circuit has a first transistor that operates as a current source, to which a first gate voltage corresponding to the first current control code is supplied to the gate. The second generation circuit has a second transistor that operates as a current source, to which a second gate voltage corresponding to the second current control code is supplied to the gate. The correction circuit has a third transistor that operates as a current source, to which a third gate voltage corresponding to at least one of the first current control code and the second current control code and the correction code is supplied to the gate. The receiving circuit according to feature 11.

13. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit, A demultiplexer circuit that converts the output signal of the comparator into a parallel signal, It has, The aforementioned phase interpolation circuit is A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal in accordance with the first current control code, A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal in accordance with the second current control code, A combining circuit that combines the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal, A correction circuit that corrects the amount of current of at least one of the first differential intermediate current and the second differential intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The receiving circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation from a predetermined value of the first phase difference.

14. The first generation circuit has first and fourth transistors that operate as current sources, to which first and fourth gate voltages corresponding to the first current control code are supplied to the gates, respectively. The second generation circuit has second and fifth transistors that operate as current sources, to which second and fifth gate voltages corresponding to the second current control code are supplied to the gates, respectively. The correction circuit has third and sixth transistors that operate as current sources, to which third and sixth gate voltages corresponding to at least one of the first current control code and the second current control code and the correction code are supplied to the gate. The receiving circuit according to feature 13.

15. The receiving circuit according to claim 13 or 14, further comprising a common mode voltage correction circuit that suppresses fluctuations in the common mode voltage corresponding to the correction current in the differential output clock signal.

16. A phase interpolation circuit that generates an output clock signal having a phase corresponding to a first current control code and a second current control code based on a first input clock signal and a second input clock signal having a first phase difference, A comparator that uses the output clock signal generated by the phase interpolation circuit to acquire data from the received signal, A demultiplexer circuit that performs serial-to-parallel conversion on the output signal of the comparator and outputs it, An internal circuit that receives the output signal of the demultiplexer circuit and performs processing operations. It has, The aforementioned phase interpolation circuit is A first generation circuit that generates a first intermediate current based on the first input clock signal in accordance with the first current control code, A second generation circuit that generates a second intermediate current based on the second input clock signal in accordance with the second current control code, A combining circuit that combines the first intermediate current and the second intermediate current to generate the output clock signal, A correction circuit that corrects the amount of current of at least one of the first intermediate current and the second intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The semiconductor integrated circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation from a predetermined value of the first phase difference.

17. The first generation circuit has a first transistor that operates as a current source, to which a first gate voltage corresponding to the first current control code is supplied to the gate. The second generation circuit has a second transistor that operates as a current source, to which a second gate voltage corresponding to the second current control code is supplied to the gate. The correction circuit has a third transistor that operates as a current source, to which a third gate voltage corresponding to at least one of the first current control code and the second current control code and the correction code is supplied to the gate. The semiconductor integrated circuit according to feature 16.

18. A phase interpolation circuit that generates a first current control code and a differential output clock signal having a phase corresponding to the second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit, A demultiplexer circuit that performs serial-to-parallel conversion on the output signal of the comparator and outputs it, An internal circuit that receives the output signal of the demultiplexer circuit and performs processing operations. It has, The aforementioned phase interpolation circuit is A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal in accordance with the first current control code, A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal in accordance with the second current control code, A combining circuit that combines the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal, A correction circuit that corrects the amount of current of at least one of the first differential intermediate current and the second differential intermediate current by generating a correction current according to at least one of the first current control code and the second current control code and a correction code set according to the amount of deviation of the first phase difference from a predetermined value. It has, The semiconductor integrated circuit is characterized in that the correction code is set to a fixed value corresponding to the amount of deviation from a predetermined value of the first phase difference.

19. The first generation circuit has first and fourth transistors that operate as current sources, to which first and fourth gate voltages corresponding to the first current control code are supplied to the gates, respectively. The second generation circuit has second and fifth transistors that operate as current sources, to which second and fifth gate voltages corresponding to the second current control code are supplied to the gates, respectively. The correction circuit has third and sixth transistors that operate as current sources, to which third and sixth gate voltages corresponding to at least one of the first current control code and the second current control code and the correction code are supplied to the gate. The semiconductor integrated circuit according to feature 18.

20. The semiconductor integrated circuit according to claim 18 or 19, further comprising a common mode voltage correction circuit that suppresses fluctuations in the common mode voltage in the differential output clock signal corresponding to the correction current.

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