3D NAND memory best read reference voltage search

Abstract

To provide a method for a memory system.SOLUTION: A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having the same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.SELECTED DRAWING: Figure 10A

Description

Technical Field

[0001] This application relates to 3-dimensional (3D) NAND flash memory operation technology.

Background Art

[0002] 3-dimensional (3D) NAND flash memory adopts state-of-the-art multi-level cell (MLC) technology to provide high storage density. A read-retry mechanism is used to improve the reliability of 3D NAND flash memory. For example, multiple retry steps with adjusted read reference voltage values can be performed to read a target page multiple times before an encoded page can be accurately decoded. A large number of read-retry operations can significantly increase the read latency and may degrade the performance of the memory system.

Summary of the Invention

Means for Solving the Problems

[0003] Aspects of the present disclosure provide a method for a memory system. The method may include determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determining an anchor read reference voltage having the same offset as the first best read offset with respect to a second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set for reading pages from a set of multi-level cells (MLCs) in a semiconductor memory device of the memory system. A first scanning range may be determined based on the anchor read reference voltage. The upper limit of the first scanning range is the anchor read reference voltage plus an upper limit offset, and the lower limit of the first scanning range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive voltage values or negative voltage values. A second best read offset of a second best read reference voltage with respect to the second read reference voltage may be determined based on the first scanning range.

[0004] In an embodiment, the step of determining a first best read offset is a step of determining a second scan range, the second scan range having an upper limit which is the first default read reference voltage plus an upper limit offset, and a lower limit which is the first default read reference voltage plus a lower limit offset, and the step of scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to the first read reference voltage, and each first single read operation generating a bit count of either 1 or 0, and each The method includes, for each first single read operation, the steps of determining, if available, a first bit count difference between the bit count of each first single read operation and the bit count of the previous first single read operation, and, if available, a second bit count difference between the bit count of each first single read operation and the bit count of the subsequent first single read operation, and determining the first read reference voltage of the first single read operation such that the sum of the respective first bit count differences and the respective second bit count differences is the smallest among the series of first single read operations, to be a coarse best read reference voltage.

[0005] In an embodiment, the method may further include the step of determining the first read reference voltage of the first single read operation having the minimum of the first bit count difference and the minimum of the second bit count difference among the two or more first single read operations, such that when there are two or more first single read operations in which the sum of

[0006] In an embodiment, the method comprises the steps of: determining a third scan range, the third scan range having an upper limit which is the coarse best read reference voltage plus a coarse step voltage, and a lower limit which is the coarse best read reference voltage minus a coarse step voltage; and scanning the third scan range based on a fine step voltage by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, and each second single read operation generating a bit count of either 1 or 0; and, if available, the bit count of each second single read operation The method may further include the steps of determining a first bit count difference between the bit count of the previous second single read operation and the bit count of the previous second single read operation, and, if available, a second bit count difference between the bit count of each second single read operation and the bit count of the subsequent second single read operation, and determining a second read reference voltage for a second single read operation in which the sum of the respective first bit count differences and the respective second bit count differences is the smallest among a series of second single read operations, such that the second read reference voltage is a first best read reference voltage, wherein the offset of the first best read reference voltage with respect to a first default read reference voltage is a first best read offset.

[0007] In one embodiment, the step of determining a second best read offset of a second best read reference voltage with respect to a second default read reference voltage based on a first scan range is to scan the first scan range by performing a series of third single read operations within the first scan range, wherein each third single read operation corresponds to a third read reference voltage, and each third single read operation generates a bit count of either 1 or 0; and for each third single read operation, if available, the bit count of each third single read operation and the bit count of the previous third single read operation The steps include determining a first bit count difference between them, and, if available, a second bit count difference between the bit count of each third single read operation and the bit count of a subsequent third single read operation; and determining a third read reference voltage for a third single read operation such that the sum of the first bit count differences and the second bit count differences is the smallest among the series of third single read operations, such that the third read reference voltage for the third single read operation is a second best read reference voltage, wherein the offset of the second best read reference voltage to a second default read reference voltage is the second best read offset. In the example, the first single read operation, the second single read operation, and the third single read operation are partial page read operations.

[0008] In an embodiment, the method may further include the steps of: collecting a first set of first best read offsets, each first best read offset being a voltage shift of a best read reference voltage from a first default read reference voltage, each first best read offset corresponding to a memory cell condition that causes a set of memory cells to have its own first best read offset, and the first set of first best read offsets having either positive or negative values; setting the maximum value of the first set of first best read offsets to be the upper limit offset of a second scanning range; and setting the minimum value of the first set of first best read offsets to be the lower limit offset of a second scanning range.

[0009] In embodiments, the method may further include the steps of: collecting a second set of second best read offsets, each second best read offset corresponding to a first set of first best read voltages and one of the respective memory cell conditions, each second best read offset being a voltage shift of the best read reference voltage from a second default read reference voltage, and each second set of second best read offsets being either positive or negative; determining the difference between each pair of first best read offsets and each second best read offset, the difference being equal to each second best read offset minus each first best read offset; setting the maximum difference between each pair of first best read offsets and each second best read offset to be the upper limit offset of a first scan range; and setting the minimum difference between each pair of first best read offsets and each second best read offset to be the lower limit offset of a first scan range.

[0010] In embodiments, the method may further include a step of determining that error correction code (ECC) decoding has failed to read a page, prior to the step of determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage. In embodiments, ECC software decoding is performed to read a page from a set of MLCs based on a first best read reference voltage and a second best read reference voltage. In embodiments, the first or second default read reference voltage corresponds to the default read reference voltage of the MLC.

[0011] A part of this disclosure provides a non-temporary computer-readable medium for storing instructions. When an instruction is executed by a processor, it causes the processor to perform a method.

[0012] Aspects of this disclosure provide a memory system. The memory system may comprise a semiconductor memory device and a memory control device for operating the semiconductor memory device. The memory control device may comprise a circuit configured to determine a first best read offset for a first best read reference voltage relative to a first default read reference voltage, and to determine an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage. The first and second default read reference voltages are set to read pages from a set of multilevel cells (MLCs) in the semiconductor memory device in the memory system. A first scan range may be determined based on the anchor read reference voltage. The upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and the lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset. The upper and lower limit offsets may be positive or negative voltage values. A second best read offset for a second best read reference voltage relative to a second read reference voltage may be determined based on the first scan range.

[0013] The disclosure of this invention can be understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practices, various features are not depicted to a constant scale. In fact, the dimensions of various features may be enlarged or reduced for clarity of consideration. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram of a system 100 having a memory device according to some aspects of the present disclosure. [Figure 2A] This is a diagram illustrating an example of a memory system according to some aspects of the present disclosure. [Figure 2B] This is a diagram illustrating an example of a memory system according to some aspects of the present disclosure. [Figure 3] This is a schematic circuit diagram of a memory device 300 including peripheral circuits according to some aspects of the present disclosure. [Figure 4] This is a diagram illustrating an example of peripheral circuitry according to several aspects of the present disclosure. [Figure 5] This is a schematic diagram of the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure. [Figure 6] This diagram illustrates a situation where the memory cell threshold voltage distribution is shifted. [Figure 7] This is a diagram of the reading process 700 according to an embodiment of the present disclosure. [Figure 8] This figure shows the search process 800 for the best read level based on the Failed Bit Count (FBC) according to an embodiment of the present disclosure. [Figure 9] This is a diagram of the Bit Count Difference (BCD) table 900 used to determine the best read level from a series of read levels (scan points) during the scanning process. [Figure 10A] This is a diagram of the best read level search process 1000 based on BCD according to an embodiment of the present disclosure. [Figure 10B]FIG. 1000 is a diagram of a BCD-based best read level search process according to an embodiment of the present disclosure. [Figure 11A] FIG. 1110 and FIG. 1120 are diagrams of two tables for showing how to optimize the scanning range used for rough search in a BCD-based search process 1000 according to an embodiment of the present disclosure. [Figure 11B] FIG. 1130 and FIG. 1140 are diagrams of two tables for showing how to optimize the scanning range used for fine search in a BCD-based search process 1000 according to an embodiment of the present disclosure. [Figure 12A] FIG. is a diagram of a best read level search process according to an embodiment of the present disclosure. [Figure 12B] FIG. is a diagram of a best read level search process according to an embodiment of the present disclosure. [Figure 12C] FIG. is a diagram of a best read level search process according to an embodiment of the present disclosure. [Figure 13] FIG. 1300 is a diagram of a best read level search process 1300 according to an embodiment of the present disclosure. [Figure 14A] FIG. is a diagram of a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure. [Figure 14B] FIG. is a diagram of a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Although specific configurations and arrangements are considered, it should be understood that this is done only for illustrative purposes. Therefore, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be used in various other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and changed in combinations, adjustments, and changes that are not clearly depicted in the drawings but are within the scope of the present disclosure.

[0016] In general, terminology can be understood at least partially from its use in context. For example, the term “one or more” as used herein may, at least partially context-dependent, be used to describe a singular feature, structure, or characteristic, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “one” or “it” may, at least partially context-dependent, be understood to convey singular use or plural use. Furthermore, the term “based on” may be understood not necessarily intended to convey an exclusive set of factors, and instead, at least partially context-dependent, may allow for the presence of additional factors that are not necessarily explicitly stated.

[0017] This disclosure is not limited to three-dimensional (3D) NAND memory devices, but 3D NAND devices may be used in some examples to illustrate the concepts of the present invention. For example, the techniques described herein can be applied to planar NAND memory devices.

[0018] Aspects of this disclosure provide methods and techniques for searching for a best read reference voltage (best read level). The best read level can subsequently be used for read retries or software decoding processes. In embodiments, a scanning process may be performed across multiple scanning points in a scanning voltage range (scanning range) in correspondence with the read level. A series of single read operations may be performed at each scanning point across a word line memory cell string storing one or more pages of data. Each single read operation may output a bit count. The best read level may be determined based on the bit count difference between two consecutive single read operations. Thus, the search process does not rely on known data stored in the memory cell.

[0019] Furthermore, a scanning range optimization method is provided to accelerate the search process to the best level. For example, data for a first best read offset relative to a first default read reference voltage and a second best read offset relative to a second default read reference voltage may be collected for different memory cell conditions. The range of the voltage difference between the voltage value of the first best read offset and the voltage value of each second best read offset may be determined. The best read level resulting from the first search process at the first read level can be used as an anchor voltage for the second search process at the second read level. The search range for the second search process may be determined based on the range of voltage differences around the anchor voltage.

[0020] Figure 1 shows a block diagram of a system 100 having a memory device according to several aspects of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device. As shown in Figure 1, system 100 may comprise a host 108 and a memory system 102 having one or more memory devices 104 and a memory control device 106. The host 108 may be an electronic device such as a central processing unit (CPU) or a system-on-a-chip (SoC) processor such as an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. The memory device 104 may be any memory device disclosed in the present disclosure.

[0021] In some embodiments, the memory control unit 106 is connected to the memory device 104 and the host 108 and configured to control the memory device 104. The memory control unit 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory control unit 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, CompactFlash (CF)® cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory control unit 106 is designed to operate in high duty cycle environments such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs) used as data storage devices for portable devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays.

[0022] The memory control unit 106 may be configured to control the operation of the memory device 104, including read, erase, and program operations. The memory control unit 106 may also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the memory control unit 106 is further configured to process error correction codes (ECC) with respect to data read from or written to the memory device 104. Any other appropriate functions may also be performed by the memory control unit 106, such as formatting the memory device 104. In accordance with some aspects of this disclosure, in some embodiments, the memory control unit 106 is configured to perform a best read reference voltage search method, either entirely or partially, as described herein.

[0023] The memory control device 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory control device 106 can communicate with an external device through at least one of various interface protocols, such as the USB protocol, MMC protocol, PCI (Peripheral Components Interconnection) protocol, PCI-Express (PCI-E) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0024] The memory control device 106 and one or more memory devices 104 can be incorporated into various types of storage devices, and may be included in the same package, for example, a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 102 can be implemented and packaged into different types of final electronic products.

[0025] In one example, as shown in Figure 2A, the memory control unit 106 and a single memory device 104 may be incorporated into a memory card 202. The memory card 202 may be a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, SmartMedia (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 for connecting the memory card 202 to a host (e.g., host 108 in Figure 1). In another example, as shown in Figure 2B, the memory control unit 106 and multiple memory devices 104 may be incorporated into an SSD 206. The SSD 206 may further include an SSD connector 208 for connecting the SSD 206 to a host (e.g., host 108 in Figure 1). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0026] Figure 3 shows a schematic circuit diagram of a memory device 300 including peripheral circuits according to several embodiments of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 1. The memory device 300 may comprise a memory cell array 301 and peripheral circuits 302 connected to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array provided in the form of an array of NAND memory strings 308, each of which memory cells 306 extend vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 comprises a plurality of memory cells 306 connected in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be either a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0027] In some embodiments, each memory cell 306 is a single-level cell (SLC) capable of storing 1 bit of data and having two possible memory states. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than 1 bit of data in four or more memory states. For example, an MLC can store 2 bits per cell (also known as a double-level cell (DLC)), 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores 2 bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal memory value may be used for the erase state.

[0028] As shown in Figure 3, each NAND memory string 308 may have a source select gate (SSG) 310 (or referred to as a source select transistor) at its source end and a drain select gate (DSG) 312 (or referred to as a drain select transistor) at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (a column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are connected through the same source line 314, such as a common SL (Source Line). In other words, all NAND memory strings 308 in the same block 304 have an array common source (ACS) according to some embodiments. The DSG 312 of each NAND memory string 308 is connected, according to some embodiments, to a respective bit line 316 on which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., above the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to each DSG 312 through one or more DSG lines 313, and / or by applying a selection voltage (e.g., above the threshold voltage of the transistor having the SSG 310) or a deselection voltage (e.g., 0V) to each SSG 310 through one or more SSG lines 315.

[0029] As shown in Figure 3, the NAND memory string 308 can be organized into multiple blocks 304, each having a common source line 314, such as being connected to an ACS. In some embodiments, each block 304 is a basic data unit for the erase operation, meaning that all memory cells 306 in the same block 304 are erased simultaneously. To erase the memory cells 306 in a selected block 304, the source line 314 connected to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). In some examples, the erase operation can be performed at the half-block level, the quarter-block level, or at any appropriate level with any appropriate number of blocks or any appropriate fragment of blocks.

[0030] Memory cells 306 of adjacent NAND memory strings 308 are connected via word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some embodiments, each word line 318 is connected to a page 320 of memory cells 306, which are the basic data units for program operations. The size of one page 320 in bits may relate to the number of NAND memory strings 308 connected by word lines 318 in one block 304. For ease of description, memory cells 306 in one page 320 may be connected to the same word line 318, and the terms “page” and “word line” may be used interchangeably in this disclosure. However, in some examples, memory cells 306 in one page 320 may be connected to two or more word lines 318. Each word line 318 may comprise a plurality of control gates (gate electrodes) in each memory cell 306 in each page 320, and gate lines connecting the control gates to each other. In some embodiments, each word line 318 may be coupled to multiple pages (or a portion of pages) of a memory cell based on the control of the SSG and DSG.

[0031] The peripheral circuit 302 can be connected to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0032] For example, Figure 4 shows several peripheral circuits, including a page buffer / sense amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, registers 414, an interface 416, and a data bus 418. It is understood that in some examples, additional peripheral circuits not shown in Figure 4 may also be included.

[0033] The page buffer / sense amplifier 404 may be configured to read data from the memory cell array 301 and to program (write) data to the memory cell array 301 according to a control signal from the control logic 412. In one example, the page buffer / sense amplifier 404 may store one page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 404 may perform a program verification operation to ensure that data has been properly programmed into the memory cell 306 connected to the selected word line 318. In yet another example, the page buffer / sense amplifier 404 may sense a low-power signal from the bit line 316 representing data bits stored in the memory cell 306, and amplify a small voltage amplitude to a logic level that is recognizable in the read operation. The column decoder / bit line driver 406 may be configured to be controlled by the control logic 412 and to select one or more NAND memory strings 308 by applying a bit line voltage generated by the voltage generator 410.

[0034] The row decoder / word line driver 408 can be configured to be controlled by control logic 412 and to select / deselect block 304 of the memory cell array 301 and to select / deselect word line 318 of block 304. The row decoder / word line driver 408 may be further configured to drive word line 318 using word line voltage generated from voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive SSG line 315 and DSG line 313. As will be described in detail later, the row decoder / word line driver 408 is configured to apply a read voltage to the selected word line 318 in a read operation in a memory cell 306 coupled to the selected word line 318. The read voltage may be either a read voltage corrected with a read offset based on empty blocks when the read voltage is applied to word line 318 in an empty block, or a default read voltage without a read offset based on empty blocks when the read voltage is applied to word line 318 in a full block.

[0035] The voltage generator 410, controlled by the control logic 412, may be configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages supplied to the memory cell array 301. Depending on whether the read operation is performed on an empty block or a full block, as will be described in detail later, the control logic 412 may control the voltage generator 410 to provide a default read voltage or a corrected read voltage with an offset from the default read voltage to the row decoder / word line driver 408.

[0036] The control logic 412 can be linked to each of the peripheral circuits described above and may be configured to control the operation of each peripheral circuit. The registers 414 can be linked to the control logic 412 and may include state registers, instruction registers, and address registers for storing state information, instruction operation codes (OP codes), and instruction addresses for controlling the operation of each peripheral circuit. As will be described in detail later, the state registers of register 414 may include one or more registers configured to store information about available blocks, such as having an ADSV list, indicating the available blocks of all blocks 304 in the memory cell array 301. In some embodiments, the information about available blocks also indicates the last programmed page of each available block.

[0037] Figure 5 shows a schematic diagram of the threshold voltage distribution of memory cells according to an embodiment of the present disclosure. The horizontal axis represents the threshold voltage of the memory cells (indicated as Vth). The vertical axis represents the number of memory cells corresponding to different threshold voltages.

[0038] In Figure 5, memory cells can be memory cells in a 3D NAND memory device, corresponding to pages, codewords, word line memory cell strings, blocks, planes, dies, etc. The memory cells are TLCs and can be programmed (or erased) to be in one of eight states (memory states) indicated by S0 to S7. A memory cell programmed (or erased) to a particular state may have a threshold voltage distributed within a voltage range. Therefore, in Figure 5, each state (S0 to S7) is shown to have a threshold voltage distribution. In some examples, these distributions can be modeled using a Poisson distribution.

[0039] A TLC memory cell can represent three bits depending on the state the memory cell is in. In other words, three bits can be encoded in one of eight states. The mapping between the states and each of the three bits can vary in different embodiments. In Figure 5, the eight states S0-S7 are mapped to 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The least significant bit (LSB) in the eight states can belong to a lower page. The middle significant bit (CSB) in the eight states can belong to the middle page. The most significant bit (MSB) in the eight states can belong to a higher page.

[0040] In Figure 5, seven default read reference voltages V1 to V7 are positioned between their respective memory cell threshold voltage distributions. Ideally, each memory cell threshold voltage distribution could fall within two neighboring default read reference voltages. In other words, it is desirable that a programmed or erased memory cell retains its intended state and thereby preserves the three bits it represents. However, memory cell threshold distributions can shift or expand from one distribution to another due to factors such as program / erase (P / E) cycles, retention periods, write or read disturbs, and temperature changes. Such changes in memory cell threshold distributions can lead to read errors.

[0041] For a given default read reference voltage, if a memory cell has a threshold voltage below the default read reference voltage, the memory cell is said to be in a lower state. If a memory cell has a threshold voltage above the default read reference voltage, the memory cell is said to be in a higher state. Also, in Figure 5, states to the right of the default read reference voltage are called higher states relative to the default read reference voltage. States to the left of the default read reference voltage are called lower states relative to the default read reference voltage.

[0042] Different sets of default reading reference voltages may be used for different MLC technologies. For example, SLC can use one default reading reference voltage to distinguish between two states. DLC can use three default reading reference voltages to distinguish between four states. QLC can use fifteen default reading reference voltages to distinguish between sixteen states.

[0043] Figure 6 shows a situation where the memory cell threshold voltage distribution is shifted. Distributions D1 and D2 (dashed lines) represent the ideal memory cell threshold voltage distribution corresponding to two neighboring states (such as S1 and S2 in Figure 5). default The default read reference voltage 601, as indicated, is positioned between distributions D1 and D2. Corresponding to an ideal threshold voltage distribution, the memory cell is in a state that accurately represents, or maps to, the encoded bits of the data programmed into the memory cell. Typically, the state of the memory cell at the time of programming can be an ideal distribution. In other words, the memory cell at the time of programming can have an ideal threshold voltage (or state) distribution.

[0044] When a single read operation is performed using the default read reference voltage 601, corresponding to distributions D1 and D2, memory cells belonging to distribution D2 are, for example, in state 0 (V default It is detected to be in a state of 1 (V), which indicates that it has a higher threshold voltage, resulting in a bit of 0. Memory cells belonging to distribution D1 are, for example, in a state of 1 (V defaultA bit is detected to indicate that the threshold voltage should be lower, resulting in a bit of 1. These detected bits correspond to the ideal threshold voltage distribution, or state of the memory cell, at the time being programmed. Thus, these bits are referred to as the original bit or ideal bit with respect to the corresponding default read reference voltage 601. It should be noted that when the data to be programmed into a set of memory cells is known, the ideal state of the set of memory cells (e.g., states S0-S7 in Figure 5) can be determined based on the data without any read operation. Thus, the original bit can be derived or calculated if the associated data is known. Thus, the original bit can also be used to refer to the derived or calculated bit in situations where an error bit is determined based on known data.

[0045] A page read operation is referred to as a single read operation when it occurs at a single read reference voltage (such as the default or non-default read reference voltage), compared to a page read operation where multiple read operations occur at multiple different read reference voltages.

[0046] Distributions D1' and D2' represent the actual threshold voltage distribution of the memory cell when the results of the ideal distributions D1 and D2 are deviated. Under the actual distribution, when a single read operation is performed using the default read reference voltage 601, it belongs to distribution D2', but V default Memory cells, each having a smaller threshold, for example, state 1 (V default This results in a detection that indicates a lower threshold voltage, yielding a bit of 1. Thus, the original bit 0 represented by these memory cells is inverted to 1. These inverted bits are called the inverted bits of the higher state when each memory cell changes its state from a higher state to a lower state.

[0047] It belongs to distribution D1', but V defaultMemory cells, each with a larger threshold, for example, state 0 (V default This results in detection that indicates a higher threshold voltage, yielding bit 0. Thus, the original bit 1 represented by these memory cells is inverted to 0. These inverted bits are referred to as lower state inverted bits when each memory cell changes its state from a lower state to a higher state. In addition to the memory cells associated with lower or higher state inverted bits, other memory cells belonging to distributions D1' and D2' can still be accurately detected to be in states 1 and 0, respectively.

[0048] During a page read operation (including multiple single read operations), inverted bit errors from multiple single read operations can result in bit errors in the page's codeword. When the raw bit error rate (RBER) of the codeword exceeds the ECC correction capability, the associated data (e.g., corresponding to the page) cannot be recovered, resulting in ECC decoding failure. To achieve successful ECC correction, it is desirable to reduce the number of inverted bits in single read operations.

[0049] This disclosure provides techniques and methods for searching for the best read reference voltage to minimize or reduce the number of inverted bits. Figure 6 shows V opt The optimal read reference voltage 602 is shown. The optimal read reference voltage 602 may be the read reference voltage in which the magnitude of the inverted bit (including inversion from 1 to 0 or 0 to 1) is smallest compared to other read reference voltages within the search range 610. The best read reference voltage 603 may be the output of the search process and is close to the optimal read reference voltage 602. The discrepancy between the best read reference voltage 603 and the optimal read reference voltage 602 may be limited to within the precision set in each search process.

[0050] As shown in the diagram, the search range 610 may have an upper limit offset 612 and a lower limit offset 611 defined with respect to the default reading reference voltage 601. Therefore, the upper limit of the search range 610 can be the default reading reference voltage 601 plus the upper limit offset 612. The lower limit of the search range 610 can be the default reading reference voltage 601 plus the lower limit offset 611 (which may have a negative value).

[0051] Figure 7 shows a read operation 700 according to an embodiment of the present disclosure. The operation 700 may be performed by a memory control device 106 to read data (such as a page or the page above) from a 3D NAND memory device 104. The operation 700 begins at S711.

[0052] In S711, a read operation may be performed, for example, to read a page from memory device 104. The page may be one of the lower, middle, or upper pages stored in the TLC set. Therefore, multiple single read operations, each based on a default read reference voltage, may be performed in the memory cell storing the page. For example, corresponding to the mapping between the three bits and eight states (S0 to S7) in Figure 5, three single read operations at default read reference voltages V2, V4, and V6 may be performed to read the middle page. The bits resulting from each single read operation may be processed to generate the raw bits of the codeword belonging to the page.

[0053] In S712, ECC decoding may be performed based on the raw bits of the codeword. Various types of ECC (low-density parity codes (LDPCs)) may be used in various embodiments. In S713, it is determined whether the ECC decoding was successful. If the RBER of the codeword exceeds the ECC correction capability, the ECC decoding of the page will fail. If the ECC decoding fails, process 700 proceeds to S714. Otherwise, process 700 proceeds to S716 and terminates in S716.

[0054] In S714, tuning of the read reference voltage is performed to determine a new read reference voltage. In S715, a read retry is performed based on the new read reference voltage. The operation in S715 may be similar to the operation in S711, but with the updated read reference voltage. Based on the raw codeword bits generated from S715, a second iteration of ECC decoding may be performed in S712. Read retries may be repeated until process 700 reaches S716, or until all available read reference voltages for read retries are exhausted.

[0055] When a read error occurs (as in S713), various methods for handling the read error can exist in various embodiments. In some examples, a read-retry table is used for the read-retry process. One or more lists of read reference voltages for read-retries may be provided in the read-retry table by, for example, the producer of each 3D NAND memory device or memory system (such as an SSD). Typically, the read-retry table is constructed based on consideration of a limited number of factors, such as retention period, read disturb, cross-temperature, and initial read problems. Therefore, the read-retry table may not be comprehensive for all situations.

[0056] In some embodiments, the best read reference voltage search method disclosed herein may be employed as an alternative to or in addition to the use of a read-retry table to determine the next read retry reference voltage.

[0057] In some embodiments, after an ECC decoding failure, a best read reference voltage search method is invoked to find the best read reference voltage. The best read reference voltage can then be used as the base voltage for the software LDPC decoding process. In the example of the software LDPC decoding process, the read reference voltages for multiple read-retries can be set around the best read reference voltage. Thus, multiple read-retry operations can be performed in a (stepwise) manner to obtain the log-likelihood ratio (LLR). The LLR can then be sent to the ECC engine (which may be separate from or part of the memory control unit 106) for software decoding of the codeword.

[0058] Figure 8 shows a best read level search process 800 based on a failed bit count (FBC) according to an embodiment of the present disclosure. The term "best read level" as used herein refers to the best read reference voltage level. The process 800 may be performed in an experimental environment where known data is programmed into blocks of memory cells in a memory device, for example.

[0059] Process 800 may include multiple coarse or fine scanning processes. Each scanning process can cover the search range of the read reference voltage in step voltages. At each scanning point (corresponding to a specific read reference voltage level, or read level), the read bits resulting from a single read operation can be compared to the original bits to determine the FBC (size of the inversion bit from 0 to 1, or from 1 to 0). The original bits can be derived based on known data. The read level with the minimum FBC can be determined to be the best read level for each scanning process. The search range can be defined for each default read reference voltage (or referred to as the default voltage). The best read level can be expressed as the best read offset relative to the default voltage.

[0060] The process 800 may include one step of coarse scanning (S810) and two steps of fine scanning (S820 and S830). TLC is used as an example to illustrate the process 800.

[0061] In S810, a coarse scan is performed on the word line cell string at default voltages. These default voltages can be, for example, V1-V7, which are all the default voltages configured for the TLC. The word line cell string may contain memory cells controlled by the word lines. A word line cell string can store three pages of known data. Therefore, the initial state or original bits of the word line cell string can be calculated based on the known data. The block under test may contain multiple layers of word lines.

[0062] Scan ranges and step voltages may be provided for each coarse scan. For example, a lower offset of -300mV and an upper offset of 300mV may be provided for each default voltage. Thus, the scan range may be {-300mV, +300mV} with each default voltage at the center point. For example, a coarse step voltage of 100mV may be provided. Thus, seven scan points are provided, namely -300mV, -200mV, -100mV, 0, 100mV, 200mV, and 300mV.

[0063] For each coarse scan, the read level at the scan point with the minimum FBC can be determined to be the best read level. In some examples, for each scan point, the read bits from the word line memory cell string may include bits from multiple codewords. The FBC for each codeword can be determined. The maximum FBC for each codeword can be determined for each scan point or read level. Therefore, the read level with the minimum maximum FBC for each codeword is determined as the best read level for each coarse scan (referred to as the coarse best read level). Therefore, the best read offset (referred to as the coarse best read offset) can be determined for each coarse scan.

[0064] If multiple read levels in a coarse scan have the same maximum FBC per codeword, the total FBC for all codewords in each read level is considered. The read level with the smallest total FBC is determined to be the best read level. If multiple read levels in a coarse scan have the same minimum total FBC, the read level with the smaller offset is determined to be the best read level.

[0065] In S820, a first fine scan is performed on the word line memory cell string in the block at a coarse best read level. For example, seven first fine scans may be performed for each word line memory cell string at seven coarse best read levels. Each first fine scan may have a scan range of {-200ms, 200ms} with its respective coarse best read level in the middle. Assuming the coarse best read level offset from S810 is -100ms, the scan range becomes {-300ms, 100ms} when the lower and upper offsets for each default voltage are used to define the scan range. Each first fine scan may be provided with a fine step voltage of 20ms, for example, smaller than a coarse step voltage of 100mV. In a similar manner to S810, the fine best read level and the corresponding fine best read offset can be found for each first fine scan based on the FBC.

[0066] In S830, a second fine scan is performed on the word line memory cell string in the block at a fine best read level. For example, for each word line memory cell string, seven second fine scans may be performed at seven fine best read levels. Each second fine scan may have a scan range of {-10ms, 10ms} with an intermediate fine best read level. Assuming the offset of the fine best read level from S820 is -120ms, the scan range becomes {-130ms, -110ms} when the lower and upper offsets for the respective default voltages are used to define the scan range. Each second fine scan may be provided with a fine step voltage of 10ms (or less than 10ms) smaller than, for example, a fine step voltage of 20mV. In the same manner as in S810 or S820, the final fine best read level and the corresponding final fine best read offset can be found for each second fine scan based on the FBC. Finally, for each block of memory cells, the best read level is obtained for each of the seven default voltages in each word-line memory cell string. In various examples, the results can be used as a basis for various evaluations or experiments. For example, the results can be used to evaluate the performance of the LDPC algorithm.

[0067] The FBC-based methods described herein are typically applicable to test or experimental environments. FBC-based methods rely on known data programmed into memory cells. For real memory systems, the data stored in the memory devices may be unknown. FBC-based methods can scan all word-line memory cell strings. For real memory systems, the best level of search is performed on one word-line memory cell string in response to a failed page read operation on that string. Scanning word-line memory cell strings in FBC-based methods may be too time-consuming and therefore unsuitable for real memory systems.

[0068] In some embodiments, a best read level search method based on bit count difference (BCD) is used. In the BCD-based method, the bit count difference between adjacent read levels (scan points) is calculated and used to determine the best read level. Therefore, the BCD-based method does not rely on known data programmed into a memory device, which may not be available in a real memory system.

[0069] Furthermore, the BCD-based method is used to find the best read level for reading a page. Therefore, the scanning operation is performed on a limited number of default voltages instead of all default voltages in the word line memory cell string. For example, to read a middle page, the scanning operation may be performed around three default voltages (e.g., V2, V4, and V6) to find three best read levels. Also, the scanning operation is not performed on all word line memory cell strings in the entire block.

[0070] In some examples, in BCD-based methods, for each read level (scan point), a partial page read is used instead of a full page read during a single read operation. For example, a page stored in a word line memory string may be 16k bytes long. The page may contain four codewords, each 4k bytes long. Therefore, the BCD-based method can read from the memory cell corresponding to the codeword instead of the page. The number of bits resulting from a single read operation can be reduced. Thus, the delay in data transmission from the memory device to the memory control unit can be reduced.

[0071] In some examples, the scan range used in the BCD-based method is optimized based on the read level deviation observed in some worst-case scenarios. Therefore, scan time can be reduced. In some examples, the BCD-based method can use one coarse scan and one fine scan. The scan process is simplified compared to one coarse scan and two fine scans in the search process 800. In some examples, hardware support is available to calculate the bit count for the BCD. This can reduce the time required to calculate the bit count compared to FBC calculations performed using software.

[0072] Figure 9 shows a BCD table 900 for determining the best read level from a series of read levels (scan points) during a scan process. The scan process may be part of a best read level search process based on the BCD. The first column of the BCD table 900 contains the series of scan points covered by the scan process. A scan point is represented by a scan point offset (or read level offset). A step voltage of 10 mV is used. At each scan point, a single read operation may be performed. Bits can be read from a set of memory cells belonging to a word line memory cell string. For example, a memory cell with a threshold voltage lower than the scan point's read level is read as 1. A memory cell with a threshold voltage higher than the scan point's read level is read as 0.

[0073] Considering the current scan point, two BCDs can be calculated. The first BCD, denoted as BCD-L, may be the BCD between the current scan point and the scan point adjacent to it on the left. The second BCD, denoted as BCD-R, may be the BCD between the current scan point and the scan point adjacent to it on the right. The left or right position may be relative to the search range along the threshold voltage axis. Typically, larger read levels are to the right of smaller read levels. For read levels near the left or right boundary of the search range, the left or right scan points are unavailable. The respective BCD-L or BCD-R are not calculated and are unavailable. Typically, read levels near the search range boundaries may be excluded from candidate scan points for selecting the best read level.

[0074] For each scan point corresponding to the above BCD-L and BCD-R values, the best read level can be selected from a set of scan points. First, the read level at the scan point with the smallest sum of BCD-L and BCD-R (indicated as Sum(BCD-L,BCD-R)) may be determined to be the best read level. If multiple scan points have the same sum of BCD-L and BCD-R, the read level at the scan point with the smallest minimum value of either BCD-L or BCD-R (indicated as Min(BCD-L,BCD-R)) may be determined to be the best read level among these scan points. If there are still multiple scan points with the same minimum value of BCD-L or BCD-R, the scan point closest to the midpoint of the scan range may be determined to be the best scan point with the best read level. In relation to the best read level, the corresponding scan point offset may be determined to be the best read offset for each default voltage.

[0075] Figures 10A and 10B show a BCD-based best read level search process 1000 according to embodiments of the present disclosure. The BCD-based search process 1000 may be performed to find the best read reference voltage for a page read operation. The process 1000 may include two parts: a coarse search part S1002 to S1016 and a fine search part S1024 to S1036.

[0076] In S1002, ECC decoding fails during the page read operation. For example, the raw codeword bits of the target page are obtained based on data read from the memory device by one or more single read operations. Hardware LDPC decoding based on the raw codeword bits may fail due to a high RBER. A search process 1000 based on BCD may then be invoked to find the best read level for a target page read retry or software LDPC decoding.

[0077] In S1004, the read level corresponding to the default voltage may be initialized. The number of read levels to be covered may be determined depending on which MLC technology the target page uses, what kind of target page it is (e.g., a lower page or a higher page), and how the bits are encoded by the memory cell state. For example, for SLC, a single read operation may be performed at a certain read level. For DLC, one read level may be covered to read a lower page, and two read levels may be covered to read a higher page. For TLC, two read levels, three read levels, and two read levels may be covered to read a lower page, a middle page, and a higher page, respectively. Coarse and fine searches cover the read levels determined in S1004.

[0078] In S1006, it is determined whether the next read level is available. If all read levels determined in S1004 have been completed and the next read level is not available, process 1000 proceeds to S1024 and enters the detailed search phase. Otherwise, process 1000 proceeds to S1008, where it selects a read level from among the read levels determined in S1004. The read levels can be selected in any order.

[0079] In S1008, the scan point offset may be initialized in accordance with the selected read level. For example, the number and position (voltage value) of each scan point may be determined based on the scan range (or scan voltage range) and step voltage. The scan points may be indicated in the form of scan point offsets relative to the respective default voltages corresponding to the selected read level. For example, upper and lower limit offsets relative to the default voltages may be provided to indicate the scan range.

[0080] In S1010, it is determined whether the next scan point offset is available. If all scan point offsets determined in S1008 have been used and no further scan point offsets are available, process 1000 proceeds to S1016. Otherwise, process 1000 proceeds to S1012. In S1012, a scan point offset is selected from the scan point offsets determined in S1008. The scan point offsets can be selected in any order.

[0081] In S1014, a single read operation may be performed at the scan point of the selected scan point offset on the memory cell that stores the target page. Bits resulting from the single read operation may be stored in memory. If read bits from neighboring scan points are available in memory, the BCD-L or BCD-R between the current scan point and neighboring scan points may be calculated and stored in a BCD table, such as the table shown in Figure 9. If available, process 1000 may return to S1010 to process the next scan point offset.

[0082] In S1016, at the current stage, the BCD-L and BCD-R for each scan point offset are placed into the BCD table corresponding to the current read level selected in S1006. Based on the BCD table, a coarse best read offset can be determined for the current read level. This coarse best read offset can be used as the central scan point offset for a finer search corresponding to the current read level. If available, process 1000 can proceed to S1006 to process the next read level.

[0083] In S1024, the fine-grained search portion of process 1000 begins based on the coarse best read offset for each read level. More specifically, in S1024, the read levels corresponding to the default voltage are initialized in the same manner as in S1004. The same set of read levels may be determined. In S1026, it may be determined whether the next read level is available. When all read levels have been covered, process 1000 can proceed to S1038, where it terminates. Otherwise, process 1000 proceeds to S1028 with the selected read level.

[0084] In S1028, scan point offsets for finer search corresponding to the selected read level may be initialized. For example, the number and location of scan point offsets for finer search may be determined based on a finer scan range and a finer step voltage. For example, the finer scan range can use each coarser best read level as its center point. Upper and lower limits may be set relative to the center location.

[0085] In S1030, it may be determined whether the next scan point offset is available. If all scan point offsets are covered, process 1000 proceeds to S1036. Otherwise, process 1000 proceeds to S1032. In S1032, the next scan point offset is selected. In S1034, a single read operation is performed at the selected scan point offset to read bits from the memory cell storing the target page. The BCD-L or BCD-R of the current scan point offset or a neighboring scan point offset may be calculated to fill the BCD table. Process 1000 can return to S1030 to process the next available scan point offset.

[0086] In S1036, the BCD table corresponding to the current read level is filled. A fine-grained best read offset can be determined for the current read level. Process 1000 can then proceed to S1026 to process the next available read level. When process 1000 finishes in S1038, the best read levels corresponding to the fine-grained best read offsets are available for each read level. In some examples, the obtained best read levels can then be used in the LDPC software decoding process.

[0087] Figure 11A shows two tables 1110 and 1120 to illustrate how to optimize the scan range used for coarse searching in a BCD-based search process 1000 according to embodiments of the present disclosure. In the example in Figure 11A, the optimized scan range for coarse searching at a particular read level corresponding to each default voltage (referred to as the optimized coarse scan range) may be determined based on the set of data provided in table 1110. Table 1110 contains seven columns. Each column corresponds to one of seven read levels (or seven default voltages) for the TLC. The seven read levels are indicated as RD1 to RD7. Table 1110 contains multiple rows.

[0088] Each row contains a set of best read offsets corresponding to one of the seven read levels, RD1 through RD7. Each best read offset has an offset value (in mV) relative to its respective default voltage (e.g., V1 through V7 in Figure 5). For example, for read level RD1, the first best read offset is -130mV, and the last best read offset is -60mV relative to the default voltage V1.

[0089] Each row of the best read offsets can correspond to a memory cell condition that causes a set of memory cells to have or exhibit a particular best read offset. For example, the condition may be a combination of several factors. Factors may include the type of workload, ambient temperature, retention period, read disturb, cross-temperature, initial read problems, and manufacturing process. Different conditions can correspond to different factor values. For example, a set of memory cells can be placed under conditions in an experimental environment. The best read offsets can then be measured from these memory cells. In some embodiments, the conditions considered may be a set of extreme conditions associated with the worst-case scenario. Thus, some of the best read offsets may represent the maximum change in the best read offset under extreme conditions.

[0090] Table 1120 shows the optimized coarse search range derived from the best read offsets collected in Table 1110. As illustrated, for each read level (RD1, RD2, and RD3), the minimum value in each column of the best read offsets is used as the lower limit offset, while the maximum value in each column of the best read offsets is used as the upper limit offset. Together, the lower and upper limit offsets can define the optimized coarse search range for each read level for each default voltage. For example, the lower boundary voltage of the optimized coarse search range is the default voltage plus the lower limit offset. The upper boundary voltage of the optimized coarse search range is the default voltage plus the upper limit offset.

[0091] In Table 1120, the offsets in the first, second, and third columns can be used for coarse searches at their respective read levels RD1, RD2, and RD3. Other upper and lower offsets for other read levels can be derived similarly, as needed.

[0092] Figure 11B shows two tables 1130 and 1140 to illustrate how to optimize the scan range used for fine-grained searching in a BCD-based search process 1000 according to embodiments of the present disclosure. Table 1130 contains a number of rows with values ​​equal to the number of rows for best read offsets in Table 1110. The first column of Table 1130 contains a list of best read offset differences between columns RD2 and RD4. Each such best read offset difference may be the difference between two best offset values ​​in the same row in Table 1110, but in different columns RD2 and RD4. For example, considering the last row of Table 1110, the difference between the value in column RD2 and the value in column RD4 is -40mV - (-30)mV = -10mV (subtracting the value at a lower level from the value at a higher read level). Similarly, the second column of Table 1130 contains a list of best read offset differences between columns RD4 and RD6.

[0093] Table 1140 shows the optimized fine-grained search ranges for read levels RD4 and RD6. The optimized search ranges can be derived based on the best read offset differences in Table 1130. Specifically, for the fine-grained search range of RD4 in Table 1140, a lower limit offset of -80mV may be the minimum of the best read offset differences listed in the first column of Table 1130, and an upper limit offset of 50mV may be the maximum of the best read offset differences listed in the first column of Table 1130. These lower and upper limit offsets can be offsets relative to the anchor voltage when used in the fine-grained search process. For example, the anchor voltage for RD4 may have an anchor offset relative to the default voltage for RD4. The anchor offset can be equal to the fine-grained best read offset for read level RD2. The fine-grained best read offset for RD2 can be found, for example, in the optimized coarse-grained search range for RD2 {-190mV, 70mV} indicated in Table 1120. Two iterations of the search (a coarse search and a fine search) can be performed to find the finest reading of the RD2 set, as in the examples in Figures 10A and 10B.

[0094] Similarly, for the fine-grained search range of RD6 in Table 1140, a lower limit offset of -160mV may be the minimum of the listed best-read offset differences in the second column of Table 1130, and an upper limit offset of 60mV may be the maximum of the listed best-read offset differences in the second column of Table 1130. These lower and upper limit offsets may be offsets relative to the anchor voltage for RD6. The anchor voltage for RD6 may have an anchor offset relative to each default voltage of RD6. The anchor offset for RD6 may be equal to the fine-grained best-read offset for read level RD4. The fine-grained best-read offset for RD4 can be found, for example, within the optimized fine-grained search range {-80mV, 50mV} for RD2 as indicated in Table 1140. Table 1140 also lists a fine-grained search range {-100mV, 100mV} for RD2. This fine-grained search range may be set based on any other method.

[0095] As described above, the combination of coarse and fine searches is first performed in the coarse search range for RD2 in Table 1120 to find the fine best read offset for RD2. When the fine best read offset for RD2 is used as the anchor offset, the fine search is performed in the fine search range for RD4 in Table 1140 to find the fine best read offset for RD4. The fine best read offset for RD4 is used as the anchor offset, and the fine search range for RD6 can be determined in the fine search range for RD6 in Table 1140. In this method, three best read offsets can be determined for read levels RD2, RD4, and RD6, and can be used to read the middle page in the example in Figure 5.

[0096] In other examples, the above order (RD2 to RD6) may be changed to any order. For example, the above search can take any order, such as RD6, RD2, and RD4. A combination of coarse and fine searches may start with RD6 and be followed by two fine searches in RD2 and RD4. In this order, the coarse and fine search ranges of the corresponding levels may be adjusted accordingly. For example, the fine best offset of RD6 can be used as the anchor offset of RD2. Thus, the fine search range of RD2 may be determined based on the best read offset difference between the best read offset of RD2 and the best read offset of RD6. Alternatively, the fine best offset of RD6 can be used as the anchor offset of RD4.

[0097] The previous description uses the middle page read levels RD2, RD4, and RD6 of the TLC as an example to illustrate methods for optimizing coarse or fine search ranges. However, the search optimization methods can be used for any type of MLC with one, two, three, four, or more pages stored.

[0098] Compared to setting the search range indiscriminately, the search range (or scan range) obtained using the search range optimization method disclosed herein can be shortened, thus accelerating the best read-level search process. Furthermore, when the search range optimization method disclosed herein is used, some coarse search processes can be skipped, further accelerating the best read-level search process. Moreover, the search range optimization method disclosed herein is not dependent on any particular search method. The search range optimization method can be used to provide an optimized search range to any best read search method.

[0099] Figures 12A to 12C illustrate the best read level search process according to embodiments of the present disclosure. The best read levels corresponding to the default voltages V2 and V4 for reading the middle page from the TLC may be determined during the process. Optimized coarse and fine search ranges are used during the process.

[0100] Figure 12A shows a coarse search range 1210. The coarse search range 1210 has an upper limit offset 1212 of 70mV and a lower limit offset 1211 of -190mV relative to the default voltage 1213 of V2. The coarse search range 1210 may be an optimized coarse search range determined using the coarse search range optimization method described in the examples in Figures 11A and 11B. A coarse search with a 100mV step voltage may be performed over the coarse search range 1210 to find a coarse best read level 1214 with a coarse best read offset 1215 of -30mV relative to the default voltage 1213 of V2.

[0101] Figure 12B shows a fine search range 1220 defined with a coarse best read level 1214 as the central scan point 1214. The fine search range 1220 may have a lower offset 1221 of -100mV and an upper offset 1222 of 100mV relative to the central scan point 1214. Following the coarse search in Figure 12A, a fine search with a 10mV step voltage may be performed over the fine search range 1220 to find a fine best read level 1223. The fine best read level may have a fine best read offset 1224 of -50mV relative to the default voltage 1213 of V2.

[0102] Figure 12C shows another finer search range 1230 for the read level corresponding to the default voltage 1235 of V4. The finer search range 1230 may be determined based on another scan point (anchor voltage) 1233. The anchor scan point 1233 may have the same offset value as the finer best read offset 1224 of -50mV relative to the default voltage 1235 of V4. The finer search range 1230 may have a lower limit offset 1231 of -80mV and an upper limit offset 1232 of 50mV relative to the anchor scan point 1233. Following the finer search in Figure 12B, another finer search may be performed on the finer search range 1230 in 10mV voltage steps to find the best read level 1236. The best read level 1236 may have a best read offset 1237 relative to the default voltage V4.

[0103] Figure 13 shows the best read level search process 1300 according to an embodiment of the present disclosure. Process 1300 can start from S1310.

[0104] In S1310, a first best read offset of a first best read reference voltage relative to a first default read reference voltage can be determined. For example, a second scan range can be determined to determine the first best read offset. The second scan range may have an upper limit, which is the first default read reference voltage plus an upper limit offset, and a lower limit, which is the first default read reference voltage plus a lower limit offset. The second scan range can be scanned based on a coarse step voltage by performing a series of first single read operations within the second scan range. Each first single read operation generates a bit count of either 1 or 0. Each first single read operation corresponds to a first read reference voltage.

[0105] For example, for each first single read operation, if available, a first bit count difference can be determined between the bit count of each first single read operation and the bit count of the previous first single read operation. If available, a second bit count difference can be determined between the bit count of each first single read operation and the bit count of the subsequent first single read operation. The first read reference voltage of the first single read operation whose sum of the first and second bit count differences is the smallest among the series of first single read operations can be determined to be the coarse best read reference voltage.

[0106] In the example, when there are two or more first single read operations in which the sum of their respective first bit count differences and their respective second bit count differences is the same, the first read reference voltage of the first single read operation having the minimum of the two or more first single read operations can be determined to be the coarse best read reference voltage.

[0107] In some cases, a third scan range may subsequently be determined. The third scan range may have an upper limit, which is the coarse best-read reference voltage plus a coarse step voltage, and a lower limit, which is the coarse best-read reference voltage minus a coarse step voltage. The third scan range may be scanned based on a fine step voltage by performing a series of second single-pass read operations within the third scan range. Each second single-pass read operation corresponds to a second read reference voltage. Each second single-pass read operation generates a bit count of either 1 or 0.

[0108] For each second single read operation, if available, a first bit count difference can be determined between the bit count of each second single read operation and the bit count of the previous second single read operation. Also, if available, a second bit count difference can be determined between the bit count of each second single read operation and the bit count of the subsequent second single read operation. Thus, the second read reference voltage of the second single read operation whose sum of the first and second bit count differences is the smallest among the series of second single read operations can be determined to be the first best read reference voltage. The offset of the first best read reference voltage to the first default read reference voltage is the first best read offset.

[0109] In S1320, an anchor read reference voltage may be determined with respect to a second default read reference voltage, having the same offset as the first best read offset. The first and second default read reference voltages are set for reading pages from a set of MLCs in a semiconductor memory device.

[0110] In S1330, the first scanning range may be determined based on the anchor reading reference voltage. For example, the upper limit of the first scanning range is the anchor reading reference voltage plus an upper limit offset. The lower limit of the first scanning range is the anchor reading reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive or negative voltage values.

[0111] In S1340, the second best read offset of the second best read reference voltage relative to the second default read reference voltage can be determined by searching within the first scan range. For example, the first scan range can be scanned by performing a series of third single read operations within the first scan range. Each third single read operation corresponds to a third read reference voltage. Each third single read operation generates a bit count of either 1 or 0.

[0112] For each third single read operation, if available, a first bit count difference can be determined between the bit count of each third single read operation and the bit count of the previous third single read operation. If available, a second bit count difference can be determined between the bit count of each third single read operation and the bit count of the subsequent third single read operation. Thus, the third read reference voltage of the third single read operation whose sum of the first and second bit count differences is the smallest among the series of third single read operations can be determined to be the second best read reference voltage. The offset of the second best read reference voltage to the second default read reference voltage is the second best read offset. In some examples, the first, second, and third single read operations are partial page read operations.

[0113] In S1350, a read operation may be performed to read a page from a set of MLCs based on a first best read reference voltage and a second best read reference voltage. Operation 1300 can then be terminated.

[0114] Figures 14A to 14B show a performance comparison between a first best read search process and a second best read search process according to embodiments of this disclosure. The first best read search process may be a best read level search process based on FBC, as in the example in Figure 8. The second best read search process may be a best read level search process based on BCD, as in the examples in Figures 9 to 13.

[0115] Figure 14A shows the total time to complete the first best read level search process for a word line memory cell string. A word line memory cell string may contain MLCs with (n+1) states. Therefore, there are n read levels to be processed. The total time, denoted by T, is T = SUM(K, M, N) * (tR + tDMA + tOH) * n levels (1) This is possible. In equation (1), n ​​levels represent the number of read levels to be processed. K, M, and N indicate the number of scan steps performed between the coarse scan, the first fine scan, and the second fine scan, respectively, when processing each read level. The time for each scan step includes the page read time tR, the data transmission time (e.g., between the memory device and the memory controller), tDMA, and the firmware (FW) processing overhead time tOH.

[0116] Figure 14B shows the total time to complete the second best read level search process for a word line memory cell string. The word line memory cell string may also contain MLCs having (n+1) states. However, the number of read levels processed is less than n. For example, to read the middle page of a TLC, the search process may be performed at three read levels (e.g., RD2, RD4, and RD4). Thus, the total time shown by T' is: T'=K'*(tR'+tDMA'+tOH')+ΣM[i]*(tR'+tDMA'+tOH') (2) This is possible. In equation (2), K' represents the number of scan steps performed during a coarse scan at the first read level among the read levels being processed. M'[i] represents the number of scan steps performed during a fine scan at each read level indexed by i. The time for each scan step includes the single read operation time tR', the data transmission time (e.g., between the memory device and the memory controller), tDMA', and the firmware (FW) processing overhead time tOH'.

[0117] Comparing the example in Figure 14B with the example in Figure 14A, the read time tR' can be made smaller than tR because a single read operation can be used instead of a normal page read operation. The data transmission time tDMA' can be made smaller than tDMA because a partial page read can be used instead of a full page read, reducing the amount of data transmitted. The FW processing overhead tOH' can be made smaller than tOH because the bit count in the second search method (at each scan step) may have hardware acceleration assistance, while the FBC (comparison between read bits and original bits) can be performed using the FW. The number of scan steps K' and M'[i] can also be reduced from K and M by employing search range optimization techniques. The second finer search is excluded from the second search method, and therefore N does not appear in equation (2). Also, as shown in Figure 14B, the coarse scan (including the K' scan step) is performed only at the first read level. The other read levels each contain only fine scans. Reducing the coarse scan to one can also save time.

[0118] In various embodiments, the best read level search methods disclosed herein may be implemented in a memory control device (such as memory control device 106) or in a memory device (such as memory device 104). These methods may be invoked in response to an ECC decoding failure or may run in the background. In some embodiments, the methods disclosed herein may be implemented in hardware, software, or a combination thereof. For example, the best read level search methods disclosed herein may be implemented using instructions stored on a non-temporary computer-readable medium. A processor or processing circuit may execute instructions to implement each method.

[0119] Aspects of this disclosure provide a memory control device that implements the technology disclosed herein. For example, the memory control device may include a circuit configured to implement the method. The method may include the steps of: determining a first best read offset for a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage for a second default read reference voltage having the same offset as the first best read offset, wherein the first and second default read reference voltages are set for reading pages from a set of multilevel cells (MLCs) in a semiconductor memory device in a memory system; determining a first scan range based on the anchor read reference voltage, wherein the upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and the lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, where the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read offset for a second best read reference voltage relative to a second read reference voltage by searching within the first scan range; and performing a read operation to read pages from a set of MLCs based on the first and second best read reference voltages.

[0120] Aspects of this disclosure provide a non-temporary computer-readable medium for storing instructions for implementing the technology disclosed herein. For example, the instructions can cause a processor (or processing circuit) to implement a method when executed by the processor (or processing circuit). The method may include the steps of: determining a first best read offset for a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage for a second default read reference voltage having the same offset as the first best read offset, wherein the first and second default read reference voltages are set for reading pages from a set of multilevel cells (MLCs) in a semiconductor memory device in a memory system; determining a first scan range based on the anchor read reference voltage, wherein the upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and the lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, where the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read offset for a second best read reference voltage relative to a second read reference voltage by searching within the first scan range; and performing a read operation to read pages from a set of MLCs based on the first and second best read reference voltages.

[0121] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also understand that such equivalent structures will not deviate from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alternatives can be made herein without departing from the spirit and scope of the present disclosure. [Explanation of Symbols]

[0122] 100 Systems 102 memory systems 104 Memory Devices 106 Memory control unit 108 hosts 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 300 memory devices 301 memory cell array 302 Peripheral Circuits 304 blocks 306 memory cells 308 NAND memory string 310 Source Selection Gate, SSG 312 Drain Select Gate, DSG 314 Source Line 316-bit line 318 Word lines 320 pages 404 Page Buffer / Sense Amplifier 406-column decoder / bit line driver 408-line decoder / word line driver 410 Voltage Generator 412 Control Logic 414 registers 416 Interface 418 Data Bus 601 Default reading reference voltage 602 Optimal reading reference voltage 603 Best Reading Reference Voltage 610 Search range 611 Lower limit offset 612 Upper limit offset 700 Loading process 800 Best read level search process 900 BCD Table Searching for the best read level based on 1000 BCD 1110, 1120 Tables for rough search 1130, 1140 Tables for detailed exploration 1210 Coarse search range 1211 Lower limit offset 1212 Upper limit offset 1213 Default Voltage 1214 Coarse best read level, central scan point 1215 Rough Best Read Offset 1220 Detailed search range 1221 Lower limit offset 1222 Upper limit offset 1223 Finest Best Loading Level 1224 Fine-grained best read offset 1230 Detailed search range 1231 Lower limit offset 1232 Upper limit offset 1233 scan points, anchor voltage 1235 Default Voltage 1236 Best Load Level 1237 Best read offset D1, D2, D1', D2' distribution S0, S1, S2, S3, S4, S5, S6, S7 status V1, V2, V3, V4, V5, V6, V7 Default reading reference voltage Vth threshold voltage

Claims

1. Memory devices and, A memory control device, Performing a first scan operation corresponding to a target page in order to obtain a first read offset, wherein the first read offset is the offset of the first read voltage with respect to a first read reference voltage of the first read level, Performing a second scan operation corresponding to the target page in order to obtain a second read offset, wherein the second read offset is the offset of the second read voltage relative to a second read reference voltage of the second read level, and the scan range of the second scan operation is determined based on an anchor read voltage having the same offset as the first read offset relative to the second read reference voltage. Based on the first and second load offsets, a second load operation corresponding to the target page is performed. A memory control device configured to perform the following: A memory system equipped with the following features.

2. The first scanning operation is Based on the first reading reference voltage, a first voltage range is determined; Scanning the first voltage range based on a first step voltage by performing a series of first single-pass reading operations within the first voltage range, wherein one first single-pass reading operation corresponds to one first scanning voltage within the first voltage range; Based on the scanning of the first voltage range, a third reading reference voltage is determined, Based on the third reading reference voltage, a second voltage range is determined, Scanning the second voltage range based on a second step voltage by performing a series of second single-pass reading operations within the second voltage range, wherein one second single-pass reading operation corresponds to one second scanning voltage within the second voltage range. The first read offset is determined based on the scanning of the second voltage range. The memory system according to claim 1, including the following:

3. Determining the first voltage range is Acquiring a first set of first reference offsets, wherein one first reference offset is a voltage shift relative to the first read reference voltage, the one first reference offset corresponds to a memory cell condition such that a set of memory cells under such memory cell conditions each have the one first reference offset, and the one first reference offset has a positive or negative value. The maximum value of the first set of the first reference offsets is set as the upper limit offset of the first voltage range, The minimum value of the first set of the first read offsets is set to the lower limit offset of the first voltage range. The memory system according to claim 2, including the memory system according to claim 2.

4. Determining the scanning range is Obtaining a second set of second reference offsets, wherein one second reference offset corresponds to the first set of first reference offsets and one of the respective memory cell conditions, the one second reference offset is a voltage shift relative to the second read reference voltage, and each of the second set of second reference offsets has either a positive or negative value. Determining the difference between each pair of the first reference offset and each pair of the second reference offsets, wherein the difference is equal to each pair of the second reference offsets minus each pair of the first reference offsets. The maximum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the upper limit offset of the scanning range, The minimum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the lower limit offset of the scanning range. The memory system according to claim 3, including the memory system according to claim 3.

5. Each single read operation generates a bit count of 1 or 0. Determining the third reading reference voltage is Determining a first bit count difference and a second bit count difference corresponding to the first scanning voltage within the first voltage range, wherein two adjacent scanning voltages of the first scanning voltage include a first low scanning voltage and a first high scanning voltage, the first bit count difference is the bit count difference between the bit counts corresponding to the first scanning voltage and the first low scanning voltage, respectively, and the second bit count difference is the bit count difference between the bit counts corresponding to the first scanning voltage and the first high scanning voltage, respectively. The third read reference voltage is determined based on the sequence of the first bit count difference and the second bit count difference corresponding to the first scanning voltage within the first voltage range. The memory system according to claim 2, including the memory system according to claim 2.

6. Determining the third reading reference voltage is The first scanning voltage is determined as the third read reference voltage such that the sum of the respective first bit count differences and the respective second bit count differences is minimized. When there are multiple first scanning voltages in which the sum of each of the first bit count differences and each of the second bit count differences is the same, the first scanning voltage in which the minimum value of each of the first bit count differences and each of the second bit count differences is minimized among the multiple first scanning voltages is determined as the third read reference voltage, When there are multiple first scanning voltages in which the minimum values ​​of the respective first bit count differences and the respective second bit count differences are the same among the plurality of first scanning voltages, the first scanning voltage closest to the midpoint of the first voltage range is determined as the third read reference voltage. The memory system according to claim 5, including the memory system according to claim 5.

7. The second voltage range has an upper limit obtained by adding the first step voltage to the third reading reference voltage, and a lower limit obtained by subtracting the first step voltage from the third reading reference voltage. Each single read operation in each second generates a bit count of either 1 or 0. Obtaining the first read offset is Determining a third bit count difference and a fourth bit count difference corresponding to a second scanning voltage within the second voltage range, wherein two adjacent scanning voltages of the second scanning voltage include a second lower scanning voltage and a second higher scanning voltage, the third bit count difference is the bit count difference between each bit count corresponding to the second scanning voltage and the second lower scanning voltage, and the fourth bit count difference is the bit count difference between each bit count corresponding to the second scanning voltage and the second higher scanning voltage. The first read voltage is determined to be the second scanning voltage having the minimum value of the sum of the third bit count difference and the fourth bit count difference, wherein the offset of the first read voltage with respect to the first read reference voltage is the first read offset. The memory system according to claim 2, including the memory system according to claim 2.

8. The second scanning operation described above is: Scanning the scanning range by performing a series of third single read operations within the scanning range, wherein one third single read operation corresponds to one third scanning voltage within the scanning range, and each third single read operation generates a bit count of either 1 or 0. Determining a fifth bit count difference and a sixth bit count difference corresponding to a third scanning voltage within the scanning range, wherein two adjacent scanning voltages of the third scanning voltage include a third lower scanning voltage and a third higher scanning voltage, the fifth bit count difference is the bit count difference between the bit count corresponding to the third scanning voltage and the third lower scanning voltage, and the sixth bit count difference is the bit count difference between the bit count corresponding to the third scanning voltage and the third higher scanning voltage. The third scanning voltage having the minimum value of the sum of each of the fifth bit count differences and each of the sixth bit count differences is determined to be the second read voltage, wherein the offset of the second read voltage with respect to the second read reference voltage is determined to be the second read offset. The memory system according to claim 1, including the following:

9. The memory system according to claim 1, wherein the second read operation is performed according to the first read voltage and the second read voltage, the first read voltage being determined based on the first read reference voltage and the first read offset, and the second read voltage being determined based on the second read reference voltage and the second read offset.

10. An error correction code (ECC) circuit configured to perform error correction code operation, It is a circuit, Performing a first scan operation corresponding to a target page in order to obtain a first read offset, wherein the first read offset is the offset of the first read voltage with respect to a first read reference voltage of the first read level, Performing a second scan operation corresponding to the target page in order to obtain a second read offset, wherein the second read offset is the offset of the second read voltage relative to a second read reference voltage of the second read level, and the scan range of the second scan operation is determined based on an anchor read voltage having the same offset as the first read offset relative to the second read reference voltage. Based on the first and second load offsets, a second load operation corresponding to the target page is performed. A circuit configured to perform the following A memory control device equipped with the following features.

11. The first scanning operation is Based on the first reading reference voltage, a first voltage range is determined, Scanning the first voltage range based on a first step voltage by performing a series of first single-pass read operations within the first voltage range, wherein one first single-pass read operation corresponds to one first scan voltage within the first voltage range. Based on the scanning of the first voltage range, a third reading reference voltage is determined, Based on the third reading reference voltage, a second voltage range is determined, Scanning the second voltage range based on a second step voltage by performing a series of second single-pass reading operations within the second voltage range, wherein one second single-pass reading operation corresponds to one second scanning voltage within the second voltage range. The first read offset is determined based on the scanning of the second voltage range. The memory control device according to claim 10, including the following:

12. Determining the first voltage range is Acquiring a first set of first reference offsets, wherein one first reference offset is a voltage shift relative to the first read reference voltage, the one first reference offset corresponds to a memory cell condition such that a set of memory cells under such memory cell conditions each have the one first reference offset, and the one first reference offset has a positive or negative value. The maximum value of the first set of the first reference offsets is set as the upper limit offset of the first voltage range, The minimum value of the first set of the first read offsets is set to the lower limit offset of the first voltage range. The memory control device according to claim 11, including the following:

13. Determining the scanning range is Obtaining a second set of second reference offsets, wherein one second reference offset corresponds to the first set of first reference offsets and one of the respective memory cell conditions, the one second reference offset is a voltage shift relative to the second read reference voltage, and each of the second set of second reference offsets has either a positive or negative value. Determining the difference between each pair of the first reference offset and each pair of the second reference offsets, wherein the difference is equal to each pair of the second reference offsets minus each pair of the first reference offsets. The maximum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the upper limit offset of the scanning range, The minimum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the lower limit offset of the scanning range. The memory control device according to claim 12, including the following:

14. Each single read operation generates a bit count of either 1 or 0. Determining the third reading reference voltage is Determining a first bit count difference and a second bit count difference corresponding to the first scanning voltage within the first voltage range, wherein two adjacent scanning voltages of the first scanning voltage include a first low scanning voltage and a first high scanning voltage, the first bit count difference is the bit count difference between the bit counts corresponding to the first scanning voltage and the first low scanning voltage, respectively, and the second bit count difference is the bit count difference between the bit counts corresponding to the first scanning voltage and the first high scanning voltage, respectively. The third read reference voltage is determined based on the sequence of the first bit count difference and the second bit count difference corresponding to the first scanning voltage within the first voltage range. The memory control device according to claim 11, including the following:

15. Determining the third reading reference voltage is The first scanning voltage is determined as the third read reference voltage such that the sum of the respective first bit count differences and the respective second bit count differences is the minimum value. When there are multiple first scanning voltages in which the sum of each of the first bit count differences and each of the second bit count differences is the same, the first scanning voltage in which the minimum value of each of the first bit count differences and each of the second bit count differences is minimized among the multiple first scanning voltages is determined as the third read reference voltage, When there are multiple first scanning voltages in which the minimum values ​​of the respective first bit count differences and the respective second bit count differences are the same among the plurality of first scanning voltages, the first scanning voltage closest to the midpoint of the first voltage range is determined as the third read reference voltage. The memory control device according to claim 14, including the following:

16. The second voltage range has an upper limit obtained by adding the first step voltage to the third reading reference voltage, and a lower limit obtained by subtracting the first step voltage from the third reading reference voltage. Each single read operation per second generates a bit count of either 1 or 0. Obtaining the first read offset is Determining a third bit count difference and a fourth bit count difference corresponding to a second scanning voltage within the second voltage range, wherein two adjacent scanning voltages of the second scanning voltage include a second lower scanning voltage and a second higher scanning voltage, the third bit count difference is the bit count difference between each bit count corresponding to the second scanning voltage and the second lower scanning voltage, and the fourth bit count difference is the bit count difference between each bit count corresponding to the second scanning voltage and the second higher scanning voltage. The second scanning voltage having the minimum value of the sum of the third bit count differences and the fourth bit count differences is determined as the first read voltage, and the offset of the first read voltage with respect to the first read reference voltage is determined to be the first read offset. The memory control device according to claim 11, including the following:

17. The second scanning operation described above is: Scanning the scanning range by performing a series of third single read operations within the scanning range, wherein one third single read operation corresponds to one third scanning voltage within the scanning range, and each third single read operation generates a bit count of either 1 or 0. Determining a fifth bit count difference and a sixth bit count difference corresponding to a third scanning voltage within the scanning range, wherein two adjacent scanning voltages of the third scanning voltage include a third lower scanning voltage and a third higher scanning voltage, the fifth bit count difference is the bit count difference between the bit count corresponding to the third scanning voltage and the third lower scanning voltage, and the sixth bit count difference is the bit count difference between the bit count corresponding to the third scanning voltage and the third higher scanning voltage. The third scanning voltage having the minimum value of the sum of each of the fifth bit count differences and each of the sixth bit count differences is determined to be the second read voltage, and the offset of the second read voltage with respect to the second read reference voltage is determined to be the second read offset. The memory control device according to claim 10, including the following:

18. A method of the memory system, A step of performing a first scan operation corresponding to a target page in order to obtain a first read offset, wherein the first read offset is the offset of the first read voltage with respect to a first read reference voltage of the first read level, A step of performing a second scan operation corresponding to the target page in order to obtain a second read offset, wherein the second read offset is the offset of the second read voltage relative to a second read reference voltage of the second read level, and the scan range of the second scan operation is determined based on an anchor read voltage having the same offset as the first read offset relative to the second read reference voltage. The steps include: performing a second loading operation corresponding to the target page based on the first loading offset and the second loading offset; A method that includes this.

19. The first scanning operation is Based on the first reading reference voltage, a first voltage range is determined, Scanning the first voltage range based on a first step voltage by performing a series of first single-pass read operations within the first voltage range, wherein one first single-pass read operation corresponds to one first scan voltage within the first voltage range. Based on the scanning of the first voltage range, a third reading reference voltage is determined, Based on the third reading reference voltage, a second voltage range is determined, Scanning the second voltage range based on a second step voltage by performing a series of second single-pass reading operations within the second voltage range, wherein one second single-pass reading operation corresponds to one second scanning voltage within the second voltage range. The first read offset is determined based on the scanning of the second voltage range. The method according to claim 18, including the method described in claim 18.

20. Determining the first voltage range is Acquiring a first set of first reference offsets, wherein one first reference offset is a voltage shift relative to the first read reference voltage, the one first reference offset corresponds to a memory cell condition such that a set of memory cells under such memory cell conditions each have the one first reference offset, and the one first reference offset has a positive or negative value. The maximum value of the first set of the first reference offsets is set as the upper limit offset of the first voltage range, The minimum value of the first set of the first read offsets is set to the lower limit offset of the first voltage range. The method according to claim 19, including the method described in claim 19.

21. Determining the scanning range is Obtaining a second set of second reference offsets, wherein one second reference offset corresponds to the first set of first reference offsets and one of the respective memory cell conditions, the one second reference offset is a voltage shift relative to the second read reference voltage, and each of the second set of second reference offsets has either a positive or negative value. Determining the difference between each pair of the first reference offset and each pair of the second reference offsets, wherein the difference is equal to each pair of the second reference offsets minus each pair of the first reference offsets. The maximum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the upper limit offset of the scanning range, The minimum value of the difference between each pair of the first reference offset and each of the second reference offsets is set as the lower limit offset of the scanning range. The method according to claim 20, including the method described in claim 20.

22. The step of performing the second reading operation is, A step of determining the first reading voltage based on the first reading reference voltage and the first reading offset, A step of determining the second reading voltage based on the second reading reference voltage and the second reading offset, The steps include reading the target page based on the first and second reading voltages, and The method according to claim 18, including the method described in claim 18.

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