The antifuse circuit senses the antifuse

Abstract

An anti-fuse circuit includes a current generator and an anti-fuse sensing unit. The current generator has at least one replica electronic element. The anti-fuse sensing unit is electrically connected to the current generator, and the anti-fuse sensing unit has at least one electronic element. The electronic element specification of the at least one electronic element of the anti-fuse sensing unit is the same as the electronic element specification of the at least one replica electronic element of the current generator. The current generator supplies current to the anti-fuse sensing unit to sense the anti-fuse. By means of the technical solution of the present application, the anti-fuse circuit can improve the accuracy of sensing the anti-fuse.

Description

Technical Field

[0001] The present invention relates to an apparatus, and more particularly to an apparatus for sensing an antifuse in a dynamic random access memory. Background Technology

[0002] Currently, Dynamic Random Access Memory (DRAM) uses antifuse technology. An antifuse is an electrical device with characteristics opposite to a fuse. In DRAM, antifuses can be programmed to determine redundant rows and columns. For example, a blown antifuse has low resistance, while a non-blown antifuse has high resistance.

[0003] If the antifuse's high or low resistance is incorrectly determined, incorrect redundant rows and columns will be identified, which will adversely affect the DRAM yield. Summary of the Invention

[0004] This invention proposes an antifuse circuit that improves upon the problems of prior art.

[0005] In one embodiment of the present invention, the antifuse circuit includes a current generator and an antifuse sensing unit. The current generator has at least one replicated electronic component. The antifuse sensing unit is electrically connected to the current generator and also has at least one electronic component. The electronic component specifications of the at least one electronic component of the antifuse sensing unit are the same as those of the at least one replicated electronic component of the current generator. The current generator supplies current to the antifuse sensing unit to sense the antifuse.

[0006] In one embodiment of the present invention, the antifuse sensing unit includes an inverter, which includes a first P-type metal-oxide-semiconductor (PMOS) transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor. The current generator includes a voltage divider, which includes a first replicated PMOS transistor, a first resistor, a second resistor, and a first replicated NMOS transistor connected in series. At least one electronic component of the antifuse sensing unit includes the first PMOS transistor and the first NMOS transistor of the inverter. At least one replicated electronic component of the current generator includes the first replicated PMOS transistor and the first replicated NMOS transistor of the voltage divider. The electronic component specifications of the first replicated PMOS transistor are the same as those of the first PMOS transistor, and the electronic component specifications of the first replicated NMOS transistor are the same as those of the first NMOS transistor.

[0007] In one embodiment of the present invention, the source of the first P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage, the source of the first N-type metal-oxide-semiconductor transistor is electrically coupled to the ground voltage, the gate of the first N-type metal-oxide-semiconductor transistor is electrically connected to the gate of the first P-type metal-oxide-semiconductor transistor, the drain of the first N-type metal-oxide-semiconductor transistor is electrically connected to the drain of the first P-type metal-oxide-semiconductor transistor, the drain of the first replicated P-type metal-oxide-semiconductor transistor is directly connected to the gate of the first replicated P-type metal-oxide-semiconductor transistor, and the drain of the first replicated N-type metal-oxide-semiconductor transistor is directly connected to the gate of the first replicated N-type metal-oxide-semiconductor transistor.

[0008] In one embodiment of the present invention, the antifuse sensing unit further includes a second P-type metal-oxide-semiconductor transistor (MOSFET). The second P-type MOSFET has a gate, a source, and a drain. The source of the second P-type MOSFET is electrically coupled to an operating voltage, and the drain of the second P-type MOSFET is electrically connected to the gate of a first P-type MOSFET and the gate of a first N-type MOSFET. One end of the antifuse is electrically connected to the drain of the second P-type MOSFET, and the other end of the antifuse is electrically coupled to ground.

[0009] In one embodiment of the invention, the current generator further includes a proportional-to-absolute-temperature (PPT) current source and a complementary-to-absolute-temperature (CTO) resistor. The PPT current source is electrically coupled to ground voltage, and the CTO resistor is electrically coupled to ground voltage. The PPT current source and the CTO resistor are connected in parallel to simulate the electrical characteristics of an antifuse.

[0010] In one embodiment of the present invention, the current generator further includes an operational amplifier, a third P-type metal-oxide-semiconductor transistor (MOSFET), and a second replicated P-type MOSFET. The operational amplifier has a non-inverting input, an inverting input, and an output. The non-inverting input is electrically connected between a first resistor and a second resistor of a voltage divider, and the inverting input is electrically connected to a current source proportional to the absolute temperature current and a resistor complementary to the absolute temperature current. The third P-type MOSFET has a gate, a source, and a drain. The gate of the third P-type MOSFET is electrically connected to the output of the operational amplifier, the source of the third P-type MOSFET is electrically coupled to the operating voltage, and the drain of the third P-type MOSFET is electrically connected to the inverting input of the operational amplifier. The second replicated P-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The gate of the second replicated P-type metal-oxide-semiconductor transistor is electrically connected to the output of the operational amplifier. The source of the second replicated P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage. The drain of the second replicated P-type metal-oxide-semiconductor transistor is electrically connected to an antifuse sensing unit. At least one electronic component of the antifuse sensing unit further includes the second P-type metal-oxide-semiconductor transistor. At least one replicated electronic component of the current generator further includes the second replicated P-type metal-oxide-semiconductor transistor. The electronic component specifications of the second replicated P-type metal-oxide-semiconductor transistor are the same as those of the second P-type metal-oxide-semiconductor transistor.

[0011] In one embodiment of the present invention, the antifuse sensing unit further includes a current mirror, which includes a fourth P-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, and a third N-type metal-oxide-semiconductor transistor. The fourth P-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The source of the fourth P-type metal-oxide-semiconductor transistor is electrically coupled to an operating voltage, and the drain of the fourth P-type metal-oxide-semiconductor transistor is electrically connected to the gate of the second P-type metal-oxide-semiconductor transistor and the gate of the fourth P-type metal-oxide-semiconductor transistor. The second N-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The gate of the second N-type metal-oxide-semiconductor transistor is electrically connected to the drain of the second replica P-type metal-oxide-semiconductor transistor, the source of the second N-type metal-oxide-semiconductor transistor is electrically coupled to a ground voltage, and the drain of the second N-type metal-oxide-semiconductor transistor is electrically connected to the drain of the fourth P-type metal-oxide-semiconductor transistor. The third N-type metal oxide semiconductor transistor has a gate, a source, and a drain. The gate of the third N-type metal oxide semiconductor transistor is electrically connected to the drain of the second replicated P-type metal oxide semiconductor transistor. The source of the third N-type metal oxide semiconductor transistor is electrically coupled to ground voltage. The drain of the third N-type metal oxide semiconductor transistor is electrically connected to the gate of the third N-type metal oxide semiconductor transistor, the gate of the second N-type metal oxide semiconductor transistor, and the drain of the second replicated P-type metal oxide semiconductor transistor.

[0012] In one embodiment of the present invention, the antifuse circuit proposed herein includes a current generator and an antifuse sensing unit. The current generator divides the voltage using a voltage divider to provide a divided voltage, and generates a current through the current unit based on the divided voltage and an analog voltage. The antifuse sensing unit is electrically coupled to the current generator to receive the current, senses the antifuse based on the current to generate a sensing result, and outputs the sensing result through an inverter. The transistors in the voltage divider have the same specifications as the transistors in the inverter.

[0013] In one embodiment of the present invention, the transistors in the voltage divider and the inverter are P-type transistors.

[0014] In one embodiment of the present invention, the transistors in the voltage divider and the transistors in the inverter are N-type transistors.

[0015] In one embodiment of the invention, the voltage-to-current unit comprises a current source proportional to the absolute temperature and a resistor complementary to the absolute temperature in parallel to provide an analog voltage.

[0016] In one embodiment of the invention, the voltage-to-current unit includes an operational amplifier and an output transistor. The operational amplifier receives a divided voltage and an analog voltage. The output transistor is electrically coupled to the operational amplifier, wherein the output transistor is controlled by the operational amplifier to output current.

[0017] In one embodiment of the invention, the antifuse sensing unit includes a sensing transistor electrically coupled to the antifuse, which senses the antifuse based on the current from a current generator.

[0018] In one embodiment of the present invention, the antifuse sensing unit includes a current mirror electrically coupled to an output transistor and a sensing transistor, wherein the current mirror receives current to control the sensing transistor.

[0019] In one embodiment of the present invention, the specifications of the output transistor are the same as those of the sensing transistor.

[0020] In one embodiment of the present invention, the output transistor and the sensing transistor are P-type transistors.

[0021] In summary, the technical solution of the present invention has significant advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the accuracy of antifuse sensing can be improved.

[0022] The above description will be given in detail below with reference to the embodiments, and a further explanation of the technical solution of the present invention will be provided. Attached Figure Description

[0023] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0024] Figure 1 This is a partial circuit block diagram of a dynamic random access memory according to an embodiment of the present invention. Detailed Implementation

[0025] To provide a more detailed and complete description of the invention, reference can be made to the accompanying drawings and the various embodiments described below, in which the same numbers represent the same or similar elements. Furthermore, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.

[0026] Please refer to Figure 1 The present invention relates to a dynamic random access memory 100, wherein a device 101 can sense an antifuse 102 in the dynamic random access memory 100. The following will be described in conjunction with... Figure 1 This section describes a specific implementation of the dynamic random access memory 100 and the device 101 sensing antifuse 102.

[0027] It should be understood that various implementations of the dynamic random access memory 100 and the device 101 sensing the antifuse 102 are combined. Figure 1 The following description provides a comprehensive account of one or more embodiments for ease of explanation. However, the art can be practiced without these specific details. In other examples, known structures and apparatuses are shown in block diagram form for the effective description of these embodiments. The term "by way of example" is used herein to mean "as an example, instance, or illustration." Any embodiment described herein as "by way of example" is not to be construed as preferred or superior to other embodiments.

[0028] Figure 1 This is a partial circuit block diagram of a dynamic random access memory 100 according to an embodiment of the present invention. Figure 1 As shown, a dynamic random access memory (DRAM) 100 is included. The DRAM 100 includes an antifuse 102 and a device 101 (e.g., an antifuse circuit) for sensing the antifuse 102. The device 101 includes a current generator 110 and an antifuse sensing unit 120. It should be understood that, in the embodiments and claims, unless specifically defined herein, the terms "a" and "the" can refer to a single or multiple entities. Furthermore, the terms "comprising," "including," "having," etc., as used in the description herein and the following claims should be understood as open-ended terms, meaning including but not limited to.

[0029] In terms of architecture, the antifuse sensing unit 120 is electrically connected to the current generator 110. The current generator 110 has at least one replicated electronic component, and the antifuse sensing unit 120 has at least one electronic component. It should be understood that, in the embodiments and claims, descriptions involving "electrical connection" or "electrical coupling" can refer to one element being indirectly electrically coupled to another element through other elements, or one element being directly linked to another element without needing to go through other elements.

[0030] The electronic component specifications of at least one electronic component of the antifuse sensing unit 120 are the same as those of at least one replicated electronic component of the current generator 110, thereby improving the accuracy of sensing the antifuse 102, wherein the electronic component specifications include, but are not limited to, channel length, channel width and threshold voltage.

[0031] In use, the current generator 110 generates current, enabling it to supply current to the antifuse sensing unit 120 to sense the antifuse. The antifuse sensing unit 120 receives the current and senses whether the antifuse 102 is a blown or unblowed antifuse, thus enabling it to detect both blown and unblowed antifuses.

[0032] At Figure 1 In this embodiment, the antifuse sensing unit 120 includes an inverter 122, which includes a first P-type metal-oxide-semiconductor (PMOS) transistor P1 and a first N-type metal-oxide-semiconductor (NMOS) transistor N1. It should be noted that although the terms "first," "second," etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] In terms of architecture, the source of the first P-type metal oxide semiconductor transistor P1 is electrically coupled to the operating voltage VDD, the source of the first N-type metal oxide semiconductor transistor N1 is electrically coupled to the ground voltage VSS, the gate of the first N-type metal oxide semiconductor transistor N1 is electrically connected to the gate of the first P-type metal oxide semiconductor transistor P1, and the drain of the first N-type metal oxide semiconductor transistor N1 is electrically connected to the drain of the first P-type metal oxide semiconductor transistor P1.

[0034] At Figure 1 In the circuit, the current generator 110 includes a voltage divider 112, which comprises a first replicated P-type metal-oxide-semiconductor transistor P11, a first resistor R1, a second resistor R2, and a first replicated N-type metal-oxide-semiconductor transistor N11 connected in series. Architecturally, the drain of the first replicated P-type metal-oxide-semiconductor transistor P11 is directly connected to its gate, and the drain of the first replicated N-type metal-oxide-semiconductor transistor N11 is directly connected to its gate.

[0035] In one embodiment of the present invention, at least one electronic component of the antifuse sensing unit 120 includes a first P-type metal-oxide-semiconductor transistor P1 and a first N-type metal-oxide-semiconductor transistor N1 of the inverter 122, and at least one replicated electronic component of the current generator 110 includes a first replicated P-type metal-oxide-semiconductor transistor P11 and a first replicated N-type metal-oxide-semiconductor transistor N11 of the voltage divider. The electronic component specifications of the first replicated P-type metal-oxide-semiconductor transistor P11 are the same as those of the first P-type metal-oxide-semiconductor transistor P1, and the electronic component specifications of the first replicated N-type metal-oxide-semiconductor transistor N11 are the same as those of the first N-type metal-oxide-semiconductor transistor N1. Thus, the first replicated P-type metal-oxide-semiconductor transistor P11 and the first replicated N-type metal-oxide-semiconductor transistor N11 respectively replicate the first P-type metal-oxide-semiconductor transistor P1 and the first N-type metal-oxide-semiconductor transistor N1 to simulate the effect of temperature changes and semiconductor process changes on the trip point of the inverter 122, thereby improving the accuracy of the device 101 in sensing the antifuse 102.

[0036] At Figure 1 In this device, the current generator 110 also includes a proportional-to-absolute-temperature (PPT) current source I1 and a complementary-to-absolute-temperature (CTT) resistor R3. Architecturally, the PPT current source I1 is electrically coupled to the ground voltage VSS, and the CTT resistor R3 is electrically coupled to the ground voltage VSS. In practice, the PPT current source I1 and the CTT resistor R3 are connected in parallel to simulate the electrical characteristics of the antifuse 102, thereby improving the accuracy of the device 101 in sensing the antifuse 102. Specifically, the parallel connection of the PPT current source I1 and the CTT resistor R3 can simulate the effect of temperature changes on the resistance of a blown antifuse. For example, the resistance of a blown antifuse does not change with temperature; therefore, the parallel connection of the PPT current source I1 and the CTT resistor R3 can serve as a resistance that does not change with temperature.

[0037] At Figure 1In this embodiment, the antifuse sensing unit 120 further includes a second P-type metal-oxide-semiconductor transistor P2. Architecturally, the source of the second P-type metal-oxide-semiconductor transistor P2 is electrically coupled to the operating voltage VDD, and the drain of the second P-type metal-oxide-semiconductor transistor P2 is electrically connected to the gate of the first P-type metal-oxide-semiconductor transistor P1 and the gate of the first N-type metal-oxide-semiconductor transistor N1. One end of the antifuse 102 is electrically connected to the drain of the second P-type metal-oxide-semiconductor transistor P2, and the other end of the antifuse 102 is electrically coupled to the ground voltage VSS.

[0038] In use, when the gate of the second P-type metal-oxide-semiconductor transistor (MOSFET) receives the second voltage V2, the drain of the second P-type MOSFET P2 provides the first voltage V1 to the gates of the first P-type MOSFET P1 and the first N-type MOSFET N1. When the antifuse 102 is a blown antifuse, the inverter 122 outputs a logic 1 voltage in response to the blown antifuse. Conversely, when the antifuse 102 is not blown, the inverter 122 outputs a logic 0 voltage in response to the not blown antifuse.

[0039] At Figure 1 In this circuit, the current generator 110 also includes an operational amplifier 114, a third P-type metal-oxide-semiconductor transistor P3, and a second replicated P-type metal-oxide-semiconductor transistor P22. Architecturally, the non-inverting input of the operational amplifier 114 is electrically connected between the first resistor R1 and the second resistor R2 of the voltage divider 112, and the inverting input of the operational amplifier 114 is electrically connected to a current source proportional to the absolute temperature current I1 and a resistor complementary to the absolute temperature current R3. The gate of the third P-type metal-oxide-semiconductor transistor P3 is electrically connected to the output of the operational amplifier 114, the source of the third P-type metal-oxide-semiconductor transistor P3 is electrically coupled to the operating voltage VDD, and the drain of the third P-type metal-oxide-semiconductor transistor P3 is electrically connected to the inverting input of the operational amplifier 114. The gate of the second replicated P-type metal oxide semiconductor transistor P22 is electrically connected to the gate of the third P-type metal oxide semiconductor transistor P3 and the output terminal of the operational amplifier 114. The source of the second replicated P-type metal oxide semiconductor transistor P22 is electrically coupled to the operating voltage VDD. The drain of the second replicated P-type metal oxide semiconductor transistor P22 is electrically connected to the antifuse sensing unit 120.

[0040] In one embodiment of the present invention, at least one electronic component of the antifuse sensing unit 120 further includes a second P-type metal-oxide-semiconductor transistor P2, and at least one replicated electronic component of the current generator 110 further includes a second replicated P-type metal-oxide-semiconductor transistor P22. The electronic component specifications of the second replicated P-type metal-oxide-semiconductor transistor P22 are the same as those of the second P-type metal-oxide-semiconductor transistor P2. Thus, the second replicated P-type metal-oxide-semiconductor transistor P22 replicates the second P-type metal-oxide-semiconductor transistor P2, thereby improving the accuracy of the device 101 in sensing the antifuse 102.

[0041] In use, the non-inverting input of operational amplifier 114 receives a third voltage V3 (e.g., a reference voltage) from voltage divider 112 to trigger operational amplifier 114; then, the drain output current of the second replica P-type metal-oxide-semiconductor transistor P22 is sent to antifuse sensing unit 120. Operational amplifier 114 adjusts the current of the third P-type metal-oxide-semiconductor transistor P3 by comparing the results of the inverting and non-inverting inputs. The voltage at the inverting input (i.e., proportional to the voltage of the absolute temperature current source I1 and the voltage complementary to the absolute temperature resistor R3 in parallel) can be equal to the third voltage V3 at the non-inverting input to replicate the tripping point of inverter 122 and the voltage of antifuse 102.

[0042] At Figure 1 In this embodiment, the antifuse sensing unit 120 also includes a current mirror 124. Architecturally, the current mirror 124 is electrically connected to the drain of the second replicated P-type metal-oxide-semiconductor transistor P22 and the gate of the second P-type metal-oxide-semiconductor transistor P2. In use, the current mirror 124 receives current from the drain of the second replicated P-type metal-oxide-semiconductor transistor P22 and provides a second voltage V2 to the gate of the second P-type metal-oxide-semiconductor transistor P2.

[0043] At Figure 1In this configuration, the current mirror 124 includes a fourth P-type metal-oxide-semiconductor transistor P21, a second N-type metal-oxide-semiconductor transistor N2, and a third N-type metal-oxide-semiconductor transistor N21. Architecturally, the source of the fourth P-type metal-oxide-semiconductor transistor P21 is electrically coupled to the operating voltage VDD, and the drain of the fourth P-type metal-oxide-semiconductor transistor P21 is electrically connected to the gate of the second P-type metal-oxide-semiconductor transistor P21. The gate of the second N-type metal-oxide-semiconductor transistor N2 is electrically connected to the drain of the second replicated P-type metal-oxide-semiconductor transistor P22, the source of the second N-type metal-oxide-semiconductor transistor N2 is electrically coupled to the ground voltage VSS, and the drain of the second N-type metal-oxide-semiconductor transistor N2 is electrically connected to the drain of the fourth P-type metal-oxide-semiconductor transistor P21. The gate of the third N-type metal oxide semiconductor transistor N21 is electrically connected to the drain of the second replicated P-type metal oxide semiconductor transistor P22. The source of the third N-type metal oxide semiconductor transistor N21 is electrically coupled to the ground voltage VSS. The drain of the third N-type metal oxide semiconductor transistor N21 is electrically connected to the gate of the third N-type metal oxide semiconductor transistor N21, the gate of the second N-type metal oxide semiconductor transistor N2, and the drain of the second replicated P-type metal oxide semiconductor transistor P22.

[0044] In use, the drain of the third N-type metal oxide semiconductor transistor N21 is used to receive current from the drain of the second replica P-type metal oxide semiconductor transistor P22, and the drain of the fourth P-type metal oxide semiconductor transistor P21 is used to provide a second voltage V2 to the gate of the second P-type metal oxide semiconductor transistor P2.

[0045] In one embodiment of the present invention, the current mirror 124 generates a second voltage V2 to the gate of the second P-type metal-oxide-semiconductor transistor P2 to resolve or improve the changes in the gate-to-source voltage (Vgs) and resistance of the second P-type metal-oxide-semiconductor transistor P2 caused by the power IR drop. In a control experiment, the current generator 110 and the antifuse sensing unit 120 are placed at different locations in the dynamic random access memory 100, with a large distance between them, and the current mirror 124 is omitted in the antifuse detection unit 120; therefore, the voltage drop (IR drop) of the operating voltage causes a difference between the operating voltage VDD of the current generator 110 and the operating voltage VDD of the antifuse sensing unit 120, thereby causing changes in the Vgs and resistance of the second P-type metal-oxide-semiconductor transistor P2, and this result may misjudge whether the antifuse 102 is melted or not.

[0046] In a control experiment, the current mirror 124 is omitted from the antifuse sensing unit 120, and the first replicated P-type metal-oxide-semiconductor transistor P11, the first replicated N-type metal-oxide-semiconductor transistor N11, the absolute temperature current source I1, the absolute temperature resistor R3, the operational amplifier 114, the third P-type metal-oxide-semiconductor transistor P3, and the second replicated P-type metal-oxide-semiconductor transistor P22 are omitted from the current generator 110. Therefore, in this control experiment, the current generator has a voltage divider consisting only of the first resistor R1 and the second resistor R2 to provide the voltage across the second resistor R2 to the gate of the second P-type metal-oxide-semiconductor transistor P2. This voltage does not change with temperature or semiconductor process variations, but the critical voltages of the first P-type metal-oxide-semiconductor transistor P1, the first N-type metal-oxide-semiconductor transistor N1, and the second P-type metal-oxide-semiconductor transistor P2 all change with temperature and semiconductor process variations. Therefore, in this control experiment, it is possible to mistakenly judge the melted state of the antifuse 102 as an unmelted state.

[0047] In one embodiment of the invention, the current generator 110 divides a voltage (e.g., the operating voltage VDD) using a voltage divider 112 to provide a divided voltage (e.g., a third voltage V3), and generates current through a voltage current unit 116 based on the divided voltage and an analog voltage V4. An antifuse sensing unit 120 is electrically coupled to the current generator 110 to receive current, senses the antifuse 102 based on the current to generate a sensing result, and outputs the sensing result through an inverter 122. The transistors in the voltage divider 112 have the same specifications as the transistors in the inverter 122.

[0048] In one embodiment of the present invention, the transistors in the voltage divider 112 (e.g., the first replicated P-type metal-oxide-semiconductor transistor P11) and the transistors in the inverter 122 (e.g., the first P-type metal-oxide-semiconductor transistor P1) are P-type transistors.

[0049] In one embodiment of the present invention, the transistors in the voltage divider 112 (e.g., the first replicated N-type metal-oxide-semiconductor transistor N11) and the transistors in the inverter 122 (e.g., the first N-type metal-oxide-semiconductor transistor N1) are N-type transistors.

[0050] In one embodiment of the invention, the voltage-to-current unit 116 includes an absolute temperature current source I1 connected in parallel with an absolute temperature resistor R3 to provide an analog voltage V4.

[0051] In one embodiment of the invention, the voltage-to-current unit 116 includes an operational amplifier 114 and an output transistor (e.g., a second replicated P-type metal-oxide-semiconductor transistor P22). The operational amplifier 114 receives a divided voltage (e.g., a third voltage V3) and an analog voltage V4. The output transistor (e.g., the second replicated P-type metal-oxide-semiconductor transistor P22) is electrically coupled to the operational amplifier 114, wherein the output transistor is controlled by the operational amplifier 114 to output current.

[0052] In one embodiment of the present invention, the antifuse sensing unit 120 includes a sensing transistor (e.g., a second P-type metal oxide semiconductor transistor P2) electrically coupled to the antifuse 102, and senses the antifuse 102 based on the current from the current generator 110.

[0053] In one embodiment of the present invention, the antifuse sensing unit 120 includes a current mirror 124 electrically coupled to an output transistor (e.g., a second replicated P-type metal oxide transistor P22) and a sensing transistor (e.g., a second P-type metal oxide transistor P2), wherein the current mirror 124 receives current to control the sensing transistor.

[0054] In one embodiment of the present invention, the output transistor (e.g., the second replicated P-type metal oxide semiconductor transistor P22) has the same specifications as the sensing transistor (e.g., the second P-type metal oxide semiconductor transistor P2).

[0055] In one embodiment of the present invention, the output transistor (e.g., the second replicated P-type metal-oxide-semiconductor transistor P22) and the sensing transistor (e.g., the second P-type metal-oxide-semiconductor transistor P2) are P-type transistors.

[0056] In summary, the technical solution of the present invention has significant advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the dynamic random access memory 100 and the device 101 can improve the accuracy of sensing the anti-fuse 102.

[0057] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0058] [Symbol Explanation]

[0059] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the appended symbols are explained as follows:

[0060] 100: Dynamic Random Access Memory

[0061] 101: Device

[0062] 102: Anti-fuse

[0063] 110: Current Generator

[0064] 112: Voltage divider

[0065] 114: Operational amplifier

[0066] 116: Voltage to Current Unit

[0067] 120: Anti-fuse sensing unit

[0068] 122: Inverter

[0069] 124: Current Mirror

[0070] I1: Current source proportional to absolute temperature

[0071] N1: First N-type metal-oxide-semiconductor transistor

[0072] N11: First replica N-type metal-oxide-semiconductor transistor

[0073] N2: Second N-type metal-oxide-semiconductor transistor

[0074] N21: Third type N-type metal-oxide-semiconductor transistor

[0075] P1: First P-type metal-oxide-semiconductor transistor

[0076] P11: First replica of a P-type metal-oxide-semiconductor transistor

[0077] P2: Second P-type metal-oxide-semiconductor transistor

[0078] P21: Fourth P-type metal-oxide-semiconductor transistor

[0079] P22: Second replica of P-type metal-oxide-semiconductor transistor

[0080] P3: Third P-type metal-oxide-semiconductor transistor

[0081] R1: First resistor

[0082] R2: Second resistor

[0083] R3: Complementary to the absolute temperature resistor

[0084] Vl: First voltage

[0085] V2: Second voltage

[0086] V3: Third voltage

[0087] V4: Analog voltage

[0088] VDD: Operating voltage

[0089] VSS: Grounding voltage.

Claims

1. An antifuse circuit, characterized in that, Include: A current generator having at least one replicated electronic component; and An antifuse sensing unit, electrically connected to the current generator, has at least one electronic component. The antifuse sensing unit includes an inverter, which includes a first P-type metal-oxide-semiconductor (PMOS) transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor. The current generator includes a voltage divider, which includes a first replicated PMOS transistor, a first resistor, a second resistor, and a first replicated NMOS transistor connected in series. At least one electronic component of the antifuse sensing unit includes the first PMOS transistor and the first NMOS transistor of the inverter. At least one replicated electronic component of the current generator includes the first replicated PMOS transistor and the first replicated NMOS transistor of the voltage divider. The electronic component specifications of the first replicated PMOS transistor are the same as those of the first PMOS transistor, and the electronic component specifications of the first replicated NMOS transistor are the same as those of the first NMOS transistor. The current generator supplies current to the antifuse sensing unit to sense the antifuse.

2. The antifuse circuit according to claim 1, characterized in that, The source of the first P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage, the source of the first N-type metal-oxide-semiconductor transistor is electrically coupled to the ground voltage, the gate of the first N-type metal-oxide-semiconductor transistor is electrically connected to the gate of the first P-type metal-oxide-semiconductor transistor, the drain of the first N-type metal-oxide-semiconductor transistor is electrically connected to the drain of the first P-type metal-oxide-semiconductor transistor, the drain of the first replicated P-type metal-oxide-semiconductor transistor is directly connected to the gate of the first replicated P-type metal-oxide-semiconductor transistor, and the drain of the first replicated N-type metal-oxide-semiconductor transistor is directly connected to the gate of the first replicated N-type metal-oxide-semiconductor transistor.

3. The antifuse circuit according to claim 1, characterized in that, The antifuse sensing unit also includes: The second P-type metal oxide semiconductor transistor has a gate, a source, and a drain. The source of the second P-type metal oxide semiconductor transistor is electrically coupled to the operating voltage, and the drain of the second P-type metal oxide semiconductor transistor is electrically connected to the gate of the first P-type metal oxide semiconductor transistor and the gate of the first N-type metal oxide semiconductor transistor. One end of the antifuse is electrically connected to the drain of the second P-type metal-oxide-semiconductor transistor, and the other end of the antifuse is electrically coupled to the ground voltage.

4. The antifuse circuit according to claim 3, characterized in that, The current generator also includes: Proportional to the absolute temperature current source, electrically coupled to the ground voltage; and The absolute temperature resistor is complementary to the ground voltage, wherein the absolute temperature current source and the absolute temperature resistor are connected in parallel to simulate the electrical characteristics of the antifuse.

5. The antifuse circuit according to claim 4, characterized in that, The current generator also includes: An operational amplifier has a non-inverting input, an inverting input, and an output. The non-inverting input is electrically connected between a first resistor and a second resistor of a voltage divider, and the inverting input is electrically connected to an absolute temperature current source and an absolute temperature complementary resistor. A third P-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The gate of the third P-type metal-oxide-semiconductor transistor is electrically connected to the output terminal of the operational amplifier, the source of the third P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage, and the drain of the third P-type metal-oxide-semiconductor transistor is electrically connected to the inverting input terminal of the operational amplifier. as well as The second replicated P-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The gate of the second replicated P-type metal-oxide-semiconductor transistor is electrically connected to the output terminal of the operational amplifier. The source of the second replicated P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage. The drain of the second replicated P-type metal-oxide-semiconductor transistor is electrically connected to the antifuse sensing unit. The at least one electronic component of the antifuse sensing unit further includes the second P-type metal-oxide-semiconductor transistor. The at least one replicated electronic component of the current generator further includes the second replicated P-type metal-oxide-semiconductor transistor. The electronic component specifications of the second replicated P-type metal-oxide-semiconductor transistor are the same as those of the second P-type metal-oxide-semiconductor transistor.

6. The antifuse circuit according to claim 5, characterized in that, The antifuse sensing unit also includes a current mirror, which comprises: A fourth P-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The source of the fourth P-type metal-oxide-semiconductor transistor is electrically coupled to the operating voltage, and the drain of the fourth P-type metal-oxide-semiconductor transistor is electrically connected to the gate of the second P-type metal-oxide-semiconductor transistor and the gate of the fourth P-type metal-oxide-semiconductor transistor. The second N-type metal oxide semiconductor transistor has a gate, a source, and a drain. The gate of the second N-type metal oxide semiconductor transistor is electrically connected to the drain of the second replicated P-type metal oxide semiconductor transistor. The source of the second N-type metal oxide semiconductor transistor is electrically coupled to the ground voltage. The drain of the second N-type metal oxide semiconductor transistor is electrically connected to the drain of the fourth P-type metal oxide semiconductor transistor. as well as A third N-type metal-oxide-semiconductor transistor has a gate, a source, and a drain. The gate of the third N-type metal-oxide-semiconductor transistor is electrically connected to the drain of the second replicated P-type metal-oxide-semiconductor transistor. The source of the third N-type metal-oxide-semiconductor transistor is electrically coupled to the ground voltage. The drain of the third N-type metal-oxide-semiconductor transistor is electrically connected to the gate of the third N-type metal-oxide-semiconductor transistor, the gate of the second N-type metal-oxide-semiconductor transistor, and the drain of the second replicated P-type metal-oxide-semiconductor transistor.

7. An antifuse circuit, characterized in that, Include: The current generator divides the voltage using a voltage divider to provide a divided voltage, and then uses this divided voltage and the analog voltage to generate current through a voltage-current unit. as well as An antifuse sensing unit is electrically coupled to the current generator to receive the current, senses the antifuse based on the current to generate a sensing result, and outputs the sensing result through an inverter. The channel length, channel width, and threshold voltage of the transistor in the voltage divider are the same as those of the transistor in the inverter.

8. The antifuse circuit according to claim 7, characterized in that, The voltage-to-current unit comprises a current source proportional to the absolute temperature and a resistor complementary to the absolute temperature in parallel to provide the analog voltage.

9. The antifuse circuit according to claim 8, characterized in that, This voltage-to-current unit includes: An operational amplifier that receives the divided voltage and the analog voltage; and An output transistor is electrically coupled to the operational amplifier, wherein the output transistor is controlled by the operational amplifier to output the current.

10. The antifuse circuit according to claim 9, characterized in that, The antifuse sensing unit includes a sensing transistor electrically coupled to the antifuse, which senses the antifuse based on the current from the current generator.

11. The antifuse circuit according to claim 10, characterized in that, The antifuse sensing unit includes a current mirror electrically coupled to the output transistor and the sensing transistor, wherein the current mirror receives the current to control the sensing transistor.

12. The antifuse circuit according to claim 10, characterized in that, The output transistor has the same channel length, channel width, and threshold voltage as the sensing transistor.

13. The antifuse circuit according to claim 12, characterized in that, Both the output transistor and the sensing transistor are P-type transistors.

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