Short circuit detection circuit

Abstract

Aspects of the present description provide a circuit (400). In at least some examples, the circuit includes an output node (420) at which a voltage for transmission over a differential conductor is present. The circuit further includes a first pull-up network coupled between a voltage supply node (418) and the output node, the first pull-up network being configured to include a first amount of resistance. The circuit further includes a second pull-up network (408) coupled between the voltage supply node and the output node, the second pull-up network being configured to include a second amount of resistance. The circuit further includes a comparator (416) having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.

Description

Technical Field

[0001] Aspects of this specification provide a circuit. In at least some examples, the circuit includes an output node having a voltage for transmission via a differential conductor. The circuit further includes a first pull-up network coupled between a voltage supply node and the output node and configured to include a first amount of resistance. The circuit further includes a second pull-up network coupled between the voltage supply node and the output node and configured to include a second amount of resistance. The circuit further includes a comparator having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.

Summary of the Invention

[0002] Other aspects of this specification provide a method. In at least some examples, the method includes receiving a common-mode voltage on which transmission on a differential conductor is at least partially based. The method further includes enabling a first pull-up network coupled to the differential conductor. The method further includes generating a comparison result indicating the presence of a fault on the differential conductor by comparing, after a first time period, a voltage present on the differential conductor to a reference voltage when the resistance of the pull-up network is greater than the resistance associated with the differential conductor. The method further includes generating a comparison result indicating that there is no fault on the differential conductor by comparing a voltage present on the differential conductor to a reference voltage when the resistance of the pull-up network is less than the resistance associated with the differential conductor.

[0003] Other aspects of this specification provide systems. In at least some examples, the system includes a transmitter including a fault detection circuit. The fault detection circuit includes an output node where a voltage for transmission over a differential conductor exists, a first pull-up network coupled between a voltage supply node and the output node, a second pull-up network coupled between the voltage supply node and the output node, and a comparator having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result. The system also includes a receiver including a termination circuit. The system further includes a differential conductor. The differential conductor includes a positive conductor that couples the output node to the receiver and is configured to couple to the fault detection circuit and the termination circuit, and a negative conductor that couples the transmitter to the receiver and is configured to couple to the fault detection circuit and the termination circuit. [Brief explanation of the drawing]

[0004] For detailed explanations of various examples, please refer to the attached drawings.

[0005] [Figure 1] Block diagrams of illustrative systems following various examples are shown.

[0006] [Figure 2] Schematic diagrams of example circuits following various examples are shown.

[0007] [Figure 3A] The diagrams show illustrative signal waveforms according to various examples.

[0008] [Figure 3B] The diagrams show illustrative signal waveforms according to various examples.

[0009] [Figure 4] Schematic diagrams of example circuits following various examples are shown.

[0010] [Figure 5A]The diagrams show illustrative signal waveforms according to various examples.

[0011] [Figure 5B] The diagrams show illustrative signal waveforms according to various examples.

[0012] [Figure 6A] The diagrams show illustrative signal waveforms according to various examples.

[0013] [Figure 6B] The diagrams show illustrative signal waveforms according to various examples.

[0014] [Figure 7] A flowchart illustrating an example method for pin strap detection according to various examples is shown. [Modes for carrying out the invention]

[0015] In modern circuit design, there are often competing interests: increasing the feature set and reducing physical size, and therefore reducing the cost of components. For example, in a system involving differential conductors (e.g., those with positive and negative differential signal lines), it may be desirable to determine whether the differential conductors are short-circuited to a voltage supply (VDD) or ground (GND) node. However, at least some circuit implementations involving differential conductors also include AC decoupling capacitors that prevent access to the DC information associated with the differential conductors. In at least some implementations, the lack of access to that DC information associated with the differential conductors makes determining the termination state of the differential conductors (e.g., valid termination or short-circuited) complex or more expensive. For example, one solution involves adding a pin (e.g., an input / output (I / O) interface) to the circuit to enable DC voltage sensing on the opposite side of the AC coupling capacitor (e.g., the side of the AC coupling capacitor coupled to the differential conductor). However, this solution increases the physical size of the circuit and therefore increases the cost of the circuit, making it undesirable for at least some circuit use cases.

[0016] At least some aspects of this specification provide a circuit, which in some examples is a termination state determination circuit. In at least some examples, the circuit includes functionality that enables the circuit to determine whether a differential conductor is effectively terminated (e.g., terminated by 50 ohms (Ω) or other specified resistance) or short-circuited (e.g., a resistance of less than about 10 ohms exists). At least some implementations of the circuit further include functionality to distinguish between a short circuit between the positive and negative conductors of a differential conductor and a short circuit between one of the positive or negative conductors of a differential conductor and VDD or GND. The circuit achieves the above functionality by implementing a pull-up network using multiple resistance values, following at least a partially two-step process. In the first step, the circuit determines whether the positive or negative conductor of a differential conductor is in a high impedance (high Z) state or a low impedance state. In the second step, the circuit determines whether the positive or negative conductor of a differential conductor is terminated with an expected resistance (e.g., about 50 ohms) or several other resistances smaller than the expected resistance. Thus, the circuit determines whether the positive or negative conductor of the differential conductor is in a high-Z state. The circuit further determines whether the positive or negative conductor of the differential conductor is terminated with other resistances smaller than the expected resistance, and in such cases, determines the presence of a short circuit to one of the positive or negative conductors of the differential conductor.

[0017] Referring here to Figure 1, a block diagram of an exemplary system 100 is shown. At least some implementations of system 100 include a transmitter 102 and a receiver 104 that are communicatively coupled via a differential conductor 106. Thus, system 100 represents multiple devices, including devices in which both the transmitter 102 and the receiver 104 are implemented in the same device, and devices that include only one of the transmitter 102 or the receiver 104. In at least some examples, system 100 represents or is implemented in an automobile or other transport vehicle (e.g., an airplane, boat, bus, truck, etc.).

[0018] In at least one implementation, the transmitter 102 includes a driver 108 and a fault detection circuit 110. The driver 108 includes a first output coupled to a first output terminal 112 of the transmitter 102 and a second output coupled to a second output terminal 114 of the transmitter 102. The differential conductor 106 includes a positive conductor 116 and a negative conductor 118. The receiver 104 includes a receiver front end 120 and an input termination circuit 122. The receiver front end 120 includes a first input terminal coupled to a first input terminal 124 of the receiver 104 and a second input terminal coupled to a second input terminal 126 of the receiver 104. The first output terminal 112 is coupled to the positive conductor 116 via a capacitor 128. The first input terminal 124 is coupled to the positive conductor 116 via a capacitor 130. The second output terminal 114 is coupled to the negative conductor 118 via a capacitor 132. The second input terminal 126 is coupled to the negative conductor 118 via the capacitor 134.

[0019] During the normal operation of system 100, the input termination circuit 122 terminates each of the positive conductor 116 and negative conductor 118 with a specified amount of resistance. In at least some examples, this resistance is approximately equal to 50Ω. In other examples, this resistance is determined and set according to industry standards or design judgments applicable to system 100. The following description is made with reference to the first output terminal 112 and positive conductor 116. However, similar functionality applies to the second output terminal 114 and negative conductor 118. In at least some implementations, to determine whether a fault exists in the positive conductor 116, the fault detection circuit 110 includes a single-step process of monitoring the first output terminal 112. For example, the fault detection circuit 110 monitors the first output terminal 112 to determine whether the value of the signal present at the first output terminal 112 (called TXP) exceeds a threshold after a specified time period. In some examples, the threshold is a reference voltage (VREF) received by the fault detection circuit 110. If TXP is greater than VREF at the end of the specified time period, the fault detection circuit 110 determines that there is no fault in the positive conductor 116. If TXP is not greater than VREF at the end of the specified time period, the fault detection circuit 110 determines that there is a fault in the positive conductor 116. The fault is a short circuit of the positive conductor 116 to either VDD or GND.

[0020] In at least some examples, the fault detection circuit 110 includes components suitable for implementing a voltage divider (not shown) in the positive conductor 116, such that the termination provided by the input termination circuit 122 is the bottom resistor of the voltage divider, one or more of the components of the fault detection circuit 110 are the top resistor of the voltage divider, and the first output terminal 112 is the output of the voltage divider. In at least some examples, one or more components of the fault detection circuit 110 are switching components, and thus they are selectively switched to route input and output to the signal path to activate or deactivate the voltage divider. For example, in at least one example, one or more components include or form one or more pull-up networks. In some examples, the system 100 further includes a circuit 136 that controls at least some of the components of the fault detection circuit 110. In various implementations, the circuit 136 takes various forms such as a logic circuit, a digital circuit, a processor, a digital core, etc. In at least some examples, the circuit 136 generates a trigger signal (TRIG1) and outputs it to the fault detection circuit 110 to control the activation or deactivation of the voltage divider. In other examples, the circuit 136 outputs VREF to the fault detection circuit 110. In yet another example, the fault detection circuit 110 includes an output terminal coupled to the circuit 136, for example, enabling the circuit 136 to sample the output value of the circuit 136 when the state of TRIG1 changes.

[0021] In other examples, the fault detection circuit 110 includes a multi-step process of monitoring a first output terminal 112 to determine whether a fault exists in the positive conductor 116. For example, the fault detection circuit 110 includes a plurality of switchably controlled components to selectively generate a plurality of voltage dividers within the fault detection circuit 110. For example, in a first step, the fault detection circuit 110 determines whether the positive conductor 116 is in a high-Z state or terminated. In some examples, the presence of a high-Z state is evidence of a fault (e.g., an open circuit), and in other examples, it is merely a notification (e.g., indicating that the receiver 104 is not ready to receive data). In a second step, the fault detection circuit 110 determines whether the termination of the positive conductor 116 is a valid termination made by the input termination circuit 122 or a short to VDD or GND. The fault detection circuit 110 performs the determination in the first step by switching a first amount of resistance into the signal path and generating a first voltage driver. The termination provided by the input termination circuit 122 is the bottom resistor of the first voltage divider, and one or more components of the fault detection circuit 110 are the top resistors of the first voltage divider, providing a first amount of resistance, in which case the first output terminal 112 is the output of the first voltage divider.

[0022] In at least some examples, capacitors 128 and 130 are coupled between the first output terminal 112 and the input termination circuit 122. Thus, in some examples, capacitors 128 and 130 alter the impedance present on the positive conductor (for example, as the bottom resistors of the first voltage divider, as can be seen from the first output terminal 112). Also, as will be described in detail elsewhere in this specification, capacitor 128 charges based on the ratio of the voltages of the top resistor and the bottom resistor, providing an indicator at the time of sampling after a predefined time period regarding whether the positive conductor 116 is effectively terminated or short-circuited. Since capacitors 128 and 130 remain unchanged, they are generally not described herein with respect to the voltage divider formed using the output at the first output node 112. The fault detection circuit 110 performs the determination in a second step by switching a second amount of resistance to a signal path that generates a second voltage divider. The termination provided by the input termination circuit 122 is the bottom resistor of the second voltage divider, and one or more other components of the fault detection circuit 110 are the top resistors of the second voltage divider, providing a second amount of resistance, in which case the first output terminal 112 is the output of the second voltage divider. In at least some examples, in addition to receiving TRIG1 to control the switching of components for the first step, the fault detection circuit 110 also receives a second trigger signal (TRIG2) from circuit 136 to control the switching of components for the second step.

[0023] When the fault detection circuit 110 implements a two-step process, in the first step, if TXP is not greater than VREF when a specified time period expires, the fault detection circuit 110 determines that the positive conductor 116 is terminated. Similarly, in the first step, if TXP is greater than VREF when a specified time period expires, the fault detection circuit 110 determines that the positive conductor 116 is in a high-Z state and is not terminated effectively. In the second step, if TXP is greater than VREF when a specified time period expires, the fault detection circuit 110 determines that the positive conductor 116 is terminated. Similarly, in the first step, if TXP is greater than VREF when a specified time period expires, the fault detection circuit 110 determines that there is no short circuit in the positive conductor 116. If TXP is not greater than VREF when a specified time period expires, the fault detection circuit 110 determines that there is a short circuit between the positive conductor 116 and VDD or GND.

[0024] In at least some examples, whether TXP exceeds VREF when a specified time period expires is determined at least partially according to the relationship between the pull-up resistance of the fault detection circuit 110 and the resistance present on the positive conductor 116. For example, the charging time is determined according to the capacitance of the capacitor 128, the resistance of the fault detection circuit 110, and the resistance present on the positive conductor 116. Since the capacitance of the capacitor 128 remains substantially constant, the variation in the charging time of TXP can then be defined according to the relationship between the resistance of the fault detection circuit 110 and the resistance present on the positive conductor 116. For example, if the resistance of the fault detection circuit 110 is smaller than the resistance present on the positive conductor 116, TXP charges at a faster rate. If the resistance of the fault detection circuit 110 is greater than the resistance present on the positive conductor 116, TXP charges at a slower rate.

[0025] In some examples, the transmitter 102 and / or circuit 136, or the device on which the transmitter 102 and / or circuit 136 is implemented, cannot exercise control over the receiver 104. However, in other examples, the transmitter 102 and / or circuit 136, or the device on which the transmitter 102 and / or circuit 136 is implemented, can exercise control over the receiver 104. In such examples where the receiver 102 is controllable by the transmitter 102 and / or circuit 136, or the device on which the transmitter 102 and / or circuit 136 is implemented, the system 100 further includes functionality for determining whether a short circuit exists between the positive conductor 116 and the negative conductor 118. In at least one implementation of short-circuit detection between the positive conductor 116 and the negative conductor 118, the receiver 104 is controlled to place the positive conductor 116 in a high-Z state and effectively terminate the negative conductor 118. The fault detection circuit 110 then implements the first step of the two-step fault detection process to determine whether the positive conductor 116 has been detected as effectively terminated by the fault detection circuit 110, even though the receiver 104 has placed the positive conductor 116 in a high-Z state. If the fault detection circuit 110 determines that the positive conductor 116 is effectively terminated, the receiver 104 is then controlled to place the negative conductor 118 in a high-Z state and effectively terminate the positive conductor 116. The fault detection circuit 110 then repeats the first step of the two-step fault detection process to determine whether the negative conductor 118 has been effectively terminated by the fault detection circuit 110, even though the receiver 104 has placed the negative conductor 118 in a high-Z state. If the fault detection circuit 110 determines that the negative conductor 118 is also effectively terminated, the fault detection circuit 110 (or circuit 136 based on one or more output signals of the fault detection circuit 110) determines that a short circuit exists between the positive conductor 116 and the negative conductor 118. If the fault detection circuit 110 determines that either the positive conductor 116 or the negative conductor 118 is in a high-Z state, the fault detection circuit 110 (or circuit 136 based on one or more output signals of the fault detection circuit 110) determines that there is no short circuit between the positive conductor 116 and the negative conductor 118.

[0026] Referring here to Figure 2, a schematic diagram of an exemplary fault detection circuit 200 is shown. In at least some examples, the circuit 200 is suitable for implementation as part of the fault detection circuit 110 of system 100 in Figure 1. For example, the circuit 200 is suitable for implementation as part of the fault detection circuit 110 that detects faults in the positive conductor 116. Another example of the circuit 200 is further suitable for implementation as part of the fault detection circuit 110 that detects faults in the negative conductor 118, substantially similar to the example described herein with respect to the positive conductor 116. Alternatively, the circuit 200 is suitable for implementation as part of the fault detection circuit 110 that determines whether the positive conductor 116 (or alternatively, the negative conductor 118) is in a high Z state. In at least one implementation, the circuit 200 includes a switch 202, a resistor 204, and a comparator 206. In at least some examples, the switch 202 is implemented as a solid-state switching device such as a transistor and is configured to receive TRIG1 and to be controlled at least partially in accordance with TRIG1. In other examples, switch 202 is implemented as a mechanical switching device configured to receive TRIG1 and to be controlled at least partially according to TRIG1. In at least one implementation of circuit 200, where the expected termination resistance of the conductor coupled to node 210 is about 50 Ω, the resistance of resistor 204 is about 20 Ω.

[0027] In the illustrative architecture of circuit 200, switch 202 and resistor 204 are connected in series between node 208 and node 210. Switch 202 and resistor 204 are collectively called a pull-up network in at least some examples. In at least some examples, node 208 is the node where VDD resides, and node 210 is the output node (for example, consequently node 208 of circuit 200 is analogous to the first output terminal 112 of transmitter 102). In Figure 2, switch 202 is shown connected to node 208 and resistor connected to node 210, but in some implementations, this direction is reversed. Comparator 206 has a first input terminal connected to node 210 (e.g., a negative or inverting input terminal) and a second input terminal connected to node 212 (e.g., a positive or non-inverting input terminal). The output terminal of comparator 206 is connected to node 214. In at least some examples, VREF is received at node 212, and the output signal COMP OUT is provided on node 214, COMP OUT indicates whether a fault (or a high-Z state, depending on the implementation of circuit 200) has been detected in the conductor connected to node 210.

[0028] In an example of the operation of circuit 200, a signal is received at node 210. In at least some examples, the signal is a common-mode voltage (VCM) for transmission as TXP. In at least some examples, the signal does not contain differential components (e.g., when fault detection as specified herein is performed at system startup before transmission of differential data). When circuit 200 is disabled, the signal received at node 210 is substantially unchanged and output as TXP, also at node 210. When circuit 200 is enabled, such as when TRIG1 is asserted, switch 202 is activated, electrically coupling resistor 204 to node 208. If VDD is present at node 208, node 210 is pulled high (e.g., close to the value of VDD) via resistor 204 and switch 202. VREF is, in at least some examples, greater than VCM and less than VDD. By knowing the expected termination resistance (approximately 50Ω, etc.) of the conductors coupled to node 210, such as the positive conductor 116 on which TXP is transmitted, circuit 200 determines whether the conductors are short-circuited to VDD or GND.

[0029] If resistor 204 has a resistance less than the expected termination resistance of the conductor on which TXP is transmitted, the value of TXP increases to exceed VREF while TRIG1 is asserted. If resistor 204 has a resistance greater than the expected termination resistance of the conductor on which TXP is transmitted, the value of TXP does not increase to exceed VREF while TRIG1 is asserted. In at least some examples, the resistance value of resistor 204 is selected such that comparator 206 has the maximum margin (e.g., a margin that allows comparator 206 to determine whether the conditions are met) for both effectively terminated conductors and conductors shorted to VDD or GND. In at least some examples, if the conductor on which TXP is transmitted is shorted to VDD or GND, the resistance present on the conductor is less than the resistance of resistor 204. For example, the resistance present on the conductor is less than approximately 10Ω. Conversely, if the conductor on which TXP is transmitted is not shorted to VDD or GND, but is effectively terminated instead, the expected termination resistance of the conductor on which TXP is transmitted is present on the conductor. In at least one example, the resistance present on the conductor is greater than approximately 40Ω or approximately equal to approximately 50Ω. The value of TXP increases based on the relationship between the resistance of resistor 204 and the resistance present on the conductor. If the resistance of resistor 204 is greater than the resistance present on the conductor, most of VDD drops across the ends of resistor 204, and as a result, the value of TXP increases slowly. Conversely, if the resistance of resistor 204 is less than the resistance present on the conductor, most of VDD drops across the ends of the conductor, and as a result, the value of TXP increases more rapidly.

[0030] For example, after the first edge transition of TRIG1 occurs, TRIG1 remains asserted for a predefined time period determined at least in part according to the expected termination resistance of the conductor from which TXP is transmitted and the resistance of resistor 204. In at least some examples, the predefined time period is determined according to the resistor-capacitor (RC) time constant generated by the resistor 204 and AC coupling capacitor (e.g., capacitor 128) coupled to node 210, as well as the resistance present on the positive conductor 116. If, at the second edge transition of TRIG1, the value of TXP increases beyond VREF, circuit 200 determines that there is no short circuit in the conductor because the resistance present on the conductor is greater than the resistance of resistor 204. However, if, at the second edge of TRIG1, TXP remains less than VREF, circuit 200 determines that there is a short circuit in the conductor because the resistance present on the conductor is less than the resistance of resistor 204. This determination is made by comparing TXP with VREF using comparator 206 in at least some examples. This is done by generating OUT. In some examples as illustrated in Figure 2, comparator 206 generates COMP when TXP is less than VREF and a short circuit is detected. OUT is configured to be asserted. In other examples, the polarity of the first and second input terminals of comparator 206 is the opposite of the polarity shown in Figure 2, and as a result COMP when TXP is less than VREF. OUT is deasserted. In at least some examples, circuit 200 is coupled to circuit 136 in Figure 1. In such examples, circuit 200 receives TRIG1 from circuit 136 and COMP OUT is provided to circuit 136. Also, in such an example, circuit 136 is substantially simultaneous with the second edge transition of TRIG1, COMP The value of OUT is sampled (e.g., recorded and / or stored). In another example, circuit 136 performs COMP at a time adjacent to the second edge transition of TRIG1. The value of OUT is sampled. For example, circuit 136 performs COMP slightly before or slightly after the second edge transition of TRIG1. Sample the value of OUT.

[0031] Referring here to Figures 3A and 3B, illustrative diagrams of signal waveforms are shown. In at least some examples, diagram 305 represents at least some signals present in system 100 in Figure 1 and / or circuit 200 in Figure 2 when a short circuit is present. Also in at least some examples, diagram 310 represents at least some signals present in system 100 in Figure 1 and / or circuit 200 in Figure 2 when a short circuit is not present (e.g., when a valid termination is present). Thus, at least some aspects of the description of Figures 3A and / or 3B refer to the components and / or signals of Figures 1 and / or 2. Furthermore, as in the above description, Figures 3A and 3B are described with respect to the first output terminal 112, TXP, and positive conductor 116. The waveforms for the second output terminal 114, the signal present at the second output terminal (referred to herein as TXN), and the negative conductor 118 are substantially similar to those shown in Figures 3A and 3B.

[0032] As shown in Figure 305, when TRIG1 is asserted, the value of TXP begins to increase. TRIG1 remains asserted for a predefined time period determined at least partially according to VREF, VCM, and the resistance value of resistor 204. For example, TRIG1 remains asserted for a sufficient time period to determine, based on the values ​​of VCM and TXP, whether the resistance of resistor 204 is greater or less than the resistance present on the positive conductor 116. If the positive conductor 116 is shorted to VDD or GND, the resistance present on the positive conductor 116 is less than the resistance of resistor 204. If the resistance present on the positive conductor 116 is less than the resistance of resistor 204, TRIG1 is asserted and COMP While OUT remains deasserted, TXP remains less than VREF (in this example, it's logically high level, but in other examples, it's logically low level).

[0033] As shown in Figure 310, when TRIG1 is asserted, the value of TXP begins to increase. As explained with reference to Figure 305, TRIG1 remains asserted for a predefined time period. If the positive conductor 116 is effectively terminated with a resistance greater than that of resistor 204 and / or not shorted to VDD or GND, the resistance present on the positive conductor 116 is greater than that of resistor 204. If the resistance present on the positive conductor 116 is greater than that of resistor 204, before TRIG1 is deasserted, TXP exceeds VREF and COMP OUT is asserted (in this example, it is set to a low logical level, but in other examples, it is set to a high logical level).

[0034] Referring here to Figure 4, a schematic diagram of an exemplary fault detection circuit 400 is shown. In at least some examples, circuit 400 is suitable for implementation as at least part of the fault detection circuit 110 of system 100 in Figure 1. For example, circuit 400 is suitable for implementation as part of the fault detection circuit 110 that detects faults or high-Z conditions in the positive conductor 116. Another example of circuit 400 is further suitable for implementation as part of the fault detection circuit 110 that detects faults or high-Z conditions in the negative conductor 118 in substantially the same manner as described with respect to the positive conductor 116. In at least one implementation, circuit 400 includes transistor 402, resistor 404, transistor 406, resistor 408, resistor 410, resistor 412, amplifier 414, and comparator 416. Transistor 402 and resistor 404 are collectively referred to as a pull-up network in at least some examples. Transistor 406 and resistor 408 are also collectively referred to as a pull-up network in at least some examples. In various other examples, transistors 402 and / or 406 are replaced with any other suitable controllable switching device, such as transistors of other process technologies or mechanical switches.

[0035] In the exemplary architecture of circuit 400, transistor 402 has a source terminal coupled to node 418, a drain terminal coupled to node 420 via resistor 404, and a gate terminal configured to receive a trigger signal TRIG1. Transistor 406 has a source terminal coupled to node 418, a drain terminal coupled to node 420 via resistor 408, and a gate terminal configured to receive a trigger signal TRIG2. Resistor 410 is coupled between node 418 and node 421, and resistor 412 is coupled between node 421 and node 420. Amplifier 414 has a first input terminal (e.g., a negative or inverting input terminal) coupled to node 421, a second input terminal (e.g., a positive or non-inverting input terminal) coupled to node 422, and an output terminal coupled to node 420. Comparator 416 has a first input terminal (e.g., a negative or inverting input terminal) coupled to node 420, a second input terminal (e.g., a positive or non-inverting input terminal) coupled to node 424, and an output terminal coupled to node 426. In at least some examples, VDD is present at node 418, VREF is received at node 424, and COMP OUT is output at node 426, COMP OUT indicates whether a fault or high-Z condition is detected in the conductor coupled to node 420. Also, in at least some examples, node 422 is configured to receive the positive output of driver 108, and node 420 is analogous to the first output terminal 112, so that TXP is present at node 420. Also, in at least some examples, resistor 410 is a controllable or programmable component, and therefore the amount of resistance of resistor 410 is variable and selectable. In at least one implementation of circuit 400 where the expected termination resistance of the conductor coupled to node 420 is about 50 Ω, the resistance of resistor 404 is about 1,000 Ω, and the resistance of resistor 408 is about 20 Ω.

[0036] In one example of the operation of circuit 400, VCM is received at node 422. Resistors 410 and 412 form a voltage divider between nodes 418 and 420 using the output at node 421. Amplifier 414, in at least some examples, is an operational amplifier and, together with resistors 410 and 412, drives node 420 to a value of approximately VDD / 2. In other examples, amplifier 414, resistors 410 and 412 drive node 420 to any other suitable value, at least partially based on VCM. In at least some examples, when amplifier 414 is enabled, it drives node 420 to VDD / 2. In some examples, when the received enable signal (EN) is asserted, amplifier 414 is enabled. In some examples, when TRIG1 and TRIG2 are deasserted, EN is asserted, and when either TRIG1 or TRIG2 is asserted, EN is deasserted. In at least some examples, EN, TRIG1, and TRIG2 are each received from circuit 136, and COMP OUT is output from circuit 136.

[0037] When TRIG1 and TRIG2 are deasserted, fault detection in circuit 400 is disabled, and VDD / 2 is output as TXP. When TRIG1 is asserted, the first step of the two-step fault detection process of circuit 400 is activated, and both EN and TRIG2 are deasserted. When the first step of the fault detection process is active, circuit 400 determines whether the conductor (e.g., positive conductor 116) coupled to node 420 is in a high-Z state or is terminated. In at least some implementations, both a valid termination using the expected termination resistance for the conductor coupled to node 420 and a short circuit of the conductor coupled to node 420 are determined to be terminations in the first step of the fault detection process.

[0038] When TRIG1 is asserted, transistor 402 is activated, electrically coupling resistor 404 to node 418. If VDD is present at node 418, node 420 is pulled high (e.g., close to the value of VDD) via resistor 404 and transistor 402. VREF is, in at least some examples, a value greater than VDD / 2 but less than VDD. By knowing the expected termination resistance (e.g., about 50Ω) of the conductor coupled to node 420, such as positive conductor 116, to which TXP is sent, circuit 400 determines whether the conductor is in a high Z state or terminated. For example, if resistor 404 has a resistance less than the expected termination resistance of the conductor, the value of TXP increases to exceed VREF while TRIG1 is asserted. If resistor 404 has a resistance greater than the expected termination resistance of the conductor to which TXP is sent, the value of TXP does not increase to exceed VREF while TRIG1 is asserted. In at least some examples, when the conductor from which TXP is transmitted is terminated, the resistance present on the conductor is less than the resistance of resistor 404. For example, the resistance present on the conductor is less than approximately 200Ω. Conversely, when the conductor from which TXP is transmitted is in a high-Z state, the resistance present on the conductor is greater than the resistance of resistor 204. For example, the resistance present on the conductor is greater than approximately 10,000Ω. The value of TXP increases based on the relationship between the resistance of resistor 404 and the resistance present on the conductor. In at least some examples, the rate of increase in the value indicates whether or not a fault (or high-Z state) is present (e.g., the conductor is in a high-Z state or the conductor is short-circuited to VDD or GND). If the resistance of resistor 404 is greater than the resistance present on the conductor, most of VDD drops across the ends of resistor 404, resulting in a slow increase in the value of TXP. Conversely, if the resistance of resistor 404 is less than the resistance present on the conductor, most of VDD drops across the ends of the conductor, resulting in a more rapid increase in the value of TXP.

[0039] For example, after the first edge transition of TRIG1 occurs, TRIG1 remains asserted for a predefined time period determined at least partially according to the expected termination resistance of the conductor to which TXP is transmitted and the resistance of resistor 404. At the second edge transition of TRIG1, if the value of TXP increases beyond VREF, circuit 400 determines that the conductor is in a high-Z state because the resistance present on the conductor is greater than the resistance of resistor 404. However, at the second edge of TRIG1, if TXP remains less than VREF, circuit 400 determines that the conductor is terminated because the resistance present on the conductor is less than the resistance of resistor 404. The determination is made in at least some examples by comparing TXP with VREF using comparator 416. This is done by generating OUT. In some examples as shown in Figure 4, comparator 416 detects termination when TXP is less than VREF, and COMP OUT is configured to be asserted. In other examples, the polarity of the first and second input terminals of comparator 416 is reversed from that shown in Figure 4, and therefore COMP when TXP is less than VREF. OUT is deasserted. In at least some examples, circuit 400 is coupled to circuit 136 in Figure 1. In such examples, circuit 400 receives TRIG1 from circuit 136 and COMP to circuit 136. It provides an OUT. Furthermore, in such an example, circuit 136 COMP substantially simultaneously with the second edge transition of TRIG1. The value of OUT is sampled (e.g., recorded and / or stored). In another example, circuit 136 performs COMP at a time temporally adjacent to the second edge transition of TRIG1. The value of OUT is sampled. For example, circuit 136 performs COMP slightly before or slightly after the second edge transition of TRIG1. Sample the value of OUT.

[0040] After determining whether the conductor is terminated or not, TRIG1 is deasserted, deactivating transistor 402 and ending the first step of the fault detection process. TRIG2 is asserted to start the second step of the fault detection process. When TRIG2 is asserted, transistor 406 is activated, electrically coupling resistor 408 to node 418. If VDD is present at node 418, node 420 is pulled high (e.g., approaching the value of VDD) via resistor 408 and transistor 406. By again knowing the expected termination resistance (e.g., about 50Ω) of the conductor coupled to node 420, such as the positive conductor 116 from which TXP is sent, circuit 400 determines whether the conductor is terminated by the expected termination resistance or shorted to VDD or GND. For example, if resistor 408 has a resistance less than the expected termination resistance of the conductor from which TXP is sent, the value of TXP increases to exceed VREF while TRIG2 is asserted. If resistor 408 has a greater resistance than the expected termination resistance of the conductor from which TXP is transmitted, the value of TXP will not increase to exceed VREF while TRIG2 is asserted. In at least some examples, if the conductor from which TXP is transmitted is shorted to VDD or GND, the resistance present on the conductor is less than the resistance of resistor 408. For example, the resistance present on the conductor is less than approximately 10Ω. Conversely, if the conductor from which TXP is transmitted is effectively terminated, the expected termination resistance of the conductor from which TXP is transmitted is present on the conductor. In at least one example, if the conductor is effectively terminated, the resistance present on the conductor is greater than approximately 40Ω or approximately equal to 50Ω. The value of TXP increases based on the relationship between the resistance of resistor 408 and the resistance present on the conductor. As described above, the rate of increase in the value indicates, in at least some examples, whether or not a fault or high-Z condition is present. If the resistance of resistor 408 is greater than the resistance present on the conductor, a large portion of VDD drops across the ends of resistor 408, and as a result, the value of TXP increases slowly. Conversely, if the resistance of resistor 408 is less than the resistance present on the conductor, most of VDD drops across the conductor, resulting in a more rapid increase in the value of TXP.

[0041] For example, after the first edge transition of TRIG2 occurs, TRIG2 remains asserted for a predefined time period determined at least partially according to the expected termination resistance of the conductor to which TXP is transmitted and the resistance of resistor 408. At the second edge transition of TRIG2, if the value of TXP increases to exceed VREF, circuit 400 determines that there is no short circuit in the conductor because the resistance present on the conductor is greater than the resistance of resistor 408. However, at the second edge of TRIG2, if TXP remains less than VREF, circuit 400 determines that there is no short circuit in the conductor because the resistance present on the conductor is less than the resistance of resistor 408. The determination is made by comparing TXP with VREF in at least some examples, as comparator 416 COMP This is done by generating OUT. In some examples, circuit 200 receives TRIG2 from circuit 136, and circuit 136 performs COMP substantially simultaneously with the second edge transition of TRIG2. The value of OUT is sampled (e.g., recorded and / or stored). In another example, circuit 136 performs COMP at a time time adjacent to the second edge transition of TRIG2. The value of OUT is sampled. For example, circuit 136 performs COMP slightly before or slightly after the second edge transition of TRIG2. Sample the value of OUT.

[0042] Referring here to Figures 5A and 5B, illustrative diagrams of signal waveforms are shown. In at least some examples, diagram 505 represents at least some signals present in system 100 in Figure 1 and / or circuit 400 in Figure 4 when the positive conductor 116 is terminated to a valid termination or short circuit. Also in at least some examples, diagram 510 represents at least some signals present in system 100 in Figure 1 and / or circuit 400 in Figure 4 when the positive conductor 116 is in a high-Z state. Accordingly, at least some aspects of the description of Figures 5A and / or 5B refer to the components and / or signals of Figures 1 and / or 4. Also, as in the above description, Figures 5A and 5B are described with respect to the first output terminal 112, TXP, and the positive conductor 116. The waveforms for the second output terminal 114, the signal present at the second output terminal (referred to herein as TXN), and the negative conductor 118 are substantially similar to those illustrated in Figures 5A and 5B.

[0043] As shown in Figure 505, when TRIG1 is asserted, the value of TXP begins to increase. TRIG1 remains asserted for a predefined time period determined at least in part according to VREF, VCM, and the resistance value of resistor 404. For example, TRIG1 remains asserted for a time period sufficient to determine, based on the values ​​of VCM and TXP, whether the resistance of resistor 404 is greater or less than the resistance present on the positive conductor 116. The resistance present on the positive conductor 116 is less than the resistance of resistor 404 if the positive conductor 116 is either short-circuited and terminated, or terminated with an expected termination resistance. If the resistance present on the positive conductor 116 is less than the resistance of resistor 404, TXP is set as TRIG1 is asserted and COMP OUT remains less than VREF for the duration that it is deasserted (this is a logical high level in this example, but a logical low level in other examples).

[0044] Furthermore, as shown in Figure 510, when TRIG1 is asserted, the value of TXP begins to increase. For example, as described elsewhere in this specification, the rate of increase in TXP after the assertion of TRIG1 depends on the ratio of the resistance of resistor 404 to the resistance present on the positive conductor 116. Furthermore, as also described elsewhere in this specification, the rate of increase in TXP indicates whether or not there is a fault or a high-Z condition on the positive conductor 116. TRIG1 remains asserted for a predefined time period, as described with reference to Figure 505. If the positive conductor 116 is in a high-Z condition (e.g., unterminated), the resistance present on the positive conductor 116 is greater than the resistance of resistor 404. If the resistance present on the positive conductor 116 is greater than the resistance of resistor 404, TXP exceeds VREF before the deassertion of TRIG1 and COMP OUT is asserted (in this example, it is set to a low logical level, but in other examples, it is set to a high logical level).

[0045] Referring here to Figures 6A and 6B, illustrative diagrams of signal waveforms are shown. In at least some examples, diagram 605 represents at least some signals present in system 100 in Figure 1 and / or circuit 400 in Figure 4 when a short circuit is present. Also in at least some examples, diagram 610 represents at least some signals present in system 100 in Figure 1 and / or circuit 400 in Figure 4 when a short circuit is not present (e.g., when a valid termination is present). Thus, at least some aspects of the description of Figures 6A and / or 6B refer to the components and / or signals of Figures 1 and / or 4. Furthermore, as in the above description, Figures 6A and 6B are described with respect to the first output terminal 112, TXP, and positive conductor 116. The waveforms for the second output terminal 114, the signal present at the second output terminal (referred to as TXN), and the negative conductor 118 are substantially similar to those illustrated in Figures 6A and 6B.

[0046] As shown in Figure 605, when TRIG2 is asserted, the value of TXP begins to increase. TRIG2 remains asserted for a predefined time period determined at least in part according to VREF, VCM, and the resistance value of resistor 408. For example, TRIG2 remains asserted for a time period sufficient to determine, based on the values ​​of VCM and TXP, whether the resistance of resistor 408 is greater or less than the resistance present on the positive conductor 116. If the positive conductor 116 is shorted to VDD or GND, the resistance present on the positive conductor 116 is less than the resistance of resistor 408. If the resistance present on the positive conductor 116 is less than the resistance of resistor 408, TXP is set, TRIG2 is asserted, and COMP OUT remains deasserted for the duration that it is less than VREF (this is a logical high level in this example, but a logical low level in other examples).

[0047] Furthermore, as shown in Figure 610, when TRIG2 is asserted, the value of TXP begins to increase. TRIG2 remains asserted for a predefined time period, as explained with reference to Figure 605. If the positive conductor 116 is effectively terminated with a resistance greater than that of resistor 408 and / or is not shorted to VDD or GND, the resistance present on the positive conductor 116 is greater than that of resistor 408. If the resistance present on the positive conductor 116 is greater than that of resistor 408, TXP exceeds VREF and COMP before TRIG2 is deasserted. OUT is asserted (in this example, it is set to a low logical level, but in other examples, it is set to a high logical level).

[0048] Referring here to Figure 7, a flowchart of the exemplary method 700 is shown. In at least some examples, method 700 is a fault detection method. In some examples, method 700 is implemented by one or more electrical components for determining whether a fault or high-Z condition is present in a conductor. In some examples, the conductor is at least one of a pair of conductors of opposing polarity in a differential conductor. In at least some examples, method 700 is implemented separately for both the positive and negative conductors of the differential conductor. In this way, it is possible to determine whether the other positive or negative conductor has encountered a fault, even if one of the positive or negative conductors is effectively terminated.

[0049] In operation 702, a common-mode voltage is received. In at least some examples, the common-mode voltage is received from a differential driver. In at least some examples, the common-mode voltage is output by a differential driver for transmitting on the positive or negative conductor of the differential conductor. In other examples, the common-mode voltage is used to determine whether a signal is to be transmitted on the positive or negative conductor of the differential conductor. Generally, transmission on the positive or negative conductor of the differential conductor is determined at least in part according to the received common-mode voltage.

[0050] In operation 704, a pull-up network coupled to the differential conductor is enabled. In at least some examples, the pull-up network is enabled by coupling the differential conductor to VDD via a pull-up resistor and a switchable component that becomes active when the pull-up network is enabled and inactive when the pull-up network is disabled. In at least some examples, the resistance of the pull-up resistor is less than the expected termination resistance of the differential conductor, but greater than the resistance found on the differential conductor when the differential conductor is shorted to VDD or GND.

[0051] In operation 706, a comparison result is generated indicating whether a fault or high Z exists on the differential conductor. In at least some examples, such as a single-step fault detection process, the comparison result indicates whether a short circuit exists on the differential conductor, for example to VDD or GND, or whether the differential conductor is in a high Z state. In at least some examples, the comparison result is generated by comparing the received VREF with the voltage present on the differential conductor after a predefined amount of time. For example, by activating a pull-up network, a voltage divider is formed having a pull-up resistor as the top resistance, a conductor termination resistor as the bottom resistance, and a differential conductor as the output point of the voltage divider. By comparing VREF with the voltage present on the differential conductor after a predefined amount of time, the comparison result indicates whether the top resistance or the bottom resistance is greater.

[0052] As already described herein, in at least some examples, one or more capacitors are coupled between the output points of the voltage divider and the impedance elements providing the termination resistance, potentially altering the bottom resistance from what would accurately reflect the termination resistance. Furthermore, in at least some examples, the capacitors alter the charging rate of the output points of the voltage divider. However, capacitors are not considered in the voltage dividers described herein because the capacitors remain unchanged and only the activation or deactivation of the pull-up network changes. For example, if the top resistance is greater in value than the bottom resistance, the voltage across the differential conductor will be less than VREF at the end of a predefined time period. Conversely, if the top resistance is less in value than the bottom resistance, the voltage across the differential conductor will be greater than VREF at the end of a predefined time period. If the voltage across the differential conductor is greater than VREF at the end of a predefined time period, the comparison result is asserted, indicating that the differential conductor is effectively terminated (e.g., not shorted to VND or GND).

[0053] In other examples, such as in a multi-step fault detection process, the comparison result indicates whether a high-Z state exists on the differential conductor. In this example, in the first step of the multi-step fault detection process, the comparison result indicates whether the differential conductor is terminated or in a high-Z state. Termination is either a valid termination (e.g., using an expected termination resistor) or a short circuit. In at least some examples, the comparison result is again generated by comparing the received VREF with the voltage present on the differential conductor after a predefined time period. For example, by activating a pull-up network, a voltage divider is formed having a pull-up resistor as the top resistance, the termination resistor of the differential conductor as the bottom resistance, and the differential conductor as the output point of the voltage divider. By comparing VREF with the voltage present on the differential conductor after a predefined time period, the comparison result indicates whether the value of the top resistance or the bottom resistance is greater. For example, if the value of the top resistance is greater than the value of the bottom resistance, the voltage present on the differential conductor will be less than VREF at the end of the predefined time period. Conversely, if the top resistance is less than the bottom resistance, the voltage across the differential conductor will be greater than VREF at the end of the predefined time period. If the voltage across the differential conductor is greater than VREF at the end of the predefined time period, the comparison result is asserted, indicating that the differential conductor is in a high-Z state (e.g., unterminated).

[0054] In an optional operation 708, based on the form operation 706 takes, another comparison result is generated indicating whether or not a fault exists on the differential conductor. In this example, in the second step of the multi-step fault detection process, the comparison result indicates whether the differential conductor is terminated or in a high-Z state. In at least some examples, the differential conductor being in a high-Z state indicates a fault on the differential conductor. In other examples, the differential conductor being in a high-Z state simply provides information such as that the component is not ready to receive data. Termination is either a valid termination (e.g., using an expected termination resistor) or a short circuit. In at least some examples, the comparison result is again generated by comparing the received VREF with the voltage present on the differential conductor after a predefined amount of time. For example, by activating another pull-up network, a second voltage divider is formed having the pull-up resistor of the other pull-up network as the top resistor, the termination resistor of the differential conductor as the bottom resistor, and the differential conductor as the output point of the voltage divider. By comparing VREF with the voltage present across the differential conductor after a predefined time period, the comparison result indicates whether the top resistance or the bottom resistance is greater. For example, if the top resistance is greater than the bottom resistance, the voltage across the differential conductor will be less than VREF at the end of the predefined time period. Conversely, if the top resistance is less than the bottom resistance, the voltage across the differential conductor will be greater than VREF at the end of the predefined time period. If the voltage across the differential conductor is greater than VREF at the end of the predefined time period, the comparison result is asserted, indicating that the differential conductor is effectively terminated (e.g., not shorted to VND or GND).

[0055] Furthermore, in at least some examples, operations 702 to 708 described above are performed to determine whether a short circuit exists between the positive and negative conductors of a differential conductor. For example, one of the positive or negative conductors is controlled to be in a high-Z state, the other positive or negative conductor is effectively terminated, and then the procedure is reversed, while monitoring the results for both configurations, to determine whether a short circuit exists between the positive and negative conductors of a differential conductor. This procedure is described in detail above with respect to Figure 1.

[0056] Optionally, method 700 further includes operation 710. In operation 710, the comparison output is sampled, and based on the comparison result, the value of the interrupt flag is set. In at least some examples, sampling and setting are performed by a circuit having at least some processing or logic function, such as a digital logic circuit. In some examples, the circuit is the same circuit that determines a predefined time period during which a pull-up network and / or another pull-up network is enabled. In some examples, if a fault is determined to be present on the conductor (e.g., the comparison result has an asserted value), the interrupt flag is asserted; otherwise, it is deasserted.

[0057] While the operation of Method 700 has been described and represented by numerical references, in various examples Method 700 includes additional operations not described herein. In some examples, any one or more operations described herein include one or more sub-operations (e.g., intermediate comparison, logical operation, output selection via multiplexer, format conversion, determination, etc.). In some examples, any one or more operations described herein are omitted. In some examples, any one or more operations described herein are performed in an order other than that presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.). Each of these options falls within the scope of this specification.

[0058] In the foregoing description, the terms “include” and “incorporate” are used in an unrestricted manner and therefore mean “include, but not limited to.” The term “combine” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with the description herein. For example, if device A generates a signal to control control device B to perform a certain action, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via an intermediate component C, but the intermediate component C does not substantially alter the functional relationship between device A and device B via the control signal generated by device A, such that device B is controlled by device A via the control signal generated by device A. Devices “configured” to perform a certain task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform those functions, or they may be configurable (or reconfigurable) by the user after manufacture to perform those functions and / or other additional or alternative functions. Such configurations may be achieved through device firmware and / or software programming, through the configuration and / or layout of hardware components, through device interconnections, or through a combination thereof. Furthermore, a circuit or device said to include certain components may instead be configured to couple with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current power supplies) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be configured to couple with at least some of the passive elements and / or sources, thereby forming the described structure, for example, by an end user and / or a third party, either at the time of manufacture or at a later point in time.

[0059] Some components are described herein as belonging to a specific process technology (e.g., FETs, metal-oxide-semiconductor FETs (MOSFETs), n-type, p-type, etc.), but these components may be interchangeable with components of other process technologies (e.g., replacing FETs and / or MOSFETs with BJTs, replacing n-type with p-type, or vice versa). A reconfigured circuit including the replaced components will provide the desired functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistors. Also, the term “ground voltage potential” in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teaching herein. Unless otherwise specified, “about,” “approximately,” or “substantially” preceding a value means + / - 10 percent of the stated value.

[0060] The above description is intended to illustrate the principles and various examples of this specification. Once the above description is fully understood, many variations and modifications will become apparent to those skilled in the art. This specification encompasses all such variations and modifications.

Claims

1. It is a circuit, An output node adapted to be coupled to a conductor having an expected termination resistance, A first pull-up network adapted to couple a voltage supply and the output node, the first pull-up network having a first resistance value smaller than the expected termination resistance value, A second pull-up network adapted to be coupled to the voltage supply and the output node, the second pull-up network having a second resistance value greater than the expected termination resistance value, A comparator having a first input connected to the output node, a second input configured to receive a reference voltage, and an output configured to output a comparison result, A circuit element coupled to the output of the comparator, based on the comparison result, A fault is indicated when the first resistance value is greater than the resistance value between the output node and the reference potential. A high impedance state is observed when the second resistance value is smaller than the resistance value between the output node and the reference potential. The circuit element is configured as follows: A circuit that includes this.

2. The circuit according to claim 1, When the aforementioned fault exists, after the first pull-up network becomes active, for a predetermined time period, the voltage at the output node is less than the reference voltage. A circuit in which, for a predetermined time period after the second pull-up network becomes active while the high impedance state exists, the voltage at the output node is greater than the reference voltage.

3. It is a circuit, An output node adapted to be coupled to a conductor having an expected termination resistance, A first pull-up network adapted to couple a voltage supply and the output node, the first pull-up network having a first resistance value smaller than the expected termination resistance value, A second pull-up network adapted to be coupled to the voltage supply and the output node, the second pull-up network having a second resistance value greater than the expected termination resistance value, A comparator having a first input connected to the output node, a second input configured to receive a reference voltage, and an output configured to output a comparison result, Includes, A circuit element coupled to the output of the comparator, If the first pull-up network is active, and the voltage at the output node is lower than the reference voltage for a predetermined time period after the first pull-up network becomes active, then a fault is detected. A high impedance state exists when the second pull-up network is active and the voltage at the output node is greater than the reference voltage for a predetermined time period after the second pull-up network becomes active. The circuit element is configured to determine that, A circuit that includes this.

4. The circuit according to claim 3, A circuit in which the first resistance value is greater than the short-circuit resistance value, and the second resistance value is less than the high-impedance resistance value.

5. It is a circuit, An output node adapted to be coupled to a conductor having an expected termination resistance, A first pull-up network coupled between a voltage supply input and the output node, the first pull-up network having a first resistance value smaller than the expected termination resistance value, A second pull-up network coupled between the voltage supply input and the output node, the second pull-up network having a second resistance value greater than the expected termination resistance value, A comparator having a first input coupled to the output node, a second input configured to receive a reference voltage, and an output, A first resistor coupled between the voltage supply input and the first node, A second resistor is coupled between the first node and the output node, An amplifier having a first input coupled to the first node, a second input configured to receive a common-mode voltage for signal transmission on the conductor, and an output coupled to the output node, A circuit that includes this.

6. The circuit according to claim 5, A circuit in which the first resistor, the second resistor, and the amplifier force the output node to a value approximately equal to half the value of the voltage supply signal present at the voltage supply input.

7. It is a method, Receiving a common-mode voltage for signal transmission on a conductor with an expected termination resistance, Enabling a first pull-up network coupled to the conductor, wherein the first pull-up network has a first resistance value smaller than the expected termination resistance value, When the first resistance value is greater than the resistance value present in the conductor, a comparison result indicating the presence of a fault on the conductor is generated by comparing the voltage present in the conductor after a first time period with a reference voltage, When the first resistance value is smaller than the resistance value present in the conductor, the voltage present in the conductor is compared with the reference voltage to generate a comparison result indicating that there is no obstruction on the conductor. Enabling a second pull-up network coupled to the conductor, wherein the second pull-up network has a second resistance value greater than the expected termination resistance value, By comparing the voltage present in the conductor when the second resistance value is smaller than the resistance value associated with the conductor with the reference voltage, a comparison result is generated indicating the presence of a high impedance state on the conductor. When the second resistance value is greater than the resistance value associated with the conductor, the voltage present in the conductor is compared with the reference voltage to generate a comparison result indicating the termination of the conductor. Methods that include...

8. The method according to claim 7, Controlling the second pull-up network to enable it during a second time period, In order to determine the state of the conductor, the comparison results are sampled at the end of the second time period, Methods that include...

9. The method according to claim 7, The first polar portion of the conductor is controlled to enter the high-impedance state, and the second polar portion of the conductor is terminated by an effective termination. The determination of whether or not the first polar portion of the conductor is terminated is made by comparing the voltage present in the first polar portion of the conductor with the reference voltage, When it is determined that the first polar portion of the conductor is terminated, the control is performed so that the first polar portion of the conductor is effectively terminated and the second polar portion of the conductor is in the high impedance state. The determination of whether or not the second polar portion of the conductor is terminated is made by comparing the voltage present in the second polar portion of the conductor with the reference voltage, When the second polar portion of the conductor is terminated, it is determined that a short circuit exists between the first polar portion of the conductor and the second polar portion of the conductor. Methods that further include the above.

10. It is a system, A transmitter including a fault detection circuit, wherein the fault detection circuit is Output node, A first pull-up network coupled between a voltage supply node and the output node, the first pull-up network having a first resistance value, A second pull-up network coupled between the voltage supply node and the output node, the second pull-up network having a second resistance value greater than the first resistance value, A comparator having a first input connected to the output node, a second input configured to receive a reference voltage, and an output terminal configured to output a comparison result, The transmitter includes, A receiver including a termination circuit, A differential conductor having an expected termination resistance between the first resistance value and the second resistance value, A positive conductor that connects the output node to the receiver, and is configured to connect the fault detection circuit to the termination circuit, A negative conductor that couples the transmitter to the receiver, and is configured to couple the fault detection circuit to the termination circuit, The differential conductor includes, A system that includes this.

11. The system according to claim 10, The fault detection circuit, The common-mode voltage for signal transmission on the differential conductor is received, Enable the first pull-up network, When the resistance value of the first pull-up network is greater than the resistance value associated with the differential conductor, the voltage present in the differential conductor is compared with the reference voltage to generate a comparison result indicating the presence of a fault on the differential conductor. When the resistance of the first pull-up network is smaller than the resistance associated with the differential conductor, the voltage present in the differential conductor is compared with the reference voltage to generate a comparison result indicating that there is no fault on the differential conductor. A system configured in such a way.

12. The system according to claim 10, The aforementioned system The termination circuit is controlled to maintain the positive conductor in a high impedance state and terminate the negative conductor using an effective termination. Based on the comparison results of the comparator, it is determined whether or not the positive conductor is terminated. If it is determined that the positive conductor is terminated, the termination circuit is controlled to maintain the negative conductor in the high impedance state and terminate the positive conductor using the effective termination. Based on the comparison results of the comparator, it is determined whether or not the negative conductor is terminated. If it is determined that the negative conductor is terminated, it is determined that a short circuit exists between the positive conductor and the negative conductor. A system configured in such a way.

13. The system according to claim 10, The fault detection circuit, Enable the second pull-up network, By comparing the voltage present in the differential conductor when the resistance value of the second pull-up network is smaller than the resistance value associated with the differential conductor with the reference voltage, a comparison result indicating the presence of a high impedance state on the differential conductor is generated. When the resistance of the pull-up network is greater than the resistance associated with the differential conductor, the voltage present in the differential conductor is compared with the reference voltage to generate a comparison result indicating effective termination of the differential conductor. A system configured in such a way.

14. The system according to claim 10, The fault detection circuit, A first resistor coupled between the voltage supply node and the first node, A second resistor is coupled between the first node and the output node, An amplifier having a first input coupled to the first node, a second input configured to receive a common-mode voltage for signal transmission on the differential conductor, and an output coupled to the output node, A system that further includes the following.

15. The system according to claim 14, When the differential conductor is short-circuited to the voltage supply node or the reference potential node, the first resistance value is smaller than the expected termination resistance value of the differential conductor and larger than the resistance value present in the differential conductor. A system in which, when the differential conductor is in a high impedance state, the second resistance value is greater than the expected termination resistance value of the differential conductor and less than the resistance value present on the differential conductor.

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