Method for manufacturing a display device

Abstract

To provide a manufacturing method of a display device, capable of suppressing performance deterioration of a display element.SOLUTION: A manufacturing method of a display device, comprises: a lower electrode; an organic layer that is arranged onto the lower electrode; and an upper electrode that is laminated onto the organic layer. A step of forming the organic layer includes: a step of forming a first carrier adjustment layer; and a step of forming a light emission layer. In the step of forming the first carrier adjustment layer, a first material is evaporated while relatively moving a first vapor deposition source to a first direction against a processing object substrate to which the lower electrode is formed. In the step of forming the light emitting layer, a second material is evaporated while relatively moving a second vapor deposition source to a second direction that is crossed to the first direction against the processing object substrate in which the first carrier adjustment layer has to be formed.SELECTED DRAWING: Figure 7B

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes an organic layer between a pixel electrode and a common electrode. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. Such an organic layer is formed, for example, by a vacuum evaporation method.

[0003] For example, in the case of mask evaporation, a fine mask having an opening corresponding to each pixel is applied. However, due to the processing accuracy of the fine mask, deformation of the opening shape, etc., there is a risk that the formation accuracy of the thin film formed by evaporation may decrease. For example, when forming an organic layer in which a plurality of functional layers are laminated, the end face of the organic layer may not be formed at a desired position, which may cause performance deterioration of the display element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] The object of the present invention is to provide a display device and a method for manufacturing a display device that can suppress performance degradation of display elements. [Means for solving the problem]

[0006] The display device according to one embodiment is The device comprises a base material, a first insulating layer disposed on the base material, a lower electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and having an opening superimposed on the lower electrode, and an organic layer having a light-emitting layer, disposed on the opening and covering the lower electrode, and an upper electrode covering the organic layer, wherein the light-emitting layer has a first bottom surface, a first end surface, and a second end surface intersecting the first end surface, and the angle between the first end surface and the first bottom surface in a cross-sectional view along a first direction is greater than the angle between the second end surface and the first bottom surface in a cross-sectional view along a second direction intersecting the first direction.

[0007] A method for manufacturing a display device according to one embodiment is: A method for manufacturing a display device comprising a lower electrode, an organic layer disposed on the lower electrode, and an upper electrode disposed on the organic layer, wherein the step of forming the organic layer comprises the steps of forming a first carrier adjustment layer and forming a light-emitting layer, wherein in the step of forming the first carrier adjustment layer, a first material is deposited while moving a first deposition source relatively in a first direction with respect to a substrate on which the lower electrode has already been formed, and in the step of forming the light-emitting layer, a second material is deposited while moving a second deposition source relatively in a second direction intersecting the first direction with respect to the substrate on which the first carrier adjustment layer has already been formed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example configuration of a display device DSP according to this embodiment. [Figure 2] Figure 2 shows an example of the configuration of the display element 20. [Figure 3] Figure 3 is a plan view showing an example of a pixel PX as shown in Figure 1. [Figure 4] Figure 4 is a diagram for explaining one method of controlling the radiation angle. [Figure 5] Figure 5 is a diagram for explaining another method of controlling the radiation angle. [Figure 6] Figure 6 is a diagram for explaining another method of controlling the radiation angle. [Figure 7A] Figure 7A shows the cross-sectional shape of the layer LY along the direction DR1. [Figure 7B] Figure 7B shows the cross-sectional shape of the layer LY along the direction DR2. [Figure 8A] Figure 8A shows another cross-sectional shape of the layer LY along the direction DR1. [Figure 8B] Figure 8B shows another cross-sectional shape of the layer LY along the direction DR2. [Figure 9] Figure 9 is a plan view showing an example of the display element 20. [Figure 10] Figure 10 is a cross-sectional view showing an example of the display element 20 along the line A-B shown in Figure 9. [Figure 11] Figure 11 is a cross-sectional view showing an example of the display element 20 along the line C-D shown in Figure 9. [Figure 12] Figure 12 is a diagram for explaining the manufacturing method of the display element 20 shown in Figure 11. [Figure 13] Figure 13 is a diagram for explaining the manufacturing method of the display element 20 shown in Figure 11. [Figure 14] Figure 14 is a plan view showing another example of the display element 20. [Figure 15] Figure 15 is a cross-sectional view showing an example of the display element 20E along the line A-B shown in Figure 14. [Figure 16] Figure 16 is a cross-sectional view showing an example of the display element 20 along the line C-D shown in Figure 14. [Figure 17] Figure 17 is a diagram for explaining the manufacturing method of the plurality of display elements 20 shown in Figure 16. [Figure 18] Figure 18 is a diagram for explaining the manufacturing method of the plurality of display elements 20 shown in Figure 16. [Figure 19] FIG. 19 is a diagram for explaining a method of manufacturing a plurality of display elements 20 shown in FIG. 16.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above with respect to the previously shown drawings may be assigned the same reference numerals, and detailed descriptions may be appropriately omitted.

[0010] It should be noted that in the drawings, for the purpose of facilitating understanding as necessary, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the X direction or the first direction, the direction along the Y-axis is referred to as the Y direction or the second direction, and the direction along the Z-axis is referred to as the Z direction or the third direction. The plane defined by the X-axis and the Y-axis is referred to as the X-Y plane, the plane defined by the Y-axis and the Z-axis is referred to as the Y-Z plane, and the plane defined by the X-axis and the Z-axis is referred to as the X-Z plane. Looking at the X-Y plane is referred to as a plan view.

[0011] The display device DSP according to the present embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and is mounted on a television, a personal computer, a portable terminal, a mobile phone, etc. It should be noted that the display element described below can be applied as a light-emitting element of a lighting device, and the display device DSP can be diverted to other electronic devices such as a lighting device.

[0012] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes a display unit DA for displaying an image on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] The display unit DA comprises multiple pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX comprises multiple sub-pixels SP1, SP2, and SP3. In one example, pixel PX comprises a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. In addition to the three sub-pixels of the above colors, pixel PX may also have four or more sub-pixels, including sub-pixels of other colors such as white.

[0014] A brief explanation of one example configuration of a sub-pixel SP included in a pixel PX is provided. In other words, the sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven and controlled by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switch elements composed of, for example, thin-film transistors.

[0015] For the pixel switch 2, the gate electrode is connected to the scan line GL, the source electrode is connected to the signal line SL, and the drain electrode is connected to one electrode constituting the capacitor 4 and the gate electrode of the drive transistor 3. For the drive transistor 3, the source electrode is connected to the other electrode constituting the capacitor 4 and the power line PL, and the drain electrode is connected to the anode of the display element 20. The cathode of the display element 20 is connected to the power supply line FL. Note that the configuration of the pixel circuit 1 is not limited to the example shown.

[0016] The display element 20 is an organic light-emitting diode (OLED), which is a light-emitting element. For example, sub-pixel SP1 has a display element that emits light corresponding to the red wavelength, sub-pixel SP2 has a display element that emits light corresponding to the green wavelength, and sub-pixel SP3 has a display element that emits light corresponding to the blue wavelength. By having multiple sub-pixels SP1, SP2, and SP3 with different display colors in pixel PX, multi-color display can be achieved.

[0017] However, each of the sub-pixels SP1, SP2, and SP3 display elements 20 may be configured to emit light of the same color. This enables monochrome display.

[0018] Furthermore, if each of the sub-pixels SP1, SP2, and SP3 display elements 20 is configured to emit white light, a color filter facing the display element 20 may be provided. For example, sub-pixel SP1 is provided with a red color filter facing the display element 20, sub-pixel SP2 is provided with a green color filter facing the display element 20, and sub-pixel SP3 is provided with a blue color filter facing the display element 20. This enables multi-color display.

[0019] Alternatively, if each of the sub-pixels SP1, SP2, and SP3 display elements 20 is configured to emit ultraviolet light, multi-color display can be achieved by arranging an optical conversion layer opposite to the display elements 20.

[0020] Figure 2 shows an example of the configuration of the display element 20. The display element 20 comprises a lower electrode (first electrode) E1, an organic layer OR, and an upper electrode (second electrode) E2. The organic layer OR includes a carrier adjustment layer (first carrier adjustment layer) CA1, an emissive layer EL, and a carrier adjustment layer (second carrier adjustment layer) CA2. The carrier adjustment layer CA1 is located between the lower electrode E1 and the emissive layer EL, and the carrier adjustment layer CA2 is located between the emissive layer EL and the upper electrode E2. The carrier adjustment layers CA1 and CA2 include multiple functional layers. Here, we will explain using the example where the lower electrode E1 corresponds to the anode and the upper electrode E2 corresponds to the cathode.

[0021] The carrier adjustment layer CA1 includes, as a functional layer, a hole injection layer F11, a hole transport layer F12, a carrier generation layer F13, and an electron blocking layer F14. The hole injection layer F11 is located on the lower electrode E1, the hole transport layer F12 is located on the hole injection layer F11, the carrier generation layer F13 is located on the hole transport layer F12, the electron blocking layer F14 is located on the carrier generation layer F13, and the light-emitting layer EL is located on the electron blocking layer F14.

[0022] The carrier adjustment layer CA2 includes, as a functional layer, a hole block layer F21, an electron transport layer F22, an electron injection layer F23, and so on. The hole block layer F21 is located on top of the light-emitting layer EL, the electron transport layer F22 is located on top of the hole block layer F21, the electron injection layer F23 is located on top of the electron transport layer F22, and the upper electrode E2 is located on top of the electron injection layer F23.

[0023] Furthermore, the carrier adjustment layers CA1 and CA2 may include other functional layers as needed, in addition to the functional layers described above, and at least one of the functional layers described above may be omitted in the carrier adjustment layers CA1 and CA2.

[0024] Figure 3 is a plan view showing an example of a pixel PX as shown in Figure 1. The sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are each formed in a roughly rectangular shape extending in the second direction Y, and are arranged in the first direction X. The outline of each sub-pixel corresponds to the outline of the light-emitting region EA in the display element 20, but this is a simplified representation and does not necessarily reflect the actual shape. Here, it is assumed that the light-emitting region EA is formed in a rectangular shape with a short side extending in the first direction X and a long side extending in the second direction Y.

[0025] The insulating layer 12, which will be described in detail later, is formed in a grid pattern in a plan view, extending in the first direction X and the second direction Y, respectively, and surrounds each of the sub-pixels SP1, SP2, and SP3, or the display element 20 of each sub-pixel. Such an insulating layer 12 may be referred to as a rib, partition, or bank. The light-emitting region EA is formed in the opening OP of the insulating layer 12 and corresponds to the region where the organic layer OR is interposed between the lower electrode E1 and the upper electrode E2.

[0026] For example, if each of the sub-pixels SP1, SP2, and SP3 display elements 20 is configured to emit light of different colors from each other, then the first direction X corresponds to the direction in which sub-pixels of different display colors are aligned, and the second direction Y corresponds to the direction in which sub-pixels of the same display color are aligned. Alternatively, sub-pixels of the same display color may be aligned in diagonal directions different from the first direction X and the second direction Y.

[0027] Each layer of the organic layer OR shown in Figure 2 is formed by vapor deposition. At this time, the radiation angle of the material emitted from the vapor deposition source can be controlled, for example, by the following method.

[0028] Figure 4 illustrates one method for controlling the radiation angle. The substrate to be processed, SUB, is positioned opposite the deposition source VS, as shown by the dotted line. The deposition source VS comprises a crucible 50 for containing the material and a nozzle 51 connected to the crucible 50. The crucible 50 is heated by a heating mechanism. The vapor of the material generated by heating the crucible 50 is emitted at a radiation angle θ.

[0029] Figure 4 shows one method for controlling the radiation angle (or steam directionality) θ by the shape of the nozzle 51. Here, the nozzle shown on the left side of the figure is referred to as the first nozzle 51, and the nozzle shown on the right side of the figure is referred to as the second nozzle 51. The shape of the first nozzle 51 is different from the shape of the second nozzle 51.

[0030] That is, the first nozzle 51 is thicker and shorter compared to the second nozzle 51. The emission angle θ1 of the vapor of the material emitted from the first nozzle 51 is larger than the emission angle θ2 of the vapor of the material emitted from the second nozzle 51 (θ1 > θ2). That is, the vapor emitted from the first nozzle 51 is likely to spread (has low directivity). On the other hand, the vapor emitted from the second nozzle 51 is unlikely to spread (has high directivity). FIG. 5 is a diagram for explaining another method of controlling the emission angle. Also in the example shown in FIG. 5, the shape of the first nozzle 51 is different from the shape of the second nozzle 51. Here, the opening diameter D1 of the first nozzle 51 is smaller than the opening diameter D2 of the second nozzle 51 (D1 < D2). Even in such an example, the vapor of the material emitted from the first nozzle 51 is likely to spread, and the vapor of the material emitted from the second nozzle 51 is unlikely to spread.

[0031] FIG. 6 is a diagram for explaining another method of controlling the emission angle. In the example shown in FIG. 6, the crucible shown on the left side of the figure is referred to as the first crucible 50, and the crucible shown on the right side of the figure is referred to as the second crucible 50. The temperature distribution of the first crucible 50 is different from the temperature distribution of the second crucible 50. For example, the heating temperature on the bottom side of the first crucible 50 is set higher than the heating temperature on the nozzle side, and the heating temperature on the bottom side of the second crucible 50 is set lower than the heating temperature on the nozzle side. Thus, by adjusting the temperature distribution of the crucible, the emission angle of the vapor can also be controlled. In the example shown in FIG. 6, the vapor of the material emitted from the first nozzle 51 is likely to spread, and the vapor of the material emitted from the second nozzle 51 is unlikely to spread.

[0032] The vapor deposition of each layer constituting the organic layer OR is performed while the vapor deposition source VS moves relative to the substrate SUB to be processed. That is, the vapor deposition source VS may move relative to the fixed substrate SUB to be processed, or the substrate SUB to be processed may move relative to the fixed vapor deposition source VS, or both the substrate SUB to be processed and the vapor deposition source VS may move.

[0033] The cross-sectional shape of the layer LY formed by the method described above will now be explained. Here, the direction in which the deposition source VS moves is defined as DR2, and the direction perpendicular to direction DR2 is defined as DR1. As the deposition source VS moves in direction DR2, the material emitted from the deposition source VS is deposited on the substrate SUB to be processed. As a result, the layer LY is formed on the surface of the substrate SUB to be processed.

[0034] Figure 7A shows the cross-sectional shape of layer LY along direction DR1. Layer LY has a bottom surface LB and an end surface LS1. The angle between the bottom surface LB and the end surface LS1 is called the inclination angle θL1 of the end surface LS1. The end surface LS1 corresponds to the end surface along direction DR2 in which the deposition source VS moves. Figure 7B shows the cross-sectional shape of layer LY along direction DR2. Layer LY further has an end face LS2. The angle between the bottom face LB and the end face LS2 is called the inclination angle θL2 of the end face LS2. The end face LS2 corresponds to an end face perpendicular to the direction DR2 in which the deposition source VS moves, or an end face along direction DR1. The inclination angle θL2 is smaller than the inclination angle θL1 (θL2 < θL1).

[0035] Figure 8A shows another cross-sectional shape of layer LY along direction DR1. In this example, the deposition source VS has multiple nozzles 51 spaced apart along direction DR1. End face LS1 corresponds to the end face along direction DR2 in which the deposition source VS moves. The angle between the bottom surface LB and the end face LS1 is referred to as the inclination angle θL1 of the end face LS1. Figure 8B shows another cross-sectional shape of layer LY along direction DR2. The end face LS2 corresponds to the end face perpendicular to the direction DR2 in which the deposition source VS shown in Figure 8A moves, or the end face along direction DR1. The angle between the bottom face LB and the end face LS2 is called the inclination angle θL2 of the end face LS2. The inclination angle θL2 is greater than the inclination angle θL1 (θL2 > θL1).

[0036] Figure 9 is a plan view showing an example of the display element 20. Note that only the components necessary for the explanation are shown here. In a plan view, at least one layer OLY constituting the organic layer OR is superimposed on the lower electrode E1 shown by the dotted line. Layer OLY is, for example, an emissive layer EL, but may be any other functional layer. Layer OLY has a pair of end faces (first end faces) SS1 that face each other in a first direction X, and a pair of end faces (second end faces) SS2 that face each other in a second direction Y. End faces SS1 extend along the second direction Y, and end faces SS2 extend along the first direction X. End faces SS1 and SS2 intersect each other.

[0037] Figure 10 is a cross-sectional view showing an example of a display element 20 along the A-B line shown in Figure 9. The pixel circuit 1 shown in Figure 1 is placed on a substrate 10 and covered by an insulating layer 11. In Figure 10, only the drive transistor 3 included in the pixel circuit 1 is shown in a simplified manner. The insulating layer (first insulating layer) 11 corresponds to the base layer of the display element 20. The insulating layer (second insulating layer) 12 is placed on top of the insulating layer 11. The insulating layers 11 and 12 are, for example, organic insulating layers.

[0038] The lower electrode E1 is located on the insulating layer 11. The lower electrode E1 is an electrode located for each sub-pixel or display element and is electrically connected to the drive transistor 3. Such a lower electrode E1 may be referred to as a pixel electrode, anode, etc.

[0039] The lower electrode E1 is a metal electrode formed from a metallic material such as silver or aluminum. Alternatively, the lower electrode E1 may be a transparent electrode formed from a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Furthermore, the lower electrode E1 may be a laminate of a transparent electrode and a metal electrode. For example, the lower electrode E1 may be configured as a laminate with transparent electrodes, metal electrodes, and transparent electrodes stacked in that order, or as a laminate of three or more layers. In the top-emission type display element 20, the lower electrode E1 includes a metal electrode as a reflective electrode.

[0040] The insulating layer 12 has an opening OP. The opening OP is formed in the region superimposed on the lower electrode E1 and is a through hole that penetrates the insulating layer 12 to the lower electrode E1. The peripheral portion of the lower electrode E1 is covered by the insulating layer 12, while the central portion of the lower electrode E1 is exposed from the insulating layer 12 at the opening OP.

[0041] The organic layer OR includes carrier conditioning layers CA1 and CA2 and an emissive layer EL. The organic layer OR is positioned at the opening OP and covers the lower electrode E1. The carrier conditioning layer CA1 is located between the lower electrode E1 and the emissive layer EL, and the carrier conditioning layer CA2 is located between the emissive layer EL and the upper electrode E2.

[0042] The illustrated carrier adjustment layer CA1 corresponds to at least one of the hole injection layer F11, hole transport layer F12, carrier generation layer F13, and electron blocking layer F14 shown in Figure 2. The carrier adjustment layer CA2 corresponds to at least one of the hole blocking layer F21, electron transport layer F22, and electron injection layer F23 shown in Figure 2.

[0043] The upper electrode E2 covers the organic layer OR. The upper electrode E2 is sometimes referred to as the common electrode, counter electrode, or cathode.

[0044] The upper electrode E2 is a semi-permeable metal electrode formed from a metallic material such as magnesium or silver. Alternatively, the upper electrode E2 may be a transparent electrode formed from a transparent conductive material such as ITO or IZO. Furthermore, the upper electrode E2 may be a laminate of a transparent electrode and a metal electrode. The upper electrode E2 is electrically connected to a power supply line located within the display unit DA, or to a power supply line located outside the display unit DA.

[0045] The portion of the organic layer OR located between the lower electrode E1 and the upper electrode E2, without passing through the insulating layer 12, can form the light-emitting region of the display element 20. In one example, the thickness of the organic layer OR along the third direction Z is set so that the peak wavelength of the emission spectrum in the light-emitting layer EL matches the effective optical path length between the lower electrode E1 and the upper electrode E2. This realizes a microcavity structure for obtaining a resonance effect.

[0046] Although not shown in the diagram, an optical adjustment layer for improving light extraction efficiency and a sealing layer for protecting the display element 20 from moisture, etc., are provided on top of the upper electrode E2.

[0047] Figure 10 shows a magnified view of the region including the end face of the light-emitting layer EL. Here, we will explain the case where the layer OLY shown in Figure 9 is the light-emitting layer EL in Figure 10. The bottom surface (first bottom surface) B1 of the light-emitting layer EL is in contact with the carrier adjustment layer CA1. In a cross-sectional view of the XZ plane defined by the first direction X and the third direction Z, the angle θ11 between the end face SS1 and the bottom surface B1 (the inclination angle θ11 of the end face SS1) is acute.

[0048] The end face SS1 is located on the carrier adjustment layer CA1 and is in contact with the carrier adjustment layer CA2. The carrier adjustment layer CA2 is outside the light-emitting layer EL, covers the carrier adjustment layer CA1, and is in contact with the insulating layer 12. The upper electrode E2 is outside the carrier adjustment layer CA2 and is in contact with the insulating layer 12.

[0049] Figure 11 is a cross-sectional view showing an example of a display element 20 along the CD line shown in Figure 9. In a cross-sectional view of the YZ plane defined by the second direction Y and the third direction Z, the angle θ12 between the end face SS2 and the bottom face B1 (the inclination angle θ12 of the end face SS2) is acute. The inclination angle θ11 of the end face SS1 shown in Figure 10 is greater than the inclination angle θ12 of the end face SS2 shown in Figure 11 (θ12 < θ11).

[0050] The end face SS2 is located on the carrier adjustment layer CA1 and is in contact with the carrier adjustment layer CA2. As shown in Figures 10 and 11, the carrier adjustment layer CA2 covers the entire light-emitting layer EL, including the end faces SS1 and SS2. In the YZ plane, the carrier adjustment layer CA2 is outside the light-emitting layer EL, covering the carrier adjustment layer CA1 and in contact with the insulating layer 12. The upper electrode E2 is outside the carrier adjustment layer CA2 and in contact with the insulating layer 12.

[0051] Next, a method for forming the light-emitting layer EL with the cross-sectional shape described above will be explained.

[0052] Figure 12 is a diagram illustrating the manufacturing method of the display element 20 shown in Figure 11. First, the substrate SUB to be processed is prepared. The substrate SUB to be processed is obtained by forming an insulating layer 11 on a base material 10, then forming a lower electrode E1 on the insulating layer 11, and then forming an insulating layer 12 having an opening OP superimposed on the lower electrode E1.

[0053] The substrate SUB to be processed is then positioned so that the insulating layer 12 and the deposition source VS face each other. Subsequently, each layer constituting the organic layer OR is formed by the deposition method. In Figure 12, the carrier adjustment layer CA1 is not shown. The light-emitting layer EL is a mixed layer containing a host material and a guest material, which is a light-emitting material.

[0054] Note that if the sublimation temperatures of the host material and the light-emitting material are different, the host material and the light-emitting material are placed in separate crucibles and heated to predetermined temperatures, but here, for simplicity, only one crucible 50 is shown in the illustration. The direction in which the deposition source VS moves is the second direction Y. In a cross-section perpendicular to the direction of movement of the deposition source VS, as shown in Figure 12, the radiation angle of the vapor emitted from the deposition source VS is controlled by a method such as the one described with reference to Figures 4 to 6. As a result, an end face SS1 with an inclination angle θ11 is formed at a position superimposed on the insulating layer 12.

[0055] Figure 13 is a diagram illustrating the manufacturing method of the display element 20 shown in Figure 11. The deposition source VS moves in the second direction Y while emitting vapor. This forms an emissive layer EL having an end face SS2 with an inclination angle θ12 at a position superimposed on the insulating layer 12. The inclination angle θ11 of the end face SS1 shown in Figure 12 is greater than the inclination angle θ12 of the end face SS2 shown in Figure 13 (θ12 < θ11). However, as explained with reference to Figures 7A and 7B, or Figures 8A and 8B, depending on the deposition method, the inclination angle θ11 may be smaller than the inclination angle θ12 (θ12 > θ11).

[0056] When subpixels of different display colors are adjacent in the first direction X, light-emitting layers EL of different emission colors are adjacent in the first direction X, and their respective end faces SS1 face each other. Since the inclination angle θ11 of the end face SS1 in each light-emitting layer EL is greater than the inclination angle θ12 of the end face SS2, the spacing between adjacent light-emitting layers EL (the spacing between opposing end faces SS1) can be ensured. As a result, unwanted light emission due to carrier movement between adjacent subpixels is suppressed, and the desired chromaticity can be obtained.

[0057] Furthermore, the carrier adjustment layer CA2 is in contact with the end faces SS1 and SS2 of the light-emitting layer EL, and moreover, it covers the light-emitting layer EL and the carrier adjustment layer CA1. Therefore, unwanted current leakage at the periphery of the organic layer OR is suppressed. Consequently, performance degradation of the display element 20 can be suppressed.

[0058] Figure 14 is a plan view showing another example of the display element 20. Note that only the configuration necessary for explanation is shown here. Multiple display elements 20 aligned in the second direction Y are configured to emit light of the same color. In other words, the second direction Y corresponds to the direction in which subpixels of the same display color are aligned. Of the multiple display elements 20, display element 20E is located on the outermost periphery of the display unit DA.

[0059] In the multiple display elements 20, at least one layer OLY constituting the organic layer OR is a common layer superimposed on the multiple lower electrodes E1 shown by the dotted line. Layer OLY is, for example, an emissive layer EL, but may be any other functional layer. Layer OLY has an end face (first end face) SS1 extending along the second direction Y and an end face (second end face) SS2 extending along the first direction X.

[0060] Figure 15 is a cross-sectional view showing an example of a display element 20E along the AB line shown in Figure 14. Note that the cross-sectional shape in the XZ plane is the same not only for the display element 20E but also for other display elements 20.

[0061] The organic layer OR includes an emissive layer EL, a carrier adjustment layer CA1 between the lower electrode E1 and the emissive layer EL, and a carrier adjustment layer CA2 between the emissive layer EL and the upper electrode E2. The carrier adjustment layer CA1 corresponds to at least one of the hole injection layer F11, hole transport layer F12, carrier generation layer F13, and electron blocking layer F14 shown in Figure 2. The carrier adjustment layer CA2 corresponds to at least one of the hole blocking layer F21, electron transport layer F22, and electron injection layer F23 shown in Figure 2.

[0062] In Figure 15, the regions including the end face of the carrier adjustment layer CA1 and the region including the end face of the light-emitting layer EL are shown in magnified view. The bottom surface (first bottom surface) B1 of the light-emitting layer EL is in contact with the carrier adjustment layer CA1. In a cross-sectional view in the XZ plane, the angle θ11 between the end face SS1 and the bottom surface B1 (the inclination angle θ11 of the end face SS1) is acute.

[0063] The carrier adjustment layer CA1 has a bottom surface (second bottom surface) B2 and an end surface (third end surface) SS3. The bottom surface B2 is in contact with the insulating layer 12. In a cross-sectional view in the XZ plane, the angle θ13 between the end surface SS3 and the bottom surface B2 (the inclination angle θ13 of the end surface SS3) is acute. The inclination angle θ13 of the end surface SS3 is smaller than the inclination angle θ11 of the end surface SS1 (θ13 < θ11). However, as explained with reference to Figures 7A and 7B, or Figures 8A and 8B, depending on the deposition method, the tilt angle θ13 may be greater than the tilt angle θ11 (θ13 > θ11).

[0064] End face SS1 is located on the carrier adjustment layer CA1 and is in contact with the carrier adjustment layer CA2. The carrier adjustment layer CA2 is outside the light-emitting layer EL and is in contact with the carrier adjustment layer CA1. End face SS3 is located on the insulating layer 12 and is in contact with the upper electrode E2. The upper electrode E2 is outside the carrier adjustment layer CA1 and is in contact with the insulating layer 12.

[0065] Figure 16 is a cross-sectional view showing an example of a display element 20 along the CD line shown in Figure 14. The carrier adjustment layers CA1 and CA2, and the light-emitting layer EL, which constitute the organic layer OR, are common layers formed continuously across multiple display elements 20, including the outermost display element 20E.

[0066] In a cross-sectional view in the YZ plane, the inclination angle θ11 of end face SS1 shown in Figure 15 is greater than the inclination angle θ12 of end face SS2 shown in Figure 16 (θ12 < θ11).

[0067] End face SS2 is located on the carrier adjustment layer CA1 and is in contact with the carrier adjustment layer CA2. The carrier adjustment layer CA2 covers the entire light-emitting layer EL, including end faces SS1 and SS2. End face SS4 of the carrier adjustment layer CA1 is located on the insulating layer 12 and is in contact with the upper electrode E2. The upper electrode E2 is in contact with the insulating layer 12 on the outside of the carrier adjustment layer CA1.

[0068] Next, a method for forming the light-emitting layer EL with the cross-sectional shape described above will be explained.

[0069] Figure 17 is a diagram illustrating the manufacturing method of the multiple display elements 20 shown in Figure 16. First, the substrate SUB to be processed is prepared. Then, the substrate SUB is positioned so that the insulating layer 12 and the evaporation source (first evaporation source) VSA face each other.

[0070] Subsequently, a carrier conditioning layer CA1 is formed by vapor deposition. The vapor deposition source VSA comprises a crucible 50A and a nozzle 51A connected to the crucible 50A. The crucible 50A contains the material (first material) for forming the functional layer. When forming a carrier conditioning layer CA1 that includes multiple functional layers, multiple crucibles containing the material for each functional layer are required, but for simplicity, only one crucible 50A is shown in this illustration.

[0071] The deposition source VSA moves in the first direction X while emitting vapor. As a result, the emitted material is deposited, and a carrier adjustment layer CA1 having an end face SS3 with an inclination angle θ13 is formed at a position superimposed on the insulating layer 12. In the cross-section in the direction perpendicular to the movement direction of the deposition source VSA, the emission angle of the vapor emitted from the deposition source VSA is controlled by a method such as the one described with reference to Figures 4 to 6.

[0072] Figure 18 is a diagram illustrating the manufacturing method of the multiple display elements 20 shown in Figure 16. In Figure 17, the substrate SUB to be processed, which has the carrier adjustment layer CA1 formed on it, is positioned so that the carrier adjustment layer CA1 and the deposition source (second deposition source) VSB face each other.

[0073] Subsequently, a light-emitting layer EL is formed by vapor deposition. The vapor deposition source VSB comprises a crucible 50B and a nozzle 51B connected to the crucible 50B. The crucible 50B contains the material (second material) for forming the light-emitting layer EL. As described above, since the light-emitting layer EL is a mixed layer of host material and light-emitting material, multiple crucibles are required, but for simplicity, only one crucible 50B is shown in this illustration.

[0074] For example, in the subpixel layout shown in Figure 2, if the display colors of the subpixels aligned in the second direction Y are the same, the direction of movement of the deposition source VSB when forming the light-emitting layer EL is set to the second direction Y. In other words, the direction of movement of the deposition source VSB (second direction Y) and the direction of movement of the deposition source VSA (first direction X) are orthogonal.

[0075] Furthermore, if the display colors of subpixels arranged in diagonal directions different from the first direction X and the second direction Y are the same, the direction of movement of the deposition source VSB when forming the light-emitting layer EL is set to the diagonal direction. In any case, the direction of movement of the deposition source VSB and the direction of movement of the deposition source VSA intersect each other in the XY plane.

[0076] The deposition source VSB moves in the second direction Y while emitting vapor. As a result, the emitted material is deposited, and a light-emitting layer EL with an end face SS2 at an inclination angle θ12 is formed at a position superimposed on the carrier adjustment layer CA1. In the cross-section perpendicular to the direction of movement of the deposition source VSB, the emission angle of the vapor emitted from the deposition source VSB is controlled by a method such as the one described with reference to Figures 4 to 6.

[0077] Figure 19 is a diagram illustrating the manufacturing method of the multiple display elements 20 shown in Figure 16. In Figure 18, the substrate SUB to be processed, which already has the light-emitting layer EL formed on it, is positioned so that the light-emitting layer EL and the deposition source (third deposition source) VSC face each other.

[0078] Subsequently, a carrier conditioning layer CA2 is formed by vapor deposition. The vapor deposition source VSC comprises a crucible 50C and a nozzle 51C connected to the crucible 50C. The crucible 50C contains the material (third material) for forming the functional layer. When forming a carrier conditioning layer CA2 that includes multiple functional layers, multiple crucibles containing the material for each functional layer are required, but for simplicity, only one crucible 50C is shown in this illustration.

[0079] The vapor deposition source VSC moves in a first direction X while emitting vapor. As a result, the emitted material is deposited, forming a carrier adjustment layer CA2 that covers the light-emitting layer EL. The carrier adjustment layer CA2 has an end face SS5 with an inclination angle θ15. In a cross-section perpendicular to the direction of movement of the vapor deposition source VSC, the emission angle of the vapor emitted from the vapor deposition source VSC is controlled by a method such as the one described with reference to Figures 4 to 6.

[0080] Even in this example, the peripheral portion of the light-emitting layer EL, particularly the end face SS1, is reliably covered by the carrier conditioning layer CA2. Therefore, the same effects as described above can be obtained.

[0081] In addition, the end face SS2 of the light-emitting layer EL in the outermost display element 20E is also reliably covered by the carrier adjustment layer CA2. This protects the light-emitting layer EL from outside air and moisture.

[0082] According to the above-described embodiment, it is possible to provide a display device and a method for manufacturing a display device that can suppress performance degradation of the display element.

[0083] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0084] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0085] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0086] DSP…Display device 10…Substrate 11…Insulating layer (first insulating layer) 12...Insulating layer (second insulating layer) OP...Opening 20...Display element E1...Lower electrode E2...Upper electrode OR...Organic layer EL...Emitting layer B1...Bottom surface SS1...End surface (1st end surface) SS2...End surface (2nd end surface)

Claims

1. Lower electrode and An organic layer placed on the lower electrode, A method for manufacturing a display device comprising an upper electrode disposed on the organic layer, The process of forming the organic layer comprises the steps of forming a first carrier adjustment layer and forming a light-emitting layer. In the step of forming the first carrier adjustment layer, the first material is deposited while the first deposition source is moved relative to the substrate to be processed, in a first direction, with respect to the substrate on which the lower electrode has already been formed. A method for manufacturing a display device, wherein in the step of forming the light-emitting layer, the second deposition source is moved relative to the substrate to be processed, on which the first carrier adjustment layer has already been formed, in a second direction intersecting the first direction, while the second material is deposited.

2. The process of forming the aforementioned interior further includes the step of forming a second carrier conditioning layer. The method for manufacturing a display device according to claim 1, wherein in the step of forming the second carrier adjustment layer, the third material is deposited while the third deposition source is moved relative to the substrate to be processed, on which the light-emitting layer has already been formed, in the first direction.

3. The first direction is the direction in which subpixels of different display colors are aligned. The method for manufacturing a display device according to claim 1, wherein the second direction is the direction in which subpixels of the same display color are aligned.

Images