Semiconductor device having a conductive element formed above a dielectric layer and method for manufacturing the same

Abstract

To provide a semiconductor device comprising conductive elements, and to provide a method of fabrication of the device.SOLUTION: A semiconductor device 100 includes: a semiconductor substrate 110; a first dielectric layer 130 disposed over an upper surface of the semiconductor substrate; and a first current-carrying electrode 140 and a second current-carrying electrode 145 formed over the semiconductor substrate within a plurality of openings 132 and 134 formed in the first dielectric layer. A control electrode 150 is formed over the semiconductor substrate and disposed between the first and second current-carrying electrodes and over the first dielectric layer. A first conductive element 160 is formed over the first dielectric layer, adjacent to the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer 170 is disposed over the control electrode and over the first conductive element. A second conductive element 180 is disposed over the second dielectric layer and over the first conductive element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments of the subject matter described herein generally relate to semiconductor devices having conductive elements and methods for manufacturing such devices. [Background technology]

[0002] Semiconductor devices are applied to a wide variety of electronic components and systems. High-power, high-frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly well-suited to these RF power and power electronics applications due to its superior electronic and thermal properties. In particular, GaN's fast electron velocity and strong breakdown field strength make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. Field plates are used to reduce gate-drain feedback capacitance and increase the device breakdown voltage of high-frequency transistors. Therefore, semiconductors, especially GaN devices with field plates, are necessary. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 9847411 [Patent Document 2] U.S. Patent No. 10593619 [Brief explanation of the drawing]

[0004] [Figure 1] This is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) according to one embodiment. [Figure 2] This is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) according to one embodiment. [Figure 3]It is a process flow diagram for explaining a manufacturing method of a GaN heterojunction field effect transistor (HFET) device shown in FIGS. 1 and 2 according to an embodiment. [Figure 4] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 5] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 6A] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 6B] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 6C] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 6D] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 7] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 8] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 9A] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 9B] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 10A] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Figure 10B] It is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. [Modes for carrying out the invention]

[0005] When considered in conjunction with the drawings, a more complete understanding of the subject matter can be achieved by referring to the detailed descriptions and claims. Here, similar reference numbers refer to the same elements throughout the drawings.

[0006] The following detailed description is by nature illustrative and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. Where used herein, the terms “exemplary” and “example” mean “serving as an example, illustration, or representation.” Implementations described herein as illustrative or illustrative should not necessarily be construed as being preferable or advantageous to other implementations. Furthermore, it is not intended to be limited to the aforementioned technical fields, background art, or the explicit or implicit theories set forth in the following detailed description.

[0007] In one embodiment, the semiconductor device may include a semiconductor substrate having a top surface and a channel, a first dielectric layer disposed above the top surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed above the semiconductor substrate within a plurality of openings formed in the first dielectric layer. Here, the first current-carrying electrode and the second current-carrying electrode are electrically coupled to the channel. A control electrode may be formed above the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode, and above the first dielectric layer. Here, according to one embodiment, the control electrode may be electrically coupled to the channel. In one embodiment, a first conductive element may be formed between the control electrode and the second current-carrying electrode, adjacent to the control electrode, and above the first dielectric layer. According to one embodiment, a second dielectric layer may be disposed above the control electrode and above the first conductive element. In one embodiment, the second conductive element may be positioned above the second dielectric layer and above the first conductive element.

[0008] In another embodiment, the subject matter of the present invention may include a gallium nitride heterojunction field-effect transistor device. In one embodiment, the device may include a semiconductor substrate comprising a gallium nitride layer, a top surface, and a channel. According to one embodiment, the first dielectric layer may be located above the top surface of the semiconductor substrate. In one embodiment, an active region defined by isolation regions may be formed within the semiconductor substrate. Source electrodes and drain electrodes may be formed above the semiconductor substrate within a plurality of openings formed in the first dielectric layer in the active region. The source electrodes and drain electrodes may be electrically coupled to the channel. A gate electrode may be formed above the semiconductor substrate and may be located between the source electrodes and the drain electrodes, and above the first dielectric layer. Here, the gate electrode may be electrically coupled to the channel. According to one embodiment, a first field plate may be formed above the first dielectric layer, adjacent to the gate electrode between the gate electrode and the drain electrode, and a first metal-insulating semiconductor region may be formed below the first field plate. According to one embodiment, the second dielectric layer may be positioned above the gate electrode and above the first field plate. In one embodiment, the second field plate may be positioned above the second dielectric layer and above the first field plate, with a second metal-insulating semiconductor region formed below the second field plate between the gate electrode and the first field plate, and a third metal-insulating semiconductor region formed below the second field plate, adjacent to the first field plate and between the first field plate and the drain electrode.

[0009] In yet another embodiment, the subject matter of the present invention may include a method for manufacturing a gallium nitride heterojunction field-effect transistor device. Embodiments of this method may include forming a semiconductor substrate containing gallium nitride having a top surface and a channel, and forming a first dielectric layer above the top surface of the semiconductor substrate. Embodiments of the method may further include forming source electrodes and drain electrodes above the semiconductor substrate within a plurality of openings formed in the first dielectric layer, wherein the source electrodes and drain electrodes are electrically coupled to the channel. According to one embodiment, the method may include forming a gate electrode above the semiconductor substrate, between the source electrodes and the drain electrodes, and above the first dielectric layer. In one embodiment, the method may include forming a first field plate above the first dielectric layer adjacent to the gate electrode between the gate electrode and the drain electrode, forming a second dielectric layer above the control electrode and above the first field plate, and forming a second field plate above the second dielectric layer and above the first field plate.

[0010] Figure 1 is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) device 100 according to one embodiment. In one embodiment, the GaN HFET device 100 may include a semiconductor substrate 110, one or more isolation regions 120, an active region 125, a first dielectric layer 130, a source electrode (generally referred to as the "first current-carrying electrode") 140, a drain electrode (generally referred to as the "second current-carrying electrode") 145, a gate electrode 150 (generally referred to as the "control electrode"), a first field plate electrode (generally referred to as the "first conductive element") 160, a second dielectric layer 170, and a second field plate 180 (generally referred to as the "second conductive element"). As will be described in more detail below, the GaN HFET device 100 is substantially contained within an active region 125 defined by an isolation region 120, with the first dielectric layer 130, source electrode 140, drain electrode 145, gate electrode 150, first field plate 160, and second field plate layer 180 positioned above the semiconductor substrate 110.

[0011] In one embodiment, the semiconductor substrate 110 may include a host substrate 102, a buffer layer 104 positioned above the host substrate 102, a channel layer 106 positioned above the buffer layer 104, a barrier layer 108 positioned above the channel layer 106, and a cap layer 109 positioned above the channel layer 106. In one embodiment, the host substrate 102 may include silicon carbide (SiC). In other embodiments, the host substrate 102 may include other materials such as sapphire, silicon (Si), GaN, aluminum nitride (AlN), diamond, polySiC, silicon-on-insulator, gallium arsenide (GaAs), indium phosphide (InP), and other substantially insulating or highly resistive materials. A nucleation layer (not shown) may be formed on the upper surface 103 of the host substrate 102 between the buffer layer 104 and the host substrate 102. In one embodiment, the nucleation layer may include AlN. The buffer layer 104 may include several group III N semiconductor layers and is supported by the host substrate 102. Each of the semiconductor layers of the buffer layer 104 may include an epitaxially grown group III nitride epitaxial layer. The group III nitride epitaxial layers constituting the buffer layer 104 may be, for example, nitrogen (N) plane or gallium (Ga) plane material. In other embodiments, the semiconductor layers of the buffer layer 104 may not be epitaxially grown. In yet another embodiment, the semiconductor layers of the buffer layer 104 may include Si, GaAs, InP, or other suitable material.

[0012] In one embodiment, the buffer layer 104 may be epitaxially grown on the host substrate 102. The buffer layer 104 is made of Al X Ga 1-XIt may include at least one AlGaN mixed crystal layer having a composition represented by N. Here, X is the aluminum molar fraction and can take a value between 0 and 1. The total thickness of the buffer layer 104, including all its layers, may be between about 200 angstroms (1 angstrom is 0.1 nanometers) and about 100,000 angstroms (1 angstrom is 0.1 nanometers), although other thicknesses can be used. Limiting the X value to 0 results in pure GaN, and setting the value to 1 results in pure aluminum nitride (AlN). One embodiment may include a buffer layer 104 disposed above a host substrate and a nucleation layer (not shown). The buffer layer 104 may include additional Al X Ga 1-X N layers. The thickness of the additional Al X Ga 1-X N layer may be between about 200 angstroms (1 angstrom is 0.1 nanometers) and about 50,000 angstroms (1 angstrom is 0.1 nanometers), although other thicknesses can be used. In one embodiment, the additional Al X Ga 1-X N layer may be configured as GaN (X = 0) in which Al X Ga 1-X N is not intentionally doped (NID: not intentionally doped). The additional Al X Ga 1-X N layer can also be configured as one or more GaN layers that are intentionally doped with one or more dopants. The dopants may include iron (Fe), chromium (Cr), carbon (C), or other suitable dopants that substantially insulate or make the buffer layer 104 highly resistive. The dopant concentration may be between about 10 17 cm -3 and 10 19 cm -3 although other higher or lower concentrations can be used. The additional Al X Ga 1-X N layer may be configured with X = 0.01 to 0.10, where Al X Ga 1-XN is NID, or Al X Ga 1-X N is intentionally doped with Fe, Cr, C, or other suitable dopant species. In other embodiments (not shown), the additional layer is a series of alternating NID or doped Al X Ga 1-X It can be configured as a superlattice containing N layers (where the value of X takes a value between 0 and 1). In yet another embodiment, the buffer layer 104 is also In Y Ga 1-Y The material may include one or more indium gallium nitride (InGaN) layers having a composition denoted by N, where Y is the mole fraction of indium and can take a value between 0 and 1. The thickness of the InGaN layer may be between approximately 50 angstroms (1 angstrom = 0.1 nanometers) and approximately 2000 angstroms (1 angstrom = 0.1 nanometers), but other thicknesses may also be used.

[0013] In one embodiment, the channel layer 106 may be formed on the buffer layer 104. The channel layer 106 may include one or more group III N semiconductor layers and may be supported by the buffer layer 104. The channel layer 106 is an Al layer where X takes a value between 0 and 1. X Ga 1-X It may include an N layer. In one embodiment, the channel layer 106 is configured as GaN (X=0), but X may be other values ​​without departing from the subject matter of the present invention. The thickness of the channel layer 106 may be between about 50 angstroms (1 angstrom = 0.1 nanometers) and about 10,000 angstroms (1 angstrom = 0.1 nanometers), but other thicknesses may be used. The channel layer 106 may be NID, or it may contain Si, germanium (Ge), C, Fe, Cr, or other suitable dopants. The dopant concentration is about 10 15 cm -3 from 10 19 cm -3It may be between these, but other higher or lower concentrations may be used. In other embodiments, the channel layer 106 is NID or doped In Y Ga 1-Y It may contain N, where Y is the mole fraction of indium and can take values ​​between 0 and 1.

[0014] According to one embodiment, the barrier layer 108 may be formed on the channel layer 106. The barrier layer 108 may include one or more group III N semiconductor layers and be supported by the channel layer 106. In some embodiments, the barrier layer 108 has a larger band gap and larger spontaneous polarization than the channel layer 106, and when the barrier layer 108 is in direct contact with the channel layer 106, the channel 107 is generated in the form of a two-dimensional electron gas (2-DEG) within the channel layer 106 near the interface between the channel layer 106 and the barrier layer 108. Furthermore, due to strain between the barrier layer 108 and the channel layer 106, additional piezoelectric charges may be introduced into the 2-DEG and channel 107. The barrier layer 108 is made of at least one NID Al where X takes a value between 0 and 1. X Ga 1-X It may include an N layer. In some embodiments, X can take values ​​from 0.1 to 0.35, but other values ​​of X may be used. The thickness of the barrier layer 108 may be between about 50 angstroms (1 angstrom = 0.1 nanometers) and about 1000 angstroms (1 angstrom = 0.1 nanometers), but other thicknesses may be used. The barrier layer 108 may be NID, or it may contain Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration is about 10 16 cm -3 from 10 19 cm -3It may be between, but other higher or lower concentrations may be used. In one embodiment, an additional AlN interbarrier layer (not shown) according to one embodiment may be formed between the channel layer 106 and the barrier layer 108. The AlN interbarrier layer may increase the channel charge and improve the electron confinement of the resulting 2-DEG. In other embodiments, the barrier layer 108 is In Y Al 1-Y The barrier may include an indium aluminum nitride (InAlN) layer denoted by N, where Y is the mole fraction of indium and can take a value between approximately 0.1 and approximately 0.2, although other values ​​of Y may be used. For an InAlN barrier, the thickness of the barrier layer 108 may be between approximately 30 angstroms (1 angstrom = 0.1 nanometers) and approximately 2000 angstroms (1 angstrom = 0.1 nanometers), although other thicknesses may be used. When forming the barrier layer 108 using InAlN, the InAlN may be NID, or it may contain Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration is approximately 10 16 cm -3 from 10 19 cm -3 It may be between these two ranges, but other higher or lower concentrations may be used.

[0015] In the embodiment shown in Figure 1, the cap layer 109 may be formed on top of the barrier layer 108. The cap layer 109 provides a stable surface for the semiconductor substrate 110 and helps protect the surface of the semiconductor substrate 110 from chemical and environmental exposures associated with wafer processing. The cap layer 109 may contain one or more group III N semiconductor layers and is supported by the barrier layer 108. In one embodiment, the cap layer 109 is GaN. The thickness of the cap layer 109 may be between about 5 angstroms (1 angstrom = 0.1 nanometers) and about 100 angstroms (1 angstrom = 0.1 nanometers), but other thicknesses may also be used. The cap layer 109 may be NID, or it may contain Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration is about 10 16 cm -3 from 10 19 cm -3 While it may be between these, other higher or lower concentrations may be used. Without departing from the scope of the subject matter of the present invention, it should be understood that the selection of materials and layer arrangement for forming the semiconductor substrate 110 are exemplary. The inclusion of a host substrate 102, buffer layer 104, channel layer 106, barrier layer 108, and cap layer 109 in the semiconductor substrate 110 is exemplary, and it should be understood that various combinations of layer functions and operations can be made and may vary depending on the materials used in any particular embodiment. For example, in some embodiments (not shown), the cap layer 109 may be omitted. In other embodiments using an N-polar material (not shown), the channel layer 106 may be placed above the barrier layer 108 to create a 2-DEG and channel 107 directly beneath an optional cap 109 and gate electrode 150. Another embodiment may include a semiconductor layer formed from a material comprising GaAs, gallium oxide (Ga2O3), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), and aluminum indium arsenide (AlInAs) to form the semiconductor substrate 110.

[0016] According to one embodiment, one or more isolation regions 120 can be formed on the semiconductor substrate 110 to define an active region 125 on and along the upper surface 103 of the host substrate 102. The isolation regions 120 can be formed via an injection procedure configured to make the semiconductor substrate 110 highly resistive or semi-insulating in the high-resistivity region 122, while damaging the epitaxial and / or other semiconductor layers in the active region 125 without damaging the crystal structure to generate the high-resistivity region 122 of the semiconductor substrate 110. In another embodiment, the isolation regions 120 can be formed by removing one or more of the epitaxial and / or other semiconductor layers of the semiconductor substrate 110, making the remaining layers of the semiconductor substrate 110 semi-insulating and leaving an active region 125 "mesas" surrounded by highly resistive or semi-insulating isolation regions 120 (not shown). In yet another embodiment, the isolation region 120 may be formed by removing one or more epitaxial and / or other semiconductor layers of the semiconductor substrate 110, and then using ion implantation to damage the remaining layers of the semiconductor substrate 110 to further enhance their semi-insulating properties, leaving behind an active region 125 "mesa" surrounded by the implanted high-resistivity or semi-insulating isolation region 120 (not shown). In one embodiment, the first dielectric layer 130 may be formed on the active region 125 and the isolation region 120. In some embodiments, the first dielectric layer 130 may be formed from one or more suitable materials including silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), but other substantially insulating materials may be used. In one embodiment, the first dielectric layer 130 may have a thickness between 200 angstroms (1 angstrom = 0.1 nanometers) and 1000 angstroms (1 angstrom = 0.1 nanometers). In another embodiment, the first dielectric layer 130 may have a thickness between 50 angstroms (1 angstrom = 0.1 nanometers) and 10000 angstroms (1 angstrom = 0.1 nanometers), but other thicknesses may be used.

[0017] In one embodiment, the source electrode 140 and drain electrode 145 may be formed on and in contact with source and drain regions 142, 147 formed on the semiconductor substrate 110 in the active region 125. The source electrode 140 and drain electrode 145 may be formed inside source openings 132 and drain openings 134 formed in the first dielectric layer 130 and may be formed from one or more conductive layers. In some embodiments, ion implantation can be used to form ohmic contact to the channel 107 and generate the source and drain regions 142, 147. In one embodiment, the one or more conductive layers used to form the source and drain electrodes 140, 145 may include Ti, Au, Al, molybdenum (Mo), nickel (Ni), Si, Ge, platinum (Pt), or other suitable materials. In one embodiment, the source electrode 140 and drain electrode 145 may be formed on and in contact with the cap layer 109. In other embodiments (not shown), one or both of the source electrode 140 and the drain electrode 145 may be recessed through the cap layer 109 and partially extend through the barrier layer 108. In one embodiment, the source electrode 140 and the drain electrode 145 may be formed from a multilayer stack. In one embodiment, the multilayer stack used to form the source electrode 140 and the drain electrode 145 may include an adhesive layer and one or more layers, which, when annealed, allow for the formation of ohmic contact between the channel 107 and the source and drain regions 142, 147. In one embodiment, the adhesive layer may include titanium (Ti), tantalum (Ta), silicon (Si), or other suitable material. In one embodiment, the adhesive layer may have a work function of less than 4.5 electron volts.

[0018] In one embodiment, the gate electrode 150 can be formed on the semiconductor substrate 110 in the active region 125. According to one embodiment, the gate electrode 150 may include a vertical stem 152 and a first protruding region 154 coupled to the vertical stem 152, which is above the first dielectric layer 130 and toward the source electrode. In one embodiment, a second protruding region 156 according to one embodiment may be coupled to the vertical stem 152 and may be formed above the first dielectric layer 130 and toward the drain electrode 145. In one embodiment, the gate electrode 150 may be electrically coupled to the channel 107 through a cap layer 109 and a barrier layer 108. A change in potential applied to the gate electrode 150 may shift the pseudo-Fermi level of the barrier layer 108 relative to the pseudo-Fermi level of the channel layer 106, thereby modulating the electron concentration in the channel 107 in the semiconductor substrate 110 beneath the gate electrode 150. According to one embodiment, a Schottky material such as Ni, Pd, Pt, iridium (Ir), or copper (Cu) may be combined in a metal stack with one or more low-stress conductive materials such as Au, Al, Cu, polysilicon, or other suitable materials to form a gate electrode 150 for a low-loss Schottky gate electrode 150 electrically coupled to the channel 107. In one embodiment, the gate electrode 150 can be formed, and a vertical stem 152 is formed within a gate opening 136 in the first dielectric layer 130.

[0019] In one embodiment, the gate electrode 150 may be characterized by a gate length 153 within the gate opening 136 and first and second protruding region lengths 158 and 159 (where the first and second protruding regions 154 and 156 overlap the first dielectric layer 130). In one embodiment, the gate length 153 may be between about 0.1 micrometers and about 1 micrometer. In other embodiments, the gate length 153 may be between about 0.05 micrometers and about 2 micrometers, and other suitable dimensions may be adopted. In one embodiment, the first protruding region length 158 may be between about 0.1 micrometers and about 0.5 micrometers. In other embodiments, the first protruding region length 158 may be between about 0.05 micrometers and about 2 micrometers, and other suitable dimensions may be adopted. In one embodiment, the second protruding region length 159 may be between about 0.1 micrometers and about 0.5 micrometers. In other embodiments, the length of the second protruding region 159 may be between about 0.1 micrometers and about 2 micrometers, and other suitable lengths may also be adopted.

[0020] Many other embodiments can be realized without departing from the subject matter of the present invention. An exemplary embodiment in Figure 1 shows a T-shaped gate electrode 150 having a vertical stem 152 and first and second protruding regions 154 and 156 positioned above the first dielectric layer 130. In other embodiments, the gate electrode 150 may be square in shape and not have protruding regions (e.g., 154 and 156) above the first dielectric layer 130. In other embodiments (not shown), the gate electrode 150 may be recessed through a cap layer 109 and partially extend into a barrier layer 108, thereby strengthening the electrical coupling of the gate electrode 150 to the channel 107 via the barrier layer 108. In other embodiments (not shown), the cap layer 109 may be omitted, and the gate electrode 150 may be in direct contact with the barrier layer (not shown). In yet another embodiment, the gate electrode 150 may be positioned above a gate dielectric formed between the gate electrode 150 and a semiconductor substrate 110 to form a metal-insulating semiconductor field-effect transistor (MISFET) device (not shown).

[0021] In one embodiment, the first field plate 160 may be formed adjacent to the gate electrode 150 and above the first dielectric layer, between the gate electrode 150 and the drain electrode 145. According to one embodiment, the first field plate 160 may be characterized by a first field plate length 163 and a distance 165 from the gate electrode 150 to the gate. In one embodiment, the first field plate length 163 may be between about 0.2 micrometers and about 0.8 micrometers. In another embodiment, the first field plate length 163 may be between about 0.1 micrometers and about 2 micrometers, and other suitable lengths may be adopted. The distance 165 from the first field plate to the gate may be between about 0.2 micrometers and about 1 micrometer. In another embodiment, the distance 165 from the first field plate to the gate may be between about 0.1 micrometers and about 2 micrometers, and other suitable lengths may be adopted. The first metal-insulating semiconductor region 167 can be generated by a first field plate 160, a first dielectric layer 130 beneath it, and a semiconductor substrate 110. In one embodiment, the first metal-insulating semiconductor region 167 functions as part of an active device and has a first threshold voltage that depends on the thickness of the dielectric layer 130 and the amount of charge in the channel 107. In one embodiment, the first threshold voltage may be between -5 volts and -15 V. In other embodiments, the threshold voltage may be between -4 volts and -30 V. In one embodiment, a second field plate 180 reduces the electric field between the gate electrode 150 and the drain electrode 145.

[0022] In one embodiment, the second dielectric layer 170 may be located above the first dielectric layer 130, the source and drain electrodes 140 and 145, the gate electrode 150, and the first field plate 160. In one embodiment, the second dielectric layer 170 may comprise one or more SiN, SiO2, AlN, HfO2, Al2O3, spin-on glass, or other suitable insulating materials. In one embodiment, the third second layer 170 may have a thickness between about 500 angstroms (1 angstrom = 0.1 nanometers) and about 5000 angstroms (1 angstrom = 0.1 nanometers). In other embodiments, the second dielectric layer 170 may have a thickness between about 100 angstroms (1 angstrom = 0.1 nanometers) and about 20000 angstroms (1 angstrom = 0.1 nanometers).

[0023] In one embodiment, the second field plate 180 may be positioned above the second dielectric layer 160 and above the gate electrode 150 and the first field plate 160. In one embodiment, the second field plate may be formed on the side of the gate electrode 150 facing the drain electrode 145. In one embodiment, the second field plate 180 may be coupled to the source electrode 140. In other embodiments (not shown), the second field plate 180 may be positioned above the second dielectric layer 170 and above the gate electrode 150 and the first field plate 160, and may surround the gate electrode 150 and the first field plate 160 so as to be in contact with the side of the gate electrode 150 facing the source electrode 140 and the drain electrode 145, and may extend to and be in contact with the source electrode 140.

[0024] In one embodiment, the second field plate generates a second metal-insulating semiconductor region 187 and a third metal-insulating semiconductor region 189, comprising the second field plate, a second dielectric layer 170, a first dielectric layer 130, and a semiconductor substrate 110. The second and third metal-insulating semiconductor regions 187 and 189 function as parts of the active device and have second and third threshold voltages, depending on the thickness of the dielectric layers 130 and the second dielectric layer 170, the amount of charge in the channel 107, and any interfacial charges that may exist between the dielectric layers themselves and between the first dielectric layer 130 and the semiconductor substrate 110. In one embodiment, the second and third threshold voltages may be between -20 volts and -80 volts. In other embodiments, the threshold voltages may be between -10 volts and -200 volts. In one embodiment, the second field plate 180 reduces the electric field and coupling between the gate electrode 150 and the drain electrode 145, as well as the associated gate-drain capacitance. In one embodiment, the field plate drain extension 182 may extend toward the drain electrode 145 from a portion of the second field plate adjacent to the first field plate 160 facing the drain electrode 145, by the length of the second field plate drain extension 184. In another embodiment, the lower surface 183 of the second field plate drain extension 182 may contact the first dielectric layer 130 around the gate electrode 150 where the second protruding region 156 contacts the first dielectric layer 130. In yet another embodiment, the lower surface 183 of the second field plate drain extension 182 may be above the second protruding region 156 of the gate electrode 150 where the second protruding region 156 contacts the first dielectric layer 130. In one embodiment, the length of the second field plate drain extension 184 characterizes the overlap of the second field plate 180 with respect to the second dielectric layer 170 and the first dielectric layer 130. In one embodiment, the extension length 184 of the second field plate drain may be between about 0.2 micrometers and 2 micrometers. In another embodiment, the extension length 184 of the second field plate drain may be between about 0.1 micrometers and 10 micrometers.Without departing from the subject matter of the present invention, the second field plate drain extension length 184 may have other longer or shorter lengths. In one embodiment, the second field plate 180 may be coupled to the same potential as the source electrode 140 or to the ground potential. In another embodiment, the second field plate 180 may be coupled to the gate electrode 150 (not shown). In yet another embodiment, the second field plate 180 may be coupled to any potential (not shown). In one embodiment, source and drain metallizations 185, 186 to the source and drain electrodes may be formed using the same conductive layer as the second field plate 180.

[0025] In one embodiment, the GaN HFET device 100 may be configured as transistor fingers, where the source electrode 140, drain electrode 145, gate electrode 150, first field plate electrode 160, and second field plate electrode 180 may be configured as elongated elements forming a gate finger (not shown). The GaN transistor device 100 may be partially defined by an isolation region 130 encompassing the gate width of the gate finger (i.e., the dimension along the axis perpendicular to the plane of the GaN transistor device 100 in Figure 1 is sufficiently larger than the gate length 153 of the gate electrode 150 (i.e., the dimension along the axis perpendicular to the gate width)). In some embodiments, the gate width may be between about 50 micrometers and about 500 microns. In other embodiments, the gate width may be between about 5 micrometers and about 1000 microns. In some embodiments, it is desirable to minimize signal attenuation along the gate finger in order to maintain a constant potential along the first field plate 160 and the second field plate 180 by electrically coupling the first field plate 160 and the second field plate 180 to the potential at one or more points. In one embodiment The first field plate 160 and the second field plate 180 can be electrically coupled to the same potential as the source electrode 140. The first field plate 160 can be connected to the source electrode 140 using a connection formed from an extension of the conductive material used to form the first field plate 160 (from one or more ends of the device finger in the isolation region 125 to the source electrode 140) (not shown). In some embodiments, conductive regions "straps" that electrically connect the second field plate 180 to the source electrode 140 can be periodically formed along the device finger using the same conductive layer used to form the second field plate 180. In one embodiment, these conductive straps may be 0.1 to 5 micrometers wide and spaced apart along the device finger.In one embodiment, the spacing between straps according to one embodiment may be between about 25 micrometers and about 100 micrometers, but other shorter or longer spacings between straps may be used. The spacing between straps according to one embodiment may be between about 5 micrometers and about 200 micrometers, but other shorter or longer spacings between straps may be used. In other embodiments (not shown), the connection of the second field plate 180 to the source electrode 140 may be achieved by a connection portion from the second field plate 180 to the source electrode 140 using the same metal used to form the second field plate 180, or by using another metal layer (e.g., an interconnection layer) at the ends of the device fingers of the isolation region 125. In yet another embodiment, the connection between the source electrode 140 and the second field plate 180 can be achieved by forming the second field plate 180 as a solid continuous connection portion to the source electrode 140 (not shown).

[0026] Figure 2 is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) 200 according to one embodiment included in the subject matter of the present invention. In one embodiment, the GaN HFET device 200 may include a semiconductor substrate 110, an isolation region 120, an active region 125, a first dielectric layer 130, a source electrode 140, a drain electrode 145, a gate electrode 150, a first field plate 160, a second dielectric layer 170, and a second field plate 280. As described in relation to the GaN HFET device 100 of Figure 1, the GaN HFET device 200 may be substantially contained within the active region 125 defined by the isolation region 120, with the first dielectric layer 130, the source electrode 140, the drain electrode 145, the gate electrode 150, the first field plate 160, the second dielectric layer 170, and the second field plate 180 positioned above the semiconductor substrate 110. In one embodiment, a field plate opening 272 may be formed in the second dielectric layer 170 above the first field plate 160. According to one embodiment, the field plate opening 272 may allow the second field plate 280 to contact the first field plate. In some embodiments, the field plate opening 272 is continuous along the entire gate width of the GaN HFET device 200. In other embodiments, the field plate opening 272 is formed in a plurality of separate regions along the unit gate width (not shown). In these embodiments, the constant interconnection distance may be a fixed value between about 5 micrometers and about 500 micrometers, but other shorter or longer values ​​for the interconnection distance may be used.

[0027] The flowchart 300 in Figure 3 illustrates an embodiment of a method for manufacturing semiconductor devices (e.g., GaN HFET devices 100, 200, Figures 1 and 2). Figure 3 shows a cross-sectional side view of a series of manufacturing steps for manufacturing the semiconductor devices of Figures 1 and 2 according to an exemplary embodiment. See also Figures 3, 4, 5, 6A, 6B, 6C, 6D, 7, 8, 9A, 9B, 10A, and 10B.

[0028] In block 302 of Figure 3, as shown in step 400 of Figure 4, a method according to one embodiment may include forming a semiconductor substrate 110. In one embodiment, step 400 may include providing a host substrate 102 and forming a plurality of semiconductor layers in contact with or on the host substrate 102. In one embodiment, the host substrate 102 may include SiC, or other materials such as sapphire, Si, GaN, AlN, diamond, polySiC, silicon-on-insulator, GaAs, InP, and other substantially insulating or highly resistive materials. Forming multiple semiconductor layers may include forming a nucleation layer (not shown) in contact with or above the upper surface 103 of the host substrate 102, forming a buffer layer 104 in contact with or above the nucleation layer, forming a channel layer 106 in contact with or above the buffer layer 104, forming a barrier layer 108 in contact with or above the channel layer 106, and forming a cap layer 109 in contact with or above the barrier layer 108. As described above, the buffer layer 104, channel layer 106, barrier layer 108, and cap layer 109 in the embodiment may include materials selected from AlN, GaN, AlGaN, InAlN, InGaN, or other suitable materials. The semiconductor layers 104, 106, 108, and 109 can be grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), or a combination thereof, but other suitable techniques may be used instead. A semiconductor substrate 110 is obtained.

[0029] In block 304 of Figure 3, as shown in step 500 of Figure 5, a method according to one embodiment may include forming a first dielectric layer 130 in contact with or above the semiconductor substrate 110. As described above, in one embodiment, the first dielectric layer 130 may include a material selected from SiN, Al2O3, SiO2, AlN, and HfO2. The first dielectric layer 130 may be formed using one or more of the following methods: low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), plasma-excited chemical vapor deposition (PECVD), MOCVD, MBE, inductively coupled plasma (ICP) growth, electron cyclotron resonance (ECR) growth, or other suitable techniques. In other embodiments, the first dielectric layer 130 may be formed immediately after the growth in the same chamber or deposition system (e.g., MOCVD or MBE) used to grow the semiconductor layer on the semiconductor substrate 110. Structure 501 is obtained.

[0030] In block 306 of Figure 3, as shown in steps 600, 602, 604, and 606 of Figures 6A, 6B, 6C, and 6D, a method according to one embodiment may include forming source and drain regions 142 and 147 in the first dielectric layer 130 and forming source and drain electrodes 140 and 145. Referring again to Figure 6A and step 600, a method according to one embodiment may include patterning an injection mask 610 and injecting dopant species 620 into the semiconductor substrate through an opening 615 of the injection mask 610 to form injection regions 630 in the semiconductor substrate 110. Once the injection mask layer is patterned, dopant species can be injected into the semiconductor substrate through the injection mask layer. In one embodiment, Si, Ge, O, or other suitable n-type dopants can be injected into the semiconductor substrate through the injection mask. A structure 601 is obtained.

[0031] Referring again to Figure 6A and step 602, with reference to Figure 6B, a method according to one embodiment may include activating the dopant species to complete the formation of source and drain regions 142 and 147 in the semiconductor substrate 110, and then removing the injection mask 610. According to one embodiment, the dopant species is activated by annealing the semiconductor substrate 110 using activation annealing at a temperature of about 900 to about 1500 degrees. Structure 603 is obtained.

[0032] In one embodiment, referring to Figure 6C, source and drain openings 132, 134 may be formed to supply a resist layer 640 to a first dielectric layer 130, and the resist layer 640 may be patterned to form a resist opening 650. In one embodiment, source and drain electrodes 140 and 145 may be created by etching the first dielectric layer 130 in the region exposed by the resist opening 650 to form the source and drain openings 132 and 134. Etching of the first dielectric layer 130 (e.g., SiN) may include etching using one or more dry and / or wet etching techniques, such as reactive ion etching (RIE), ICP etching, ECR etching, and wet chemical etching according to one embodiment. According to one embodiment, a suitable wet etching chemistry may include hydrofluoric acid (HF), buffered HF, buffered oxide etching (BOE), phosphoric acid (H3PO4), or other suitable wet etching agents. These dry etching techniques, according to one embodiment, can remove SiN using one or more of the following: sulfur hexafluoride (SF6), dicarbon hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other suitable chemicals. In one embodiment, the etchant used to etch the first dielectric 130 can selectively etch a portion of the first dielectric layer 130 and then stop at an etching stop layer (not shown) (e.g., Al2O3 or AlN). In one embodiment, etching of the etching stop layer (e.g., an etching stop layer of Al2O3 or AlN) may include wet and / or dry etching techniques. In other embodiments, dry etching of the etching stop layer (e.g., an etching stop of AlN or Al2O3) may include dry etching using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a chlorine-based chemistry such as Cl2, boron trichloride (BCl3), or other suitable dry etching chemistry. A structure 605 is obtained.

[0033] Referring again to block 306 in Figure 3 and step 604 in Figure 6C, a method according to one embodiment may include forming and patterning source and drain electrodes 140 and 145 at source and drain openings 132 and 134. In one embodiment, the method may include forming a metal layer 660 at source and drain openings 132 and 134 formed by etching the first dielectric layer 130 against the resist layer 640 and exposed at resist openings 650 formed in the resist layer 640. In one embodiment, the metal layer 660 may include one or more metal layers containing Ti, Ta, Al, Mo, Au, Ni, Si, Ge, platinum (Pt), tungsten (W), and / or other refractory metals, which, when annealed, form ohmic contact with the source and drain regions 142, 147. In one embodiment, the metal layer 660 may include a stack formed on a substrate containing Ti, Al, and Au. In one embodiment, to form the metal layer 660, the Ti layer may be positioned above the semiconductor substrate 110 at the opening 650, the Al layer may be positioned above the Ti layer, a barrier layer formed from Mo or other suitable barrier metal (such as Ni or tungsten) may be positioned above the Al layer, and the Au layer may be positioned above the barrier layer. In one embodiment, the metal layer 660 may be deposited by vapor deposition. In other embodiments, the metal layer 660 may be deposited by sputtering, PVD, or other suitable deposition techniques.In one embodiment, the thickness of the Ti layer may be between approximately 100 angstroms (1 angstrom = 0.1 nanometers) and 200 angstroms (1 angstrom = 0.1 nanometers), the thickness of the Al layer may be between approximately 600 angstroms (1 angstrom = 0.1 nanometers) and 1500 angstroms (1 angstrom = 0.1 nanometers), the thickness of the Mo layer may be between approximately 200 angstroms (1 angstrom = 0.1 nanometers) and 700 angstroms (1 angstrom = 0.1 nanometers), and the thickness of the Au layer may be between approximately 300 angstroms (1 angstrom = 0.1 nanometers) and 1000 angstroms (1 angstrom = 0.1 nanometers). In other embodiments, other metals may be substituted (for example, Ni or Pt may be added instead of Mo, or Ta may be added instead of Ti), and other thicknesses may be used. In one embodiment, the resist layer 640 may be configured with a lift-off profile, and the openings of the resist layer 640 have a retrograde profile, allowing for "lift-off" when the undeposited metal in the resist openings 650 dissolves in the solvent. In other embodiments (not shown), the source and drain electrodes 140 and 145 may be patterned by dry etching. A structure 605 is obtained.

[0034] Referring again to block 306 in Figure 3, as shown in step 606 of Figure 6D, a method according to one embodiment may include annealing the source and drain electrodes 140 and 145 at the source and drain openings 132 and 134. In one embodiment, annealing the source and drain electrodes 140 and 145 may include an annealing step used to alloy the metal layer 660 in Figure 6C, which results in ohmic contact to the source and drain regions 142 and 147 formed on the semiconductor substrate 110 on which the source and drain electrodes 140 and 145 are formed. In one embodiment, the annealing step can be achieved by rapid thermal annealing. In one embodiment, the metal layer 660 in Figure 6C remaining at the source and drain openings 132 and 134 in Figure 6C may be alloyed over a period of about 15 to 60 seconds at a temperature between about 500 and 700 degrees Celsius. In other embodiments, the metal layer 660 in Figure 6C may be annealed for about 10 to 600 seconds at a temperature between about 400 to about 800 degrees Celsius, although other higher or lower temperatures and other longer or shorter times may be used. In one embodiment, the metal stack used to form the metal layer 660 (e.g., Ti, Al, Mo, and Au) is mixed to form source and drain electrodes 140 and 145. A structure 607 is obtained.

[0035] Without departing from the scope of the subject matter of the present invention, the drain and source electrodes 140 and 145 may be formed using ohmic contact with an alloy (not shown). In these embodiments, the source and drain regions may not be formed. Rather, ohmic contact with the semiconductor substrate 110 is achieved by high-temperature annealing of an ohmic metal (for example, Ti, Al, Mo, and Au can be used to form a metal stack 660).

[0036] Refer again to block 308 and step 700 in Figure 7, in one embodiment the method may include creating an isolation region 120. Forming the isolation region 120 may include supplying and patterning a resist mask 710 to a first dielectric layer 130, and then defining an opening 720 in the resist mask 710. Using ion implantation, dopant species 725 (e.g., one or more of oxygen, nitrogen, boron, and helium) can be implanted into the semiconductor substrate 110 to create a high resistivity region 122. In one embodiment the energy and amount of implantation may be configured to cause a sufficient amount of damage to the crystalline structure of the semiconductor substrate 110 so that the semiconductor substrate becomes substantially resistive or semi-insulating within the high resistivity region 122 of the isolation region 120. In other embodiments (not shown), forming the isolation region 120 may include first etching some or all of the semiconductor layers in the semiconductor substrate 110, and then performing ion implantation to increase the resistivity of the remaining semiconductor layers and / or the host substrate 102. A structure 701 is obtained.

[0037] Next, with reference to blocks 310 and 312 in Figure 3 and step 800 in Figure 8, in one embodiment, forming the gate electrodes and first field plates of the transistor devices 100 and 200 in Figures 1 and 2 may include forming a gate opening 136 in the first dielectric layer 130. In one embodiment, forming the gate electrodes 150 and first field plates 160 may include depositing and patterning a conductive material to form the gate electrodes 150 and first field plates 160. In the embodiments shown, the gate electrodes 150 and first field plates 160 may be manufactured using the same conductive (e.g., metal) layer. In other embodiments (not shown), separate metal layers and processing steps may be used to form the gate electrodes 150 and first field plates 160.

[0038] In one embodiment, a photoresist or electron beam resist (not shown) can be patterned to create openings in the resist in the same manner as described above with respect to Figure 6C and step 604. Using the openings created in the resist layer, according to one embodiment, the first dielectric layer 130 may be etched to form a gate opening 136, thereby exposing a portion of the upper substrate surface 112. In one embodiment, one or more layers of gate metal can then be deposited on the openings in the resist to form a gate electrode 150 above the upper substrate surface 112 of the substrate 110 and a first field plate 160 above the first dielectric layer 130. The deposition of the gate metal for forming the gate electrode 150 and the first field plate 160 may involve deposition of a multilayer stack comprising one or more metal layers and / or other suitable materials. The first layer in the multilayer stack used to form the gate electrode 150 and the first field plate 160 may include Ti, Ni, Pt, Cu, palladium (Pd), Cr, W, iridium (Ir), polysilicon, or other suitable materials. The thickness of the first layer may be between about 30 angstroms (1 angstrom = 0.1 nanometers) and about 2000 angstroms (1 angstrom = 0.1 nanometers), but other thickness values ​​may be used. According to one embodiment, one or more layers acting as conductive layers can be deposited on the first layer to form the gate electrode 150 and the first field plate 160. The conductive layers may include Au, Ag, Al, Cu, Ti, or other substantially conductive materials. The thickness of the conductive layers may be between about 50 angstroms (1 angstrom = 0.1 nanometers) and about 20,000 angstroms (1 angstrom = 0.1 nanometers), but other thickness values ​​may be used. Optionally, one or more barrier metal layers may be placed between the first layer and the conductive layer, wherein the barrier metal layer may include a material such as Ni, Pt, Cu, Pd, Cr, W, Ir, or other substantially refractive material, which functions as a barrier between the portion of the first layer in contact with the substrate 110 and the first dielectric layer 130 and the conductive layer.The barrier layer thickness can range from approximately 50 angstroms (1 angstrom = 0.1 nanometers) to approximately 10,000 angstroms (1 angstrom = 0.1 nanometers), but other thickness values ​​may be used. In one embodiment, the various layers used to form the gate electrode 150 and the first field plate 160 can be deposited by vapor deposition, sputtering, PVD, ALD, or other suitable deposition techniques.

[0039] It should be understood that other methods can be used to form the gate electrode 150 and the first field plate 160 without departing from the subject matter of the present invention. In methods for manufacturing these other embodiments (not shown), the gate electrode 150 and the first field plate 160 may be formed by patterning a first resist layer to form an opening, etching a first dielectric layer 130 to create an opening that exposes the upper substrate surface 212 of the substrate 110, and then removing the first resist layer. In this embodiment, forming the gate electrode 150 and the first field plate 160 includes patterning an opening in a second resist layer aligned with the opening created in the first dielectric layer 130 to expose the upper substrate surface 112. The opening in the second resist layer may be smaller or larger than the opening in the first dielectric layer 122. In other embodiments, the gate metal may be located above the gate dielectric, such as SiO2, HfO2, Al2O3, or a similar material (not shown). According to one embodiment, the gate dielectric may be deposited on or above the upper substrate surface 112. In yet another embodiment, the gate electrode 150 and the first field plate 160 can be formed using a gate metal deposited above the substrate 110, then patterned with a photoresist, and then etched with the gate metal. In any selected embodiment or method for forming the gate electrode 150 and the first field plate 160, the gate metal may then be deposited using the method described in relation to the formation of the gate electrode 150 shown in Figure 8.

[0040] Referring here to block 314 in Figure 3, Figures 9A and 9B, and steps 900 and 902, a method for fabricating the transistor devices 100 and 200 of Figures 1 and 2 may, according to one embodiment, further include depositing and patterning a second dielectric layer 170 onto the source and drain electrodes 140, 145, gate electrode 150, first field plate layer, and first dielectric layer 130 of the structure 801 of Figure 8. In one embodiment, the second dielectric layer 170 may include one of SiN, Al2O3, SiO2, HfO2, ITO, diamond, polydiamond, AlN, BN, SiC, or a combination of these or other insulating materials. The total thickness of the multiple layers used to form the second dielectric layer 170 may be between about 100 angstroms (1 angstrom = 0.1 nanometers) and about 10,000 angstroms (1 angstrom = 0.1 nanometers), although other thickness values ​​may be used. The second dielectric layer 170 can be deposited using LPCVD, PECVD, sputtering, PVD, ALD, Cat-CVD, HWCVD, ECRCVD, CVD, ICP-CVD, or a combination of these or other suitable dielectric deposition techniques.

[0041] In one embodiment, an additional process step for etching the second dielectric layer 170 is similar to that used to etch the first dielectric layer 130, as described in relation to step 604 in Figure 6C, and may be used to create openings 172, 174, and 178. In one embodiment, the second dielectric layer 170 may be patterned by placing a resist layer (not shown) relative to the second dielectric layer 170 and patterning the resist layer to form openings to portions of the second dielectric layer 170 above the source and drain electrodes 140, 145. The second dielectric layer 170 may then be etched through the openings in the resist layer using a technique similar to that used to etch the first dielectric layer 130, as described in relation to step 604 in Figure 6C. Thus, openings 172 and 174 are created in structure 901 in Figure 9A, and openings 172, 174, and 178 are formed in structure 903 in Figure 9B. Structures 901 and 903 are obtained.

[0042] Herein, with reference to block 316 in Figure 3, Figures 10A and 10B, and steps 1000 and 1002, according to one embodiment, a method for manufacturing the transistor structure of device 200 of Figure 2 on the second dielectric layer 170 and source and drain electrodes 140 and 145 in structures 901 and 903 of Figure 9 may further include depositing and patterning second field plates 180 and 280 and source and drain metallizations 185 and 186. In one embodiment, the formation and patterning of the second field plates 180, 280 and source and drain metallizations 185, 186 can be achieved by coating and patterning a resist layer (not shown), depositing the second field plates 180, source and drain metallizations 185, 186, and removing the metal and resist layer covering the second field plates 180, 280, source and drain metallizations 185, 186 and other structures (e.g., interconnects, not shown) in a lift-off configuration. Similar to step 700 in Figure 7, in one embodiment, the second field plate metal is formed by depositing one or more adhesive and conductive metal layers into openings (not shown) patterned in the resist layer coated on the partially formed device as described above. In one embodiment, the adhesive layer may be deposited first, followed by the conductive layer. In one embodiment, the adhesive and conductive layers may be deposited in the same deposition step. The adhesive layer may contain one of Ti, Ni, Cr, or other suitable adhesive layer materials. The thickness of the adhesive layer may range from approximately 50 angstroms (1 angstrom = 0.1 nanometers) to approximately 2,000 angstroms (1 angstrom = 0.1 nanometers), but other thickness values ​​may be used. The conductive layer may contain Cu, Au, Al, or Ag, but other suitable materials may be used. The thickness of the conductive layer may range from approximately 200 angstroms (1 angstrom = 0.1 nanometers) to approximately 40,000 angstroms (1 angstrom = 0.1 nanometers), but other thickness values ​​may be used.In one embodiment, the adhesive and conductive layer used to form the second field plate metal 280 may be deposited on top of the second dielectric layer 170 and the first field plate 160, and may be in contact with them. In one embodiment, the adhesive and conductive layers may be formed by sputtering, vapor deposition, or electroplating. In one embodiment, after coating and patterning the resist layer and depositing the second field plates 180, 280, the resist layer and any metal not included in the portion of the second field plate metal that is deposited on top of the resist layer and in contact with the second dielectric layer 170 and the first field plate 160 are removed using a solvent similar to the solvent described in step 604 of Figure 6C. In other embodiments, the second field plate metal may be formed by depositing the adhesive and conductive layer (which is later patterned by appropriate dry or wet chemical etching techniques). The completed transistor devices 100, 200 are obtained.

[0043] While at least one exemplary embodiment is presented in the above detailed description, it should be understood that a vast number of variations exist. It should also be understood that the exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the subject matter of the claims. Rather, the above detailed description will provide a useful roadmap for those skilled in the art to implement the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including known and foreseeable equivalents at the time of filing this patent application.

[0044] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may be used herein for reference only and are not intended to be limiting, and terms such as “first,” “second,” and other such numerical terms referring to structures do not mean arrangement or order unless explicitly indicated by the context.

[0045] In the foregoing, elements, nodes, or features are described as either “connected” or “coupled.” As used herein, unless otherwise specified, “connected” means that one element is directly connected to (or communicates directly with) another element, and does not necessarily mean mechanically connected. Similarly, unless otherwise specified, “coupled” means that one element is directly or indirectly connected to (or communicates directly or indirectly with) another element, and does not necessarily mean mechanically connected. Therefore, while the schematic diagrams shown in the figures represent one exemplary arrangement of multiple elements, additional intervening elements, devices, features, or components may be present in embodiments of the subject matter described.

Claims

1. A semiconductor substrate including the top surface and channel, A first dielectric layer disposed above the upper surface of the semiconductor substrate, Within a plurality of openings formed in the first dielectric layer, a first current-carrying electrode and a second current-carrying electrode are formed above the semiconductor substrate and are electrically coupled to the channel, A control electrode formed above the semiconductor substrate and positioned between the first current-carrying electrode and the second current-carrying electrode, and above the first dielectric layer, wherein the control electrode is electrically coupled to the channel, Between the control electrode and the second current-carrying electrode, a first conductive element is formed adjacent to the control electrode and above the first dielectric layer, A second dielectric layer is positioned above the control electrode and above the first conductive element, A second conductive element, Equipped with, The second conductive element is positioned in part above the second dielectric layer and above the first conductive element. A semiconductor device in which a portion of the second conductive element located between the control electrode and the first conductive element is below the upper surface of the first conductive element.

2. The first conductive element is electrically coupled to the second conductive element. The semiconductor device according to claim 1.

3. The first current-carrying electrode is configured as a source electrode, the second current-carrying electrode is configured as a drain electrode, and the control electrode is configured as a gate electrode. The semiconductor device according to claim 1.

4. The first metal-insulating semiconductor region is formed below the first conductive element. The semiconductor device according to claim 3.

5. The second metal-insulating semiconductor region is formed below the second conductive element and between the gate electrode and the first conductive element. The semiconductor device according to claim 4.

6. A third metal-insulating semiconductor region is formed below the second conductive element and between the drain electrode and the first conductive element. The semiconductor device according to claim 5.

7. The first conductive element is adjacent to the control electrode while being electrically insulated from the control electrode. The semiconductor device according to claim 1.

8. The first conductive element is configured as a first field plate, and the second conductive element is configured as a second field plate. The semiconductor device according to claim 6.

9. The gate electrode and the first field plate are formed from the same material. The semiconductor device according to claim 8.

10. The first field plate and the second field plate are at the same potential as the source electrode. The semiconductor device according to claim 8.

11. The horizontal distance between the gate electrode and the first field plate is between 0.2 micrometers and 1 micrometer. The semiconductor device according to claim 8.

12. The semiconductor substrate includes a group III nitride material. The semiconductor device according to claim 1.

13. A semiconductor substrate including a gallium nitride layer, a top surface and a channel, A first dielectric layer disposed above the upper surface of the semiconductor substrate, An active region defined by an isolated region formed within the semiconductor substrate, Within the active region, in a plurality of openings formed in the first dielectric layer, a source electrode and a drain electrode formed above the semiconductor substrate, which are electrically coupled to the channel, A gate electrode formed above the semiconductor substrate and positioned between the source electrode and the drain electrode, and above the first dielectric layer, which is electrically coupled to the channel, A first field plate is formed between the gate electrode and the drain electrode, adjacent to the gate electrode, and above the first dielectric layer, wherein the first metal-insulating semiconductor region is formed below the first field plate. A second dielectric layer is disposed above the gate electrode and above the first field plate, A second field plate, the second field plate is partially positioned above the second dielectric layer and above the first field plate, a portion of the second field plate between the gate electrode and the first field plate is below the upper surface of the first field plate, a second metal-insulating semiconductor region is formed below the second field plate between the gate electrode and the first field plate, and a third metal-insulating semiconductor region is formed below the second field plate, adjacent to the first field plate and between the first field plate and the drain electrode, A gallium nitride heterojunction field-effect transistor device comprising the above features.

14. Forming a semiconductor substrate including a gallium nitride layer, a top surface, and a channel, A first dielectric layer is formed above the upper surface of the semiconductor substrate, The method involves forming source electrodes and drain electrodes above the semiconductor substrate within a plurality of openings formed in the first dielectric layer, wherein the source electrodes and drain electrodes are electrically coupled to the channel. A gate electrode is formed above the semiconductor substrate, between the source electrode and the drain electrode, and above the first dielectric layer. A first field plate is formed between the gate electrode and the drain electrode, adjacent to the gate electrode, and above the first dielectric layer. A second dielectric layer is formed above the gate electrode and above the first field plate. To form a second field plate, Includes, The second field plate is formed in part above the second dielectric layer and above the first field plate. A method for manufacturing a gallium nitride heterojunction field-effect transistor device, wherein a portion of the second field plate located between the gate electrode and the first field plate is below the upper surface of the first field plate.

15. The further includes forming an active region by defining an isolated region within the semiconductor substrate. The method according to claim 14.

16. The formation of the gate electrode and the formation of the first field plate are performed using the same conductive layer. The method according to claim 14.

17. Forming the source electrode and drain electrode includes forming ohmic contact regions that define the source region and drain region in the semiconductor substrate. The method according to claim 14.

18. Further comprising forming a plurality of openings in the second dielectric layer above the source electrode and the drain electrode, The method according to claim 14.

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