Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device which enables formation of a bonding pad in a suitable manner, and a method for manufacturing the same.SOLUTION: A semiconductor device includes: a first substrate; a first insulation film provided on the first substrate; a first pad provided in the first insulation film; a second insulation film provided on the first insulation film; and a second pad which is provided in the second insulation film, is arranged on the first pad and is brought into contact with the first pad. The device further includes: a third pad which is provided in the second insulation film and is arranged above the second pad; a third insulation film provided on the second insulation film; and a fourth pad which is provided in the third insulation film, is arranged on the third pad and is brought into contact with the third pad. The shape of the third or fourth pad is different from the shape of the first or second pad.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] When manufacturing a semiconductor device by bonding three or more substrates via an interlayer insulating film, a problem arises as to how to form bonding pads in the interlayer insulating film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can form bonding pads in a suitable manner.

Means for Solving the Problems

[0005] [[ID=4**]]According to one embodiment, a semiconductor device includes a first substrate, a first insulating film provided on the first substrate, a first pad provided in the first insulating film, a second insulating film provided on the first insulating film, a second pad provided in the second insulating film, disposed on the first pad, and in contact with the first pad. The device further includes a third pad provided in the second insulating film, disposed above the second pad, a third insulating film provided on the second insulating film, a fourth pad provided in the third insulating film, disposed on the third pad, and in contact with the third pad. Further, the shape of the third or fourth pad is different from the shape of the first or second pad.

Brief Description of the Drawings

[0006] [Figure 1]This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is a cross-sectional view showing the structure of the memory cell arrays 26 and 36 of the first embodiment. [Figure 3] This is a cross-sectional view (1 / 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (2 / 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (3 / 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view (4 / 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view (5 / 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 9] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 10] This is a plan view showing a first example of the metal pads 17, 22, 29, and 32 of the first embodiment. [Figure 11] This is a plan view showing a second example of the metal pads 17, 22, 29, and 32 of the first embodiment. [Figure 12] This is a plan view showing a third example of the metal pads 17, 22, 29, and 32 of the first embodiment. [Figure 13] This is a cross-sectional view showing a fourth example of the metal pads 17, 22, 29, and 32 of the first embodiment. [Figure 14] This is a cross-sectional view (1 / 2) illustrating the advantages of the semiconductor device of the first embodiment. [Figure 15] This is a cross-sectional view (2 / 2) illustrating the advantages of the semiconductor device of the first embodiment. [Figure 16] This is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 17] This is a cross-sectional view comparing the semiconductor device of the second embodiment with the semiconductor device of the comparative example. [Figure 18]It is a cross-sectional view showing the structure of a semiconductor device according to a first modification of the second embodiment. [Figure 19] It is a cross-sectional view showing the structure of a semiconductor device according to second to fourth modifications of the second embodiment. [Figure 20] It is a cross-sectional view showing a method of manufacturing a semiconductor device according to the third embodiment. [Figure 21] It is a cross-sectional view showing a method of manufacturing a semiconductor device according to a modification of the third embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 21, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment.

[0009] The semiconductor device in FIG. 1 is, for example, a three-dimensional memory in which a circuit chip 1, an array chip 2, and an array chip 3 are bonded together. FIG. 1 shows a bonding surface S1 between the circuit chip 1 and the array chip 2 and a bonding surface S2 between the array chip 2 and the array chip 3.

[0010] The circuit chip 1 includes a substrate 11, a plurality of transistors 12, an interlayer insulating film 13, a plurality of contact plugs 14, a plurality of wirings 15, a plurality of via plugs 16, and a plurality of metal pads 17. Each transistor 12 includes a gate insulating film 12a, a gate electrode 12b, a diffusion layer 12c, and a diffusion layer 12d. The substrate 11 is an example of a first substrate, and the interlayer insulating film 13 is an example of a first insulating film. The metal pad 17 is an example of a first pad and a first metal layer.

[0011] The array chip 2 includes an interlayer insulating film 21, a plurality of metal pads 22, a plurality of via plugs 23, a plurality of wirings 24, a plurality of via plugs 25, a plurality of memory cell arrays 26, a plurality of wirings 27, a plurality of via plugs 28, and a plurality of metal pads 29. The interlayer insulating film 21 is an example of a second insulating film, and the metal pad 22 is an example of a second pad and a second metal layer. The memory cell array 26 is an example of a first memory cell array, and the metal pad 29 is an example of a third pad and a third metal layer.

[0012] The array chip 3 includes an interlayer insulating film 31, a plurality of metal pads 32, a plurality of via plugs 33, a plurality of wirings 34, a plurality of via plugs 35, a plurality of memory cell arrays 36, a plurality of wirings 37, a plurality of via plugs 38, and a passivation film 39. The interlayer insulating film 31 is an example of a third insulating film, and the metal pad 32 is an example of a fourth pad and a fourth metal layer. The memory cell array 36 is an example of a second memory cell array.

[0013] The substrate 11 is a semiconductor substrate such as a Si (silicon) substrate, for example. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 11 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 11. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0014] Each transistor 12 includes a gate insulating film 12a and a gate electrode 12b provided in sequence on the substrate 11, and diffusion layers 12c and 12d provided in the substrate 11. The gate electrode 12b of each transistor 12 is formed in the interlayer insulating film 13. The diffusion layers 12c and 12d of each transistor 12 function as a source diffusion layer and a drain diffusion layer. Each transistor 12 forms, for example, a logic circuit that controls the operation of the memory cell arrays 26 and 36.

[0015] The interlayer insulating film 13 is formed on the substrate 11. The interlayer insulating film 13 is, for example, a laminated insulating film including a SiO2 film (silicon oxide film) and other insulating films.

[0016] The contact plugs 14, wiring 15, via plugs 16, and metal pads 17 are formed within the interlayer insulating film 13 and are arranged sequentially on the gate electrode 12b, the diffusion layer 12c, or the diffusion layer 12d. The multiple contact plugs 14 shown in Figure 1 may further include contact plugs 14 formed on portions of the substrate 11 other than the diffusion layers 12c and 12d. The multiple wiring 15 shown in Figure 1 are provided within the same wiring layer. Each metal pad 17 includes, for example, a Cu (copper) layer.

[0017] The interlayer insulating film 21 is formed on the interlayer insulating film 13. The interlayer insulating film 21 is, for example, a multilayer insulating film including an SiO2 film and other insulating films.

[0018] The metal pads 22, via plugs 23, wiring 24, and via plugs 25 are formed within the interlayer insulating film 21 and arranged sequentially on the metal pads 17. Each metal pad 22 is in contact with the corresponding metal pad 17 and is electrically connected to the corresponding metal pad 17. Each metal pad 22 contains, for example, a Cu layer. The multiple wirings 24 shown in Figure 1 are provided within the same wiring layer.

[0019] The memory cell array 26 is formed within the interlayer insulating film 21 and is placed on the via plug 25. The operation of the memory cell array 26 is controlled by the logic circuit via the metal pads 17 and 22. Each memory cell array 26 contains multiple memory cells, and data can be stored in these memory cells. Further details of the structure of each memory cell array 26 will be described later.

[0020] The wiring 27, via plugs 28, and metal pads 29 are formed within the interlayer insulating film 21 and arranged sequentially on the memory cell array 26. The multiple wirings 27 shown in Figure 1 are provided within the same wiring layer. These wirings 27 function, for example, as source lines for the memory cell array 26. These wirings 27 may also include wirings 27 other than source lines, and these non-source wirings 27 may be located at positions other than those on the memory cell array 26. Each metal pad 29 includes, for example, a Cu layer.

[0021] The interlayer insulating film 31 is formed on the interlayer insulating film 21. The interlayer insulating film 31 is, for example, a multilayer insulating film including an SiO2 film and other insulating films.

[0022] The metal pads 32, via plugs 33, wiring 34, and via plugs 35 are formed within the interlayer insulating film 31 and arranged sequentially on the metal pads 29. Each metal pad 32 is in contact with the corresponding metal pad 29 and is electrically connected to the corresponding metal pad 29. Each metal pad 32 contains, for example, a Cu layer. The multiple wirings 34 shown in Figure 1 are provided within the same wiring layer.

[0023] The memory cell array 36 is formed within the interlayer insulating film 31 and is placed on the via plug 35. The operation of the memory cell array 36 is controlled by the logic circuit via the metal pads 17, 22, 29, and 32. Each memory cell array 36 contains multiple memory cells, and data can be stored in these memory cells. Further details of the structure of each memory cell array 36 will be described later.

[0024] The wiring 37 and via plugs 38 are formed within the interlayer insulating film 31 and are arranged sequentially on the memory cell array 36. The multiple wirings 37 shown in Figure 1 are provided within the same wiring layer. These wirings 37 function, for example, as source lines for the memory cell array 36. These wirings 37 may also include wirings 37 other than source lines, and these non-source wirings 37 may be formed at locations other than those on the memory cell array 36.

[0025] The passivation film 39 is formed on the interlayer insulating film 31. The passivation film 39 is, for example, a multilayer insulating film containing an SiO2 film and a SiN film (silicon nitride film).

[0026] As described above, the semiconductor device of this embodiment includes metal pads 17, 22, 29, and 32, with metal pads 29 and 32 positioned above metal pads 17 and 22. Specifically, metal pads 17 and 22 are positioned on the bonding surface S1 and electrically connect the circuit chip 1 and the array chip 2. Also, metal pads 29 and 32 are positioned on the bonding surface S2 and electrically connect the array chip 2 and the array chip 3. On the other hand, each metal pad 22 is positioned on the corresponding metal pad 17, and each metal pad 32 is positioned on the corresponding metal pad 29. In this embodiment, as will be described later, the shapes of metal pads 29 and 32 differ from the shapes of metal pads 17 and 22. Further details of the shapes of metal pads 17, 22, 29, and 32 will be described later.

[0027] Figure 2 is a cross-sectional view showing the structure of memory cell arrays 26 and 36 of the first embodiment.

[0028] Each memory cell array 26 in this embodiment has the structure shown in Figure 2(a). The memory cell array 26 shown in Figure 2(a) includes a plurality of electrode layers 41, a plurality of insulating films 42, and a plurality of columnar portions 43. Figure 2(a) illustrates one of the columnar portions 43.

[0029] The plurality of electrode layers 41 and the plurality of insulating films 42 are stacked alternately along the Z direction. Each electrode layer 41 includes, for example, a W (tungsten) layer and functions as a word line. Each insulating film 42 is, for example, an SiO2 film.

[0030] Each columnar portion 43 sequentially includes a block insulating film 43a, a charge storage layer 43b, a tunnel insulating film 43c, a channel semiconductor layer 43d, and a core insulating film 43e, which are formed sequentially on the sides of the electrode layer 41 and the insulating film 42. The block insulating film 43a is, for example, an SiO2 film. The charge storage layer 43b is, for example, an insulating film such as a SiN film. The charge storage layer 43b may also be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 43c is, for example, an SiO2 film. The channel semiconductor layer 43d is, for example, a polysilicon layer. The core insulating film 43e is, for example, an SiO2 film.

[0031] Each memory cell array 36 in this embodiment has the structure shown in Figure 2(b). The memory cell array 36 shown in Figure 2(b) includes a plurality of electrode layers 51, a plurality of insulating films 52, and a plurality of columnar portions 53. Figure 2(b) illustrates one of the columnar portions 53.

[0032] The plurality of electrode layers 51 and the plurality of insulating films 52 are stacked alternately along the Z direction. Each electrode layer 51 includes, for example, a W layer and functions as a word line. Each insulating film 52 is, for example, an SiO2 film.

[0033] Each columnar portion 53 sequentially includes a block insulating film 53a, a charge storage layer 53b, a tunnel insulating film 53c, a channel semiconductor layer 53d, and a core insulating film 53e, which are formed sequentially on the sides of the electrode layer 51 and the insulating film 52. The block insulating film 53a is, for example, an SiO2 film. The charge storage layer 53b is, for example, an insulating film such as a SiN film. The charge storage layer 53b may also be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 53c is, for example, an SiO2 film. The channel semiconductor layer 53d is, for example, a polysilicon layer. The core insulating film 53e is, for example, an SiO2 film.

[0034] Figures 3 to 7 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0035] Figure 3 shows a circuit wafer W1 containing multiple circuit chips 1, an array wafer W2 containing multiple array chips 2, and an array wafer W3 containing multiple array chips 3. Circuit wafer W1 is also called a CMOS wafer, and array wafers W2 and W3 are also called memory wafers.

[0036] The orientation of array wafers W2 and W3 shown in Figure 3 is the opposite of the orientation of array chips 2 and 3 shown in Figure 1. In this embodiment, a semiconductor device is manufactured by bonding circuit wafer W1, array wafer W2, and array wafer W3 together. Figure 3 shows array wafers W2 and W3 before their orientation is reversed for bonding, while Figure 1 shows array chips 2 and 3 after their orientation has been reversed for bonding, and after bonding and dicing.

[0037] In Figure 3, array wafer W2 comprises a substrate 61 provided beneath the interlayer insulating film 21, and array wafer W3 comprises a substrate 62 provided beneath the interlayer insulating film 31. Substrates 61 and 62 are semiconductor substrates such as Si substrates. Substrate 61 is an example of a second substrate, and substrate 62 is an example of a third substrate.

[0038] The semiconductor device of this embodiment is manufactured, for example, as follows.

[0039] First, a transistor 12, an interlayer insulating film 13, a contact plug 14, wiring 15, a via plug 16, and a metal pad 17 are formed on the substrate 11 of the circuit wafer W1 (Figure 3). Next, an interlayer insulating film 21, a metal pad 22, a via plug 23, wiring 24, a via plug 25, a memory cell array 26, and wiring 27 are formed on the substrate 61 of the array wafer W2 (Figure 3). Furthermore, an insulating film 31a, a metal pad 32, a via plug 33, wiring 34, a via plug 35, a memory cell array 36, and wiring 37 are formed on the substrate 62 of the array wafer W2 (Figure 3). The insulating film 31a is part of the interlayer insulating film 31. In the process shown in Figure 3, the processes for circuit wafer W1, array wafer W2, and array wafer W3 may be performed in any order.

[0040] Next, as shown in Figure 4, the circuit wafer W1 and the array wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 21. Next, the circuit wafer W1 and the array wafer W2 are annealed at 400°C (Figure 4). This heats the metal pads 17 and 22, and the metal pad 17 and the metal pad 22 are bonded together. Further details of this annealing will be described in the third embodiment. In this way, the substrate 11 and the substrate 61 are bonded together via the interlayer insulating film 13 and the interlayer insulating film 21. The lower surface of the interlayer insulating film 21 is bonded to the upper surface of the interlayer insulating film 13.

[0041] Next, the substrate 61 is removed, and via plugs 28 and metal pads 29 are sequentially formed on the wiring 27 within the interlayer insulating film 21 (Figure 5). The substrate 61 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0042] Next, as shown in Figure 6, array wafer W2 and array wafer W3 are bonded together by mechanical pressure. This bonds the interlayer insulating film 21 and the insulating film 31a (interlayer insulating film 31). Next, circuit wafer W1, array wafer W2, and array wafer W3 are annealed at 400°C (Figure 6). This heats the metal pads 17, 22, 29, and 32, and bonds metal pad 29 and metal pad 32. This annealing may be performed such that metal pads 29 and 32 are heated, while metal pads 17 and 22 are not. Further details of this annealing will be described in the third embodiment. In this way, substrate 11 and substrate 62 are bonded together via the interlayer insulating film 13, interlayer insulating film 21, and insulating film 31a. The lower surface of insulating film 31a is bonded to the upper surface of interlayer insulating film 21.

[0043] Next, the substrate 62 is removed, via plugs 38 are formed on the wiring 37 within the insulating film 31a, and insulating film 31b is formed on the insulating film 31a and the via plugs 38 (Figure 7). The insulating film 31b is part of the interlayer insulating film 31. The substrate 62 is removed, for example, by CMP.

[0044] Subsequently, a passivation film 39 (see Figure 1) is formed on the insulating film 31b, and the circuit wafer W1, array wafer W2, and array wafer W3 are cut into multiple chips. In this way, the semiconductor device shown in Figure 1 is manufactured. Note that the substrate 11 may be thinned by CMP before cutting.

[0045] In this embodiment, the semiconductor device is manufactured by bonding a circuit wafer W1 and an array wafer W2, and then bonding array wafer W2 and array wafer W3. However, it may also be manufactured by bonding array wafer W2 and array wafer W3, and then bonding circuit wafer W1 and array wafer W2. Furthermore, the semiconductor device of this embodiment may be manufactured by bonding three or more array wafers. The contents described above with reference to Figures 1 to 7, and the contents described later with reference to Figures 8 to 21, are also applicable to the bonding described in this paragraph.

[0046] Furthermore, Figure 1 shows the interface between the interlayer insulating film 13 and the interlayer insulating film 21, and the interface between the metal pad 17 and the metal pad 22. However, after annealing in Figure 4, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated, for example, by detecting the inclination of the side surfaces of the metal pad 17 and the metal pad 22, or the positional displacement between the side surface of the metal pad 17 and the metal pad 22. The same applies to the interface between the interlayer insulating film 21 and the interlayer insulating film 31, the interface between the metal pad 29 and the metal pad 32, and the annealing in Figure 6.

[0047] Furthermore, the semiconductor device of this embodiment may be traded in the state shown in Figure 1 after being cut into multiple chips, or in the state shown in Figure 7 before being cut into multiple chips. Figure 1 shows a semiconductor device in chip form, and Figure 7 shows a semiconductor device in wafer form. In this embodiment, multiple chip-shaped semiconductor devices (Figure 1) are manufactured from a single wafer-shaped semiconductor device (Figure 7).

[0048] Next, with reference to Figures 8 and 9, we will compare the semiconductor device of this embodiment with the semiconductor device of the comparative example.

[0049] Figure 8 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment.

[0050] Figure 8, similar to Figure 1, shows the metal pad 17 in circuit chip 1, the metal pads 22 and 29 in array chip 2, the metal pad 32 in array chip 3, etc. Figure 8 further shows the insulating films 71, 72, and 73 contained within the interlayer insulating films 13, 21, and 31. Insulating film 71 is, for example, an SiO2 film. Insulating film 72 is, for example, a SiN film. Insulating film 73 is, for example, a SiN film. Insulating film 72 is used as an etching stopper when forming via holes for embedding via plugs 16, 23, 28, and 33. Insulating film 73 is used as an etching stopper when forming openings for embedding metal pads 17, 22, 29, and 32.

[0051] In this comparative example, metal pads 17, 22, 29, and 32 have the same shape. Therefore, in this comparative example, the shapes of metal pads 17, 22, 29, and 32 in plan view are the same, and the thicknesses of metal pads 17, 22, 29, and 32 are the same. The shapes of these metal pads 17, 22, 29, and 32 in plan view are, for example, squares, rectangles, or circles. Also, the thickness of these metal pads 17, 22, 29, and 32 is the length of metal pads 17, 22, 29, and 32 in the Z direction. In this comparative example, metal pads 22 and 32 have a shape that is a 180-degree rotation of the shape of metal pads 17 and 29.

[0052] Figure 9 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment.

[0053] Figure 9 shows the insulating film 74 contained within the interlayer insulating films 13 and 21, in addition to the components shown in Figure 8. The insulating film 74 is, for example, a SiCN film (silicon carbonitride film). In this embodiment, the upper surface of the interlayer insulating film 13 and the lower surface of the interlayer insulating film 21 are formed of insulating film 74, and the upper surface of the interlayer insulating film 21 and the lower surface of the interlayer insulating film 31 are formed of insulating film 71. Therefore, the bonding surface S1 in this embodiment is formed of insulating film 74, and the bonding surface S2 in this embodiment is formed of insulating film 71. One of the insulating films 71 and 74 is an example of a first insulating material, and the other of the insulating films 71 and 74 is an example of a second insulating material.

[0054] In this embodiment, metal pads 17 and 22 have the same shape, and metal pads 19 and 32 have the same shape, but metal pads 17 and 22 have different shapes from metal pads 29 and 32. Therefore, in this embodiment, the shapes of metal pads 17 and 22 and metal pads 29 and 32 are different in plan view, and / or the thicknesses of metal pads 17 and 22 and metal pads 29 and 22 are different. In Figure 9, the shapes of metal pads 17 and 22 and metal pads 29 and 32 are different in plan view, but the thicknesses of metal pads 17 and 22 and metal pads 29 and 22 are the same. In this embodiment, metal pad 22 has a shape obtained by rotating the shape of metal pad 17 by 180 degrees in the Z direction, and metal pad 32 has a shape obtained by rotating the shape of metal pad 29 by 180 degrees in the Z direction.

[0055] Note that the wiring 27 shown in Figure 1 extends in the X direction, while the wiring 27 shown in Figures 8 and 9 extends in the Y direction. Thus, the wiring 27 in this embodiment may extend in any direction. The same applies to the other wirings 15, 24, 34, and 37 in this embodiment.

[0056] The advantages of having different shapes for the metal pads 17, 22 and 29, 32 in this embodiment will be explained below.

[0057] In Figure 9, the areas of metal pads 17 and 22 in a plan view are set to be small, while the areas of metal pads 29 and 32 in a plan view are set to be large. Setting the areas of metal pads 17 and 22 to be small makes it possible to shorten the pitch between adjacent metal pads 17 and between adjacent metal pads 22, thereby improving the integration density of metal pads 17 and 22. On the other hand, setting the areas of metal pads 17 and 22 to be small makes it difficult to properly bond metal pads 17 and 22 together. For example, if at least one of the warpage of the circuit wafer W1 and the warpage of the array wafer W2 is large, the likelihood of misalignment between metal pads 17 and 22 increases. If the areas of metal pads 17 and 22 are set to be small, even if such misalignment is small, high resistance or disconnection of metal pads 17 and 22 is more likely to occur.

[0058] When bonding circuit wafer W1 and array wafer W2, and then bonding array wafer W2 and array wafer W3, wafer warping is likely to become significant when bonding array wafer W2 and array wafer W3. Therefore, if the area of ​​metal pads 29 and 32 is also set to be small, the likelihood of high resistance or disconnection of metal pads 29 and 32 increases. On the other hand, even if the area of ​​metal pads 17 and 22 is set to be small, the likelihood of high resistance or disconnection of metal pads 29 and 32 is low. Therefore, in this embodiment, the area of ​​metal pads 17 and 22 is set to be small, and the area of ​​metal pads 29 and 32 is set to be large. This makes it possible to improve the integration density of these pads while suppressing high resistance and disconnection of these pads.

[0059] In Figure 9, the bonding surface S1 is formed of a SiCN film (insulating film 74), and the bonding surface S2 is formed of an SiO2 film (insulating film 71). The SiCN film is more effective at suppressing the diffusion of Cu atoms than the SiO2 film. In Figure 9, if the pitch between the metal pads 17 and the pitch between the metal pads 22 is shortened, the density of the metal pads 17 and 22 on the bonding surface S1 increases, and there is a risk that a large amount of Cu atoms will diffuse from the metal pads 17 and 22. According to this embodiment, by forming the bonding surface S1 with a SiCN film, it is possible to effectively suppress the diffusion of Cu atoms from the metal pads 17 and 22 even if the density of the metal pads 17 and 22 on the bonding surface S1 increases.

[0060] In this embodiment, the metal pads 17, 22 and 29, 32 may have different shapes for other reasons. For example, when array wafer W2 and array wafer W3 are bonded together, and then circuit wafer W1 and array wafer W2 are bonded together, wafer warping is likely to become significant when circuit wafer W1 and array wafer W2 are bonded together. In this case, the area of ​​metal pads 17, 22 may be set to be larger, and the area of ​​metal pads 29, 32 may be set to be smaller.

[0061] Furthermore, while the metal pad 22 in this embodiment has the same shape as the metal pad 17, it may also have a different shape from the metal pad 17. Similarly, while the metal pad 32 in this embodiment has the same shape as the metal pad 29, it may also have a different shape from the metal pad 29. Moreover, the plurality of metal pads 17 shown in Figure 9 may include metal pads 17 having two or more different shapes. The same applies to metal pads 22, 29, and 32.

[0062] Next, various examples of the metal pads 17, 22, 29, and 32 of this embodiment will be described with reference to Figures 10 to 13.

[0063] Figure 10 is a plan view showing a first example of the metal pads 17, 22, 29, and 32 of the first embodiment.

[0064] Figures 10(a), 10(b), 10(c), and 10(d) respectively show the shapes of metal pads 17, 22, 29, and 32 in a plan view. The shapes of metal pads 17 and 22 in a plan view are squares having four sides of length L1. On the other hand, the shapes of metal pads 29 and 32 in a plan view are squares having four sides of length L2 (L1 < L2). Therefore, metal pads 17, 22 and metal pads 29, 32 have different shapes. Note that the thicknesses of metal pads 17 and 22 in this example may be the same as or different from the thicknesses of metal pads 29 and 32.

[0065] Figure 11 is a plan view showing a second example of metal pads 17, 22, 29, and 32 of the first embodiment.

[0066] Figures 11(a), 11(b), 11(c), and 11(d) respectively show the shapes of metal pads 17, 22, 29, and 32 in a plan view. The shapes of metal pads 17 and 22 in a plan view are rectangles having two sides of length L3 and two sides of length L4 (L3 < L4). On the other hand, the shapes of metal pads 29 and 32 in a plan view are squares having four sides of length L2. Therefore, metal pads 17, 22 and metal pads 29, 32 have different shapes. Note that the thicknesses of metal pads 17 and 22 in this example may be the same as or different from the thicknesses of metal pads 29 and 32. In this example, the area L3 × L4 of metal pads 17 and 22 is set to be smaller than the area L2 × L2 of metal pads 29 and 32 (L3 × L4 < L2 × L2).

[0067] Figure 12 is a plan view showing a third example of metal pads 17, 22, 29, and 32 of the first embodiment.

[0068] Figures 12(a), 12(b), 12(c), and 12(d) respectively show the shapes of the metal pads 17, 22, 29, and 32 in a plan view. The shapes of the metal pads 17 and 22 in a plan view are circles having a diameter D1. On the other hand, the shapes of the metal pads 29 and 32 in a plan view are circles having a diameter D2 (D1 < D2). Therefore, the metal pads 17, 22 and the metal pads 29, 32 have different shapes. Note that the thicknesses of the metal pads 17 and 22 in this example may be the same as or different from the thicknesses of the metal pads 29 and 32.

[0069] Note that the first and third examples have advantages such as being able to shorten both the pitch between the metal pads 17 (or 22) in the X direction and the pitch between the metal pads 17 (or 22) in the Y direction. Also, the metal pads 17, 22, 29, and 32 may have shapes other than the shapes described in the first, second, and third examples in a plan view.

[0070] FIG. 13 is a cross-sectional view showing a fourth example of the metal pads 17, 22, 29, and 32 of the first embodiment.

[0071] FIG. 13(a) shows a longitudinal cross-section of the metal pads 17 and 22, and FIG. 13(b) shows a longitudinal cross-section of the metal pads 29 and 32. The metal pads 17 and 22 have a thickness T1, and the metal pads 29 and 32 have a thickness T2 (T1 < T2). Therefore, the metal pads 17, 22 and the metal pads 29, 32 have different shapes. Note that the shapes of the metal pads 17 and 22 in this example may be the same as or different from the shapes of the metal pads 29 and 32 in a plan view.

[0072] Generally, the thicker the metal pad, the more likely a large amount of Cu atoms will diffuse from the metal pad. Therefore, when adopting the fourth example, the bonding surface S1 may be formed of a SiO2 film and the bonding surface S2 may be formed of a SiCN film. Thereby, even if the metal pads 29 and 32 are thick, it becomes possible to effectively suppress the diffusion of Cu atoms from the metal pads 29 and 32.

[0073] Figures 14 and 15 are cross-sectional views illustrating the advantages of the semiconductor device of the first embodiment.

[0074] Figures 14(a) and 14(b) show the metal pad 17 in circuit chip 1, the metal pads 22 and 29 in array chip 2, and the metal pad 32 in array chip 3. Figures 14(a) and 14(b) further show the pitch P1 between the metal pads 17 (or 22) and the pitch P2 between the metal pads 29 (or 32). According to this embodiment, by reducing the area of ​​the metal pads 17 and 22 in plan view, it is possible to shorten the pitch P1 as described above. This makes it possible to improve the integration density of the metal pads 17 and 22.

[0075] Figures 15(a) and 15(b) show the width X of the misalignment between metal pad 17 and metal pad 22, and between metal pad 29 and metal pad 32. Because the area of ​​metal pads 29 and 32 is large, high resistance or disconnection of metal pads 29 and 32 due to misalignment is less likely. On the other hand, because the area of ​​metal pads 17 and 22 is small, high resistance or disconnection of metal pads 17 and 22 due to misalignment is more likely. The misalignment shown in Figure 15(a) and the misalignment shown in Figure 15(b) have the same width X, but the metal pads 17 and 22 shown in Figure 15(b) are more prone to misalignment problems than the metal pads 29 and 32 shown in Figure 15(a).

[0076] However, when bonding circuit wafer W1 and array wafer W2, and then bonding array wafer W2 and array wafer W3, the warping of the wafers is less likely to increase when bonding circuit wafer W1 and array wafer W2. Therefore, when bonding circuit wafer W1 and array wafer W2, it is possible to perform the bonding in a way that suppresses misalignment. Accordingly, in this embodiment, the area of ​​metal pads 17 and 22 is set to be small, and the area of ​​metal pads 29 and 32 is set to be large. This makes it possible to improve the integration density of these pads while suppressing high resistance and disconnection of these pads.

[0077] As described above, the shapes of the metal pads 29 and 32 in this embodiment differ from the shapes of the metal pads 17 and 22. Therefore, according to this embodiment, as described above, it is possible to form these metal pads 17, 22, 29, and 32 in a preferred manner.

[0078] (Second Embodiment) Figure 16 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0079] The semiconductor device of this embodiment (Figure 16) has the same components as the semiconductor device of the first embodiment. However, the array chip 2 of this embodiment does not have a metal pad 29, but has a via plug 28 near the bonding surface S2. Therefore, the metal pad 32 of this embodiment is bonded to the via plug 28 instead of the metal pad 29, as shown in Figure 16. The via plug 28 and metal pad 32 in Figure 16 are, for example, a W layer and a Cu layer, respectively. The via plug 28 and metal pad 32 in Figure 16 are examples of a third and fourth metal layer, respectively. The semiconductor device of this embodiment can be manufactured, for example, by omitting the step of forming the metal pad 29 using the method shown in Figures 3 to 7.

[0080] Figure 16 shows the width W1 of the upper surface of the wiring 27, the width W2 of the lower surface of the via plug 28, the width W3 of the upper surface of the metal pad 32, the width W4 of the lower surface of the via plug 33, the width W5 of the upper surface of the via plug 33, and the width W6 of the wiring 34. Widths W2, W4, and W5 correspond to the plug diameter on the upper or lower surface of the via plugs 28 and 33. The wirings 27 and 34 shown in Figure 16 extend in the Y direction, and the widths W1 and W6, which are the lengths in the X direction, correspond to the wiring width on the upper or lower surface of the wirings 27 and 34.

[0081] In this embodiment, since the via plug 28 is disposed on the wiring 27, the width W2 of the via plug 28 is shorter than the width W1 of the wiring 27 (W2 < W1). Also, since the metal pad 32 is disposed under the via plug 33, the width W3 of the metal pad 32 is longer than the width W4 of the via plug 33 (W3 > W4). Further, since the via plug 33 is disposed under the wiring 34, the width W5 of the via plug 33 is shorter than the width W6 of the wiring 34 (W5 < W6).

[0082] Note that the structure of the via plug 28 of this embodiment may be applied to the via plug 33 instead of the via plug 28. In this case, the array chip 3 does not include the metal pad 32, and the metal pad 29 is joined to the via plug 33 instead of the metal pad 32. Similarly, the structure of the via plug 28 of this embodiment may be applied to either of the via plugs 17 and 22.

[0083] FIG. 17 is a cross-sectional view for comparing the semiconductor device of the second embodiment and the semiconductor device of its comparative example.

[0084] FIG. 17(a) shows the semiconductor device of the above comparative example. In FIG. 17(a), the metal pad 32 is joined to the metal pad 29. In FIG. 17(a), a misalignment occurs between the metal pad 29 and the metal pad 32.

[0085] FIG. 17(b) shows the semiconductor device of this embodiment. In FIG. 17(b), the metal pad 32 is joined to the via plug 28. In FIG. 17(b), a misalignment occurs between the via plug 28 and the metal pad 32.

[0086] Arrow A1 shown in FIG. 17(a) indicates the gap between the metal pad 29 and the metal pad 32 of the above comparative example. Since both the size of the metal pad 29 and the size of the metal pad 32 are large, the gap between the metal pads 29 and 32 is very short due to the misalignment. Therefore, there is a risk that the withstand voltage of the semiconductor device deteriorates, such as a short circuit occurring between the metal pads 29 and 32.

[0087] The arrow A2 shown in Figure 17(b) indicates the gap between the via plug 28 and the metal pad 32 in this embodiment. Because the via plug 28 is small in size, the gap between the via plug 28 and the metal pad 32 is long enough even if misalignment occurs. Therefore, according to this embodiment, it is possible to suppress the deterioration of the withstand voltage of the semiconductor device, such as by suppressing short circuits between the via plug 28 and the metal pad 32.

[0088] Figures 18 and 19 are cross-sectional views showing the structure of the first to fourth modified semiconductor devices of the second embodiment.

[0089] The semiconductor device of the first modified example (Figure 18) has the same components as the semiconductor device of the first embodiment. However, the array chips 2 and 3 of this modified example do not have metal pads 29 and 32, but have via plugs 28 and 33 near the bonding surface S2. Therefore, the via plug 33 of this embodiment is bonded to the via plug 28, as shown in Figure 18. The via plugs 28 and 33 in Figure 18 are, for example, W layers. The via plugs 28 and 33 in Figure 18 are examples of third and fourth metal layers, respectively. The semiconductor device of this modified example can be manufactured, for example, by omitting the step of forming the metal pads 29 and 32 using the method shown in Figures 3 to 7. According to this modified example, similar to the second embodiment, it is possible to suppress the deterioration of the withstand voltage of the semiconductor device, such as by suppressing short circuits between the via plugs 28 and 33.

[0090] The second modified semiconductor device (Figure 19(a)) includes, in addition to the components shown in Figure 16, a plurality of metal pads (dummy pads) 32'. These metal pads 32' are made of the same material as the metal pads 32. The third modified semiconductor device (Figure 19(b)) includes, in addition to the components shown in Figure 18, a plurality of via plugs (dummy plugs) 28'. These via plugs 28' are made of the same material as the via plugs 28. The fourth modified semiconductor device (Figure 19(c)) includes, in addition to the components shown in Figure 16, a plurality of via plugs (dummy plugs) 28'. These via plugs 28' are made of the same material as the via plugs 28.

[0091] Thus, when adopting the structure of the second embodiment or the first modified example, the array chip 2 or array chip 3 may be equipped with a dummy pad 32' or a dummy plug 28'. The dummy pad 32' is a metal pad that is not used as a pad to electrically connect components within the semiconductor device. The dummy plug 28' is a via plug that is not used as a plug to electrically connect components within the semiconductor device. The dummy pad 32' and dummy plug 28' make it possible to suppress CMP erosion. When adopting the structure of the second embodiment or the first modified example, in order to secure a wide gap indicated by arrows A1 and A2, it is desirable to place the dummy pad 32' (or dummy plug 28') on only one of the array chips 2 or 3, as shown in Figures 19(a) to 19(c).

[0092] As described above, the array chips 2 and 3 of this embodiment have a structure in which a metal pad 32 and a via plug 28 are joined together, or a structure in which a via plug 33 and a via plug 28 are joined together. Therefore, according to this embodiment, as described above, it is possible to form these metal pads 32 and via plugs 28 and 33 in a suitable manner. According to this embodiment, it is possible to provide the via plugs 28 and 33 with the same functions as bonded pads such as the metal pad 32.

[0093] Furthermore, the structures of the second embodiment and the first to fourth modified examples may be applied to the bonding surface S1 instead of the bonding surface S2. However, when the circuit wafer W1 and the array wafer W2 are bonded together, and then the array wafer W2 and the array wafer W3 are bonded together, the warping of the wafers is likely to become significant when the array wafer W2 and the array wafer W3 are bonded together. In this case, misalignment between the metal pads is likely to occur when the array wafer W2 and the array wafer W3 are bonded together. Therefore, in this case, it is preferable to apply the structures of the second embodiment and the first to fourth modified examples to the bonding surface S2 rather than the bonding surface S1.

[0094] (Third embodiment) Figure 20 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.

[0095] The method for manufacturing the semiconductor device in this embodiment is the same as the method for manufacturing the semiconductor device in the first embodiment shown in Figures 3 to 7. However, in this embodiment, the annealing temperature immediately after bonding the array wafer W2 and the array wafer W3 is set to a different temperature from the annealing temperature immediately after bonding the circuit wafer W1 and the array wafer W2.

[0096] First, the circuit wafer W1 and the array wafer W2 are bonded together (Figure 20(a)). Next, the circuit wafer W1 and the array wafer W2 are annealed at temperature Ta (Figure 20(b)). This heats the metal pads 17 and 22. Temperature Ta is an example of a first temperature.

[0097] The metal pads 17 and 22 in this embodiment include, for example, a Cu layer. The Cu layers can be sufficiently bonded together by annealing at 400°C or higher. However, the annealing in Figure 20(b) is performed with the temperature Ta set to less than 400°C. Therefore, the metal pads 17 and 22 in this embodiment are not sufficiently bonded by the annealing in Figure 20(b). The annealing in Figure 20(b) is performed, for example, with the temperature Ta set to less than 300°C for 1 hour. With this annealing, the bonding between the interlayer insulating film 13 and the interlayer insulating film 21 is promoted, but the metal pads 17 and 22 are not sufficiently bonded.

[0098] Next, array wafers W2 and W3 are bonded together (Figure 20(c)). Then, circuit wafer W1, array wafer W2, and array wafer W3 are annealed at a temperature Tb different from temperature Ta (Figure 20(d)). This heats the metal pads 17, 22, 29, and 32. Temperature Tb is an example of a second temperature.

[0099] The metal pads 29 and 32 in this embodiment include, for example, a Cu layer. The annealing shown in Figure 20(d) is performed with the temperature Tb set to 400°C or higher. As a result, the metal pads 17 and 22 in this embodiment are sufficiently bonded by the annealing shown in Figure 20(d), and the metal pads 29 and 32 in this embodiment are also sufficiently bonded by the annealing shown in Figure 20(d). The annealing shown in Figure 20(d) is performed, for example, with the temperature Tb set to 400°C for 1 hour. This annealing not only promotes the bonding between the interlayer insulating film 21 and the interlayer insulating film 31, but also ensures that the metal pads 17 and 22 are sufficiently bonded, and that the metal pads 22 and 32 are sufficiently bonded.

[0100] If the temperature Ta is set to 400°C or higher, the metal pads 17 and 22 will be sufficiently bonded by the annealing shown in Figure 20(b), and further exposed to a temperature at which sufficient bonding can be achieved by the annealing shown in Figure 20(d). As a result, there is a risk of excessive stress being placed on the metal pads 17 and 22, and a risk of a large amount of Cu atoms diffusing from the metal pads 17 and 22. On the other hand, according to this embodiment, these problems can be suppressed by setting the temperature Ta to less than 400°C.

[0101] Furthermore, the diffusion of Cu atoms is considered to have a significant adverse effect on the circuit wafer W1. Therefore, it is desirable to suppress the diffusion of Cu atoms from the metal pads 17 and 22 that are close to the circuit wafer W1 more than the diffusion of Cu atoms from the metal pads 29 and 32 that are farther away from the circuit wafer W1. According to this embodiment, by performing the annealing shown in Figure 20(b), in which only the metal pads 17 and 22 are heated, at a low temperature, it is possible to effectively suppress the diffusion of Cu atoms from the metal pads 17 and 22.

[0102] Note that temperature Ta may be set to a different temperature from temperature Tb for other reasons. For example, the semiconductor device may be manufactured by the method shown in Figure 21.

[0103] Figure 21 is a cross-sectional view showing a modified example of the third embodiment for manufacturing a semiconductor device.

[0104] First, array wafers W2 and W3 are bonded together (Figure 21(a)). Next, array wafers W2 and W3 are annealed at temperature Tb (Figure 21(b)). This heats the metal pads 29 and 32. This temperature Tb is also an example of a second temperature.

[0105] The metal pads 29 and 32 in this modified example include, for example, a Cu layer. The annealing in Figure 21(b) is performed with the temperature Tb set to 400°C or higher. As a result, the metal pads 29 and 32 in this modified example are sufficiently bonded by the annealing in Figure 21(b). The annealing in Figure 21(b) is performed, for example, with the temperature Ta set to 420°C for 1 hour. This annealing not only promotes bonding between the interlayer insulating film 21 and the interlayer insulating film 31, but also ensures that the metal pads 29 and 32 are sufficiently bonded.

[0106] Next, the circuit wafer W1 and the array wafer W2 are bonded together (Figure 21(c)). Then, the circuit wafer W1, array wafer W2, and array wafer W3 are annealed at a temperature Ta different from temperature Tb (Figure 21(d)). This heats the metal pads 17, 22, 29, and 32. This temperature Ta is also an example of the first temperature.

[0107] The metal pads 17 and 22 in this modified example include, for example, a Cu layer. The annealing in Figure 21(d) is performed with the temperature Ta set to 400°C or higher. As a result, the metal pads 17 and 22 in this modified example are sufficiently bonded by the annealing in Figure 21(d). The annealing in Figure 21(d) is performed, for example, with the temperature Ta set to 400°C for 1 hour. This annealing not only promotes bonding between the interlayer insulating film 13 and the interlayer insulating film 21, but also ensures that the metal pads 17 and 22 are sufficiently bonded.

[0108] As described above, it is desirable to suppress the diffusion of Cu atoms from metal pads 17 and 22 that are close to the circuit wafer W1 more than the diffusion of Cu atoms from metal pads 29 and 32 that are farther from the circuit wafer W1. In this modified example, since the metal pads 17 and 22 are heated only in the annealing shown in Figure 21(d) of the annealing shown in Figures 21(b) and 21(d), it is possible to effectively suppress the diffusion of Cu atoms from the metal pads 17 and 22. Furthermore, in this modified example, by making the temperature Ta lower than the temperature Tb, it is possible to perform the annealing of the metal pads 17 and 22 at a lower temperature, which further effectively suppresses the diffusion of Cu atoms from the metal pads 17 and 22.

[0109] As described above, according to this embodiment, by setting temperature Tb to a temperature different from temperature Ta, it is possible to form the metal pads 17, 22, 29, and 32 in a suitable manner. In the above description, temperature Tb is set higher than temperature Ta, but conversely, a method in which temperature Tb is set lower than temperature Ta may also be adopted.

[0110] Furthermore, the method of this embodiment may be applied to the manufacturing of a semiconductor device of the second embodiment instead of the first embodiment. In this case, the annealing of this embodiment will not only join metal pads together, but will also join metal pads and via plugs, or join via plugs together.

[0111] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of symbols]

[0112] 1: Circuit chip, 2: Array chip, 3: Array chip 11: substrate, 12: transistor, 12a: gate insulator, 12b: gate electrode, 12c: diffusion layer, 12d: diffusion layer, 13: interlayer insulating film, 14: contact plug, 15: Wiring, 16: Via plug, 17: Metal pad, 21: Interlayer insulating film, 22: Metal pad, 23: Via plug, 24: Wiring, 25: Via plug, 26: Memory cell array, 27: Wiring, 28: Via plug, 29: Metal pad, 31: Interlayer insulating film, 31a: insulating film, 31b: insulating film, 32: metal pad, 33: Via plug, 34: Wiring, 35: Via plug, 36: Memory cell array, 37: Wiring, 38: Via plug, 39: Passivation membrane, 41: Electrode layer, 42: Insulating film, 43: Columnar part, 43a: Block insulating film, 43b: Charge storage layer, 43c: Tunnel insulating film, 43d: Channel semiconductor layer, 43e: Core insulating film, 51: Electrode layer, 52: Insulating film, 53: Columnar part, 53a: Block insulating film, 53b: Charge storage layer, 53c: Tunnel insulating film, 53d: Channel semiconductor layer, 53e: Core insulating film, 61: circuit board, 62: circuit board, 71: insulating film, 72: insulating film, 73: insulating film, 74: insulating film

Claims

1. First circuit board and A first insulating film provided on the first substrate, A first pad provided within the first insulating film, A second insulating film provided on the first insulating film, A second pad provided within the second insulating film, positioned on the first pad, and in contact with the first pad, A third pad is provided within the second insulating film and positioned above the second pad, A third insulating film provided on the second insulating film, The third insulating film is provided within the third pad, and the fourth pad is positioned on the third pad and in contact with the third pad, The shapes of the first pad and the second pad in a plan view are the same, and the shapes of the third pad and the fourth pad in a plan view are the same. The shapes of the third and fourth pads in plan view differ from the shapes of the first and second pads in plan view. The sizes of the third and fourth pads in a plan view are larger than the sizes of the first and second pads in a plan view. The thickness of the third and fourth pads is the same as the thickness of the first and second pads. Semiconductor equipment.

2. The first memory cell array provided within the second insulating film, A second memory cell array provided within the third insulating film, The semiconductor device according to claim 1, further comprising:

3. The semiconductor device according to claim 2, further comprising a circuit provided within the first insulating film for controlling the first and second memory cell arrays.

4. The upper surface of the first insulating film or the lower surface of the second insulating film is formed of the first insulating material. The semiconductor device according to claim 1, wherein the upper surface of the second insulating film or the lower surface of the third insulating film is formed of a second insulating material different from the first insulating material.

5. One of the first and second insulating materials comprises silicon and oxygen. The other of the first and second insulating materials comprises silicon, carbon, and nitrogen. The semiconductor device according to claim 4.

6. First circuit board and A first insulating film provided on the first substrate, A first metal layer provided within the first insulating film, A second insulating film provided on the first insulating film, A second metal layer provided within the second insulating film, positioned on the first metal layer, and in contact with the first metal layer, A third metal layer is provided within the second insulating film and positioned above the second metal layer, A third insulating film provided on the second insulating film, The third insulating film is provided within the third metal layer, which is arranged on the third metal layer and in contact with the third metal layer, and comprises a fourth metal layer. The first, second, third, or fourth metal layer is a plug provided on the surface of the wiring. The shapes of the first and second metal layers in a plan view are the same, and the shapes of the third and fourth metal layers in a plan view are the same. The shapes of the third and fourth metal layers in plan view differ from the shapes of the first and second metal layers in plan view. The sizes of the third and fourth metal layers in a plan view are larger than the sizes of the first and second metal layers in a plan view. The thicknesses of the third and fourth metal layers are the same as the thicknesses of the first and second metal layers. Semiconductor equipment.

7. One of the first and second metal layers, or one of the third and fourth metal layers, is a plug provided on the surface of the wiring. The other of the first and second metal layers, or the other of the third and fourth metal layers, is a pad provided on the surface of the wiring via a plug. The semiconductor device according to claim 6.

8. One of the first and second metal layers, or one of the third and fourth metal layers, is a plug provided on the surface of the wiring. The other of the first and second metal layers, or the other of the third and fourth metal layers, is a plug provided on the surface of the wiring. The semiconductor device according to claim 6.

9. The first memory cell array provided within the second insulating film, A second memory cell array provided within the third insulating film, The semiconductor device according to claim 6, further comprising:

10. The semiconductor device according to claim 9, further comprising a circuit provided within the first insulating film for controlling the first and second memory cell arrays.

11. A first insulating film is formed on the first substrate. A first metal layer is formed within the first insulating film. A second insulating film is formed on the second substrate. A second metal layer and a third metal layer are formed within the second insulating film. A third insulating film is formed on the third substrate. A fourth metal layer is formed within the third insulating film. The first insulating film and the second insulating film are bonded together so that the first metal layer and the second metal layer are in contact, and after bonding the first insulating film and the second insulating film, at least the first and second metal layers are annealed at a first temperature. The second insulating film and the third insulating film are bonded together such that the third metal layer and the fourth metal layer are in contact, and after bonding the second insulating film and the third insulating film, at least the third and fourth metal layers are annealed at a second temperature. This includes, A method for manufacturing a semiconductor device, wherein the second temperature is different from the first temperature.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the bonding of the second insulating film and the third insulating film is performed after annealing at a first temperature.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the bonding of the first insulating film and the second insulating film is performed after annealing at the second temperature.

14. A first memory cell array is formed on the second substrate. A second memory cell array is formed on the third substrate. A method for manufacturing a semiconductor device according to claim 11, further comprising the following:

15. The method for manufacturing a semiconductor device according to claim 14, further comprising forming circuits for controlling the first and second memory cell arrays on the first substrate.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the second temperature is higher than the first temperature.

17. The method for manufacturing a semiconductor device according to claim 11, wherein the first, second, third, and fourth metal layers are, respectively, the first, second, third, and fourth pads.

18. The method for manufacturing a semiconductor device according to claim 11, wherein the first, second, third, or fourth metal layer is a plug provided on the surface of the wiring.

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