Pattern formation method, template manufacturing method, and semiconductor device manufacturing method

Abstract

To provide a pattern forming method, a template manufacturing method, and a semiconductor device manufacturing method that improve manufacturing efficiency and precision.SOLUTION: A pattern formation method includes forming a first pattern having a concave portion in an inclined portion on a surface of a second layer opposite to the first layer that is in contact with the first layer, and performing first etching to remove a part of the first layer using the second layer as a mask. The step of forming a pattern includes forming a second pattern by forming an inclined portion on the surface and forming a recessed portion exposing the first layer in the inclined portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a pattern formation method, a template manufacturing method, and a semiconductor device manufacturing method.

Background Art

[0002] As a semiconductor device, a semiconductor package using a NAND-type flash memory is known. In order to increase the capacity of such a NAND-type flash memory, a three-dimensional NAND-type flash memory having a configuration in which a large number of memory cells are stacked has been put into practical use. A plurality of conductive layers connected to each memory cell are stacked on a substrate and connected to a drive circuit or the like.

[0003] Contacts connecting to each of the plurality of conductive layers stacked on the substrate have a multi-tone pattern in the stacking direction. Therefore, nanoimprint lithography for forming a pattern by pressing a multi-tone template onto a resist is useful.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

[0005] The embodiments relating to this disclosure provide a pattern formation method, a template manufacturing method, and a semiconductor device manufacturing method that improve manufacturing efficiency and accuracy. [Means for solving the problem]

[0006] A pattern forming method according to one embodiment includes forming a first pattern having recesses in the inclined portion on the surface of the second layer opposite to the first layer that is in contact with the first layer, and forming a second pattern by performing a first etching in which a part of the first layer is removed using the second layer as a mask. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view showing the configuration of a template pattern according to one embodiment. [Figure 2] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 3] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 4] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 5] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 6] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 7] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 8] This is a perspective view showing the overall configuration of a semiconductor device according to one embodiment. [Figure 9] A perspective view showing the configuration of the memory cell region (MCR) and the contact region (HUR) of a semiconductor device according to one embodiment. [Figure 10] This is a cross-sectional view showing the configuration of a stacked wiring structure of a semiconductor device according to one embodiment. [Figure 11]It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 12] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 13] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 14] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 15] It is a cross-sectional view showing the configuration of a template pattern according to an embodiment. [Figure 16] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 17] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 18] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 19] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 20] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 21] It is a cross-sectional view showing the configuration of a multilayer wiring structure according to an embodiment. [Figure 22] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 23] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 24] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 25] It is a cross-sectional view showing a method for manufacturing a multilayer wiring structure of a semiconductor device according to an embodiment. [Figure 26] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 27] It is a cross-sectional view showing a method for forming a template pattern according to an embodiment. [Figure 28] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 29] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 30] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 31] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 32] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 33] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 34] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 35] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 36] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 37] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 38] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 39] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 40] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 41] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 42] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Figure 43] This is a cross-sectional view showing a template pattern formation method according to one embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, the pattern formation method, template manufacturing method, and semiconductor device manufacturing method according to this embodiment will be specifically described with reference to the drawings. In the following description, elements having substantially the same function and configuration are denoted by the same reference numeral or by an alphabet letter added to the same reference numeral, and will be described redundantly only when necessary. The embodiments shown below illustrate apparatuses and methods for realizing the technical idea of ​​this embodiment. Various modifications can be made to one embodiment without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention and its equivalents as described in the claims.

[0009] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, elements having the same function as those described in previously shown drawings are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] In this specification, expressions such as "α includes A, B, or C" do not exclude cases where α includes multiple combinations of A, B, and C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0011] In this specification, "horizontal" may refer to the direction parallel to the bottom surface of the substrate (XY direction), and "vertical" may refer to the direction substantially perpendicular to the horizontal direction (Z direction).

[0012] The following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0013] In the following embodiments, templates used in nanoimprint lithography are used as examples of substrates for forming patterns, but the technology of this disclosure can also be applied to the formation of patterns other than templates. Furthermore, in the following embodiments, methods for manufacturing semiconductor devices using templates are used as examples, but the technology of this disclosure can also be applied to manufacturing methods other than semiconductor devices. <First Embodiment> [Template structure] Figure 1 is a cross-sectional view showing the configuration of template 1. Template 1 has a pattern 2 on its first surface A. Pattern 2 is formed inside the outer periphery A1 of the first surface A. That is, the outer periphery A1 of the first surface A is substantially parallel to the second surface B on the opposite side of the first surface A. However, it is not limited to this, and pattern 2 can be formed in any region of the first surface A. It is preferable that pattern 2 is formed inside any two sides of the outer periphery A1. The material of template 1 is, for example, quartz. However, it is not limited to this, and the material of template 1 may be, for example, silicon. [Pattern composition] Pattern 2 includes a recess D in the inclined portion C. The inclined portion C has a virtual plane (dashed line) that intersects the first surface A and the bottom surface E of the recess D. The shape of the virtual plane (dashed line) is substantially planar. However, it is not limited to this, and the virtual plane (dashed line) may intersect the bottom surface E of the recess D with a gently curved surface, with two or more planes, or with a combination of a plane and a curved surface. If it intersects with two or more planes, each plane may intersect at a different angle and may have inclinations in opposite directions. The virtual plane (dashed line) may be located between the first surface A and the bottom surface E of the recess D. The virtual plane (dashed line) of the inclined portion C and the bottom surface E of the recess D may intersect at an acute angle. The bottom surface E and the first surface A are connected by a side wall G. The side wall G connects the bottom surface E and the first surface A substantially perpendicular to the first surface A and the second surface B.

[0014] The inclined portion C has a recess D. The recess D has a side surface F and a bottom surface E connecting the side surfaces F. The side surfaces F of the recess D connect to the top surface c approximately perpendicular to the first surface A and the second surface B. The bottom surface E of the recess D connects the side surfaces F of the recess D on a plane approximately parallel to the first surface A and the second surface B. In other words, pattern 2 has a plurality of protrusions H on the bottom surface E. The protrusions H have side surfaces F and top surfaces c connecting the side surfaces F. The side surfaces F of the protrusions H connect to the top surface c approximately perpendicular to the first surface A and the second surface B. The top surface c of the protrusions H connects the side surfaces F of the protrusions H along a virtual plane (dashed line). That is, the top surface c of the protrusions H is at the same height as the first surface A or lower than the first surface A.

[0015] Pattern 2 according to this embodiment is provided with a plurality of protrusions H of different heights (gradations) on the bottom surface E of the recess D. In Figure 1, seven protrusions H are shown in one recess D. However, the number of protrusions H is not particularly limited, and Pattern 2 only needs to have two or more protrusions H of different heights on the bottom surface E of the recess D. Pattern 2 may also have areas on the bottom surface E where no protrusions H are arranged. All of the protrusions H according to this embodiment are cylindrical in shape. However, the shape of the protrusions H is not particularly limited, and the protrusions H may be prism-shaped or wall-shaped. For example, the recess D may be divided into multiple parts by wall-shaped protrusions H. In this case, the bottom surfaces E of the multiple recesses D may be arranged on a single surface that is substantially parallel to the first surface A and the second surface B. Although Figure 1 shows protrusions H of different heights in the left-right direction of the paper, Pattern 2 according to this embodiment can also be applied in the depth direction of the paper. [Method for forming patterns] Referring to Figures 2 to 7, the method for manufacturing a template according to this embodiment, particularly the method for forming the template pattern, will be described. Although Figures 2 to 7 show an example of forming protrusions H of different heights in the left-right direction of the paper, the method for forming pattern 2 according to this embodiment can also be applied to the depth direction of the paper.

[0016] As shown in Figure 2, a laminate is prepared in which a first layer 100, a second layer 200, and a third layer 300 (first resin layer) are stacked in this order. The method for manufacturing the laminate is not particularly limited. The first layer 100, the second layer 200, and the third layer 300 are formed so as to be in contact with each other. In this embodiment, the material of the first layer 100 is exemplified as quartz, but the material of the first layer 100 is not limited to this and may be silicon, for example. The second layer 200 only needs to function as a hard mask, and the material of the second layer 200 may be, for example, a compound containing carbon or silicon. Alternatively, the material of the second layer 200 may be a metal compound containing chromium or tantalum. The third layer 300 only needs to function as a resist, and the material of the third layer 300 may be, for example, a photosensitive resin.

[0017] A slanted portion C3 is formed on the surface 301 of the third layer 300 that is in contact with the second layer 200 and is opposite to the second layer 200. The method of forming the slanted portion C3 is not particularly limited. The slanted portion C3 may be formed, for example, by nanoimprint lithography, by photolithography with a gradient in the exposure amount, or by laser irradiation with a gradient in the energy amount. The slanted portion C3 is formed inside the outer peripheral portion 302 of the surface 301. That is, the outer peripheral portion 302 of the surface 301 is substantially parallel to the surface B of the first layer 100 that is opposite to the second layer 200. However, it is not limited to this, and the slanted portion C3 can be formed in any region of the surface 301. It is preferable that the slanted portion C3 be formed inside any two sides of the outer peripheral portion 302. In addition, structures other than the slanted portion C3 may be formed on the surface 301 of the third layer 300, for example, in combination with a recess that exposes the second layer 200.

[0018] As shown in Figure 3, the second layer 200 is processed using the third layer 300, which has an inclined portion C3, as a mask. The inclined portion C2, which is determined by the processing speed (etching rate) of the third layer 300 and the second layer 200, is transferred to the second layer 200. For example, if the processing speed of the third layer 300 is higher than that of the second layer 200, the angle θ2 between the surface 202 of the second layer 200 that is in contact with the first layer 100 and the inclined portion C2 will be smaller than the angle θ3 between the surface 302 of the third layer 300 that is in contact with the second layer 200 and the inclined portion C3. For example, if the processing speed of the second layer 200 is higher than that of the third layer 300, the angle θ2 between the surface 202 of the second layer 200 and the inclined portion C2 will be larger than the angle θ3 between the surface 302 of the third layer 300 and the inclined portion C3.

[0019] As shown in Figure 4, a fourth layer 400 (second resin layer) is formed on the second layer 200 which has an inclined portion C2, so as to fill the inclined portion C2. The fourth layer 400 only needs to function as a resist, and the material of the fourth layer 400 may be, for example, a photosensitive resin.

[0020] As shown in Figure 5, a recess D4 is formed on the surface 401 of the fourth layer 400 that is in contact with the second layer 200 and is opposite to the second layer 200. The recess D4 is formed on the inclined portion C2 of the second layer 200, with the inclined portion C2 acting as a stopper. The recess D4 exposes the inclined portion C2 of the second layer 200. The method of forming the recess D4 is not particularly limited. The recess D4 may be formed, for example, by photolithography using a mask having the upper surface pattern of the recess D4.

[0021] As shown in Figure 6, the second layer 200 is processed using the fourth layer 400, which has a recess D4, as a mask. The recess D2 is transferred to the inclined portion C2 of the second layer 200, with the surface A of the first layer 100 opposite to surface B acting as a stopper, and a pattern 3 having the recess D2 on the inclined portion C2 is formed. The bottom of the recess D2 exposes the surface A of the first layer 100. The thickness of the fourth layer 400 is appropriately set depending on the processing speed of the fourth layer 400 and the second layer 200 and the thickness of the second layer 200. After that, the remaining fourth layer 400 is peeled off. The pattern forming method according to this embodiment makes it possible to form a pattern 3 having protrusions H2 of different heights on the surface A of the first layer 100 by forming a recess D2 on the inclined portion C2 of the second layer 200.

[0022] As shown in Figure 7, the first layer 100 is processed (first etching) using the second layer 200 having pattern 3 as a mask. The first layer 100 exposed by the recess D2 of pattern 3 is etched by the first etching. At this time, the second layer 200 is also reduced by the first etching. The first etching may be, for example, RIE using a fluorine-based reaction gas.

[0023] A pattern 2 is transferred to surface A of the first layer 100, which has recesses D in inclined sections C determined by the processing speeds of the first layer 100 and the second layer 200. For example, if the processing speed of the first layer 100 is higher than that of the second layer 200, the angle θ between the bottom surface E of the recess D and the inclined section C will be greater than the angle θ2 between the surface 202 of the second layer 200 and the inclined section C2, and the depth of the recess D from surface A to bottom surface E will be greater than the depth of the recess D2 from surface 201 to surface 202. In other words, a pattern 2 can be formed which has protrusions H of different heights on the bottom surface E, which is an extension of pattern 3 in the stacking direction. The thickness of the second layer 200 and the angle θ2 (number of gradations of pattern 3) between the surface 202 of the second layer 200 and the inclined portion C2 are appropriately set based on the processing speed of the first layer 100 and the second layer 200 in the first etching, the arrangement of the recesses D or protrusions H of pattern 2, the angle θ (number of gradations of pattern 2) between the bottom surface E of the recess D and the inclined portion C, the height from the bottom surface E to the surface A (height of pattern 2), the depth of the recess D from the surface A to the bottom surface E (depth of pattern 2), and the control accuracy of the processing amount of the first layer 100 in the first etching. After that, the template 1 shown in Figure 1 can be manufactured by peeling off the remaining second layer 200.

[0024] In the template manufacturing method according to this embodiment, the formation efficiency and accuracy of the pattern 2, which has multiple protrusions H of different heights (gradations) on the bottom surface E of the recess D, can be improved. [Overall configuration of semiconductor device] The overall configuration of the semiconductor device according to this embodiment will be described with reference to Figure 8. Figure 8 is a perspective view showing the arrangement of each element of the semiconductor device 10 according to this embodiment.

[0025] The semiconductor device 10 is a NAND flash memory device and is formed on a semiconductor substrate 11. The semiconductor substrate 11 is divided into a memory cell region (MCR) and a contact region (HUR). A memory cell array 16, including multiple memory cells stacked in three dimensions, is formed in the memory cell region (MCR). Specifically, a memory string is formed by connecting a source-side select gate transistor, a large number of memory cell transistors (e.g., 64), and a drain-side select gate transistor in series perpendicular to the surface of the semiconductor substrate 11. Dummy cell transistors may be included at both ends of the series-connected memory cell transistors, or in some of the spaces between the memory cell transistors. The memory cell array 16 includes a laminate in which multiple conductive layers, each connected to a source-side select gate line, word line, and drain-side select gate line, are stacked with an insulating layer in between. The multiple conductive layers extend into the contact region (HUR) to form a stacked wiring structure 17. Bit lines (not shown) are provided on the memory cell array 16 and connected to peripheral circuits 18. Wiring (not shown) is provided on the stacked wiring structure 17 and connected to peripheral circuits 18.

[0026] The semiconductor substrate 11 is further divided into a peripheral circuit region PER. Peripheral circuits 18 are formed in the peripheral circuit region PER. The peripheral circuits 18 have a large number of CMOS transistors. The peripheral circuits 18 include a column system circuit that includes a drive circuit for driving each word line connected to the memory cell, a decoder circuit for selecting each word line, a sense amplifier for sensing the bit line potential during reading, and a bit line potential control circuit for supplying voltage to the bit line during writing. Note that the wiring of the peripheral circuit region PER is omitted in Figure 8. The semiconductor substrate 11 has a row of pads 19 that receive signals and power from the outside of the chip. [Configuration of memory cell area (MCR) and contact area (HUR)] Figure 9 is a perspective view showing the configuration of the memory cell region (MCR) and contact region (HUR) of the semiconductor device according to this embodiment. To prevent confusion in the figure, conductive components are shown, while insulating components are omitted. The parts of Figure 9 where components are not shown are insulated using an insulating material such as silicon dioxide.

[0027] In the memory cell region (MCR), a memory cell array 16 is formed on a semiconductor substrate 11 made of silicon single crystal. The memory cell array 16 has conductive layers 71, 72, 73, and 74 (referred to as conductive layer 70 when conductive layers 71 to 74 are not distinguished) that extend substantially parallel to the surface of the semiconductor substrate 11. The memory cell array 16 has a laminate in which these multiple conductive layers 70 are stacked with insulating layers in between. Although only four conductive layers are shown in the figure, many more layers, such as 33 or 65 layers, are stacked. These conductive layers correspond to source-side select gate lines, word lines, or drain-side select gate lines connected to the transistors.

[0028] In the memory cell region (MCR), a memory pillar 40 is formed that penetrates multiple conductive layers and multiple insulating layers. The memory pillar 40 is cylindrical, and from the outer periphery toward the center, a block insulating film containing a silicon dioxide film, a charge storage film containing a silicon nitride film, a tunnel insulating film containing a silicon dioxide film, a semiconductor channel containing an amorphous or polycrystalline silicon film, and a silicon dioxide film are stacked. A portion of the charge storage film located between the conductive layers 71, 72, 73, and 74 corresponding to the select gate line or word line and the semiconductor channel functions as part of a non-volatile memory cell that traps carriers.

[0029] In the contact region HUR, a multilayer wiring structure 17 is formed on a semiconductor substrate 11 made of silicon single crystal. The contact region HUR also has multiple insulating layers and multiple conductive layers that extend from the memory cell region MCR. The multilayer wiring structure 17 has conductive layers 71, 72, 73, and 74 that extend substantially parallel to the surface of the semiconductor substrate 11. The multilayer wiring structure 17 has a laminate in which these multiple conductive layers 70 are stacked with insulating layers in between. Although only four conductive layers are shown in the figure, as mentioned above, many more layers, such as 33 layers and 65 layers, are stacked. These multiple conductive layers 70 in the contact region HUR correspond to wiring drawn from the source-side select gate line, word line, or drain-side select gate line.

[0030] In the contact region HUR, conductive layers 71, 72, 73, and 74 corresponding to wiring drawn from select gate lines or word lines are formed in a stepped structure so as to expose a portion of the underlying conductive layer. Conductive layers 71, 72, 73, and 74 are connected to corresponding contact plugs 51, 52, 53, and 54 (referred to as contact plug 50 when contact plugs 51 to 54 are not distinguished) in the region exposed by the stepped structure. Here, conductive layer 71 is connected to contact plug 51, conductive layer 72 is connected to contact plug 52, conductive layer 73 is connected to contact plug 53, and conductive layer 74 is connected to contact plug 54. Although only four contact plugs 50 are shown in the figure, for example, the same number as the number of conductive layers may be arranged. Each contact plug 50 is drawn onto the laminated wiring structure 17 through a contact hole that penetrates an insulator (not shown). [Configuration of a stacked wiring structure] Figure 10 is a cross-sectional view showing the configuration of a multilayer wiring structure 17. The multilayer wiring structure 17 has an insulating layer 31, a conductive layer 71, an insulating layer 32, a conductive layer 72, an insulating layer 33, a conductive layer 73, an insulating layer 34, a conductive layer 74, an insulating layer 35, a conductive layer 75, an insulating layer 36, a conductive layer 76, an insulating layer 37, and a conductive layer 77 (where, when conductive layers 71 to 77 are not distinguished, they are referred to as conductive layer 70, and when insulating layers 31 to 37 are not distinguished, they are referred to as insulating layer 30) stacked on a semiconductor substrate 11. The multiple conductive layers 70 and the multiple insulating layers 30 are stacked alternately, one layer at a time, periodically in a direction perpendicular to the main surface of the semiconductor substrate 11 (stacking direction). An insulating layer 31 is also formed between the semiconductor substrate 11 and the bottommost conductive layer 71. An insulator 60 is formed on top of the topmost conductive layer 77. The insulator 60 may be thicker in the stacking direction than the insulating layers 31 to 37.

[0031] Each conductive layer 70 is a single layer. That is, when observing the cross-sectional shape of a single conductive layer 70, a single material may be continuous in the thickness direction (Z direction) of the conductive layer 70. Also, there does not need to be an interface inside a single conductive layer 70. Alternatively, the conductive layer 70 may consist of two layers: a barrier metal layer and a metal layer. The material of the conductive layer 70 may be, for example, tungsten. The barrier metal layer may be, for example, titanium nitride (TiN) or tantalum nitride (TaN). Adjacent conductive layers 70 in the stacking direction only need to be insulated from each other, and the material of the insulating layer 30 may be, for example, silicon dioxide (SiO2) or silicon oxide such as TEOS (Tetra Ethyl Ortho Silicate). The insulating layer 30 is deposited, for example, using a CVD (Chemical Vapor Deposition) apparatus.

[0032] Multiple conductive layers 70 and multiple insulating layers 30 are each formed in a stepped structure so as to expose a portion of the underlying conductive layer 70. An insulator 60 is formed on top of the stepped structure of the laminate, embedding the stepped structure. The material of the insulator 60 is, for example, silicon dioxide (SiO2), T Silicon oxide such as EOS (Tetra Ethyl Ortho Silicate) may also be used.

[0033] The insulator 60 has multiple contact holes CH1, CH2, CH3, CH4, CH5, CH6, and CH7 (where contact holes CH1 through CH7 are not distinguished and are referred to as contact holes CH) that expose a portion of the conductive layer 77 from the conductive layer 71. The contact holes CH are formed to penetrate the insulator 60 to the corresponding conductive layer 70. In a stepped structure, the contact holes CH expose the corresponding conductive layer 70 at the bottom. That is, each contact hole CH has a different depth from the top surface of the semiconductor device.

[0034] Contact plugs 51, 52, 53, 54, 55, 56, and 57 (here, when contact plugs 51 through 57 are not distinguished, they are referred to as contact plug 50) are formed in contact holes CH1 through CH7. Each contact plug 50 is connected to the corresponding conductive layer 70 at the bottom of the contact hole CH. Each contact plug 50 is drawn out onto the multilayer wiring structure 17 (on the opposite side from the substrate 11) through a contact hole CH that penetrates an insulator 60 placed on top of the corresponding conductive layer 70. Specifically, contact plug 51 is connected to the conductive layer 71 via contact hole CH1, contact plug 52 is connected to the conductive layer 72 via contact hole CH2, contact plug 53 is connected to the conductive layer 73 via contact hole CH3, contact plug 54 is connected to the conductive layer 74 via contact hole CH4, contact plug 55 is connected to the conductive layer 75 via contact hole CH5, contact plug 56 is connected to the conductive layer 76 via contact hole CH6, and contact plug 57 is connected to the conductive layer 77 via contact hole CH7. In other words, each contact hole CH and each contact plug 50 has a different length from the upper surface of the insulator 60. Although all contact plugs 50 are cylindrical, the shape of the contact plugs 50 is not particularly limited. The material of the contact plugs 50 may be a metal such as tungsten.

[0035] The contact region of the conductive layer 70 to which the contact plug 50 is connected may have a boundary 70a corresponding to the shape of the tip of the template that forms the contact hole CH. The boundary 70a may be located within each conductive layer 70 (between the top and bottom surfaces). Each contact plug 50 is connected at the boundary 70a of each conductive layer 70.

[0036] In the semiconductor device according to this embodiment, the stacked wiring structure has contact plugs 50 connected at the boundary 70a of the conductive layer 70, which increases the contact area between the contact plugs 50 and the conductive layer 70, thereby further improving the reliability of the semiconductor device. [Manufacturing method for stacked wiring structures] Referring to Figures 11 to 14, the method for manufacturing a stacked wiring structure of a semiconductor device according to this embodiment, particularly the method for forming the pattern of the stacked wiring structure, will be described. Although Figures 11 to 14 show an example in which contact holes CH and contact plugs 50 of different depths are formed in the left-right direction of the paper, the method for manufacturing a stacked wiring structure of a semiconductor device according to this embodiment can also be applied in the depth direction of the paper.

[0037] As shown in Figure 11, a laminate is prepared by sequentially depositing insulating layer 31, conductive layer 71, insulating layer 32, conductive layer 72, insulating layer 33, conductive layer 73, insulating layer 34, conductive layer 74, insulating layer 35, conductive layer 75, insulating layer 36, conductive layer 76, insulating layer 37, and conductive layer 77 on a semiconductor substrate 11. The manufacturing method of the laminate is not particularly limited. The alternately stacked insulating layers 30 and conductive layers 70 are formed to be in contact with each other. Multiple conductive layers 70 and multiple insulating layers 30 are each formed in a stepped structure so as to expose a portion of the underlying conductive layer 70. Contact plugs 50, described later, are connected to the contact areas where the conductive layer 70 is exposed in the stepped structure. In this embodiment, the material of the insulating layer 30 is exemplified as a TEOS film, but the material of the insulating layer 30 is not limited to this, and may be, for example, silicon dioxide (SiO2). Although tungsten is used as an example for the conductive layer 70, the conductive layer 70 is not limited to this. For example, it may be a sacrificial layer before being replaced by a conductive layer in a known semiconductor device manufacturing method, and may be silicon nitride (SiN) or silicon. In this embodiment, the laminate is shown as having a stepped structure, but is not limited to this. The laminate may have a power-law contact structure in which insulating layers 30 and conductive layers 70 of approximately the same size are alternately stacked horizontally behind the semiconductor substrate 11, and the conductive layer 70 may be a sacrificial layer before being replaced by a conductive layer. In this case, the laminate is processed together with the processing of the insulator 60, which will be described later, and the contact 50 penetrates the conductive layer 70.

[0038] An insulator 60 is formed on top of the laminate so as to cover the stepped structure of the laminate. The material of the insulator 60 may be, for example, silicon oxide.

[0039] As shown in Figure 12, an insulator 80 is applied on top of an insulator 60. The material of the insulator 80 is, for example, a resist, but it may also be a thermosetting resin or a photocurable resin. Alternatively, a film such as a hard mask may be formed between the insulator 60 and the insulator 80. A pattern of contact holes CH1, CH2, CH3, CH4, CH5, CH6, and CH7 is formed on the applied insulator 80 by nanoimprint lithography. The upper surface of the insulator 80 is partially flattened and partially patterned by nanoimprint lithography. For nanoimprint lithography, a template 1 is used, which has a flat bottom surface E and multiple protrusions H with different heights (gradations) on the bottom surface E. The multiple protrusions H of the template 1 each have different heights (gradations), with the sum of the thicknesses of one layer each of the insulating layer 30 and conductive layer 70 in the stacking direction as one unit. By pressing the template 1 onto the insulator 80, the upper surface of the insulator 80 is flattened, and a pattern of multiple contact holes CH of different depths is formed. It is preferable to press the template 1 so that the surface B of the template 1 (the surface opposite to the surface with the convex portion) and the lower surface of the semiconductor substrate 11 (the surface opposite to the surface with the laminate) are substantially parallel. The insulator 80 with the contact hole CH pattern pressed onto it may be cured, for example, by UV irradiation.

[0040] As shown in Figure 13, by demolding the template 1, the upper surface of the insulator 80 is flattened and a pattern of multiple contact holes CH of different depths is formed.

[0041] As shown in Figure 14, an insulator 60 is processed using an insulator 80 having a pattern of multiple contact holes CH of different depths as a mask. Parts of the insulator 80 and the insulator 60 may be removed by anisotropic etching, such as reactive ion etching (RIE). The pattern of multiple contact holes CH of different depths from the insulator 80 is transferred to the insulator 60. The formed contact holes CH1, CH2, CH3, CH4, CH5, CH6, and CH7 each have different depths from the top surface of the insulator 60. The bottom of the contact holes CH (contact region) exposes the conductive layer 70. At this time, along with the processing of the insulator 80 and the insulator 60, parts of the conductive layer 70 may also be removed. A pattern (recess) corresponding to the shape of the tip of the template that forms the contact holes CH may be formed in the conductive layer 70 of the contact region. However, it is not limited to this, and the conductive layer 70 may function as a stopper, exposing the flat top surface of the conductive layer 70.

[0042] A contact plug 50, as shown in Figure 10, is formed by embedding a metal (conductor), such as tungsten, in the contact hole CH that exposes the conductive layer 70 corresponding to the bottom.

[0043] In the manufacturing method of the stacked wiring structure of the semiconductor device according to this embodiment, contact holes CH of different depths (gradations) can be patterned on the insulator 60 in one step by nanoimprint lithography using the template 1 according to this embodiment, thereby improving manufacturing efficiency and accuracy. Since the template 1 according to this embodiment has an upper surface c of the convex portion H along a virtual plane (dashed line), stress is reduced when pressing the template 1, making alignment easier. Since the template 1 according to this embodiment has an upper surface c of the convex portion H along a virtual plane (dashed line), a pattern (recess) corresponding to the contact area of ​​the conductive layer 70 can be formed, and the contact area can be increased by fitting the contact plug 50, further improving the reliability and yield of the semiconductor device. <Second Embodiment> The template configuration according to this embodiment is the same as that of the template according to the first embodiment, except for the shape of the upper surface of the protrusions of the pattern. The method for forming the pattern of the template according to this embodiment is the same as that of the template according to the first embodiment up to forming a pattern 3 on the second layer 200 that has a recess D2 in the inclined portion C2. The configuration of the laminated wiring structure according to this embodiment is the same as that of the laminated wiring structure according to the first embodiment, except for the shape of the contact portion between the contact plug and the conductive layer. The method for manufacturing the laminated wiring structure according to this embodiment is the same as that of the laminated wiring structure according to the first embodiment, except for the shape of the contact portion between the contact plug and the conductive layer. Descriptions that are the same as the first embodiment will be omitted, and the parts that differ from the first embodiment will be described here. [Pattern composition] Figure 15 is a cross-sectional view showing the configuration of template 1a. Template 1a has a pattern 2a on its first surface A. Pattern 2a has a recess D in an inclined section C. The inclined section C has a virtual plane (dashed line) that intersects with the first surface A and the bottom surface E of the recess D. The shape of the virtual plane (dashed line) is substantially planar. The virtual plane (dashed line) of the inclined section C and the bottom surface E of the recess D may intersect at an acute angle. The bottom surface E and the first surface A are connected by a side wall G. The side wall G connects the bottom surface E and the first surface A substantially perpendicular to the first surface A and the second surface B.

[0044] The inclined portion C has a recess D. The recess D has a side surface F and a bottom surface E connecting the side surfaces F. The side surfaces F of the recess D connect to the top surface c2 substantially perpendicular to the first surface A and the second surface B. The bottom surface E of the recess D connects the side surfaces F of the recess D on a plane substantially parallel to the first surface A and the second surface B. In other words, pattern 2a has a plurality of protrusions Ha on the bottom surface E. The protrusions Ha have side surfaces F and top surfaces c2 connecting the side surfaces F. The side surfaces F of the protrusions Ha connect to the top surface c2 substantially perpendicular to the first surface A and the second surface B. At least a portion of the top surface c2 of the protrusions Ha is arranged along a virtual plane (dashed line). That is, the top surface c2 of the protrusions H is at the same height as the first surface A or lower than the first surface A. [Method for forming patterns] Referring to Figures 16 to 20, the method for manufacturing a template according to this embodiment, and in particular the method for forming the template pattern, will be described.

[0045] The method for forming the template pattern according to this embodiment is the same as the method for forming the template pattern according to the first embodiment (Figures 2 to 6) up to the point of forming a pattern 3 with a recess D2 in the inclined portion C2 on the second layer 200, so a repeated explanation will be omitted here.

[0046] As shown in Figure 16, a process (first etching) is performed to remove a portion of the first layer 100 using the second layer 200 having pattern 3 as a mask. The first layer 100 exposed by the recess D2 of pattern 3 is etched by the first etching. At this time, the second layer 200 is also reduced by the first etching. The first etching may be, for example, RIE using a fluorine-based reactive gas. The first etching is stopped before the lowest convex portion H2 of the inclined portion C2 is removed and the first layer 100 is exposed. That is, the first etching is stopped before the thinnest second layer 200 is removed and the first layer 100 is exposed.

[0047] As shown in Figure 17, the first layer 100 acts as a stopper to remove a portion of the second layer 200 which has pattern 3 (second etching). The second etching may be, for example, RIE using a chlorine-based reaction gas. The second etching removes the convex portion H2 at the lowest position of the inclined portion C2, exposing the first surface A of the first layer 100. That is, the second etching removes the thinnest part of the second layer 200, exposing the first surface A of the first layer 100. After the second layer 200 is removed, the convex portion h1 of the first layer 100 is formed.

[0048] As shown in Figure 18, the remaining second layer 200, which includes part of pattern 3, is used as a mask to remove a portion of the first layer 100 again (first etching). The first layer 100 exposed by the recess D2 of pattern 3 is etched by the first etching. The protrusion h1 after the removal of the second layer 200 is also etched by the first etching approximately parallel to the first surface A. At this time, the second layer 200 is also reduced by the first etching. The first etching is stopped before the second lowest protrusion H2 of the inclined portion C2 is removed and the first layer 100 is exposed. That is, the first etching is stopped before the second thinnest second layer 200 is removed and the first layer 100 is exposed.

[0049] As shown in Figure 19, a process (second etching) is performed to remove a portion of the remaining second layer 200 that includes part of pattern 3. The second etching removes the second lowest convex portion H2 of the inclined portion C2, exposing the first surface A of the first layer 100. In other words, the second etching removes the second thinnest second layer 200, exposing the first surface A of the first layer 100. After the second layer 200 is removed, the convex portion h2 of the first layer 100 is formed.

[0050] As shown in Figure 20, by repeating the first etching and the second etching for the number of gradations of pattern 3, a pattern 2a with recesses D in inclined portions C determined by the processing speeds of the first layer 100 and the second layer 200 is transferred to surface A of the first layer 100. For example, if the processing speed of the first layer 100 is greater than that of the second layer 200, the angle θ between the bottom surface E of the recess D and the inclined portion C will be greater than the angle θ2 between the surface 202 of the second layer 200 and the inclined portion C2, and the depth of the recess D from surface A to bottom surface E will be greater than the depth of the recess D2 from surface 201 to surface 202. In other words, a pattern 2a having protrusions Ha of different heights on the bottom surface E can be formed by extending pattern 3 in the stacking direction. The thickness of the second layer 200 and the angle θ2 (number of gradations of pattern 3) between the surface 202 of the second layer 200 and the inclined portion C2 are appropriately set by the processing speed of the first layer 100 and the second layer 200 in the first etching, the arrangement of the recesses D or protrusions Ha of pattern 2a, the angle θ (number of gradations of pattern 2a) between the bottom surface E of the recess D and the inclined portion C, the height from the bottom surface E to surface A (height of pattern 2a), the depth of the recess D from surface A to bottom surface E (depth of pattern 2a), the control accuracy of the processing amount of the first layer 100 in the first etching, the processing speed of the first layer 100 and the second layer 200 in the second etching, and the processing amount buffer of the second layer 200 in the second etching. Subsequently, the template 1a shown in Figure 15 can be manufactured by peeling off the remaining second layer 200.

[0051] In the template manufacturing method according to this embodiment, the formation efficiency and accuracy of a pattern 2a having multiple protrusions Ha of different heights (gradations) on the bottom surface E of a recess D can be improved. [Configuration of a stacked wiring structure] Figure 21 is a cross-sectional view showing the configuration of the laminated wiring structure. The configuration of the laminated wiring structure according to this embodiment is the same as that of the laminated wiring structure according to the first embodiment, except for the shape of the contact portion between the contact plug and the conductive layer, so a repeated explanation will be omitted here.

[0052] The multilayer wiring structure 17 has multiple conductive layers 70 and multiple insulating layers 30 stacked on a semiconductor substrate 11. The multiple conductive layers 70 and the multiple insulating layers 30 are stacked alternately, one layer at a time, periodically in a direction perpendicular to the main surface of the semiconductor substrate 11 (the stacking direction). An insulating layer 31 is also formed between the semiconductor substrate 11 and the bottommost conductive layer 71. An insulator 60 is formed on top of the topmost conductive layer 77. Each of the multiple conductive layers 70 and the multiple insulating layers 30 is formed in a stepped structure so as to expose a portion of the underlying conductive layer 70. An insulator 60 is formed on top of the stepped structure of the stack, embedding the stepped structure.

[0053] The insulator 60 has multiple contact holes CH formed therein, exposing a portion of the conductive layer 77 from the conductive layer 71. The contact holes CH penetrate the insulator 60 to the corresponding conductive layer 70. In a stepped structure, the contact holes CH expose the corresponding conductive layer 70 at the bottom. That is, each contact hole CH has a different depth from the top surface of the semiconductor device.

[0054] A contact plug 50 is formed in the contact hole CH. The contact plug 50 is connected to the corresponding conductive layer 70 at the bottom of the contact hole CH. Each contact plug 50 is drawn out onto the multilayer wiring structure 17 (on the opposite side from the substrate 11) through the contact hole CH that penetrates the insulator 60 placed on top of the corresponding conductive layer 70. Each contact hole CH and each contact plug 50 has a different length from the top surface of the insulator 60. The contact plugs 50 are connected to the contact areas of the conductive layer 70. Each contact plug 50 is connected to the top surface of the respective conductive layer 70.

[0055] In this embodiment, the stacked wiring structure of the semiconductor device has a contact plug 50 connected to the upper surface of the conductive layer 70, thereby improving the reliability of the semiconductor device. [Manufacturing method for stacked wiring structures] Referring to Figures 22 to 25, the manufacturing method of the laminated wiring structure of the semiconductor device according to this embodiment, particularly the pattern formation method of the laminated wiring structure, will be described. The manufacturing method of the laminated wiring structure according to this embodiment is the same as the configuration of the laminated wiring structure according to the first embodiment, except for the shape of the contact portion between the contact plug and the conductive layer, so a repeated explanation will be omitted here.

[0056] As shown in Figure 22, a laminate is prepared on a semiconductor substrate 11 by alternately depositing conductive layers 70 and insulating layers 30. The alternately stacked insulating layers 30 and conductive layers 70 are formed to be in contact with each other. Each of the multiple conductive layers 70 and multiple insulating layers 30 is formed in a stepped structure so as to expose a portion of the underlying conductive layer 70. Contact plugs 50, described later, are connected to the contact areas where the conductive layer 70 is exposed in the stepped structure. An insulator 60 is formed on top of the laminate so as to cover the stepped structure of the laminate.

[0057] As shown in Figure 23, an insulator 80 is applied on top of an insulator 60. A pattern of contact holes CH1, CH2, CH3, CH4, CH5, CH6, and CH7 is formed on the applied insulator 80 by nanoimprint lithography. The upper surface of the insulator 80 is partially flattened and partially patterned by nanoimprint lithography. For nanoimprint lithography, a template 1a is used, which has a flat bottom surface E and multiple protrusions Ha of different heights (gradations) on the bottom surface E. The multiple protrusions Ha of the template 1a each have different heights (gradations), with the sum of the thicknesses of one layer each of the insulating layer 30 and conductive layer 70 in the stacking direction as one unit. By pressing the template 1a onto the insulator 80, the upper surface of the insulator 80 is flattened and a pattern of multiple contact holes CH of different depths is formed. It is preferable to press the template 1a so that the surface B of the template 1a (the surface opposite to the surface with the protrusions) and the lower surface of the semiconductor substrate 11 (the surface opposite to the surface with the laminates) are substantially parallel. The insulator 80 on which the contact hole CH pattern is pressed may be cured, for example, by UV irradiation.

[0058] As shown in Figure 24, by demolding the template 1a, the upper surface of the insulator 80 is flattened and a pattern of multiple contact holes CH of different depths is formed.

[0059] As shown in Figure 25, the insulator 60 is processed using an insulator 80 having a pattern of multiple contact holes CH of different depths as a mask. Parts of the insulator 80 and the insulator 60 may be removed by anisotropic etching such as RIE. The pattern of multiple contact holes CH of different depths from the insulator 80 is transferred to the insulator 60. The formed contact holes CH1, CH2, CH3, CH4, CH5, CH6, and CH7 each have different depths from the top surface of the insulator 60. The bottom of the contact holes CH (contact area) exposes the top surface of the conductive layer 70.

[0060] A contact plug 50, as shown in Figure 21, is formed by embedding a metal such as tungsten in the contact hole CH that exposes the conductive layer 70 corresponding to the bottom.

[0061] In the manufacturing method of the stacked wiring structure of the semiconductor device according to this embodiment, contact holes CH of different depths (gradations) can be patterned on the insulator 60 in one step by nanoimprint lithography using the template 1a according to this embodiment, thereby improving manufacturing efficiency and accuracy. Since the template 1a according to this embodiment has an upper surface c of a convex portion H that is substantially parallel to the contact area of ​​the conductive layer 70, good contact can be achieved, thereby improving the reliability of the semiconductor device. <Third Embodiment> The template configuration according to this embodiment is the same as that of the template configuration according to the second embodiment. The method for forming the pattern of the template according to this embodiment is the same as that of the template configuration according to the second embodiment, except that the second layer 200 includes the first film 210 and the second film 220. The configuration of the stacked wiring structure according to this embodiment is the same as that of the stacked wiring structure according to the second embodiment. The method for manufacturing the stacked wiring structure according to this embodiment is the same as that of the stacked wiring structure according to the second embodiment. Descriptions that are the same as the first and second embodiments will be omitted, and here we will describe the parts that differ from the first and second embodiments. [Method for forming patterns] Referring to Figures 26 to 36, the method for manufacturing a template according to this embodiment, particularly the method for forming the template pattern, will be described. Although Figures 26 to 36 show an example of forming protrusions H of different heights in the left-right direction of the paper, the method for forming pattern 2a according to this embodiment can also be applied to the depth direction of the paper.

[0062] As shown in Figure 26, a laminate is prepared in which a first layer 100, a second layer 200, and a third layer 300 are stacked in this order. The method for manufacturing the laminate is not particularly limited. The first layer 100, the second layer 200, and the third layer 300 are formed to be in contact with each other. The second layer 200 includes a first film 210 in contact with the first layer 100 and a second film 220 in contact with the first film 210. In this embodiment, the first film 210 only needs to function as a hard mask, and the material of the first film 210 may be, for example, a metal compound containing chromium or tantalum. The second film 220 also needs to function as a hard mask, and the material of the second film 220 may be, for example, a compound containing carbon or silicon.

[0063] An inclined portion C3 is formed on the surface 301 of the third layer 300 that is in contact with the second layer 220 and is opposite to the second layer 220. The method for forming the inclined portion C3 is the same as in the second embodiment and is therefore omitted here.

[0064] As shown in Figure 27, the second film 220 of the second layer 200 is processed using the third layer 300, which has an inclined portion C3, as a mask. The inclined portion C2, which is determined by the processing speed of the third layer 300 and the second film 220, is transferred to the second film 220. For example, if the processing speed of the third layer 300 is higher than that of the second film 220, the angle θ2 between the surface 222 of the second film 220 that is in contact with the first film 210 and the inclined portion C2 will be smaller than the angle θ3 between the surface 302 of the third layer 300 that is in contact with the second layer 200 and the inclined portion C3. For example, if the processing speed of the second film 220 is higher than that of the third layer 300, the angle θ2 between the surface 222 of the second film 220 and the inclined portion C2 will be larger than the angle θ3 between the surface 302 of the third layer 300 and the inclined portion C3.

[0065] As shown in Figure 28, a fourth layer 400 is formed on the second film 220 which has an inclined portion C2, so as to fill the inclined portion C2.

[0066] As shown in Figure 29, a recess D4 is formed on the surface 401 of the fourth layer 400 that is in contact with the second layer 220 and is opposite to the second layer 220. The recess D4 is formed on the inclined portion C2 of the second layer 220, with the inclined portion C2 acting as a stopper. The recess D4 exposes the inclined portion C2 of the second layer 220.

[0067] As shown in Figure 30, the second film 220 is processed using the fourth layer 400, which has a recess D4, as a mask. The recess D2 is transferred to the inclined portion C2 of the second film 220, with the first film 210 acting as a stopper, and a pattern 3 having the recess D2 in the inclined portion C2 is formed. The first film 210 is exposed at the bottom of the recess D2. The thickness of the fourth layer 400 is appropriately set depending on the processing speed of the fourth layer 400 and the second film 220 and the thickness of the second film 220. After that, the remaining fourth layer 400 is peeled off. The pattern forming method according to this embodiment makes it possible to form a pattern 3 having protrusions H2 of different heights on the first film 210 by forming a recess D2 in the inclined portion C2 of the second film 220.

[0068] As shown in Figure 31, the first film 210 is processed using the second film 220, which has pattern 3, as a mask. The first film 210 exposed by the recess D2 of pattern 3 is removed by etching with the first layer 100 as a stopper. At this time, the second film 220 is also reduced by etching. The amount of the first film 210 processed in this etching is greater than the amount of the second film 220 processed. That is, the processing speed of the first film 210 in this etching is greater than that of the second film 220. By partially removing the first film 210, the first layer 100 is exposed below the recess D2 of pattern 3.

[0069] As shown in Figure 32, a process (first etching) is performed to remove a portion of the first layer 100 using the second film 220 having pattern 3 as a mask. The first layer 100 exposed by the recess D2 of pattern 3 is etched by the first etching. At this time, the second film 220 is also reduced by the first etching. The first etching may be, for example, RIE using a fluorine-based reactive gas. The first etching removes the convex portion H2 at the lowest position of the inclined portion C2, exposing the first film 210. That is, the thinnest part of the second film 220 is removed by the first etching, exposing the first film 210. The amount of processing of the second film 220 in the first etching is greater than the amount of processing of the first film 210. That is, the processing speed of the second film 220 in the first etching is greater than that of the first film 210.

[0070] As shown in Figure 33, the first layer 100 is used as a stopper to remove the first film 210 exposed by the first etching (third etching). The amount of the first film 210 processed in the third etching is greater than the amount of the second film 220 processed. That is, the processing speed of the first film 210 in the third etching is greater than that of the second film 220. The amount of the first film 210 processed in the third etching is greater than the amount of the first layer 100 processed. That is, the processing speed of the first film 210 in the third etching is higher than that of the first layer 100. The third etching may be, for example, RIE using a chlorine-based reaction gas. The first film 210 exposed by the first etching is removed by the third etching, and the first surface A of the first layer 100 is exposed. After the first film 210 is removed, a protrusion h1 of the first layer 100 is formed.

[0071] As shown in Figure 34, the remaining second film 220, which includes part of pattern 3, is used as a mask to remove a portion of the first layer 100 again (first etching). The first layer 100 exposed by the recess D2 of pattern 3 is etched by the first etching. The protrusion h1 after the removal of the first film 210 is also etched by the first etching approximately parallel to the first surface A. At this time, the second film 220 is also reduced by the first etching. The first etching removes the second lowest protrusion H2 of the inclined portion C2, exposing the first film 210. That is, the first etching removes the second thinnest second film 220, exposing the first film 210.

[0072] As shown in Figure 35, the first layer 100 acts as a stopper to remove the first film 210 exposed by the first etching (third etching). The third etching removes the first film 210 exposed by the first etching, exposing the first surface A of the first layer 100. After the first film 210 is removed, a protrusion h2 is formed on the first layer 100.

[0073] As shown in Figure 36, by repeating the first etching and the third etching for the number of gradations of pattern 3, a pattern 2a with recesses D in inclined portions C determined by the processing speed of the first layer 100 and the second film 220 is transferred to surface A of the first layer 100. For example, if the processing speed of the first layer 100 is greater than that of the second film 220, the angle θ between the bottom surface E of the recess D and the inclined portion C will be greater than the angle θ2 between the surface 222 of the second film 220 and the inclined portion C2, and the depth of the recess D from surface A to bottom surface E will be greater than the depth of the recess D2 from surface 221 to surface 222. In other words, a pattern 2a having protrusions Ha of different heights on the bottom surface E can be formed by extending pattern 3 in the stacking direction. The thickness of the second film 220 and the angle θ2 (number of gradations of pattern 3) between the surface 222 of the second film 220 and the inclined portion C2 are appropriately set by the processing speed of the first layer 100 and the second film 220 in the first etching, the arrangement of the recesses D or protrusions Ha of pattern 2a, the angle θ (number of gradations of pattern 2a) between the bottom surface E of the recess D and the inclined portion C, the height from the bottom surface E to surface A (height of pattern 2a), the depth of the recess D from surface A to bottom surface E (depth of pattern 2a), the control accuracy of the processing amount of the first layer 100 in the first etching, the processing speed of the first layer 100, the first film 210 and the second film 220 in the third etching, and the processing amount buffer of the second film 220 in the third etching. Subsequently, the template 1a shown in Figure 15 can be manufactured by peeling off the remaining first film 210 and the second film 220.

[0074] In the template manufacturing method according to this embodiment, the formation efficiency and accuracy of a pattern 2a having multiple protrusions Ha of different heights (gradations) on the bottom surface E of a recess D can be improved. <Fourth Embodiment> The template configuration according to this embodiment is the same as that of the template configuration according to the second embodiment. The method for forming the pattern of the template according to this embodiment is the same as that of the template configuration according to the third embodiment, except for the method for forming the pattern of the second film 220. The configuration of the stacked wiring structure according to this embodiment is the same as that of the stacked wiring structure according to the second embodiment. The method for manufacturing the stacked wiring structure according to this embodiment is the same as that of the stacked wiring structure according to the second embodiment. Descriptions that are the same as those of the first to third embodiments will be omitted, and here we will describe the parts that differ from the first to third embodiments. [Method for forming patterns] Referring to Figures 37 to 42, the method for manufacturing a template according to this embodiment, particularly the method for forming the template pattern, will be described. Although Figures 37 to 42 show an example of forming protrusions H of different heights in the left-right direction of the paper, the method for forming the pattern 2a according to this embodiment can also be applied to the depth direction of the paper.

[0075] As shown in Figure 37, a laminate is prepared in which a first layer 100, a second layer 200, and a fourth layer 400 are stacked in this order. The method for manufacturing the laminate is not particularly limited. The first layer 100, the second layer 200, and the fourth layer 400 are formed so as to be in contact with each other. The second layer 200 includes a first film 210 in contact with the first layer 100 and a second film 220 in contact with the first film 210.

[0076] As shown in Figure 38, a recess D4 is formed on the surface 401 of the fourth layer 400 that is in contact with the second layer 220 and is opposite to the second layer 220. The recess D4 is formed on the second layer 220, with the second layer 220 acting as a stopper. The recess D4 exposes the second layer 220.

[0077] As shown in Figure 39, the second film 220 is processed using the fourth layer 400, which has a recess D4, as a mask. The recess D2 is transferred to the second film 220 using the first film 210 as a stopper. The first film 210 is exposed at the bottom of the recess D2. The thickness of the fourth layer 400 is appropriately set by the processing speed of the fourth layer 400 and the second film 220, and the thickness of the second film 220. After that, the remaining fourth layer 400 is peeled off.

[0078] As shown in Figure 40, a third layer 300 is formed on the second film 220 which has a recess D2, so as to fill the recess D2.

[0079] As shown in Figure 41, an inclined portion C3 is formed on the surface 301 of the third layer 300 that is in contact with the second layer 220 and is opposite to the second layer 220. The method for forming the inclined portion C3 is the same as in the second embodiment and is therefore omitted here.

[0080] As shown in Figure 42, a second film 220 having a recess D2 is processed using a third layer 300 having an inclined portion C3 as a mask. The inclined portion C2, determined by the processing speed of the third layer 300 and the second film 220, is transferred to the second film 220, forming a pattern 3 with the inclined portion C2 in the recess D2. For example, if the processing speed of the third layer 300 is higher than that of the second film 220, the angle θ2 between the surface 222 of the second film 220 that is in contact with the first film 210 and the inclined portion C2 will be smaller than the angle θ3 between the surface 302 of the third layer 300 that is in contact with the second film 220 and the inclined portion C3. For example, if the processing speed of the second film 220 is higher than that of the third layer 300, the angle θ2 between the surface 222 of the second film 220 and the inclined portion C2 will be larger than the angle θ3 between the surface 302 of the third layer 300 and the inclined portion C3. In this embodiment, the pattern forming method allows for the formation of a pattern 3 having protrusions H2 of different heights on the first film 210 by forming an inclined portion C2 in the recess D2 of the second film 220.

[0081] As shown in Figure 43, the first film 210 is processed using the second film 220, which has pattern 3, as a mask. The first film 210 exposed by the recess D2 of pattern 3 is removed by etching with the first layer 100 as a stopper. At this time, the second film 220 is also reduced by etching. The amount of the first film 210 processed in this etching is greater than the amount of the second film 220 processed. That is, the processing speed of the first film 210 in this etching is greater than that of the second film 220. By partially removing the first film 210, the first layer 100 is exposed below the recess D2 of pattern 3.

[0082] The method for forming a pattern 2a on surface A of the first layer 100, which includes a recess D in an inclined portion C determined by the processing speed of the first layer 100 and the second film 220, is the same as the method for forming the pattern of the template according to the third embodiment (Figures 30 to 34), so a repeated explanation is omitted here. By peeling off the remaining first film 210 and second film 220, the template 1a shown in Figure 14 can be manufactured.

[0083] In the template manufacturing method according to this embodiment, the formation efficiency and accuracy of a pattern 2a having multiple protrusions Ha of different heights (gradations) on the bottom surface E of a recess D can be improved.

[0084] Although the present invention has been described above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, a semiconductor device based on this embodiment, to which a person skilled in the art has added, deleted, or modified components as appropriate, is also included in the scope of the present invention as long as it retains the gist of the present invention. Furthermore, the embodiments described above can be combined as appropriate as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even if they are not explicitly described.

[0085] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0086] 1: Template, 2: Pattern, 3: Pattern, 10: Semiconductor device, 11: Semiconductor substrate, 16: Memory cell array, 17: Stacked wiring structure, 18: Peripheral circuit, 19: Pad row, 30: Insulating layer, 40: Memory pillar, 50: Contact plug, 60: Insulator, 70: Conductive layer, 70a: Recess, 100: First layer, 200: Second layer, 210: First film, 220: Second film, 300: Third layer, 400: Fourth layer

Claims

1. A first pattern is formed on the side of the second layer provided on the first layer that is opposite to the first layer, comprising a first inclined portion and a plurality of first recesses that expose a part of the first layer provided in the first inclined portion. The method includes performing a first etching using the second layer as a mask to remove the first layer exposed by the plurality of first recesses and a part of the second layer, thereby forming a second pattern comprising a second inclined portion on which the first pattern is transferred and a plurality of second recesses provided in the second inclined portion, Forming the plurality of first recesses in the first pattern is A second resin layer is formed on the second layer having the first inclined portion, exposing a portion of the second layer and having a plurality of recesses of different depths. Using the second resin layer as a mask, the second layer exposed by the plurality of recesses is removed. A pattern formation method that includes the following.

2. Forming the two patterns described above is The first layer, which is exposed by the removal of the second layer by the first etching, is removed. The pattern forming method according to claim 1, further comprising the following:

3. Forming the two patterns described above is The first etching is stopped before the second layer at the lowest position of the first inclined portion is removed by the first etching, The second etching process is performed until the second layer at the lowest position of the first inclined portion is removed and the first layer is exposed. The pattern forming method according to claim 1, further comprising repeating the first etching and the second etching.

4. The pattern forming method according to claim 3, wherein the first pattern is determined by one or more of the following: the processing speed of the first layer and the second layer in the first etching, the arrangement of the second pattern, the angle between the bottom surface of the first layer and the second inclined portion of the second pattern, the height of the second pattern, the depth of the second pattern, and the amount of processing of the second layer in the second etching.

5. Forming the first inclined portion of the first pattern is A first resin layer having an inclination is formed on the second layer. The inclination is transferred to the second layer to form the first inclined portion. A pattern forming method according to claim 1, including the following:

6. A first pattern is formed on the surface of a first layer provided on a substrate that is opposite to the substrate, the first pattern comprising a first inclined portion and a plurality of first recesses that expose a part of the substrate provided in the first inclined portion. The method includes performing a first etching using the first layer as a mask to remove the substrate exposed by the plurality of first recesses and a part of the first layer, thereby forming a second pattern on the substrate comprising a second inclined portion on which the first pattern is transferred and a plurality of second recesses provided in the second inclined portion, Forming the plurality of first recesses in the first pattern is A second resin layer is formed on the first layer having the first inclined portion, exposing a portion of the first layer and having a plurality of recesses of different depths. Using the second resin layer as a mask, the first layer exposed by the plurality of recesses is removed. A method for manufacturing templates, including the following.

7. The method for forming the first pattern includes: forming a first pattern on a substrate on the side of the first layer opposite to the substrate, comprising a first inclined portion and a plurality of first recesses that expose a portion of the substrate provided in the first inclined portion; performing a first etching using the first layer as a mask to remove the substrate exposed by the plurality of first recesses and a portion of the first layer, thereby forming a second pattern on the substrate comprising a second inclined portion and a plurality of second recesses provided in the second inclined portion, wherein forming the plurality of first recesses of the first pattern involves forming a second resin layer on the first layer comprising the first inclined portion, exposing a portion of the first layer and having a plurality of recesses of different depths, and using the second resin layer as a mask to remove the first layer exposed by the plurality of recesses; and preparing a template manufactured using such a pattern forming method and a laminate on a semiconductor substrate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. An insulator is applied to cover the laminate, By pressing the template, a first hole is formed in the insulator that exposes one of the plurality of conductive layers, and a second hole is formed that has a different depth from the first hole and exposes another of the plurality of conductive layers. To form a conductor in the first hole and the second hole, A method for manufacturing a semiconductor device containing [a specific component].

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