Indication device

Abstract

To provide a semiconductor device with high reliability, in which a back plate is formed of an oxide semiconductor film.SOLUTION: A semiconductor device includes a first conductive film, a first insulating film on the first conductive film, an oxide semiconductor film overlapping with the first conductive film on the first insulating film, a second insulating film on the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film in an opening of the second insulating film. The second insulating film overlaps with a region of the oxide semiconductor film where carriers flow between the pair of second conductive films, and an end part of the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof .

Background Art

[0002] Attention has been focused on metal oxides that exhibit semiconductor characteristics, called oxide semiconductors. Metal oxides are used in various applications. For example, indium oxide, which is a well-known metal oxide, is used for pixel electrodes having translucency in liquid crystal display devices and light-emitting devices. As metal oxides that exhibit semiconductor characteristics, there are, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors that use such metal oxides that exhibit semiconductor characteristics in a channel formation region are already known (Patent Document 1 and Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] ​​ Semiconductors using transistors with channel formation regions in oxide semiconductor films as backplanes One major challenge in mass-producing the device is improving reliability. One aspect of the present invention is: To provide a highly reliable semiconductor device in which the backplane is fabricated from an oxide semiconductor film, This will be one of the challenges.

[0005] Furthermore, one aspect of the present invention aims to provide a novel semiconductor device and the like. The description of these problems does not preclude the existence of other problems. Furthermore, one aspect of the present invention is: It is not necessarily required to solve all of these issues. Other issues are detailed below. This will become clear from the description in the document, drawings, and claims, etc. It is possible to extract other issues from the descriptions in the sections and other documents. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present invention comprises a first conductive film and a first insulating film on the first conductive film. A border film, an oxide semiconductor film that overlaps with the first conductive film on the first insulating film, and the A second insulating film on an oxide semiconductor film, and the oxidation in the openings of the second insulating film The material comprises a pair of second conductive films electrically connected to a semiconductor film, wherein the second insulating film is Among the oxide semiconductor films mentioned above, a region in which carriers flow between a pair of the second conductive films and , overlapping with the edge of the oxide semiconductor film mentioned above.

[0007] Alternatively, a semiconductor device according to one aspect of the present invention comprises a first conductive film and a first conductive film on the first conductive film. A first insulating film and an oxide semiconductor film that overlaps the first conductive film on the first insulating film. And, the second insulating film on the oxide semiconductor film and the openings in the second insulating film A pair of second conductive films electrically connected to the oxide semiconductor film, and the second insulating film and A pair of the above-mentioned second conductive films, a third insulating film containing an oxide, and a nitride on the third insulating film The second insulating film comprises a fourth insulating film containing a material, and the second insulating film is made up of one of the oxide semiconductor films. A region in which carriers flow between the pair of the second conductive films, and the edge of the oxide semiconductor film It overlaps with it.

[0008] Alternatively, a semiconductor device according to one aspect of the present invention comprises a first conductive film and a first conductive film on the first conductive film. A first insulating film and an oxide semiconductor film that overlaps the first conductive film on the first insulating film. And, a second insulating film on the oxide semiconductor film and a first opening in the second insulating film A pair of second conductive films electrically connected to the oxide semiconductor film, and the second insulating film A film and a pair of the second conductive films, a third insulating film containing an oxide, and on the third insulating film A fourth insulating film containing a nitride, and an oxide semiconductor film overlapping the oxide semiconductor film on the fourth insulating film. The second insulating film comprises a third conductive film and a pair of oxide semiconductor films. The region in which carriers flow between the second conductive films overlaps with the edge of the oxide semiconductor film. Furthermore, the third conductive film has the second openings of the first insulating film to the fourth insulating film. In this, the first conductive film is electrically connected, and the pair of second conductive films are located In a region different from the region, the edge of the oxide semiconductor film is on the first insulating film or above. It overlaps with the third conductive film via the fourth insulating film.

[0009] Furthermore, in one aspect of the present invention, the semiconductor device is made of the oxide semiconductor film In, Ga, and It may contain zinc.

[0010] Furthermore, in one aspect of the present invention, the semiconductor device is a CAAC-OS film in which the oxide semiconductor film is That's fine too. [Effects of the Invention]

[0011] According to one aspect of the present invention, a backplane is fabricated from an oxide semiconductor film, providing high reliability. We can provide semiconductor devices.

[0012] Furthermore, according to one aspect of the present invention, a novel semiconductor device and the like can be provided. The description of these effects does not preclude the existence of other effects. Furthermore, one aspect of the present invention is: It is not necessarily required to have all of these effects. Other effects are described in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims From descriptions such as these, it is possible to extract other effects. [Brief explanation of the drawing]

[0013] [Figure 1] A diagram showing the configuration of a transistor. [Figure 2] A diagram showing the configuration of a transistor. [Figure 3] A diagram showing the configuration of a transistor. [Figure 4] A diagram showing the configuration of a transistor. [Figure 5] Top view of a pixel. [Figure 6] Cross-sectional view of a pixel. [Figure 7] A diagram showing the configuration of a display device. [Figure 8] A diagram showing a cross-section of a transistor and the connection configuration between conductive films. [Figure 9] A diagram showing a cross-sectional view of a pixel, a cross-section of a transistor, and the connection configuration between conductive films. [Figure 10] A diagram illustrating the method for fabricating a semiconductor device. [Figure 11] A diagram illustrating the method for fabricating a semiconductor device. [Figure 12] A diagram illustrating the method for fabricating a semiconductor device. [Figure 13] A diagram illustrating the method for fabricating a semiconductor device. [Figure 14] A diagram illustrating the method for fabricating a semiconductor device. [Figure 15] A diagram illustrating the method for fabricating a semiconductor device. [Figure 16] A diagram illustrating the method for fabricating a semiconductor device. [Figure 17] A diagram illustrating the method for fabricating a semiconductor device. [Figure 18] A diagram showing the configuration of a sequential circuit. [Figure 19] A schematic diagram illustrating the configuration of a sequential circuit. [Figure 20] A diagram showing the configuration of a shift register. [Figure 21] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 22] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 23] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 24] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 25] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 26] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 27] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 28] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 29] A schematic diagram illustrating the film deposition models for CAAC-OS and nc-OS. [Figure 30] A diagram illustrating InGaZnO4 crystals and pellets. [Figure 31]A schematic diagram illustrating the film deposition model of CAAC-OS. [Figure 32] Top view of a liquid crystal display device. [Figure 33] Cross-sectional view of a liquid crystal display device. [Figure 34] A diagram of an electronic device. [Figure 35] This figure shows the results of measuring the drain current ID(A) value for a transistor with respect to the gate voltage VG(V). [Figure 36] A diagram showing the transmittance values ​​of metal oxide films against wavelength. [Figure 37] A photograph showing an image displayed on a prototype liquid crystal display device. [Modes for carrying out the invention]

[0014] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the invention may have forms and characteristics that do not depart from the spirit and scope of the present invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0015] The source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to the region, or the source electrode connected to the semiconductor film mentioned above. Similarly, the transistor's Rain refers to a drain region which is part of the semiconductor film, or a region connected to the semiconductor film. It refers to the drain electrode. Similarly, "gate" refers to the gate electrode.

[0016] <Transistor Configuration Example 1> Figure 1 shows the specific configuration of a transistor 10 in a semiconductor device according to one aspect of the present invention. Let's look at an example. Figure 1(A) shows a top view of transistor 10. Note that in Figure 1(A), To clarify the layout of transistor 10, various insulating films such as the gate insulating film are used. It has been omitted. Also, the cross-sectional view along the dashed line Y1-Y2 in the top view shown in Figure 1(A) is shown in Figure 1(A). Figure 1(B) shows the cross-sectional view along the dashed line X1-X2, and Figure 1(C) shows the cross-sectional view along the dashed line X1-X2.

[0017] As shown in Figure 1, the transistor 10 has a gate electrode and a substrate 11 having an insulating surface. A conductive film 12 having the function of a gate insulating film, and a conductive film 1 having the function of a gate insulating film. An insulating film 13 located on 2, and an oxide semiconductor film overlapping the conductive film 12 on the insulating film 13. 14, an insulating film 15 on the oxide semiconductor film 14, and a source electrode or drain electrode It has a function, and in the openings 23 and 24 of the insulating film 15, oxide semiconductors are present. It has conductive films 16 and 17 that are electrically connected to the conductive film 14. In Figure 1, the insulating film 15 is composed of insulating film 15a and insulating film 15b, which are stacked in order. This provides examples of situations where this might occur.

[0018] Furthermore, the insulating film 15 is formed between the conductive film 16 and the conductive film 17 of the oxide semiconductor film 14. The region 18 through which carriers flow overlaps with the edge 19 of the oxide semiconductor film 14. Now, the example given is that all of the edges 19 of the oxide semiconductor film 14 overlap with the insulating film 15. A portion of the edge 19 of the oxide semiconductor film 14 may overlap with the insulating film 15.

[0019] Region 18 and edge 19 overlap with insulating film 15 to form conductive film 16 and conductive film 17. By etching or other means, the metal contained in conductive films 16 and 17 becomes an oxide semiconductor. This prevents contamination of the body membrane 14. Therefore, the transistor 10 caused by impurities This makes it possible to suppress the deterioration of electrical characteristics and provide highly reliable semiconductor devices.

[0020] Furthermore, in Figure 1, insulating film 20 and insulating film 17 are placed on insulating film 15, conductive film 16 and conductive film 17. 21 is arranged in a stacked manner. Transistor 10 is an insulating film 20 and an insulating film The film 21 may be included as a component. In Figure 1, a multilayer insulating film 20 and a single layer The example shows insulating film 21, but insulating film 20 can be a single layer insulating film or a stack of three or more layers. It may also be composed of an insulating film. Alternatively, the insulating film 21 may be made of two or more stacked insulating films. It's okay if it's structured that way.

[0021] As insulating films 15 and 20, compared to insulating film 21, they supply oxygen to the oxide semiconductor film 14. Insulating films with high absorption capacity, such as silicon oxide films and silicon oxide nitride films, which have insulating properties. A dielectric film (hereinafter referred to as an oxide insulating film) can be used. In addition, as the insulating film 21, Compared to the edge film 20, an insulating film with a higher ability to block oxygen, hydrogen, water, etc. is used. This can be achieved. The insulating film 15 and insulating film 20 are sandwiched between the insulating film 21 and the oxide semiconductor film 14. By stacking them, oxygen released from the insulating film 15 or insulating film 20 is absorbed by the oxide semiconductor film 14. It can be supplied efficiently. Also, by stacking the insulating film 21 with the oxide semiconductor film 14 This prevents the intrusion of hydrogen, water, and other substances into the oxide semiconductor film 14 from the outside.

[0022] For example, a nitride insulating film can be used as the insulating film 21. Nitride insulating films are acid In addition to its ability to block elements, hydrogen, water, etc., it also blocks alkali metals and alkaline earth metals. It has the ability to lock. The above nitride insulating film includes silicon nitride film, silicon oxide nitride film, and nitrogen Aluminum oxide film, aluminum nitride film, etc. can be used. By using the film as an insulating film 21, not only hydrogen and water, but also alkali metals and alkaline earth This prevents metal-like substances from being mixed into the oxide semiconductor film 14 from the outside.

[0023] Furthermore, an oxide insulating film having the ability to block oxygen, hydrogen, water, etc. is provided with insulating film 21 and It may also be used as an oxide insulating film having the ability to block oxygen, hydrogen, water, etc. For example, aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, acid Examples include yttrium oxide, yttrium oxidizate, hafnium oxide, and hafnium oxidizate. It is possible.

[0024] Therefore, by using insulating film 15, insulating film 20, and insulating film 21 having the above configuration, This further suppresses the degradation of the electrical characteristics of the converter 10 and provides a more reliable semiconductor device. This becomes possible.

[0025] Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Purified oxide semiconductors (purified Oxi) are achieved by reducing elemental defects. Because there are few carrier sources, type i (intrinsic semiconductor) It can be made to be as close as possible to type i (or body). Therefore, a highly purified oxide semiconductor can be produced. Transistors with a channel-forming region in the film have significantly low off-current and high reliability. Furthermore, the transistor in which a channel formation region is formed in the oxide semiconductor film has a threshold voltage. It tends to exhibit electrical characteristics where the voltage is positive (also known as normally-off characteristics).

[0026] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small current can be proven through various experiments. For example, if the channel width is 1 × 1 0 6 Even with a μm element and a channel length of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current normalized by the transistor channel width is 100 Hz A / μm or less. It can be seen that there is a capacitive element and a transistor are connected so that the current flows into the capacitive element or The off-current is measured using a circuit that controls the charge flowing out of a capacitive element with the transistor. The measurement was performed using a highly purified oxide semiconductor film as the channel of the transistor. Used in the formation region, the transistor's off state is determined from the change in the amount of charge per unit time of the capacitive element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In some cases, it was found that even smaller off-currents, such as tens of yA / μm, can be obtained. Therefore Therefore, transistors that use a highly purified oxide semiconductor film in the channel formation region are off-voltage. The current is significantly lower compared to transistors using crystalline silicon.

[0027] <Transistor Configuration Example 2> Next, another example of the configuration of the transistor 10 in a semiconductor device according to one aspect of the present invention This is shown in Figure 2. Figure 2(A) shows a top view of transistor 10. Note that in Figure 2(A) To clarify the layout of transistor 10, various insulating films such as gate insulating films are used. The following has been omitted. Also, the cross-sectional view along the dashed line Y1-Y2 in the top view shown in Figure 2(A) is Figure 2(B) shows the cross-sectional view along the dashed line X1-X2, and Figure 2(C) shows the cross-sectional view along the dashed line X1-X2.

[0028] The transistor 10 shown in Figure 2, like the transistor 10 shown in Figure 1, has an insulating surface. A conductive film 12 having the function of a gate electrode and a gate insulating film are placed on the substrate 11. An insulating film 13 that has a function and is located on the conductive film 12, and a conductive film 13 on the insulating film 13 A film 12 overlaps with an oxide semiconductor film 14, an insulating film 15 is on the oxide semiconductor film 14, and a source electric It has the function of an electrode or drain electrode, and the opening 23 and in the insulating film 15 And conductive films 16 and 16 that are electrically connected to the oxide semiconductor film 14 at the opening 24. It has a conductive film 17.

[0029] And the transistor 10 shown in Figure 2 is similar to the transistor 10 shown in Figure 1, in terms of insulating film. 15 indicates that carriers flow between the conductive film 16 and the conductive film 17 in the oxide semiconductor film 14. The region 18 overlaps with the edge 19 of the oxide semiconductor film 14. Note that in Figure 2, the oxide semiconductor The example shows the case where all of the edges 19 of the conductive film 14 overlap with the insulating film 15, but this is an oxide semiconductor. A portion of the edge 19 of the film 14 may overlap with the insulating film 15.

[0030] Region 18 and edge 19 overlap with insulating film 15 to form conductive film 16 and conductive film 17. By etching or other means, the metal contained in conductive films 16 and 17 becomes an oxide semiconductor. This prevents contamination of the body membrane 14. Also, the region 18 and the edge 19 are insulated from the insulating film 15. By overlapping, etching occurs when forming conductive film 16 and conductive film 17, affecting region 18 and the edges. This prevents the part 19 from being exposed to plasma. This prevents the region 18 and the end 19 This prevents oxygen from being released and forming an oxygen deficiency. Alternatively, region 18 and To prevent oxygen from easily detaching from the end 19 and creating a condition where oxygen deficiency is likely to form, This is possible. Therefore, the deterioration of the electrical characteristics of transistor 10 caused by impurities is suppressed. This makes it possible to provide highly reliable semiconductor devices.

[0031] Furthermore, in Figure 2, insulating film 20 and insulating film 17 are placed on insulating film 15, conductive film 16 and conductive film 17. 21 is provided so as to be stacked in order. The insulating film 15 and insulating film 20 are, Compared to 21, an insulating film with a higher capacity to supply oxygen to the oxide semiconductor film 14 can be used. It can do so. Also, as an insulating film 21, compared to insulating film 20, it blocks oxygen, hydrogen, water, etc. An insulating film with high conductivity can be used. With the above configuration, the electrical conductivity of transistor 10 This makes it possible to further suppress the deterioration of performance characteristics and provide a more reliable semiconductor device. .

[0032] Furthermore, the transistor 10 shown in Figure 2 has a conductive film 22 on the insulating film 21. The configuration differs from that of transistor 10 shown in Figure 1. The conductive film 22 is acid-treated on the insulating film 21. It is provided in a position that overlaps with the semiconductor film 14. Furthermore, the conductive film 22 is electrically connected to the conductive film 12. They are connected by gas. Specifically, in Figure 2, insulating film 13, insulating film 15, insulating film 20, and In the opening 25 provided in the insulating film 21, the conductive film 22 and the conductive film 12 are electrically in contact. It continues.

[0033] The transistor 10 shown in Figure 2 has a conductive film 16 and a conductive film at the edge of the oxide semiconductor film 14. The edges that do not overlap with film 17, in other words, the region where conductive film 16 and conductive film 17 are located The structure has an overlapping configuration between the end portions located in different regions and the conductive film 12 and the conductive film 22. The edges of the oxide semiconductor film 14 are exposed to plasma during etching to form the edges. When etching, chlorine radicals, fluorine radicals, etc., generated from the etching gas are used in oxide semiconductors. It readily bonds with the metal elements that make up the film. Therefore, at the edges of the oxide semiconductor film 14, the metal Because the oxygen that was bonded to the element is in a state where it can easily be removed, an oxygen vacancy is formed, resulting in n-type formation. It is considered easy. However, in the transistor 10 shown in Figure 2, the conductive film 16 and the conductive film The edge of the oxide semiconductor film 14, which does not overlap with 17, overlaps with the conductive film 12 and the conductive film 22. Therefore, by controlling the potential of the conductive film 12 and the conductive film 22, the electric field applied to the end is It can be controlled. Therefore, the conductive film 16 and the conductive film through the edge of the oxide semiconductor film 14 The current flowing between 17 is controlled by the potential applied to the conductive film 12 and the conductive film 22. This is possible. The structure of such a transistor 10 is called Surrounded Channel This is called an l(S-Channel) structure.

[0034] Specifically, the conductive film 12 and conductive film 22 are set to a potential such that transistor 10 becomes non-conductive. When applied, the off-current flowing between the conductive film 16 and the conductive film 17 through that end is reduced. This can be suppressed. Therefore, in transistor 10, in order to obtain a large on current, By shortening the channel length, the conductive film 16 and the conductive film at the edge of the oxide semiconductor film 14 Even if the length of the interval between 17 is shortened, the off-current of transistor 10 can be kept low. Therefore, by shortening the channel length, transistor 10 can conduct electricity. It is possible to obtain an on-current and keep the off-current low when in a non-conductive state. Also, the conductive film 12 and conductive film 22 are set to a potential such that the transistor 10 becomes conductive. When applied, the edge 19 of the oxide semiconductor film 14 overlaps with the conductive film 12 and the conductive film 22. As a result, the region 18 where carriers flow in the oxide semiconductor film 14 is close to the insulating film 15. Because it extends not only to the vicinity of the interface of the oxide semiconductor film 14, but also to a wide area of ​​the oxide semiconductor film 14, The amount of carrier movement in transistor 10 increases. As a result, transistor 10 This allows for an increase in on-current and a higher field-effect mobility.

[0035] The channel length refers to the region where the oxide semiconductor film 14 overlaps with the conductive film 12, and the conductivity within that region. This refers to the distance between film 16 and conductive film 17 in the direction in which carriers travel the shortest distance. .

[0036] <Transistor Configuration Example 3> Next, another example of the configuration of the transistor 10 in a semiconductor device according to one aspect of the present invention This is shown in Figure 3. Figure 3(A) shows a top view of transistor 10. Note that in Figure 3(A) To clarify the layout of transistor 10, various insulating films such as gate insulating films are used. The following has been omitted. Also, the cross-sectional view along the dashed line Y1-Y2 in the top view shown in Figure 3(A) is Figure 3(B) shows the cross-sectional view along the dashed line X1-X2, and Figure 3(C) shows the cross-sectional view along the dashed line X1-X2.

[0037] The transistor 10 shown in Figure 3 does not have an insulating film 15, and an insulating film is placed on the oxide semiconductor film 14. The edge film 20 is located in the openings 23 and 24 of the insulating film 20, where the conductive film 16 And in the point where the conductive film 17 is electrically connected to the oxide semiconductor film 14, Figure The configuration differs from that of transistor 10 shown in 1.

[0038] Specifically, the transistor 10 shown in Figure 3 has a gate electrode on a substrate 11 having an insulating surface. A conductive film 12 that has the function of a gate insulating film, and a conductive film that has the function of a gate insulating film. An insulating film 13 located on 12, and an oxide semiconductor that overlaps with the conductive film 12 on the insulating film 13. The film 14, the insulating film 20 on the oxide semiconductor film 14, and functions as a source or drain. Furthermore, the oxide semiconductor film is present in the openings 23 and 24 of the insulating film 20. It has conductive films 16 and 17 that are electrically connected to 14, respectively.

[0039] Furthermore, in the transistor 10 shown in Figure 3, the insulating film 20 is a conductive film among the oxide semiconductor film 14. A region 18 in which carriers flow between the electroluminescent film 16 and the conductive film 17, and the oxide semiconductor film 14 It overlaps with edge 19. Note that in Figure 3, the entire edge 19 of the oxide semiconductor film 14 is an insulating film. Although an example is given where it overlaps with 20, a part of the edge 19 of the oxide semiconductor film 14 is the insulating film 2 It's okay if it overlaps with 0.

[0040] Region 18 and edge 19 overlap with the insulating film 20 to form conductive film 16 and conductive film 17. By etching or other means, the metal contained in conductive films 16 and 17 becomes an oxide semiconductor. This prevents contamination of the body membrane 14. Also, region 18 and edge 19 are separated from the insulating film 20. By overlapping, etching occurs when forming conductive film 16 and conductive film 17, affecting region 18 and the edges. This prevents the part 19 from being exposed to the plasma. This prevents the region 18 and the end 19 from being exposed to the plasma. This prevents oxygen from being released and forming an oxygen deficiency. Alternatively, region 18 and The end portion 19 is designed to prevent oxygen from being easily removed and oxygen deficiency from forming. This is possible. Therefore, the deterioration of the electrical characteristics of transistor 10 caused by impurities is suppressed, and the signal This will enable the provision of highly reliable semiconductor devices.

[0041] Furthermore, in Figure 3, an insulating film 21 is provided on the insulating film 20, conductive film 16, and conductive film 17. As an insulating film 20, it supplies oxygen to the oxide semiconductor film 14 compared to insulating film 21. A high-performance insulating film can be used. Also, as insulating film 21, compared to insulating film 20, An insulating film with high ability to block oxygen, hydrogen, water, etc. can be used. This configuration further suppresses the deterioration of the electrical characteristics of transistor 10, resulting in a more reliable semiconductor. This makes it possible to provide a body device.

[0042] In the transistor 10 shown in Figure 3, by not having an insulating film 15, the transistor shown in Figure 1 The number of manufacturing steps can be reduced compared to Ta10.

[0043] The transistor 10 shown in Figures 1 and 2 consists of an oxide semiconductor film 14, an insulating film 15, and a conductive film. A metal oxide film may be provided between the electrolytic film 16 and the conductive film 17. Also, see Figure 3. The transistor 10 shown in Figure 4 consists of an oxide semiconductor film 14, an insulating film 20, a conductive film 16 and A metal oxide film may be provided between the conductive film 17 and the metal oxide film.

[0044] When the above metal oxide film is an In-M-Zn oxide film, the element M is Ti, Ga, Y, By having Zr, La, Ce, Nd, Sn, or Hf in a higher atomic ratio than In, metals The energy gap of the oxide film can be increased and the electron affinity can be decreased. Therefore, oxide films In some cases, the difference in electron affinity with the conductive film 14 can be controlled by the composition of element M. Yes. Also, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf can bond with oxygen. Because these elements are metallic elements with a strong resultant force, having these elements in a higher atomic ratio than In, Oxygen deficiency becomes less likely.

[0045] Furthermore, when the metal oxide film is an In-M-Zn oxide, In is used in addition to Zn and O. The atomic ratio of In and M is preferably less than 50 atoms and 50 atoms of M. ic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% It must be % or greater.

[0046] Furthermore, the oxide semiconductor film 14 and the metal oxide film are In-M-Zn oxide films (where M is Ti, G In the case of a, Y, Zr, La, Ce, Nd, Sn, or Hf, compare with oxide semiconductor film 14. And the metal oxide film contains M(Ti, Ga, Y, Zr, La, Ce, Nd, Sn) The atomic ratio of Hf is large, and typically, the ratio of the above atoms contained in the oxide semiconductor film 14 is In comparison, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher. be.

[0047] Furthermore, the oxide semiconductor film 14 and the metal oxide film are In-M-Zn oxide films (where M is Ti, G In the case of a, Y, Zr, La, Ce, Nd, Sn, or Hf, the oxide semiconductor film 14 is In :M:Zn=x1:y1:z1 [atomic ratio], metal oxide film In:M:Zn=x2:y If the atomic ratio is 2:z2, then y2 / x2 is greater than y1 / x1, and preferably y 2 / x2 is 1.5 times or more than y1 / x1. More preferably, y2 / x2 is y1 / x1 is at least twice as large, and more preferably y2 / x2 is at least three times larger than y1 / x1. Or it is four times larger or more. In this case, in the oxide semiconductor film 14, y1 is greater than or equal to x1. This allows for stable electrical characteristics to be imparted to the transistor 10 using the oxide semiconductor film 14. It is preferable. However, if y1 is more than 3 times x1, the oxide semiconductor film 14 is used. Because the field-effect mobility of the inverter decreases, it is preferable that y1 be less than 3 times x1. stomach.

[0048] The oxide semiconductor film 14 is an In-M-Zn oxide film (where M is Ti, Ga, Y, Zr, La, C). In the case of e, Nd, Sn, or Hf, the target used to deposit the oxide semiconductor film 14 In the set, if the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, 、 x1 / y1 is between 1 / 3 and 6, and moreover, between 1 and 6, and z1 / y1 is between 1 / 3 and It is preferable that z1 / y1 be 6 or less, and more preferably between 1 and 6. By doing so, the CAAC-OS film described later is more easily formed as the oxide semiconductor film 14. A typical example of the atomic ratio of the target metal elements is In:M:Zn=1:1:1. Examples include In:M:Zn=1:1:1.2 and In:M:Zn=3:1:2.

[0049] Furthermore, the metal oxide film is an In-M-Zn oxide film (where M is Ti, Ga, Y, Zr, La, C). In the case of e, Nd, Sn, or Hf, the target used to deposit the metal oxide film is Let the atomic ratio of the metal elements be In:M:Zn = x²:y²:z². 、 x2 / y2 <x1 / y1, where z2 / y2 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less is preferable. Also, by increasing the atomic number ratio of M to indium, it is possible to increase the energy gap of the metal oxide film and decrease the electron affinity. Therefore, it is preferable that y2 / x2 is 3 or more, or 4 or more. Representative examples of the atomic number ratio of the target metal elements include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:5, In:M:Zn = 1:3:6, In:M:Zn = 1:4:2 In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, etc.

[0050] Also, when the metal oxide film is an In-M oxide film (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf), by configuring it to not contain a divalent metal atom (for example, zinc, etc.) as M, it is possible to form a metal oxide film that does not contain a spinel-type crystal structure. Also, as the metal oxide film, for example, an In-Ga oxide film can be used. As the In-Ga oxide, for example, it can be formed by a sputtering method using an In-Ga metal oxide target (In:Ga = 7:93). Also, in order to form the metal oxide film by a sputtering method using DC discharge, when In:M = x:y [atomic number ratio], y / (x + y) should be 0.96 or less, preferably 0.95 or less, for example, 0.93.

[0051]

[0052] Note that the atomic number ratios of the oxide semiconductor film 14 and the metal oxide film each include a fluctuation of plus or minus 40% of the above atomic number ratio as an error.

[0052] <Example of the structure of a transistor 4> Next, another example of the configuration of the transistor 10 in a semiconductor device according to one aspect of the present invention This is shown in Figure 4. Figure 4(A) shows a top view of transistor 10. Note that in Figure 4(A) To clarify the layout of transistor 10, various insulating films such as gate insulating films are used. The following has been omitted. Also, the cross-sectional view along the dashed line Y1-Y2 in the top view shown in Figure 4(A) is Figure 4(B) shows the cross-sectional view along the dashed line X1-X2, and Figure 4(C) shows the cross-sectional view along the dashed line X1-X2.

[0053] The transistor 10 shown in Figure 4 has a conductive film 22 on an insulating film 21, which is different from the transistor 10 shown in Figure 3. The transistor 10 shown has a different configuration. The conductive film 22 is an oxide semiconductor on the insulating film 21. It is positioned in a location that overlaps with the body membrane 14. Furthermore, the conductive film 22 is electrically connected to the conductive film 12. It continues. Specifically, in Figure 4, the insulating film 13, insulating film 20, and insulating film 21 are provided. In the opening 25, the conductive film 22 and the conductive film 12 are electrically connected.

[0054] As shown in Figure 4, transistor 10 has an S-Channel structure due to the above configuration. By shortening the channel length, the conductive film 16 and the conductive film at the edge of the oxide semiconductor film 14 Even if the length of the interval between 17 is shortened, the off-current of transistor 10 can be kept low. Furthermore, the amount of carrier movement in the oxide semiconductor film 14 increases, so the transistor This allows for increasing the ON current of 10 and also increasing the field-effect mobility.

[0055] <Example of display device configuration> Next, regarding an example of the configuration of a display device according to an example of a semiconductor device according to one aspect of the present invention: explain.

[0056] The display device 70 shown in Figure 7(A) has a pixel section 71 with multiple pixels 30 and the pixels 30 in rows. For selection, wiring GL is represented by wiring GL1 to wiring GLy (where y is a natural number), and Wiring SL1 to SLx (where x is a natural number) for supplying an image signal to the selected pixel 30. Wiring SL, indicated by ), is provided. The signal input to wiring GL is to drive circuit 72 It is controlled by the following. The input of the image signal to the wiring SL is controlled by the drive circuit 73. Multiple pixels 30 are connected to at least one of the wiring GLs and at least one of the wiring SLs. They are electrically connected to each other.

[0057] The type and number of wirings provided in the pixel section 71 are determined by the configuration, number, and arrangement of the pixels 30. Therefore, it can be determined. Specifically, in the case of the pixel section 71 shown in Figure 7(A), x columns × y rows. The pixels 30 are arranged in a matrix, with wiring SL1 to SLx, wiring GL1 This example illustrates the case where the wiring GLy is located within the pixel section 71.

[0058] In Figure 7(A), the drive circuits 72 and 73 are located on the same substrate as the pixel section 71. Although the example shows the case where it is formed on top, the drive circuits 72 and 73 are located in the pixel section 7 It may be formed on a different substrate than the one specified in 1.

[0059] Furthermore, Figure 7(B) shows an example of the configuration of pixels 30 in a liquid crystal display device, which is one type of display device. This is shown. Each pixel 30 controls the supply of an image signal to a liquid crystal element 74. A transistor 10P and a device for maintaining the voltage between the pixel electrode and the common electrode of the liquid crystal element 74 It has a capacitive element 31. The liquid crystal element 74 has a pixel electrode, a common electrode, and a common electrode with the pixel electrode. It has a liquid crystal layer containing a liquid crystal material to which a voltage is applied between the electrodes.

[0060] Transistor 10P controls whether or not to apply the potential of wiring SL to the pixel electrodes of liquid crystal element 74. To control. A predetermined potential is applied to the common electrode of the liquid crystal element 74.

[0061] The following describes the specific connection configuration between transistor 10P and liquid crystal element 74. (Figure 7) In B), the gate of transistor 10P is connected to one of the wires from GL1 to GLy. Electrically connected. One of the sources and drains of transistor 10P is connected to wiring SL. Electrically connected from 1 to one of the SLx wires, and the source and of transistor 10P The other end of the drain is electrically connected to the pixel electrode of the liquid crystal element 74.

[0062] In the liquid crystal element 74, the liquid crystal layer contains according to the voltage value applied between the pixel electrode and the common electrode. The orientation of the liquid crystal molecules changes, and the transmittance changes. Therefore, the liquid crystal element 74 is a pixel electrode. The transmittance is controlled by the potential of the image signal applied to it, thereby displaying grayscale. This is possible. And in each of the multiple pixels 30 that the pixel unit 71 has, liquid crystal element The gradation of sub 74 is adjusted according to the image signal containing image information, thereby the image in the pixel section 71. This will be displayed.

[0063] In Figure 7(B), a switch controls the input of the image signal to pixel 30. The example then illustrates the case where a single transistor 10P is used. However, as a single switch... Multiple transistors that function together may be used in the pixel 30.

[0064] In one aspect of the present invention, a transistor 10P with a remarkably low off-current is used for the pixel 3 of the image signal. It is preferable to use it as a switch to control the input to 0. The off-power of transistor 10P. If the current is small, it is possible to prevent charge leakage through transistor 10P. This ensures that the potential of the image signal applied to the liquid crystal element 74 and the capacitive element 31 is maintained more reliably. Therefore, within one frame period, the transmittance of the liquid crystal element 74 due to charge leakage This prevents changes in the image quality, thereby improving the quality of the displayed image. Also, If the off-current of transistor 10P is small, charge will leak through transistor 10P. This prevents the drive circuit 72 and drive during the period when a still image is displayed. The power supply potential or signal supply to circuit 73 may be stopped. With the above configuration, the pixel unit 71 This reduces the number of times the image signal is written to the display device, thereby lowering the power consumption of the display device. .

[0065] For example, transistors containing oxide semiconductors in their semiconductor films have a remarkably low off-current, It is suitable for use as transistor 10P.

[0066] Next, Figure 7(C) shows another example of a pixel 30 in a light-emitting device, which is one of the display devices. Pixel 30 includes a transistor 76 that controls the input of an image signal to pixel 30, and a light-emitting element 79 And, a transistor 77 that controls the current value supplied to the light-emitting element 79 according to the image signal, and It has a capacitive element 78 for holding the potential of the image signal.

[0067] The light-emitting element 79 is an LED (Light Emitting Diode) or an OLED (O2 Current or voltage, such as in an electromagnetic light-emitting diode. Therefore, elements whose brightness is controlled are included in that category. For example, an OLED has an EL layer and It has at least an anode and a cathode. The EL layer has between the anode and the cathode It consists of one or more layers, and these layers contain a luminescent substance. It includes at least one light-emitting layer.

[0068] Furthermore, the EL layer is activated when the potential difference between the cathode and anode exceeds the threshold voltage of the light-emitting element 79. Electroluminescence is obtained by the current supplied when this occurs. Nessens exhibits luminescence (fluorescence) when returning from the singlet excited state to the ground state, and the triplet excited state. This includes the emission (phosphorescence) that occurs when returning to the ground state.

[0069] Either the anode or cathode of the light-emitting element 79 is connected to the image signal input to the pixel 30. Therefore, its potential is controlled. Of the anode and cathode, its potential is controlled according to the image signal. The controlled electrode is designated as the pixel electrode, and the other electrode is designated as the common electrode. A predetermined potential is applied to the electrodes, and the brightness of the light-emitting element 79 is determined between the pixel electrode and the common electrode. It is determined by the potential difference. Therefore, the brightness of the light-emitting element 79 is determined according to the potential of the image signal. By being controlled, it is possible to display gradations. And the multiple pixels that the pixel part has 3 In each of the 0s, the gradation of the light-emitting element 79 is adjusted according to the image signal containing image information. As a result, an image is displayed in the pixel section 71.

[0070] Next, the pixel 30 has transistor 76, transistor 77, capacitive element 78, and light emission The connection configuration of element 79 will now be described.

[0071] Transistor 76 has either its source or drain electrically connected to wiring SL, and The other end of the drain or the other end is electrically connected to the gate of transistor 77. The gate of transistor 76 is electrically connected to wiring GL. Transistor 77 is connected to the saw One of the source or drain is electrically connected to the power line VL, and the other of the source or drain... The source of transistor 77 or The other end of the drain is electrically connected to either the anode or cathode of the light-emitting element 79. A predetermined potential is applied to either the anode or cathode of the light-emitting element 79. It can be done.

[0072] The transistor 10 shown in Figures 1 to 4 is used as transistor 10P in Figure 7(B). It is possible. Also, the transistor 10 shown in Figures 1 to 4 is the same as the transistor in Figure 7(C). It can be used as a transistor 76 or transistor 77.

[0073] Here, we will show an example where a light-emitting element 79 and a liquid crystal element 74 are used as display elements. However, one aspect of the present invention is not limited thereto.

[0074] For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having sub-elements and light-emitting elements, can use various forms, or various It may have elements. Examples of display elements, display devices, light-emitting elements, or light-emitting devices include EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL) Elements (inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) ), transistor (a transistor that emits light in response to current), electron emission element, liquid crystal element, electric Ink cartridges, electrophoretic elements, grating light bulbs (GLVs), plasma displays (i) Display using PDP (Photographic Display Panel) and MEMS (Micro-Electro-Mechanical Systems) Elements, digital micromirror devices (DMDs), DMS (digital micromirror devices) (Tatter), MIRASOL (registered trademark), IMOD (Interference Modulation) MEMS display elements (shutter type), MEMS display elements (optical interference type), Lectrowetting elements, piezoelectric ceramic displays, carbon nanotubes, etc. Display media whose contrast, brightness, reflectivity, transmittance, etc., change due to electromagnetic interference. Some have bodies. An example of a display device using EL elements is an EL display. There are such devices. An example of a display device using an electron-emitting element is a field emission device. Surface-to-Eye Display (FED) or Surface-to-Eye Display (SED: Surface-to-Eye Display) Examples include (e.g., an Electron-emitter Display). An example of a display device using liquid crystal elements is a liquid crystal display (transmissive liquid crystal display). Semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection Examples include liquid crystal displays. An example of a display device using electronic ink or electrophoretic elements. Examples include electronic paper. Furthermore, semi-transmissive liquid crystal displays and reflective liquid crystal displays... When implementing a spray, some or all of the pixel electrodes function as reflective electrodes. It would be sufficient to have such a feature. For example, part or all of the pixel electrodes may be made of aluminum. It would be good to have silver, etc. Furthermore, in that case, SRAM, etc., below the reflective electrode. It is also possible to incorporate a memory circuit. This further reduces power consumption. can.

[0075] <Example of pixel configuration 1> Next, we will take a liquid crystal display device, which is one of the semiconductor devices according to one aspect of the present invention, as an example. An example configuration of component 30 will be explained. Figure 5 shows the transistor 10 shown in Figure 1 along with the circuit board 1. A top view of a pixel 30 formed on 1 is shown as an example. Note that in Figure 5, the ray of pixel 30 To clarify the output, various insulating films have been omitted. Also, as shown in Figure 5, pixel 30 Figure 6 shows a cross-sectional view of a liquid crystal display device formed using an element substrate having the above characteristics. This corresponds to the cross-sectional view along the dashed line A1-A2 in section 5.

[0076] The pixel 30 shown in Figures 5 and 6 has a transistor 10P and a capacitive element 31. Furthermore, the pixel 30 shown in Figure 6 has a liquid crystal element 74. Note that in Figures 5 and 6, as shown in Figure 1 The example shown is when the transistor 10 is used as transistor 10P, but Figure 2 The transistor 10 shown in any of the figures up to 4 may be used as transistor 10P.

[0077] In addition to functioning as the gate of transistor 10P, the conductive film 12 also functions as shown in Figure 7(B). It functions as a linear GL. In addition, the conductive film 17 is the source of the transistor 10P or In addition to its function as a drain, it also functions as a wiring SL as shown in Figure 7(B).

[0078] Furthermore, the pixel 30 has a metal oxide film 32 on the insulating film 13. The metal oxide film 32 is It is a conductive film that is transparent to light. And on the metal oxide film 32, A conductive film 33 electrically connected to the physical film 32 is provided. The conductive film 33 is a metal oxide It has a function as a wiring for supplying a predetermined potential to the film 32.

[0079] Also, the insulating film 15 and the insulating film 20 have openings on the metal oxide film 32. Specifically the insulating film 15 has an opening 34, and the insulating film 20 has an opening 35. And, in the overlapping region of the openings 34 and the opening 35, the insulating film 21 contacts the metal oxide film 32.

[0080] Note that an oxide semiconductor film is formed on the insulating film 13, and an insulating film 21 which is a nitride insulating film is formed so as to contact the oxide semiconductor film, whereby the conductivity of the oxide semiconductor film can be increased. And, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 32. The conductivity of the oxide semiconductor film is increased because oxygen vacancies are formed in the oxide semiconductor film during the formation of the opening 35 or during the formation of the insulating film 21, and hydrogen diffusing from the insulating film 21 binds to the oxygen vacancies to generate donors. Specifically, the resistivity of the metal oxide film 32 is typically 1×10 Ωcm or more and less than 1×10 Ωcm, and more preferably, the resistivity is 1×10 Ωcm or more and less than 1×10 -3 Ωcm. 4 Further, it is preferably that the resistivity is 1×10 Ωcm or more and less than 1×10 -3 Ωcm. -1 It is good if it is less than Ωcm. .

[0081] The metal oxide film 32 preferably has a higher hydrogen concentration than the oxide semiconductor film 14. In the metal oxide film 32, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion M ass Spectrometry) is 8×10 19 atom s / cm 3Preferably 1 × 10 20 atoms / cm 3 The above is a comfortable 5x 10 20 atoms / cm 3 That concludes the explanation. In the oxide semiconductor film 14, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5 × 10⁻⁶ 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 below, Comfortable 5x10 17 atoms / cm 3 More preferably 1 × 10 16 a toms / cm 3 The following applies:

[0082] Examples of nitride insulating films include silicon nitride film, silicon oxide nitride film, aluminum nitride film, and aluminum nitride film as the insulating film 21. Aluminum films, aluminum nitride oxide films, and the like can be used.

[0083] Furthermore, the insulating film 20 and insulating film 21 are provided with openings 36 at positions that overlap with the conductive film 17. Furthermore, the insulating film 20 and insulating film 21 have light-transmitting properties to visible light, and pixels A conductive film 37 that functions as an electrode is provided. The conductive film 37 is located at the opening 36. The conductive film 37 is electrically connected to the opening 34 and the opening 37. In the overlapping region of 35, it overlaps with the metal oxide film 32. Conductive film 37 and metal oxide The portion where the film 32 and the insulating film 21 overlap, with the insulating film 21 in between, functions as a capacitive element 31.

[0084] The capacitive element 31 consists of a metal oxide film 32 and a conductive film 37 that function as a pair of electrodes, and a dielectric The insulating film 21, which functions as a film, is transparent to visible light. Therefore, the capacitance element Sub-31 will have light transmission to visible light, and the light transmission of the capacitive element to visible light will be Compared to lower pixel sizes, the aperture ratio of pixel 30 can be increased. Therefore, higher image quality can be achieved. To ensure the necessary capacitance while minimizing light loss within the panel, the display device This can reduce power consumption.

[0085] An orientation film 38 is provided on the conductive film 37.

[0086] Furthermore, a substrate 40 is provided so as to face the substrate 11. Visible light A shielding film 41 that has the function of blocking light, and a colored layer 42 that transmits visible light in a specific wavelength range, A resin film 43 is provided on the shielding film 41 and the colored layer 42, and the resin A conductive film 44, which functions as a common electrode, is provided on the film 43. An alignment film 45 is provided on 44.

[0087] Then, between substrate 11 and substrate 40, the liquid crystal is sandwiched between alignment film 38 and alignment film 45. A liquid crystal layer 46 containing the material is provided. The liquid crystal element 74 is provided with a conductive film 37, a conductive film 44, and It has a liquid crystal layer 46.

[0088] In Figures 5 and 6, the driving method for the liquid crystal is TN (Twisted Nematic). The example given was using the ) mode, but as for the LCD driving method, FFS (Fringe Field Switching (Field Switching) mode, STN (Super Twisted Ne matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment) mode, IPS ( In-Plane Switching mode, OCB (Optically Com Pensated Birefringence mode, Blue phase mode, TBA (T (Transverse Bend Alignment) mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) Mode, FLC (Ferroelectric Liquid Crystal) Mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal) l) Mode, PNLC (Polymer Network Liquid Crystal) l) Mode, Guest Host Mode, ASV (Advanced Super View) It is also possible to apply modes and other settings.

[0089] Furthermore, in a liquid crystal display device, the liquid crystal layer may include, for example, thermotropic liquid crystal or liotropic liquid crystal. Liquid crystal materials classified as tropic liquid crystals can be used. Alternatively, the liquid crystal layer can be, for example, Nematic liquid crystal, smectic liquid crystal, cholesteric liquid crystal, or discotic liquid crystal Liquid crystal materials classified as crystal can be used. Alternatively, the liquid crystal layer may contain, for example, ferroelectric materials. Liquid crystal materials classified as liquid crystals or antiferroelectric liquid crystals can be used. Alternatively, liquid crystals The layers may include, for example, main-chain polymer liquid crystals, side-chain polymer liquid crystals, or composite polymer liquid crystals. Liquid crystal materials classified as polymer liquid crystals or low-molecular-weight liquid crystals can be used. Alternatively, For the liquid crystal layer, for example, a liquid crystal material classified as polymer-dispersed liquid crystal (PDLC) is used. can be achieved.

[0090] Also, a liquid crystal showing a blue phase without using an alignment film may be used for the liquid crystal layer. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric liquid crystal phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only within a narrow temperature range, a chiral agent or an ultraviolet curable resin is added to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time of 1 msec or less and is optically isotropic, so alignment treatment is not required and the viewing angle dependence is small, which is preferable.

[0091] <000089x>Also, in FIG. 6, a liquid crystal display device that displays a color image by using a color filter is illustrated. However, the liquid crystal display device according to one aspect of the present invention may have a configuration in which a plurality of light sources that emit light of different hues are sequentially lit to display a color image.

[0092] <Example 1 of the connection configuration between conductive films> Next, an example of the connection configuration between a conductive film 50 located in the same layer as the conductive film 12 that functions as the gate of the transistor 10 shown in FIG. 1 and a conductive film 51 located in the same layer as the source electrode or drain electrode of the transistor 10 shown in FIG. 1 will be described. FIG. 8 shows an example of the cross-sectional structure of the transistor 10D, the conductive film 50, and the conductive film 51. In FIG. 8, the case where the transistor 10 shown in FIG. 1 is used as the transistor 10D is illustrated.

[0093] 8, the conductive film 50 is located on the substrate 11. And on the conductive film 50, an insulating film is provided. In FIG. 8, the case where the transistor 10 shown in FIG. 1 is used as the transistor 10D is illustrated.

[0094] In FIG. 8, the conductive film 50 is located on the substrate 11. And on the conductive film 50, an insulating film​​​ 13 and the insulating film 15 are arranged in order to be stacked. And on the insulating film 15 A conductive film 51 is provided. On the insulating film 15 and the conductive film 51, there is an insulating film 20 and an insulating film The 21s are arranged in a stacked manner.

[0095] Then, on the conductive film 50, insulating film 13, insulating film 15, insulating film 20 and insulating film 21 An opening 52 is provided. Also, on the conductive film 51, insulating film 20 and insulating film 2 An opening 53 is provided in 1. And in openings 52 and 53, conductive A conductive film 54 is placed on the insulating film 21 so as to be electrically connected to film 50 and conductive film 51, respectively. It is provided. Therefore, the conductive film 54 is the conductive film of the pixel 30 shown in Figures 5 and 6. It is provided in the same layer as 37. Conductive film 37 and conductive film 54 are provided in the same layer as one conductive film. It can be formed by doing so.

[0096] In Figure 8, after forming openings in insulating film 15 and insulating film 20, insulating film 21 is formed. In the region overlapping with the above-mentioned opening, an opening is formed in the insulating film 13 and the insulating film 21. The present invention illustrates the case in which an opening 52 is formed. In one aspect of the present invention, the insulating film 13, insulating The film 15, insulating film 20, and insulating film 21 are etched using a single mask to create openings 52 A is formed. However, the transistor 10D shown in Figure 8 is electrically connected to The conductive film 50 and conductive film 51 are placed on the same substrate 11 as the pixel 30 shown in Figures 5 and 6. When forming, the opening 36 shown in Figures 5 and 6 and the opening 52 shown in Figure 8 are etched. This results in a significant difference in the total thickness of the insulating film removed by the process. When both the opening 36 and the opening 52 are formed with a single mask, the conductive film 17 is formed at the opening 36 In some areas, the etching is too excessive or insufficient, resulting in the opening 52 This could lead to problems such as the conductive film 50 not being exposed. However, the cross-section shown in Figure 8 After forming openings in insulating film 15 and insulating film 20 to obtain the structure shown in the figure, insulating film 2 Forming 1, and in the region overlapping with the above-mentioned opening, forming an opening in the insulating film 13 and insulating film 21. When forming the opening 52, one mask can be used to form the opening 36 and the opening 52. Even if both are formed, the thickness of the insulating film to be removed by etching at openings 36 and 52 Differences are less likely to occur. Therefore, the aforementioned defects are less likely to occur, and yield can be increased. can.

[0097] Furthermore, if transistor 10 shown in Figure 2 is used as transistor 10D, then as shown in Figure 2 The conductive film 22 can be formed in the same layer as the conductive film 54. Therefore, the conductive film 22 and The conductive film 54 can be formed by etching one conductive film.

[0098] <Example 2 of pixel configuration and example 2 of connection configuration between conductive films> Next, we will take a liquid crystal display device, which is one of the semiconductor devices according to one aspect of the present invention, as an example. Let's explain another example of a basic configuration. Figure 9 shows a cross-sectional view of the element substrate in a pixel as an example. To show.

[0099] The pixel shown in Figure 9(A) has a transistor 10P and a capacitive element 31. Now, let's take the example of using transistor 10 as transistor 10P, as shown in Figure 3. Yes, they are.

[0100] The pixel shown in FIG. 9(A) has a metal oxide film 32 on the insulating film 13. The metal oxide film 32 is a conductive film having translucency to visible light. Also, the insulating film 20 has an opening 55 on the metal oxide film 3 2. And at the opening 55, the insulating film 21 contacts the metal oxide film 32.

[0101] Also, an opening 36 is provided in the insulating film 21 at a position overlapping with the conductive film 17. And on the insulating film 21, a conductive film 37 having translucency to visible light and functioning as a pixel electrode is provided. The conductive film 37 is electrically connected to the conductive film 17 at the opening 36 and also overlaps with the metal oxide film 32 at the opening 55 . A portion where the conductive film 37 and the metal oxide film 32 overlap with the insulating film 21 interposed therebetween functions as a capacitor 31 .

[0102] The capacitor 31 has translucency to visible light, with the metal oxide film 32 and the conductive film 37 functioning as a pair of electrodes and the insulating film 21 functioning as a dielectric film. Therefore, the capacitor 31 has translucency to visible light, and compared with a pixel having low translucency of the capacitor to visible light, the aperture ratio of the pixel can be increased. Thus, while securing the capacitance value necessary for obtaining high image quality, the light loss in the panel can be suppressed to a small level, and the power consumption of the display device can be reduced.

[0103] Note that an alignment film 38 may be provided on the conductive film 37 as in FIG. 6

[0104] Next, it is located in the same layer as the conductive film 12 that functions as the gate of the transistor 10 shown in FIG. 3 ​​​The conductive film 50 is used as the source electrode or drain electrode of the transistor 10 shown in Figure 3. An example of a connection configuration between the functional conductive film 16 and conductive film 17 and the conductive film 51 located in the same layer. I will explain this.

[0105] Figure 9(B) shows an example of the cross-sectional structure of transistor 10D, conductive film 50, and conductive film 51. In Figure 9(B), transistor 10D is the transistor 10 shown in Figure 3. This provides examples of situations.

[0106] In Figure 9(B), the conductive film 50 is located on the substrate 11. And on the conductive film 50, The insulating film 13 and the insulating film 20 are arranged to be stacked in order. A conductive film 51 is provided on top. The insulating film 21 is provided on the insulating film 20 and the conductive film 51. It's being kicked.

[0107] Furthermore, on the conductive film 50, the insulating film 13, insulating film 20, and insulating film 21 have openings 5 2 is provided. Furthermore, on the conductive film 51, an opening 53 is provided in the insulating film 21. And in the openings 52 and 53, the conductive film 50 and conductive film 51 are A conductive film 54 is provided on the insulating film 21 so that they are electrically connected. Therefore, The conductive film 54 is provided in the same layer as the conductive film 37 in Figure 9(A). Conductive film 37 and conductive film 54 can be formed by etching a conductive film.

[0108] In Figure 9(B), after forming openings in insulating film 13 and insulating film 20, insulating film 21 is... By forming an opening in the insulating film 21 in the region that overlaps with the above-mentioned opening, An example of forming part 52 is shown. In one aspect of the present invention, insulating film 13, insulating film 20, An opening 52 may be formed in the insulating film 21 by etching using a mask. However, the conductive film 50 and the transistor 10D shown in Figure 9(B) are electrically connected. When the conductive film 51 is formed on the same substrate 11 as the pixels shown in Figure 9(A), The opening 36 shown in ) and the opening 52 shown in Figure 9(B) are removed by etching. This results in a significant difference in the total thickness of the insulating film. Therefore, openings are made with a single mask. When both part 36 and the opening 52 are formed, the conductive film 17 partially e The conductive film 50 is exposed at the opening 52 due to excessive etching or insufficient etching. There is a risk of malfunctions such as not being able to do so. However, the structure of the cross-sectional view shown in Figure 9(B) can be obtained. To achieve this, after forming openings in insulating film 13 and insulating film 20, insulating film 21 is formed. In the region overlapping with the above-mentioned opening, an opening is formed in the insulating film 21, thereby creating the opening 52. When forming, even if both the opening 36 and the opening 52 are formed with a single mask, the opening 3 There is little difference in the thickness of the insulating film removed by etching between 6 and the opening 52. Therefore, This reduces the likelihood of the aforementioned problems and improves yield.

[0109] Furthermore, if transistor 10 shown in Figure 4 is used as transistor 10D, then as shown in Figure 4 The conductive film 22 can be formed in the same layer as the conductive film 54. Therefore, the conductive film 22 and The conductive film 54 can be formed by etching one conductive film.

[0110] <Example of manufacturing method 1> Next, an example of a method for manufacturing a semiconductor device according to one aspect of the present invention is shown in Figures 10 to 1. I will explain using number 4.

[0111] As shown in Figure 10(A), after forming a conductive film on the substrate 11, the conductive film is etched. By processing (patterning) the shape using methods such as the above, conductive films 12A and 12B are formed. do.

[0112] The substrate 11 is preferably a substrate with sufficient heat resistance to withstand subsequent manufacturing processes. For example, glass substrates, quartz substrates, ceramic substrates, sapphire substrates, etc., are used.

[0113] The conductive films 12A and 12B include aluminum, titanium, chromium, cobalt, and nickel. Copper, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum and A film made of a conductive material containing one or more types of tungsten is used, with one or more layers laminated together. For example, a copper film on a tungsten nitride film may be used as conductive film 12A and conductive film 12B. Laminated conductive films or single-layer tungsten films can be used. In this fabrication method, conductive The film 12A and conductive film 12B consist of a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm. The conductive film obtained by stacking these materials in order from bottom to top will be used.

[0114] Next, as shown in Figure 10(B), an insulating layer is applied to cover the conductive film 12A and the conductive film 12B. After forming the film 13, an oxide semiconductor film 14A, an oxide semiconductor film 14B, and Then an oxide semiconductor film 32a is formed. Note that the oxide semiconductor film 14A overlaps with the conductive film 12A. The oxide semiconductor film 14B is formed in a position where it overlaps with the conductive film 12B.

[0115] The insulating film 13 can be aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, Silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, gallium oxide One or more of the following: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film can be used as a single layer or in a stacked configuration.

[0116] In this specification, oxidnitrides are defined as having a composition in which the oxygen content is greater than the nitrogen content. The term refers to materials with a high nitrogen content, and nitride oxides are materials whose composition contains more nitrogen than oxygen. To point.

[0117] For example, if the insulating film 13 has a two-layer structure, the first layer will be a silicon nitride film and the second layer will be silicon oxide A multilayer film can be formed as a thin film. The second layer, a silicon oxide film, can be a silicon oxide nitride film. Furthermore, the first layer of silicon nitride film can be a silicon oxide nitride film. In this fabrication method, the film A silicon nitride film with a thickness of 400 nm and a silicon oxidizide film with a thickness of 50 nm are sequentially laminated to provide insulation. It is used as membrane 13.

[0118] It is preferable to use a silicon oxide film with a low defect density. Specifically, electron speed The g value is 2.0 in electron spin resonance (ESR). The spin density of the spins originating from the O1 signal is 3 × 10 17 spins / cm 3 The following are preferred Or 5 x 10 16 spins / cm 3 The following silicon oxide film will be used. The silicon oxide film is, It is preferable to use a silicon oxide film containing an excess of oxygen. The silicon nitride film contains hydrogen and ammonia. A silicon nitride film with low emission levels is used. The amount of hydrogen and ammonia released is measured using TDS (Therm al Desorption Spectroscopy (temperature-controlled desorption gas spectroscopy) for analysis You can measure it that way.

[0119] Oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are oxide A monocrystalline semiconductor film can be used. As oxide semiconductor film 14A and oxide semiconductor film 14B If the oxide semiconductor film used contains a large amount of hydrogen, it will bond with the oxide semiconductor. As a result, some of the hydrogen becomes a donor, generating electrons which are carriers. The threshold voltages of transistor 10A and transistor 10B are shifted in the negative direction. Therefore, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed on the oxide semiconductor film. It is preferable to remove hydrogen or moisture from the conductive film to minimize the presence of impurities. stomach.

[0120] The oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are representative of These include In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga). These include Y, Zr, La, Ce, Nd, Sn, or Hf. In particular, oxide semiconductor film 14 A. The oxide semiconductor film 14B is In-M-Zn oxide (where M is Ti, Ga, Y, Z). It is preferable to use r, La, Ce, Nd, Sn, or Hf.

[0121] Oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are In-M- In the case of Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) The metal elements of the sputtering target used to deposit In-M-Zn oxide films The atomic ratio preferably satisfies In≧M and Zn≧M. Such a sputtering machine As for the atomic ratio of metal elements in the GET, In:M:Zn = 1:1:1, In:M:Zn = A ratio of 1:1:1.2 and In:M:Zn = 3:1:2 are preferred. Furthermore, the oxide semiconductor film to be formed is... The atomic ratios of the body film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are, respectively, The error is the positive or negative of the atomic ratio of the metal elements contained in the sputtering target mentioned above. Includes a 40% fluctuation in eggplant.

[0122] Furthermore, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are In When it is an -M-Zn oxide, the atomic ratio of In to M, excluding Zn and O, is preferably In is 25 atomic % or more, M is less than 75 atomic %, and more preferably In The threshold for is 34 atomic% or higher, and the threshold for M is less than 66 atomic%.

[0123] Furthermore, the oxide semiconductor film 14A and oxide semiconductor film 14B have an energy gap of 2 eV or less. The above is preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor with a wide G-gap, transistor 10A and transistor The 10B off-current can be reduced.

[0124] Furthermore, the thickness of oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a The wavelength is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably The wavelength should be between 3nm and 50nm.

[0125] Furthermore, the oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a are also used. This uses an oxide semiconductor film with a low carrier density. For example, the oxide semiconductor film 14 is a carrier Rear density is 1x10 17 pieces / cm 3 The following is preferably 1 × 10 15pieces / cm 3 The following, Preferably 1 × 10 13 pieces / cm 3 More preferably 1 × 10 11 pieces / cm 3 below , particularly preferably 1 × 10 10 / cm 3 The following is true: 1 × 10 -9 / cm 3 That concludes this section.

[0126] In this fabrication method, the metal oxide is constructed with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. A 35nm thick In-Ga-Zn oxide semiconductor was formed using the target created. The films are defined as oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a. Use.

[0127] Furthermore, the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film removes acid from the oxide semiconductor film. The amount of element may decrease. Therefore, dehydration treatment (dehydrogenation treatment) of oxide semiconductor films is necessary. To compensate for the increased oxygen deficiency caused by ), a process is performed to add oxygen to the oxide semiconductor film. This is preferable. In this way, the oxide semiconductor film is subjected to a dehydration treatment (dehydrogenation treatment) and water By removing elements or moisture and compensating for the oxygen deficiency through oxygenation treatment, type i ( It is possible to create an oxide semiconductor film that is intrinsically modified or very close to type i.

[0128] Next, as shown in Figure 11(A), oxide semiconductor film 14A, oxide semiconductor film 14B, and Insulating film 15a and insulating film 15b are laid on insulating film 13 so as to cover the oxide semiconductor film 32a. They are formed by stacking them in sequence.

[0129] The insulating film 15b is formed continuously after the insulating film 15a is formed, without exposure to the atmosphere. Preferably, after forming the insulating film 15a, the flow rate of the raw material gas, pressure, and high frequency are controlled without opening to the atmosphere. By adjusting the power and substrate temperature to one or more units, the insulating film 15b is formed continuously. The impurity concentration at the interface between 15a and the insulating film 15b can be reduced, and the The oxygen contained in the edge film 15b is moved to the oxide semiconductor film 14A and the oxide semiconductor film 14B. It is possible to reduce the amount of oxygen vacancies in oxide semiconductor film 14A and oxide semiconductor film 14B. It can be reduced.

[0130] A substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 180°C to 400°C. More preferably, the temperature is maintained between 200°C and 370°C, and the raw material gas is introduced into the processing chamber. The pressure inside the processing chamber is set to 30 Pa or more and 250 Pa or less, more preferably 40 Pa or more. The pressure is kept below 200 Pa, and high-frequency power is supplied to electrodes installed in the processing chamber. A silicon oxide film or silicon oxide-nitride film is formed as the edge film 15a.

[0131] As the raw material gas for insulating film 15a, a silicon-containing depositing gas and an oxidizing gas are used. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and trisyl Examples include ores and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and diacitates. It includes nitrogen dioxide, etc.

[0132] By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the insulating film 15a. This can be done. Also, by providing the insulating film 15a, the process of forming the insulating film 15b which will be formed later can be made possible. In this case, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a Damage reduction is possible.

[0133] Furthermore, by increasing the amount of oxidizing gas relative to the silicon-containing sedimentary gas to more than 100 times, It is possible to reduce the hydrogen content in the edge film 15a, and also to include in the insulating film 15a The formation of dangling bonds can be reduced. Oxygen moving from insulating film 15b Because it may be trapped by dangling bonds contained in the insulating film 15a, Efficiently transfer the oxygen contained in 15b to oxide semiconductor films 14A and 14B. This compensates for the oxygen vacancies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B. This is possible. As a result, the oxide semiconductor film 14A and oxide semiconductor film 14B are mixed with The amount of hydrogen can be reduced, and the acid contained in oxide semiconductor film 14A and oxide semiconductor film 14B can be reduced. It is possible to reduce elemental defects. Therefore, transistor 10A and transistor This can suppress the negative shift of the threshold voltage of 10B, and transistor 10A Furthermore, the off-current of transistor 10B can be reduced.

[0134] In this manufacturing method, the insulating film 15a is silane at a flow rate of 20 sccm and silane at a flow rate of 3000 sccm. Using nitrous oxide at a concentration of 1 cm as the raw material gas, the pressure in the processing chamber was set to 200 Pa and the substrate temperature to 350°C. Then, a 27.12MHz high-frequency power supply is used to supply 100W of high-frequency power to the parallel plate electrodes. A silicon oxide nitride film with a thickness of 50 nm is formed by the plasma CVD method. The MCVD device has an electrode area of ​​6000 cm². 2 It is a parallel-plate type plasma CVD apparatus. When the supplied power is converted to power per unit area (power density), it is 1.6 × 10⁻⁶. -2 W / cm 2Under these conditions, an oxygen-permeable silicon oxide nitride film can be formed. .

[0135] As insulating film 15b, a substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus Maintain the temperature between 180°C and 260°C, more preferably between 180°C and 230°C, and process. The raw material gas is introduced into the chamber, and the pressure inside the processing chamber is set to between 100 Pa and 250 Pa, and further Preferably, the pressure is 100 Pa or more and 200 Pa or less, and 0.17 W is applied to the electrode installed in the processing chamber. / cm 2 More than 0.5W / cm 2 More preferably, 0.25 W / cm² 2 0.35 W / cm 2 Under the following conditions for supplying high-frequency power, the silicon oxide film or silicon oxide nitride film To form.

[0136] As the film deposition conditions for insulating film 15b, the high-frequency power of the above power density in the processing chamber at the above pressure By supplying this, the decomposition efficiency of the raw material gas in the plasma is increased, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 15b becomes greater than the stoichiometric composition. The amount increases. However, if the substrate temperature is at the above temperature, the bonding force between silicon and oxygen weakens. During frying and heating, some of the oxygen is removed. As a result, there is more oxygen than the stoichiometric composition. It can form an oxide insulating film containing [a specific substance] in which some of the oxygen is removed upon heating. Insulating film 1 on oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a Because 5a is provided, in the process of forming the insulating film 15b, the insulating film 15a is an oxide semi It has the function of protecting the conductive film 14A, the oxide semiconductor film 14B, and the oxide semiconductor film 32a. As a result, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 3 While reducing damage to 2a, the insulating film 15b is formed using high-power-density high-frequency power. It is possible.

[0137] In this manufacturing method, the insulating film 15b is made of silane at a flow rate of 160 sccm and at a flow rate of 3000 s. The reaction chamber pressure was set to 200 Pa and the substrate temperature to 220°C, using nitrous oxide (CCM) as the raw material gas. Using a 27.12MHz high-frequency power supply, 1500W of high-frequency power is applied to parallel plate electrodes. A silicon oxide nitride film with a thickness of 200 nm is formed using the supplied plasma CVD method. The plasma CVD apparatus has an electrode area of ​​6000 cm². 2 This is a parallel-plate type plasma CVD apparatus. Therefore, when the supplied power is converted to power per unit area (power density), it is 2.5 × 10⁻⁶. - 1 W / cm 2 That is the case.

[0138] Next, as shown in Figure 11(B), at the position overlapping with the oxide semiconductor film 14A, insulation The film 15a and the insulating film 15b have openings 23A and 24A, and the oxide semiconductor film 14B At the position where they overlap, the insulating film 15a and insulating film 15b have openings 23B and 24B These are formed respectively.

[0139] Furthermore, when forming openings 23A and 24A, and openings 23B and 24B As a result of over-etching, a portion of the oxide semiconductor film 14A and oxide semiconductor film 14B When etched, recesses are formed in the oxide semiconductor film 14A and the oxide semiconductor film 14B. There is a match. Note that openings 23A and 24A and openings 23B and 24B are , wet etching method, dry etching method, or wet etching method and dry etching It can be formed by an etching method that combines different etching techniques.

[0140] Next, to cover openings 23A and 24A and openings 23B and 24B Next, a conductive film is formed on the insulating film 15b, and then the shape of the conductive film is processed by etching or the like. By doing so, the conductive film 16A and conductive film 17A in contact with the oxide semiconductor film 14A, and oxidation A conductive film 16B and a conductive film 17B are formed in contact with the semiconductor film 14B (see Figure 12(A)). (See). Conductive film 16A and conductive film 17A, and conductive film 16B and conductive film 17B are conductive film 1 The same conductive material as 2A and conductive film 12B can be used.

[0141] In this fabrication method, a titanium film with a thickness of 35 nm and a copper film with a thickness of 200 nm are layered from bottom to top. The conductive film obtained by doing so is composed of conductive film 16A and conductive film 17A, conductive film 16B and conductive film It will be used as film 17B.

[0142] Next, as shown in Figure 12(B), conductive film 16A and conductive film 17A, and conductive film 16B and An insulating film 20a and an insulating layer 20b are formed on the insulating film 15b so as to cover the conductive film 17B. do.

[0143] The insulating film 20a can be formed using the same materials and manufacturing methods as the insulating layer 15a. Furthermore, the insulating layer 20b is formed using the same material and manufacturing method as the insulating film 15b. It is possible.

[0144] In this manufacturing method, the insulating film 20a is silane at a flow rate of 20 sccm and silane at a flow rate of 3000 sccm. Using nitrous oxide at a concentration of 1 cm as the raw material gas, the pressure in the processing chamber was set to 200 Pa and the substrate temperature to 350°C. Then, a 27.12MHz high-frequency power supply is used to supply 100W of high-frequency power to the parallel plate electrodes. A silicon oxide nitride film with a thickness of 50 nm is formed by the plasma CVD method. The MCVD device has an electrode area of ​​6000 cm². 2 It is a parallel-plate type plasma CVD apparatus. When the supplied power is converted to power per unit area (power density), it is 1.6 × 10⁻⁶. -2 W / cm 2 Under these conditions, an oxygen-permeable silicon oxide nitride film can be formed. Furthermore, as the insulating film 20b, silane at a flow rate of 160 sccm and at a flow rate of 4000 sccm Using nitrous oxide as the raw material gas, the pressure in the reaction chamber was set to 200 Pa, and the substrate temperature was set to 220°C. A 7.12MHz high-frequency power supply was used to supply 1500W of high-frequency power to the parallel plate electrodes. A silicon oxide nitride film with a thickness of 200 nm is formed using plasma CVD. The CVD apparatus has an electrode area of ​​6000 cm². 2 It is a parallel-plate type plasma CVD apparatus, Converting the supplied power to power per unit area (power density) gives 2.5 × 10⁻⁶ -1 W / c m 2 That is the case.

[0145] Next, after forming the insulating film 20b, a heat treatment is performed to form insulating film 15a or insulating film 15b The oxygen contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B is moved to the oxide semiconductor film It is preferable to fill the oxygen vacancies in the conductive film 14A and the oxide semiconductor film 14B. The heat treatment dehydrogenates or dehydrates the oxide semiconductor film 14A and the oxide semiconductor film 14B. This can be done as a heat treatment. Specifically, in this manufacturing method, under a nitrogen and oxygen atmosphere, Then, heat-treat it at 350°C for 1 hour.

[0146] Through the above series of steps, transistors 10A and 10B are formed.

[0147] Next, as shown in Figure 13(A), insulating film 15a and insulating film 15b, insulating film 20a, insulating film The edge film b is partially etched to form the opening 60. In the opening 60, The oxide semiconductor film 32a is partially or completely exposed.

[0148] Next, insulating film 21 and insulating film 61 are sequentially applied to the insulating film 20b so as to cover the opening 60. The films are formed in a stacked manner. The insulating film 21 is in contact with the oxide semiconductor film 32a at the opening 60. do.

[0149] As the insulating film 21, for example, a silicon nitride film, silicon oxide nitride, etc., formed using a CVD method. Nitride insulating films such as substrate films, aluminum nitride films, and aluminum nitride oxide films can be used. Yes, it is possible. At the opening 60, a nitride insulating film is placed in contact with the oxide semiconductor film 32a. By forming the border film 21, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a with enhanced properties is shown as the metal oxide film 32 in Figure 13(B). .

[0150] In this fabrication method, the insulating film 21 is made of silane at a flow rate of 50 sccm and at a flow rate of 5000 sccc. The raw material gases are nitrogen at m and ammonia at a flow rate of 100 sccm, and the pressure in the processing chamber is set to 100. Pa, substrate temperature set to 350°C, 1000W (electrical power) using a 27.12MHz high-frequency power supply. The force density is 1.6 × 10⁻⁶ -1 W / cm2 A high-frequency power of ) is supplied to parallel plate electrodes. A silicon nitride film with a thickness of 100 nm is formed using the razma CVD method.

[0151] The insulating film 61 is an insulating film with a lower relative permittivity and lower internal stress than the insulating film 21. This is desirable. Specifically, as the insulating film 61, for example, silicon oxide film, silicon oxide nitride film, oxide Aluminum and other materials can be used.

[0152] Note that the insulating film 61 is not necessarily required. However, the insulating film 61 is provided together with the insulating film 21. It functions as a dielectric film for the pixel's capacitive element. The insulating film 21 is made of silicon dioxide and other oxides. Compared to a material insulating film, it tends to have a higher relative permittivity and greater internal stress. Therefore, the capacitance element When using only the insulating film 21 as the dielectric film without using the insulating film 61, the film of the insulating film 21 If the thickness is small, the capacitance value of the capacitive element becomes too large, making it difficult to write the image signal to the pixels. It becomes difficult to increase the speed with low power consumption. Conversely, if the thickness of the insulating film 21 is large, When internal stress becomes too large, the threshold voltage of the transistor shifts, etc., when using a semiconductor film This may lead to a deterioration in the properties of the semiconductor device formed. Furthermore, the internal stress of the insulating film 21 may also be affected. If the size becomes too large, the insulating film 21 becomes more likely to peel off from the substrate 11, hindering the improvement of yield. On the other hand, insulating film 61 using an insulating material such as silicon oxide, which has a lower dielectric constant than insulating film 21. When used together with the insulating film 21 as the dielectric film of the pixel's capacitive element, the dielectric constant of the dielectric film This can be adjusted to a desired value without increasing the thickness of the insulating film 21.

[0153] For example, as the insulating film 61, a silicon oxide film formed by a CVD method using organic silane gas. It can be used. As an organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylsilane Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC) Using 2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. It is possible.

[0154] In this fabrication method, the insulating film 61 is formed by a CVD method using ethyl silicate, resulting in a film thickness 3 A 20 nm silicon oxide film is used.

[0155] Next, as shown in Figure 14(A), the insulating film 21 and insulating film 61 are partially etched. This forms an opening 36. At least a portion of the conductive film 17B in the opening 36. It is exposed.

[0156] Next, as shown in Figure 14(B), a transparent conductive film is formed on the insulating film 61, followed by etching, etc. By processing the shape of the transparent conductive film, conductive film 22A and conductive film 37 are formed. The conductive film 22A is provided in a position that overlaps with the conductive film 12A, with the oxide semiconductor film 14A in between. Furthermore, the conductive film 37 is connected to the conductive film 17B at the opening 36.

[0157] Furthermore, the transparent conductive film used to form the conductive film 12A and the conductive film 37 is an oxide film. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Titanium oxide containing indium oxide, titanium oxide containing indium tin oxide, indium Tin oxide, indium zinc oxide, zinc oxide, zinc oxide with added gallium, silicon oxide A conductive film containing added indium tin oxide or the like can be used.

[0158] In this fabrication method, a silicon dioxide-doped indium tin oxide with a film thickness of 110 nm is used. A conductive film 12A and a conductive film 37 are formed using an electrolytic film.

[0159] After forming the conductive film 12A and the conductive film 37, a heat treatment may be performed. The heat treatment may be, for example, In this case, the process should be carried out at 250°C for 1 hour under a nitrogen atmosphere.

[0160] Furthermore, the various films described above, such as conductive films, insulating films, oxide semiconductor films, and metal oxide films, are It can be formed by the puttering method or the PECVD method, but other methods, for example, thermal C It may also be formed by the VD (Chemical Vapor Deposition) method. An example of a thermal CVD method is MOCVD (Metal Organic Chemical). Vapor Deposition (Vapor Deposition) and ALD (Atomic Layer Deposition) The sition method may also be used.

[0161] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0162] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber pressure is reduced to atmospheric pressure. Alternatively, the film is formed by reacting the material near or on the substrate under reduced pressure, causing it to deposit on the substrate. That's fine.

[0163] Furthermore, the ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber, and sequentially supplying the raw material gases for the reaction. The gas can then be introduced into the chamber, and the film deposition process may be carried out by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), you can create two or more types. The raw material gases are supplied to the chamber in order, and the first raw material gas is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the refrigerant gas, Introducing the raw material gas (2). Note that if an inert gas is introduced simultaneously, the inert gas should be... It becomes a carrier gas, and when introducing the second raw material gas, an inert gas may also be introduced at the same time. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. A second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate to form the first layer. The film is formed and reacts with a second raw material gas introduced later, so that the second layer is laminated on top of the first layer. A thin film is formed. This process is repeated multiple times while controlling the gas introduction sequence until the desired thickness is reached. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. Because it can be adjusted by the number of times the process is repeated, precise film thickness adjustment is possible. It is suitable for fabricating thin FETs.

[0164] Thermal CVD methods such as MOCVD and ALD are used for conductive films, insulating films, and oxides as described herein. It can form various films such as semiconductor films and metal oxide films, for example, In-Ga-Z When forming an nO film, trimethylindium, trimethylgallium, and dimethyl Zinc is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. Also, the chemical formula for dimethylzinc... The formula is Zn(CH3)2. Furthermore, it is not limited to these combinations, but trimethyl gas Triethylgallium (chemical formula Ga(C2H5)3) can also be used instead of lium. Diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. .

[0165] For example, when forming a hafnium oxide film using an ALD-based film deposition apparatus, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrak The raw material gas is vaporized dimethylamide hafnium (TDMAH), and the oxidizing agent is O Two types of gases, O3, are used. Furthermore, the chemical reaction of tetrakisdimethylamidehafnium... The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(eth Examples include methylamide (hafnium).

[0166] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent And a liquid containing an aluminum precursor compound (such as trimethylaluminum (TMA)) Two types of gases are used: a converted raw material gas and H2O as an oxidizing agent. The chemical formula for luminium is Al(CH3)3. Other materials include Tris(Di Methylamide) Aluminum, Triisobutylaluminum, Aluminum Tris(2, Examples include 2,6,6-tetramethyl-3,5-heptanedione).

[0167] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0168] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by simultaneously introducing gas and H2 gas. Note that B2H6 gas can be used instead. SiH4 gas may also be used.

[0169] For example, oxide semiconductor films, such as In-Ga-ZnO films, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. A layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, an In-Ga-O layer is formed. Alternatively, mixed compound layers such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. Alternatively, you can use H2O gas obtained by bubbling with an inert gas such as Ar instead of the three gases. However, it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas Alternatively, In(C2H5)3 gas may be used. Also, Ga(CH3)3 gas can be used instead. (C2H5)3 gas may be used. Alternatively, In(C2)3 gas can be used instead. H5)3 gas may be used. Alternatively, Zn(CH3)2 gas may be used.

[0170] Next, an orientation film can be formed on the conductive film 37 to form an element substrate.

[0171] The orientation film can be formed using organic resins such as polyimide and polyvinyl alcohol. Furthermore, the surface is subjected to orientation treatments such as rubbing to align the liquid crystal molecules in a specific direction. The process involves rubbing, which is done by wrapping a cloth such as nylon around a roller so that it is in contact with the orientation film. This can be done by rotating the device and rubbing the surface of the orientation film in a certain direction. Using inorganic materials such as silicon dioxide, orientation characteristics are achieved by vapor deposition without any orientation treatment. It is also possible to form a film directly.

[0172] After forming the element substrate and the opposing substrate, a liquid crystal layer is placed between substrate 11 and substrate 40, as shown in Figure 6. By encapsulating 46, a panel for a liquid crystal display device can be formed. The liquid crystal injection performed for this purpose may be done using a dispenser (dropping) method, or a dip method. A pumping system may also be used.

[0173] <Example of manufacturing method 2> Next, another example of a method for manufacturing a semiconductor device according to one aspect of the present invention is shown with reference to Figure 10. This will be explained using Figures 15 to 17.

[0174] First, the process is carried out in the same manner as described above up to the step shown in Figure 10(B), and then as shown in Figure 15(A)... As shown, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a The insulating film 20a and insulating film 20b are layered sequentially on the insulating film 13 so as to cover it. To accomplish.

[0175] The insulating film 20b is formed continuously after the insulating film 20a is formed, without exposure to the atmosphere. Preferably, after forming the insulating film 20a, the flow rate of the raw material gas, pressure, and high frequency are controlled without opening to the atmosphere. By adjusting the power and substrate temperature to one or more units, the insulating film 20b is formed continuously. The impurity concentration at the interface between 20a and the insulating film 20b can be reduced, and the The oxygen contained in the edge film 20b is moved to the oxide semiconductor film 14A and the oxide semiconductor film 14B. It is possible to reduce the amount of oxygen vacancies in oxide semiconductor film 14A and oxide semiconductor film 14B. It can be reduced.

[0176] A substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 180°C to 400°C. More preferably, the temperature is maintained between 200°C and 370°C, and the raw material gas is introduced into the processing chamber. The pressure inside the processing chamber is set to 30 Pa or more and 250 Pa or less, more preferably 40 Pa or more. The pressure is kept below 200 Pa, and high-frequency power is supplied to electrodes installed in the processing chamber. A silicon oxide film or a silicon oxide-nitride film is formed as the edge film 20a.

[0177] As the raw material gas for the insulating film 20a, a silicon-containing depositing gas and an oxidizing gas are used. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and trisyl Examples include ores and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and diacitates. It includes nitrogen dioxide, etc.

[0178] By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the insulating film 20a. This can be done. In addition, by providing the insulating film 20a, the process of forming the insulating film 20b later can be made possible. In this case, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a Damage reduction is possible.

[0179] Furthermore, by increasing the amount of oxidizing gas relative to the silicon-containing sedimentary gas to more than 100 times, It is possible to reduce the hydrogen content in the edge film 20a, and also to include in the insulating film 20a The dangling bond that is formed can be reduced. Oxygen moving from the insulating film 20b Because dangling bonds contained in the insulating film 20a may be trapped, Efficiently transfer the oxygen contained in 20b to oxide semiconductor film 14A and oxide semiconductor film 14B. This compensates for the oxygen vacancies contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B. This is possible. As a result, the oxide semiconductor film 14A and oxide semiconductor film 14B are mixed with The amount of hydrogen can be reduced, and the acid contained in oxide semiconductor film 14A and oxide semiconductor film 14B can be reduced. It is possible to reduce elemental defects. Therefore, transistor 10A and transistor This can suppress the negative shift of the threshold voltage of 10B, and transistor 10A Furthermore, the off-current of transistor 10B can be reduced.

[0180] In this manufacturing method, the insulating film 20a is silane at a flow rate of 20 sccm and silane at a flow rate of 3000 sccm. Using nitrous oxide at a concentration of 1 cm as the raw material gas, the pressure in the processing chamber was set to 200 Pa and the substrate temperature to 350°C. Then, a 27.12MHz high-frequency power supply is used to supply 100W of high-frequency power to the parallel plate electrodes. A silicon oxide nitride film with a thickness of 50 nm is formed by the plasma CVD method. The MCVD device has an electrode area of ​​6000 cm². 2 It is a parallel-plate type plasma CVD apparatus. When the supplied power is converted to power per unit area (power density), it is 1.6 × 10⁻⁶. -2 W / cm 2 Under these conditions, an oxygen-permeable silicon oxide nitride film can be formed. .

[0181] Furthermore, as the insulating film 20b, it is placed in the vacuum-evacuated processing chamber of the plasma CVD apparatus. The substrate is kept at a temperature of 180°C to 260°C, more preferably 180°C to 230°C. The raw material gas is introduced into the processing chamber, and the pressure inside the processing chamber is set to between 100 Pa and 250 Pa. More preferably, the pressure should be 100 Pa or more and 200 Pa or less, and the electrode provided in the processing chamber should be 0. 17W / cm 2 More than 0.5W / cm 2 More preferably, 0.25 W / cm² 2 0 0.35W / cm 2 Under the following conditions for supplying high-frequency power, silicon oxide film or silicon oxide nitride It forms a film.

[0182] As a film deposition condition for insulating film 20b, high-frequency power of the above power density in a processing chamber at the above pressure By supplying this, the decomposition efficiency of the raw material gas in the plasma is increased, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 20b becomes greater than the stoichiometric composition. The amount increases. However, if the substrate temperature is at the above temperature, the bonding force between silicon and oxygen weakens. During frying and heating, some of the oxygen is removed. As a result, the amount of oxygen remaining is less than the amount of oxygen that satisfies the stoichiometric composition. It also contains a lot of oxygen, and when heated, some of the oxygen is removed, forming an oxide insulating film. Also, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a Since insulating film 20a is provided on top, in the process of forming insulating film 20b, insulating film 20 a protects oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide semiconductor film 32a. It has the function of doing so. As a result, oxide semiconductor film 14A, oxide semiconductor film 14B, and oxide While reducing damage to the material semiconductor film 32a, high-frequency power with high power density is used for insulation. A film 20b can be formed.

[0183] In this manufacturing method, the insulating film 20 is silane at a flow rate of 160 sccm and silane at a flow rate of 3000 sccm. Using nitrous oxide at a concentration of 1 cm as the raw material gas, the pressure in the processing chamber was set to 200 Pa and the substrate temperature to 220°C. Then, using a 27.12MHz high-frequency power supply, 1500W of high-frequency power is supplied to the parallel plate electrodes. A silicon oxide nitride film with a thickness of 400 nm is formed by the supplied plasma CVD method. The Razma CVD apparatus has an electrode area of ​​6000 cm². 2 In a parallel-plate type plasma CVD apparatus Yes, and when the supplied power is converted to power per unit area (power density), it is 2.5 × 10⁻⁶. -1 W / cm 2 That is the case.

[0184] Next, after forming the insulating film 20b, a heat treatment is performed to form insulating film 20a or insulating film 20b The oxygen contained in the oxide semiconductor film 14A and the oxide semiconductor film 14B is moved to the oxide semiconductor film It is preferable to fill the oxygen vacancies in the conductive film 14A and the oxide semiconductor film 14B. The heat treatment dehydrogenates or dehydrates the oxide semiconductor film 14A and the oxide semiconductor film 14B. This can be done as a heat treatment. Specifically, in this manufacturing method, under a nitrogen and oxygen atmosphere, Then, heat-treat it at 350°C for 1 hour.

[0185] Next, as shown in Figure 15(B), at the position overlapping with the oxide semiconductor film 14A, insulation Apertures 23A and 24A are made in film 20a and insulating film 20b, and oxide semiconductor film 14B and At the overlapping position, openings 23B and 24B are made in insulating film 20a and insulating film 20b. At a position overlapping with the oxide semiconductor film 32a, an opening is made in the insulating film 20a and insulating film 20b. Each of these forms 60.

[0186] Furthermore, openings 23A and 24A, openings 23B and 24B, and opening 60 During the formation of the oxide semiconductor film 14A and oxide semiconductor film 1, over-etching occurs. 4B and a portion of the oxide semiconductor film 32a are etched, and the oxide semiconductor film 14A and oxide Recesses may be formed in the monocrystalline semiconductor film 14B and the oxide semiconductor film 32a. The mouth portion 23A and opening 24A, opening 23B and opening 24B, and opening 60 are, Wet etching method, dry etching method, or wet etching method and dry etching It can be formed by an etching method that combines different etching techniques.

[0187] Next, openings 23A and 24A, openings 23B and 24B, and opening 6 After forming a conductive film on insulating film 20a and insulating film 20b so as to cover 0, the conductive film By processing the shape through etching or the like, a conductive film 1 in contact with the oxide semiconductor film 14A 6A and conductive film 17A, and conductive films 16B and 17B in contact with oxide semiconductor film 14B (See Figure 16(A)). Conductive film 16A and conductive film 17A, and conductive film 16B and The conductive film 17B can be made using the same conductive material as conductive film 12A and conductive film 12B. Cut.

[0188] Through the above series of steps, transistors 10A and 10B are formed.

[0189] Next, as shown in Figure 16(B), conductive film 16A and conductive film 17A, and conductive film 16B and An insulating film 20a and insulating film 20b are coated with an insulating film 20a so as to cover the conductive film 17B and the opening 60. The edge film 21 and the insulating film 61 are formed in order to be stacked. The insulating film 21 is formed at the opening 60. It then comes into contact with the oxide semiconductor film 32a. The insulating film 21 and insulating film 61 are used for insulating The types of films, film thicknesses, and manufacturing methods are explained using Figures 10 to 14, as described above. The manufacturing method can be referenced.

[0190] At the opening 60, the insulating film 21, which is a nitride insulating film, is in contact with the oxide semiconductor film 32a. By forming this, the conductivity of the oxide semiconductor film 32a can be increased. The oxide semiconductor film 32a is shown as the metal oxide film 32 in Figure 16(B).

[0191] Next, as shown in Figure 17(A), the insulating film 21 and insulating film 61 are partially etched. This forms an opening 36. At least a portion of the conductive film 17B in the opening 36. It is exposed.

[0192] Next, as shown in Figure 17(B), a transparent conductive film is formed on the insulating film 61, followed by etching, etc. By processing the shape of the transparent conductive film, conductive film 22A and conductive film 37 are formed. The conductive film 22A is provided in a position that overlaps with the conductive film 12A, with the oxide semiconductor film 14A in between. Furthermore, the conductive film 37 is connected to the conductive film 17B at the opening 36.

[0193] Furthermore, the type of transparent conductive film used to form conductive film 22 and conductive film 37, the film thickness, and For details on the manufacturing method, please refer to the manufacturing method described above using Figures 10 to 14. It is possible.

[0194] After forming the conductive films 22 and 37, a heat treatment may be performed. The heat treatment may be, for example, This can be done under a nitrogen atmosphere at 250°C for 1 hour.

[0195] Next, an orientation film can be formed on the conductive film 37 to form an element substrate.

[0196] <Examples of sequential circuit configurations> Next, Figure 18 shows an example of the configuration of a sequential circuit in a semiconductor device according to one aspect of the present invention. .

[0197] The sequential circuit SR shown in Figure 18 consists of transistors M1 through M15 and a capacitive element C It has transistor 1 and a capacitive element C2. And in Figure 18, transistor M1 to transistor Of the M15 transistors, all transistors except transistor M5 and transistor M7 are S - An example is given of a case having a channel structure. However, in one aspect of the present invention, It is also acceptable for all transistors M1 through M15 to have an S-Channel structure. i. Or, one or more of transistors M1 through M15. However, it may also have an S-Channel structure.

[0198] Specifically, the gates of transistors M3, M12, and M13 are , electrically connected to the wiring to which the signal LIN is supplied. Transistor M3, Transistor Either the source or drain of transistor M5 or transistor M7 is at a high potential VDD. The source or drain of transistor M3 is electrically connected to the given wiring. The other end is electrically connected to either the source or the drain of transistor M15. The source or drain of transistor M10 is connected to the source of transistor M15. One side is electrically connected to the drain, and the other side is connected to the source or drain of transistor M11. It is electrically connected to one of the inputs.

[0199] Transistors M11, M13, M14, and M2 Either the source or the drain is electrically connected to a wiring to which the potential VSS is applied. Transistor M10, Transistor M11, Transistor M14, Transistor M2 The gate is the source or gate of transistors M6, M7, and M8. One side of the rain is electrically connected to either the source or drain of transistor M12. It is being done.

[0200] The gate of transistor M5 is electrically connected to the wiring to which the signal CLK3 is supplied. The gate of transistor M6 is electrically connected to the wiring to which the signal CLK2 is supplied. The source or drain of transistor M5 is connected to the source of transistor M6. It is electrically connected to the other side of the drain. The gate of transistor M7 is connected to the signal RIN It is electrically connected to the given wiring.

[0201] The gate of transistor M8 is electrically connected to the wiring to which the signal INI_RES is supplied. The source or drain of transistor M8 is connected to a circuit where potential VDD is applied. It is electrically connected to the wire. The gate of transistor M4 is connected to the wire to which a potential VDD is applied. It is electrically connected to the wire. Either the source or the drain of transistor M4 is connected to the transistor. It is electrically connected to the other side of the source or drain of transistor M3. The source or drain of 4 is electrically connected to the gate of transistor M9. The source or drain of transistor M9 is connected to the wiring to which the signal CLK1 is given. It is electrically connected to the other side of the source or drain of transistor M9, and the Either the source or drain of the ZISTA M14 is connected to the wiring to which the signal SROUT is given. They are connected by energy.

[0202] Either the source or drain of transistor M15 supplies electrical power to the gate of transistor M1. They are connected. The gate of transistor M15 is connected to the wiring to which the potential VDD is applied. They are electrically connected. Either the source or drain of transistor M1 is connected to the signal PWC. Electrically connected to the given wiring of 1. Source or slave of transistor M1. The other end of the signal OUT is connected to the other end of the source or drain of transistor M2. It is electrically connected to the wiring.

[0203] One of the pair of electrodes of the capacitive element C1 is electrically connected to a wiring to which the potential VSS is applied. The other end is electrically connected to the gate of transistor M2. Capacitive element C2 The pair of electrodes it possesses are such that one is the source or drain of transistor M15 and the other is electrically charged. They are connected one way, and the other is electrically connected to the wiring to which the signal OUT is supplied.

[0204] The transistor 10 shown in Figure 2 or Figure 4 is a transistor M1 to M4 Alternatively, it can be used as transistor M8 to transistor M15. Also, Figure 1 Alternatively, the transistor 10 shown in Figure 3 can be used as transistors M5 to M7. It is possible to be there.

[0205] Next, Figure 19 shows a shift circuit that is constructed by connecting multiple sequential circuits SR shown in Figure 18 in stages. A shift register is shown as an example. The shift register shown in Figure 19 has y sequential circuits SR( y is a natural number greater than or equal to 2. The y sequential circuits SR each have the order shown in Figure 18. It has the same configuration as circuit SR.

[0206] Furthermore, the shift register shown in Figure 19 has y+1 stages of sequential circuits SR after y sequential circuits SR. It further has a sequential circuit SR of the y+2th stage and y The second-stage sequential circuit SR does not have transistor M7, in that it is the sequential circuit shown in Figure 18. The circuit SR has a different configuration. That is, the sequential circuit SR has a y+1 stage and the sequential circuit has a y+2 stage. SR supplies potential VDD to the gate of transistor M2 according to the signal RIN. It differs in configuration from the sequential circuit SR shown in Figure 18 in that it does not have a control function. .

[0207] Furthermore, in the shift register shown in Figure 19, the j-th stage sequential circuit SR(j is less than or equal to y) Figure 20 schematically shows the positions of each wire connected to the natural numbers. The sequential circuit S shown in Figure 18. In the case of R, wiring T1 corresponds to signal LIN, wiring T2 corresponds to signal PWC1, wiring T3 Wiring T4 corresponds to signal CLK1, wiring T4 corresponds to signal CLK2, and wiring T5 corresponds to signal CLK3. Wiring T6 corresponds to the INI_RES signal, and wiring T7 corresponds to the SROUT signal. Wiring T8 corresponds to signal OUT, and wiring T9 corresponds to signal RIN.

[0208] As can be seen from Figures 19 and 20, in the j-th stage sequential circuit SR, the wiring T1 has j- The signal SROUT, output from wiring T7 of the first stage sequential circuit SR, is given as the signal LIN. It can be obtained. However, the wiring T1 of the first stage sequential circuit SR is connected to the start pulse signal SP. The structure is such that ranks are assigned.

[0209] Furthermore, in the sequential circuit SR shown in Figure 18, signals CLK1 to CLK3 are connected to wiring T3 to Although the example shows the case where each of the wires T5 is given, Figure 19 does not necessarily follow the same procedure as Figure 18. Similar to the sequential circuit SR shown, signals CLK1 to CL are connected to wiring T3 to T5. It is not guaranteed that K3 will be given to each individual.

[0210] Specifically, in the 4m+1 stage sequential circuit SR, the signal CLK1 is connected to wiring T3 through T5. Each is given the signal CLK3. In the 4m+2 stage sequential circuit SR, wiring T3 Signals CLK2 and CLK4 are supplied to wiring T5, respectively. 4m + 3 stages In the sequential circuit SR, signals CLK3, CLK4, and signal CLK3 are connected to wiring T3 through T5. Each is given the number CLK1. In the 4m+4th stage sequential circuit SR, wiring T3 to The signals CLK4, CLK1, and CLK2 are supplied to wiring T5, respectively. However, m is any integer that satisfies the condition that the total number of sequential circuits SR is y.

[0211] Furthermore, in the j-th stage sequential circuit SR, the wiring T9 is connected to the wiring T of the second-to-last stage sequential circuit SR. The signal SROUT output from 7 is given as the signal RIN. However, the last two stages The sequential circuit SR of the y+1 stage and the sequential circuit SR of the y+2 stage correspond to the signal RIN. It is not given.

[0212] <Method for manufacturing a display device> Next, Figures 21 and 22 show a method for manufacturing a display device 400 according to one aspect of the present invention. We will explain using this method.

[0213] First, an insulating film 420 is formed on the substrate 462, and a first element layer 410 is formed on the insulating film 420. This is achieved (see Figure 21(A)). A semiconductor element is provided in the first element layer 410. Alternatively, the first element layer 410 may include, in addition to semiconductor elements, display elements or pixel electrodes, etc. It is acceptable for some of the display elements to be provided.

[0214] The substrate 462 must have at least enough heat resistance to withstand subsequent heat treatment. There are. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., substrate 4 It may also be used as 62.

[0215] When a glass substrate is used for substrate 462, a silica oxide film is placed between substrate 462 and insulating film 420. When insulating films such as glass films, silicon oxide nitride films, silicon nitride films, and silicon oxide nitride films are formed, the glass base This is preferable as it prevents contamination from the board.

[0216] The insulating film 420 can be, for example, epoxy resin, aramid resin, acrylic resin, or polyimide resin. Organic resin films such as lipids, polyamide resins, and polyamide-imide resins can be used. Polyimide resin is preferable because it has high heat resistance. For example, as the insulating film 420, When using polyimide resin, the film thickness of the polyimide resin is preferably 3 nm to 20 μm. The thickness is between 500 nm and 2 μm. Polyimide resin is used as the insulating film 420. In such cases, the surface is formed using methods such as spin coating, dip coating, or doctor blade coating. This is possible. For example, when using polyimide resin as the insulating film 420, doctor blade By removing a portion of the film made of the polyimide resin according to the law, a film with the desired thickness can be obtained. An insulating film 420 can be obtained.

[0217] Furthermore, the temperature during the manufacturing process of the first element layer 410 is between room temperature and 300°C. This is preferable. For example, the first element layer 410 may contain an insulating film or conductive film made of an inorganic material. The film is formed at a temperature of 150°C to 300°C, and even more specifically, at 200°C to 270°C. It is preferable that this is done. Furthermore, the first element layer 410 contains an organic resin material. Insulating films and the like are preferably formed at a film deposition temperature of room temperature or higher and 100°C or lower.

[0218] Furthermore, the oxide semiconductor film of the transistor included in the first element layer 410 contains CA, which will be described later. It is preferable to use AC-OS. CAAC-OS is used for the oxide semiconductor film of the transistor. Using S, for example, when the display device 400 is bent, cracks will form in the channel formation region. This makes it difficult for imperfections to enter, and improves resistance to bending.

[0219] Furthermore, the conductive film included in the first element layer 410 is indium with silicon oxide added. When tin oxide is used, cracks may form in the conductive film when the display device 400 is bent. This is preferable because it makes it more difficult.

[0220] Next, the first element layer 410 and the temporary support substrate 466 are bonded together using a release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. Layers 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see Figure 21(B)). .

[0221] The temporary support substrate 466 can be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, A metal substrate or the like can be used. Furthermore, the heat resistance that can withstand the processing temperature of this embodiment is A plastic substrate may be used, or a flexible substrate such as a film may be used. .

[0222] The release adhesive 464 can be soluble in water or solvents, or it can be plasticized by irradiation with ultraviolet light or the like. It is possible to do so, as necessary, with the temporary support substrate 466 and the first element layer 410 An adhesive is used that allows for chemical or physical separation of the two components.

[0223] Furthermore, various methods can be used as appropriate for the transfer process to the temporary support substrate 466. , the side of the substrate 462 where the insulating film 420 is not formed, i.e., the lower side shown in Figure 21(B) By irradiating the insulating film 420 with laser light 468, the insulating film 420 is weakened. This allows the substrate 462 and the insulating film 420 to be separated. Also, irradiation with the laser light 468 By adjusting the energy density, regions with high adhesion between the substrate 462 and the insulating film 420, and the base Alternatively, areas with low adhesion between the plate 462 and the insulating film 420 may be created before peeling.

[0224] In this embodiment, the method for peeling at the interface between the substrate 462 and the insulating film 420 is described below. The examples given are not limited to these. For example, the boundary between the insulating film 420 and the first element layer 410. It may be peeled off in a surface area.

[0225] Furthermore, the liquid is permeated into the interface between the substrate 462 and the insulating film 420, allowing the insulating film 42 to penetrate from the substrate 462. Layer 0 may be peeled off. Alternatively, a liquid may be permeated into the interface between the insulating film 420 and the first element layer 410. The first element layer 410 may be peeled off from the insulating film 420. The above liquid may be, for example, Alternatively, water, polar solvents, etc., can be used. The interface that peels off the insulating film 420, specifically the base A liquid is injected into the interface between plate 462 and insulating film 420 or the interface between insulating film 420 and first element layer 410. By allowing the body to penetrate, electrostatic discharge is generated on the first element layer 410 due to delamination. It can suppress the influence of energy and other factors.

[0226] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (Figure 21( See C).

[0227] Next, the release adhesive 464 is dissolved or plasticized to remove the release adhesive from the first element layer 410. Remove the adhesive 464 and the temporary support substrate 466 (see Figure 21(D)).

[0228] Furthermore, the surface of the first element layer 410 is exposed by applying the release adhesive 464 with water or a solvent. It is preferable to remove it.

[0229] As a result, the first element layer 410 can be fabricated on the first substrate 401.

[0230] Next, the second substrate 4 is formed using the same formation method as shown in Figures 21(A) to 21(D). 05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second The element layer 411 and are formed (see Figure 22(A)).

[0231] The insulating film 440 of the second element layer 411 is made of the same material as the insulating film 420, where It can be formed using organic resin.

[0232] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first The element layer 410 and the second element layer 411 are bonded together (see Figure 22(B)).

[0233] The sealing layer 432 allows for, for example, solid sealing. However, the sealing layer 432 is Therefore, a flexible configuration is preferred. As the sealing layer 432, for example, glass frit Glass materials such as glass, two-component resins that harden at room temperature, and photocurable resins. Resin materials such as thermosetting resins can be used.

[0234] Based on the above, the display device 400 can be manufactured.

[0235] <Method for manufacturing a display device 2> Next, another method for manufacturing a display device 400 according to one aspect of the present invention will be described using Figure 23. Let me explain. Note that in Figure 23, inorganic insulating films are used as insulating film 420 and insulating film 440. Let me explain the configuration.

[0236] First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is applied to the release layer 463. The first element layer 410 is formed on the insulating film 420 (see Figure 23(A)).

[0237] Examples of materials for the release layer 463 include tungsten, molybdenum, titanium, tantalum, and niobium. Nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, os An element selected from iridium, iridium, and silicon, an alloy material containing the element, or the element Compound materials containing elements can be used, and single-layer or laminated structures can be employed. In the case of a layer containing silicon, the crystal structure of the silicon-containing layer may be amorphous, microcrystalline, or polycrystalline. Either crystal or single crystal is acceptable.

[0238] The release layer 463 is formed by sputtering, PECVD, coating, printing, or the like. Yes, it is possible. The coating methods include spin coating, droplet dispensing, and dispensing.

[0239] If the release layer 463 has a single-layer structure, it may contain tungsten, molybdenum, or tungsten and molybdenum. It is preferable to form a layer containing a butene mixture. Alternatively, tungsten oxide or This is a layer containing oxidized nitride, a layer containing molybdenum oxide or oxidized nitride, or tang A layer containing an oxide or oxidized nitride of a mixture of stainless steel and molybdenum may be formed. Oh, a mixture of tungsten and molybdenum is, for example, an alloy of tungsten and molybdenum. It corresponds to this.

[0240] Furthermore, the release layer 463 is the sum of a layer containing tungsten and a layer containing tungsten oxide. When forming a layered structure, a layer containing tungsten is formed, and an oxide layer is formed on top of it. By forming an insulating layer, tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. The formation of a tungsten-containing layer may also be utilized. Alternatively, the surface of the tungsten-containing layer may be treated with hot acid. Oxidizing power of chemical treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, ozonated water, etc. A layer containing tungsten oxide may be formed by treatment with a strong solution. Razma treatment and heat treatment can be performed using oxygen, nitrogen, nitrous oxide alone, or a combination of these gases and other gases. This may be carried out in a mixed gas atmosphere with S. The above plasma treatment or heat treatment produces a peeled layer 4 By changing the surface state of 63, the tightness between the release layer 463 and the later formed insulating film 420 can be improved. It is possible to control the adhesion.

[0241] The insulating film 420 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, or a silicon oxide nitride film. A low-permeability inorganic insulating film, such as an aluminum oxide film, can be used. The border film can be formed using methods such as sputtering or PECVD.

[0242] Next, the first element layer 410 and the temporary support substrate 466 are bonded together using a release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the peeling layer 463. The film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see Figure 23(B)). ).

[0243] Furthermore, various methods can be used as appropriate for the transfer process to the temporary support substrate 466. If a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal By weakening the oxide film through crystallization, the insulating film 420 can be peeled off from the peeling layer 463. Furthermore, if the release layer 463 is formed with a tungsten film, ammonia water and hydrogen peroxide are used. The tungsten film may be removed while etching it with a water-based solution.

[0244] Furthermore, by permeating the interface between the release layer 463 and the insulating film 420 with liquid, the insulating film is released from the release layer 463. 420 may be peeled off. As the above liquid, for example, water, a polar solvent, etc. can be used. It can be done. At the interface where the insulating film 420 is peeled off, specifically at the interface between the peeling layer 463 and the insulating film 420. By permeating the liquid, static electricity generated during peeling is applied to the first element layer 410. It can suppress the effects of electricity, etc.

[0245] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (Figure 23(C)). reference).

[0246] Next, the release adhesive 464 is dissolved or plasticized to remove the release adhesive from the first element layer 410. Remove the adhesive 464 and the temporary support substrate 466 (see Figure 23(D)).

[0247] Furthermore, the surface of the first element layer 410 is exposed by applying the release adhesive 464 with water or a solvent. It is preferable to remove it.

[0248] As a result, the first element layer 410 can be fabricated on the first substrate 401.

[0249] Next, the second substrate 4 is formed using the same formation method as shown in Figures 23(A) to 23(D). 05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second The element layer 411 and the second element layer 411 are formed. Then between the first element layer 410 and the second element layer 411 A sealing layer 432 is filled into the first element layer 410 and the second element layer 411 are bonded together. ru.

[0250] Finally, an anisotropic conductive film and FPC (Flexible Printed Circuit) are applied to the connecting electrodes. Attach the cuit. You can also mount an IC chip or other components if necessary.

[0251] Based on the above, the display device 400 can be manufactured.

[0252] <About the structure of oxide semiconductors> The structure of oxide semiconductors will be described below.

[0253] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Examples include conductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors.

[0254] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0255] <caac-os> First, let's explain CAAC-OS. Note that CAAC-OS is referred to as CANC(CA This is called an oxide semiconductor having xis (aligned nanocrystals). It's also possible.

[0256] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0257] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur.

[0258] The following describes CAAC-OS as observed by TEM. Figure 24(A) shows, This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, done in Japan. This is performed using an atomic-resolution analytical electron microscope, such as the JEM-ARM200F, manufactured by this electronics company. It is possible.

[0259] Figure 24(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 24(A). Figure 24(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is such that the surface forming the CAAC-OS film (also called the surface to be formed) Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed.

[0260] As shown in Figure 24(B), CAAC-OS has a characteristic atomic arrangement. Figure 24(C) The characteristic atomic arrangement is shown with auxiliary lines. Figures 24(B) and 24(C) Therefore, the size of each pellet is approximately 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. Therefore, Lett can also be called a nanocrystal (nc).

[0261] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 6120 are used. The arrangement of the To6100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 24(D)). The tilt between the pellets observed in Figure 24(C) The area where the condensation is occurring corresponds to region 6161 shown in Figure 24(D).

[0262] Furthermore, Figure 25(A) shows the Cs in the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 25(A). Magnified Cs-corrected high-resolution TEM images are shown in Figures 25(B), 25(C), and 25(B), respectively. As shown in 25(D). From Figures 25(B), 25(C), and 25(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0263] Next, the CA was analyzed by X-ray diffraction (XRD). Let's discuss AC-OS. For example, CAAC-OS, which has an InGaZnO4 crystal. In contrast, when structural analysis is performed using the out-of-plane method, as shown in Figure 26(A)... In some cases, a peak may appear at a diffraction angle (2θ) near 31°. This peak is in InGaZ Since it is attributed to the (009) plane of the nO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0264] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31°. In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that some of the crystals in CAAC-OS do not have c-axis orientation. This indicates that the more preferable CAAC-OS is the structural solution by the out-of-plane method. Analysis revealed a peak around 31° for 2θ, but no peak around 36° for 2θ.

[0265] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 26(B). Furthermore, if it is a single-crystal oxide semiconductor of InGaZnO4, then fixing 2θ to around 56°, φs If this occurs, the crystal plane is assigned to the equivalent of the (110) plane, as shown in Figure 26(C). Six lines are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0266] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 27(A) (limited field transmission electron diffraction) is observed. Sometimes a pattern (also called a diffraction pattern) may appear. This diffraction pattern is indicative of InGaZnO4. The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals... The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be seen that it is oriented in a vertical direction. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. Figure 27(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. Figure 27 (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also shows that It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. Note that the first ring in Figure 27(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the (100) surface, etc. Also, the second ring in Figure 27(B) is (110) This is thought to be caused by the surface, etc.

[0267] Furthermore, CAAC-OS is an oxide semiconductor with a low defect level density. Examples include defects caused by impurities and oxygen deficiencies. Therefore, CAA C-OS can also be described as an oxide semiconductor with a low impurity concentration. Also, CAAC-OS It can also be described as an oxide semiconductor with few oxygen vacancies.

[0268] Impurities contained in oxide semiconductors can act as carrier traps or carrier sources. In some cases, oxygen vacancies in oxide semiconductors can act as carrier traps, or water Capturing a primal can sometimes lead to the generation of a carrier.

[0269] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0270] Furthermore, oxide semiconductors with a low defect level density (few oxygen vacancies) have a low carrier density. Such oxide semiconductors can be processed using high-purity intrinsic or substantially high-purity intrinsic acid. It is called a monoxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, It is likely to become a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore, CAA Transistors using C-OS exhibit an electrical characteristic where the threshold voltage is negative (normally). Also called "on." ) It rarely becomes [unclear]. Also, high-purity intrinsic or substantially high-purity intrinsic acid. Ion semiconductors have fewer carrier traps. Carriers are trapped in the carrier traps of oxide semiconductors. The charged particles take a long time to release, behaving almost like fixed charges. Yes, there is. Therefore, transients using oxide semiconductors with high impurity concentrations and high defect level densities are used. The sta may have unstable electrical characteristics. On the other hand, the transistor using CAAC-OS This results in a transistor with minimal fluctuations in electrical characteristics and high reliability.

[0271] Furthermore, because CAAC-OS has a low defect level density, it is less susceptible to defects generated by light irradiation, etc. The rear is rarely captured by the defect level. Therefore, the tracer using CAAC-OS The radiator exhibits minimal changes in electrical properties due to irradiation with visible or ultraviolet light.

[0272] <Microcrystalline oxide semiconductor> Next, we will explain microcrystalline oxide semiconductors.

[0273] Microcrystalline oxide semiconductors are regions where crystalline parts can be observed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be identified. It is contained in microcrystalline oxide semiconductors. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline It is called Oxide Semiconductor. nc-OS is, for example, high resolution. In TEM images, grain boundaries may not be clearly visible. Note that the nanocrystals are CAAC. -It may share the same origin as pellets in OS. Therefore, nc-O The crystalline portion of S is sometimes called a pellet.

[0274] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. However, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a larger diameter than pellets compared to nc-OS. When structural analysis is performed using this method, the out-of-plane method shows the crystal planes. No peak is detected. Also, for nc-OS, a probe diameter larger than the pellet (e.g.) For example, when electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or more, A diffraction pattern resembling a halo pattern is observed for nc-OS. Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the pellet size. When this is done, a spot is observed. Also, when nanobeam electron diffraction is performed on nc-OS In some cases, a region of high brightness can be observed in a circular (ring-shaped) pattern. Furthermore, phosphorus Multiple spots may be observed within a circular area.

[0275] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0276] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than amorphous oxide semiconductors. However, nc-OS There is no regularity in crystal orientation between different pellets. Therefore, nc-OS is CA Compared to AC-OS, the defect level density is higher.

[0277] <Amorphous oxide semiconductor> Next, we will explain amorphous oxide semiconductors.

[0278] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and which do not have crystalline regions. It is a semiconductor. One example is an oxide semiconductor that has an amorphous state, such as quartz.

[0279] In amorphous oxide semiconductors, crystalline regions cannot be observed in high-resolution TEM images.

[0280] When structural analysis of amorphous oxide semiconductors is performed using an XRD device, out-of-pl Analysis using the ANE method does not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semiconductors... When electron diffraction is performed on a material, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... In contrast, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is visible. It is measured.

[0281] Various views have been expressed regarding amorphous structures. For example, some argue that the atomic arrangement has absolutely no order. A structure that does not have a completely amorphous structure It is sometimes called the cture. Also, up to the nearest neighbor distance or the second nearest neighbor distance. A structure that possesses order but lacks long-range order is sometimes called an amorphous structure. According to the most rigorous definition, an amorphous oxide semiconductor is defined as an oxide semiconductor that has even a slight order in its atomic arrangement. It cannot be called a crystalline oxide semiconductor. Furthermore, it is an oxide with long-range order. A semiconductor cannot be called an amorphous oxide semiconductor. Therefore, since it has crystalline parts, For example, CAAC-OS and nc-OS are amorphous oxide semiconductors or completely amorphous acids It cannot be called a monstrous semiconductor.

[0282] <Amorphous-like oxide semiconductor> Furthermore, oxide semiconductors may have a structure between nc-OS and amorphous oxide semiconductors. Such an oxide semiconductor having such a structure is called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called.

[0283] a-like OS exhibits porosity (also called voids) in high-resolution TEM images. In some cases, the crystalline region can be clearly identified in high-resolution TEM images. It has a region where the crystalline part cannot be identified, and a region where the crystalline part cannot be identified.

[0284] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0285] As samples to be irradiated with electrons, a-like OS, nc-OS, and CAAC-OS were selected. All samples are In-Ga-Zn oxide.

[0286] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts.

[0287] The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0288] Figure 28 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 28, a-lik It can be seen that the crystalline portion of eOS increases in proportion to the cumulative amount of electron irradiation. As shown in (1) in Figure 28, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially 4.2 × 10¹⁶ in size, changed when the cumulative irradiation dose reached 4.2 × 10¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS And CAAC-OS has a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, Figure As shown in (2) and (3) of 28, regardless of the cumulative dose of electrons, nc-OS and The size of the crystalline portion of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It becomes clear that...

[0289] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It can be seen that it cannot be seen. That is, a-like OS is nc-OS and CAAC-O Compared to S, it is clear that it has an unstable structure.

[0290] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0291] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0292] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, we can estimate the density equivalent to a single crystal at any given composition. It is possible to achieve a density equivalent to a single crystal of any composition by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals.

[0293] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, and microcrystalline oxides. The film may be a multilayer film containing two or more types of semiconductors and CAAC-OS.

[0294] <Film deposition model> The following describes an example of a film deposition model for CAAC-OS and nc-OS.

[0295] Figure 29(A) shows the deposition process of CAAC-OS by sputtering. This is a schematic diagram of the interior.

[0296] Target 6130 is bonded to the backing plate. Multiple magnets are placed in positions facing the target 6130. A magnetic field is generated by the magnet. The magnetic field from the magnet is used to increase the film deposition rate. The sputtering method is also known as magnetron sputtering.

[0297] The substrate 6120 is positioned facing the target 6130, and the distance d(t The distance between the board and the substrate (also called the TS distance) is preferably 0.01m or more and 1m or less. The depth should be between 0.02 m and 0.5 m. The deposition chamber should be mostly filled with deposition gas (e.g., acid Filled with a mixed gas containing 5% or more by volume of ions, argon, or oxygen, and 0.01 The pressure is controlled to be between Pa and 100 Pa, preferably between 0.1 Pa and 10 Pa. By applying a voltage above a certain level to target 6130, discharge begins and plasma is confirmed. It is confirmed. Furthermore, a high-density plasma region is formed in the vicinity of target 6130 by the magnetic field. This is achieved. In the high-density plasma region, the film deposition gas is ionized, and ion 6101 is produced. It occurs. Ion 6101 is, for example, the cation of oxygen (O + ) and argon cations (A r + ) and so on.

[0298] Here, target 6130 has a polycrystalline structure having multiple crystal grains, and any of the The crystal grains contain cleavage planes. Figure 30(A) shows, as an example, the grains contained in target 6130. The crystal structure of InGaZnO4 is shown. Note that Figure 30(A) is taken from a direction parallel to the b-axis. This is the structure when observing the crystal of InGaZnO4. From Figure 30(A), two adjacent structures In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged in close proximity to each other. It can be seen that it is present. And because the oxygen atom has a negative charge, two adjacent G A repulsive force is generated between the a-Zn-O layers. As a result, the InGaZnO4 crystals are adjacent to each other. There is a cleavage plane between the two Ga-Zn-O layers.

[0299] Ions 6101 generated in the high-density plasma region are applied towards the target 6130 by the electric field. It is accelerated and eventually collides with target 6130. At this time, from the cleavage plane, it becomes flat or pellet-like. The pellets 6100a and 6100b, which are sputtered particles in a tang shape, peel off and are struck. It is released. Note that pellets 6100a and 6100b are ions 6101 The impact of a collision can cause structural distortion.

[0300] Pellet 6100a is a flat plate or pellet having a triangular, for example, equilateral triangle plane. These are sputtered particles. Also, pellet 6100b has a hexagonal, for example, regular hexagonal plane. These are flat or pellet-shaped sputtered particles. Note that pellet 6100a and Pellet 6 is a general term for flat or pellet-shaped sputtered particles such as pellet 6100b. It is called 100. The planar shape of pellet 6100 is not limited to triangles or hexagons, for example. In some cases, the shape may be formed by combining multiple triangles. For example, a triangle (for example, an equilateral triangle) In some cases, the shape may be a quadrilateral (for example, a rhombus) formed by combining two of the shapes.

[0301] The thickness of pellet 6100 is determined by the type of film-forming gas used, etc. The reason will be explained later. The thickness of the pellet 6100 is preferably uniform. Also, the sputtered particles have a uniform thickness. A pellet shape is preferable to a thick, cube-shaped shape. T6100 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. The following applies. Furthermore, for example, the pellet 6100 has a width of 1 nm to 3 nm, preferably. The size shall be between 1.2 nm and 2.5 nm. Pellet 6100 is (1) in Figure 28 above. This corresponds to the initial nucleus described above. For example, target 61 having In-Ga-Zn oxide. When ion 6101 is collided with 30, the Ga-Zn-O layer, as shown in Figure 30(B), Pellet 6100, which has three layers including an In-O layer and a Ga-Zn-O layer, peels off. Figure 30 (C) shows the structure of the detached pellet 6100 as observed from a direction parallel to the c-axis. The 6100 has two Ga-Zn-O layers (pan) and an In-O layer (fill). It can also be called a sandwich structure of no size.

[0302] Pellet 6100 may become negatively or positively charged on its sides as it passes through the plasma. Pellet 6100 may have negatively charged oxygen atoms located on its sides, for example. Because the sides have charges of the same polarity, repulsion occurs between the charges, resulting in a flat or plate-like shape. It becomes possible to maintain a net-like shape. Furthermore, CAAC-OS is In-Ga-Zn In the case of an oxide, the oxygen atom bonded to the indium atom may become negatively charged. Alternatively, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom becomes negatively charged. It is possible. Also, when pellet 6100 passes through the plasma, the in When growing by bonding with atoms such as zinc, gallium, zinc, and oxygen. There is a difference in size between (2) and (1) in Figure 28 above, which corresponds to the growth in the plasma. Here, if the substrate 6120 is at room temperature, the pellets on the substrate 6120 Growth of 6100 is unlikely, so it becomes nc-OS (see Figure 29(B)). At room temperature. Because it can be formed in this way, nc-OS can be formed even when the substrate 6120 has a large area. Yes. Furthermore, in order to grow pellet 6100 in plasma, the sputtering method is used. It is effective to increase the film deposition power. By increasing the film deposition power, pellet 61 The structure of 00 can be stabilized.

[0303] As shown in Figures 29(A) and 29(B), for example, the pellet 6100 is plasma It flies through the air like a kite, fluttering upwards onto circuit board 6120. Pellet 61 Because 00 is charged, it approaches an area where other pellets 6100 have already accumulated. Then, a repulsive force is generated. Here, on the upper surface of the substrate 6120, in an orientation parallel to the upper surface of the substrate 6120 A magnetic field (also called a horizontal magnetic field) is generated. Also, the substrate 6120 and target 61 Between 30, a potential difference is applied, so the direction from substrate 6120 to target 6130 Current flows in the direction of the magnetic field. Therefore, the pellet 6100 is magnetic on the upper surface of the substrate 6120. A force (Lorentz force) is exerted by the action of a field and an electric current. This is Fleming's It can be understood through the left-hand rule.

[0304] Pellet 6100 has a larger mass than a single atom. Therefore, the upper surface of substrate 6120 In order to move something, it is important to apply some kind of external force. One of those forces is magnetism. It is possible that this force is generated by the action of a field and an electric current. To apply sufficient force to move the upper surface of 120, on the upper surface of the substrate 6120, A magnetic field parallel to the upper surface of plate 6120 is 10G or more, preferably 20G or more, more preferably Alternatively, a region with a capacitance of 30G or more, more preferably 50G or more, may be provided. On the upper surface of 6120, a magnetic field parallel to the upper surface of the substrate 6120 is present on the upper surface of the substrate 6120. A magnetic field perpendicular to the plane that is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. It is preferable to provide a region that is five times or more more.

[0305] At this time, the magnet and the substrate 6120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 6120 continues to change. On the upper surface of 6120, the pellet 6100 is subjected to forces from various directions, and in various directions It can be moved.

[0306] Furthermore, as shown in Figure 29(A), when the substrate 6120 is heated, the pellet 6100 The resistance between the pellet and the substrate 6120 due to friction and other factors is low. As a result, The pellet 6100 moves as if gliding across the top surface of the substrate 6120. The movement occurs with the flat surface facing the substrate 6120. Subsequently, other particles already deposited... When it reaches the side of the pellet 6100, the sides connect. At this point, pellet 610 The oxygen atom on the 0 side is eliminated. The eliminated oxygen atom then acts as an acid in CAAC-OS. Because primary defects may be filled, CAAC-OS results in a low defect level density. The temperature of the top surface of the 6120 is, for example, between 100°C and 500°C, and between 150°C and 450°C. It is sufficient to set it to full temperature, or between 170°C and 400°C. Therefore, the substrate 6120 has a large area Even in that case, CAAC-OS film deposition is possible.

[0307] Furthermore, when the pellet 6100 is heated on the substrate 6120, the atoms rearrange, The structural strain caused by the collision of ion 6101 is relieved. The strain-relieved pellet 61 00 is almost a single crystal. Because pellet 6100 is almost a single crystal, Even if the pellets 6100 are heated after they have bonded together, the pellets 6100 themselves do not expand or contract. This is highly unlikely to occur. Therefore, the gaps between pellets 6100 widen, causing the crystal grains to expand. It does not form defects such as boundaries or crevasses.

[0308] Furthermore, CAAC-OS is not made of a single sheet of single-crystal oxide semiconductor, The aggregate of pellet 6100 (nanocrystals) is arranged like a stack of bricks or blocks. They are arranged in rows. Also, there are no grain boundaries between the pellets 6100. Therefore, CAAC-OS underwent deformation such as shrinkage due to heating during film formation, heating after film formation, or bending. Even in such cases, it is possible to relieve local stress or release strain. Therefore, This structure is suitable for use in semiconductor devices that have ductility. Note that nc-OS is a pellet The arrangement resembles a chaotic stacking of 6100 (nanocrystals).

[0309] When target 6130 was sputtered with ion 6101, not only pellet 6100 but also In some cases, zinc oxide may peel off. Zinc oxide is lighter than pellet 6100. First, it reaches the top surface of substrate 6120. Then, 0.1nm to 10nm, 0.2 Forms a zinc oxide layer 6102 with a thickness of 0.5 nm to 2 nm or between 5 nm. Figure 31 shows a schematic cross-sectional view.

[0310] As shown in Figure 31(A), pellets 6105a and pellets are placed on the zinc oxide layer 6102. 6105b and 6105b are deposited. Here, pellets 6105a and 6105b are mutual They are arranged so that their sides are in contact with each other. Also, pellet 6105c is pellet 6105 After being deposited on b, it moves by sliding on pellet 6105b. Also, pellet 610 In another aspect of 5a, multiple particles 6103 detached from the target along with zinc oxide. However, heating from the substrate 6120 causes crystallization, forming region 6105a1. Particle 6103 may contain oxygen, zinc, indium, and gallium, among other things.

[0311] Then, as shown in Figure 31(B), region 6105a1 is integrated with pellet 6105a. And it becomes pellet 6105a2. Also, pellet 6105c has its side surface as pellet 6 Position it so that it is in contact with another side of 105b.

[0312] Next, as shown in Figure 31(C), pellet 6105d is further placed on pellet 6105a2. And after being deposited on pellet 6105b, on pellet 6105a2 and pellet 61 It moves smoothly along 05b. It also moves towards another side of pellet 6105c. The pellet 6105e slides along the zinc oxide layer 6102.

[0313] Then, as shown in Figure 31(D), the pellet 6105d has a side surface that is that of pellet 610 It is positioned so as to be in contact with the side of 5a2. Also, the side of pellet 6105e is pellet Position it so as to be in contact with another side of pellet 6105c. Also, position it so as to be in contact with another side of pellet 6105d. In this case, multiple particles 6103 that were peeled off from target 6130 together with zinc oxide are on the substrate Crystallization occurs upon heating from 6120, forming region 6105d1.

[0314] As described above, the piled pellets are arranged so that they are in contact with each other, and the sides of the pellets are formed As lengthening occurs, CAAC-OS is formed on the substrate 6120. Therefore, CAA C-OS pellets are larger than nc-OS pellets. (3) The difference in size between (1) and (2) corresponds to the growth after deposition.

[0315] Furthermore, the gaps between pellets become extremely small, allowing for the formation of a single large pellet. In some cases, one large pellet has a single-crystal structure. For example, the size of the pellet The grain, when viewed from the top surface, is between 10nm and 200nm, between 15nm and 100nm, or The wavelength may be between 20nm and 50nm. In this case, the acid used in the miniature transistors... In synthetic semiconductors, the channel formation region can sometimes be contained within a single large pellet. Furthermore, regions having a single-crystal structure can be used as channel-forming regions. As the size increases, the region having a single crystal structure becomes the channel formation region of the transistor. It may be used as both a source area and a drain area.

[0316] Thus, the channel formation region of the transistor, etc., is formed in a region having a single crystal structure. This can sometimes improve the frequency characteristics of a transistor.

[0317] Based on the above model, it is thought that the pellets 6100 will accumulate on the substrate 6120. It is possible to form CAAC-OS films even when the surface to be formed does not have a crystalline structure. This indicates that it is a different growth mechanism from epitaxial growth. C-OS does not require laser crystallization and allows for uniform film deposition even on large-area glass substrates. This is possible. For example, if the structure of the upper surface (the surface to be formed) of the substrate 6120 is an amorphous structure (for example, non It is possible to deposit CAAC-OS even on crystalline silicon oxide.

[0318] Furthermore, CAAC-OS can be used even if the upper surface of the substrate 6120, which is the surface to be formed on, has irregularities. It can be seen that the pellets 6100 are arranged along the shape of the substrate 6120. If the plane is atomically flat, then the pellet 6100 has a flat surface that is parallel to the ab plane. They are placed side by side toward each other. If the thickness of the pellet 6100 is uniform, then the thickness is uniform and flat, A layer with high crystallinity is formed. Then, n layers of this layer are stacked (where n is a natural number). This allows you to obtain CAAC-OS.

[0319] On the other hand, even if the upper surface of the substrate 6120 has irregularities, CAAC-OS can still use pellets 610 The structure consists of n layers (where n is a natural number) in which zeros are juxtaposed along the contours. (Substrate 61) Because 20 has an uneven surface, CAAC-OS is prone to gaps forming between pellets 6100. There is a fit. However, even in this case, intermolecular forces act between the pellets 6100, and there are irregularities. The pellets are arranged so that the gaps between them are as small as possible. Therefore, even if there are bumps and unevenness This allows for the production of CAAC-OS with high crystallinity.

[0320] Because CAAC-OS is deposited using this model, the sputtered particles have no thickness. Pellet-like form is preferable. Note that if the sputtered particles are in the form of thick cubes... In cases where the surface facing the substrate 6120 is not constant, and the thickness and crystal orientation cannot be made uniform, be.

[0321] The film formation model described above allows for high crystallinity even on a film-forming surface having an amorphous structure. A CAAC-OS having the following characteristics can be obtained.

[0322] <Top view and cross-sectional view of a semiconductor device> Next, using a liquid crystal display device as an example, the appearance of a semiconductor device according to one aspect of the present invention This will be explained using Figure 32. Figure 32 shows substrate 4001 and substrate 4006 sealed with encapsulating material 4005 This is a top view of a liquid crystal display device bonded by [a specific method]. Also, Figure 33 shows the dashed line C1- in Figure 32. This corresponds to the cross-sectional view in C2.

[0323] The pixel section 4002 and the pair of drive circuits 4004 are surrounded on the substrate 4001. A sealing material 4005 is provided. Also, a base is provided on the pixel section 4002 and the drive circuit 4004. A plate 4006 is provided. Therefore, the pixel unit 4002 and the drive circuit 4004 are connected to the substrate. It is sealed by 4001, the sealing material 4005, and the substrate 4006.

[0324] Furthermore, in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, The dynamic circuit 4003 is implemented.

[0325] Furthermore, the pixel section 4002 and the drive circuit 4004 provided on the substrate 4001 are transistors It has multiple such elements. Figure 33 illustrates the transistor 4010 included in the pixel section 4002. On transistor 4010, insulating film 4020 and insulating film 4021 are sequentially layered. The transistor 4010 is provided with insulating film 4020 and insulating film 40 In the opening provided in 21, connected to the pixel electrode 4022 on the insulating film 4021 ru.

[0326] Furthermore, a resin film 4059 is provided on the substrate 4006, and a common resin film 4059 is provided on the resin film 4059. An electrode 4060 is provided. And between substrate 4001 and substrate 4006, a pixel electrode A liquid crystal layer 4028 is provided so as to be sandwiched between electrode 4022 and common electrode 4060. The liquid crystal element 4023 has a pixel electrode 4022, a common electrode 4060, and a liquid crystal layer 4028. do.

[0327] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4022 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Then, the liquid crystal element 4023 is affected by the potential of the image signal applied to the pixel electrode 4022. By controlling the transmittance, it is possible to display gradations.

[0328] Furthermore, as shown in Figure 33, in one embodiment of the present invention, the insulating film 4020 is located at the edge of the panel. And it is removed. And in the region where the insulating film 4020 has been removed, the conductive film 4 050 is formed. Conductive film 4050 and source or drain of transistor 4010 A conductive film that functions as an insulator can be formed by etching a conductive film. ru.

[0329] Furthermore, conductive particles 4061 having electrical conductivity are separated between substrate 4001 and substrate 4006. A scattered resin film 4062 is provided. The conductive film 4050 is connected to the common electrode 4060 and They are electrically connected via the electrically charged particle 4061. That is, the common electrode 4060 and the conductive The film 4050 is electrically connected at the edge of the panel via conductive particles 4061. This means that the resin film 4062 is made of a thermosetting resin or an ultraviolet curing resin. It is possible to do so. In addition, the conductive particles 4061 can be, for example, spherical organic resins such as Au, Ni, and C. Particles coated with a thin film of metal such as o can be used.

[0330] Although the alignment layer is not shown in Figure 33, the alignment layer is connected to the pixel electrode 4022 and the common electrode 4 When placed on 060, the common electrode 4060, conductive particles 4061, and conductive film 4050 To electrically connect them, a portion of the alignment film is removed in the area overlapping with the common electrode 4060. Therefore, the alignment film can be partially removed in the area where it overlaps with the conductive film 4050.

[0331] Furthermore, a liquid crystal display device may display color images by using a color filter. By sequentially illuminating multiple light sources that emit light of different hues, a color image can be displayed. That's good too.

[0332] Furthermore, the image signal from the drive circuit 4003 and various control signals and potentials from the FPC 4018 are also transmitted. The drive circuit 4004 or the pixel unit 400 is connected via the routing wires 4030 and 4031. It is given to 2.

[0333] <Examples of electronic device configurations> A semiconductor device according to one aspect of the present invention is a display device, a notebook personal computer, and a recording device. Image playback device equipped with a media (typically DVD: Digital Versatile) (A device that plays recording media such as discs and has a display capable of displaying the images thereof) It is possible to use a semiconductor device according to one aspect of the present invention. As sub-devices, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, etc. Digital still cameras and other cameras, goggle-type displays (head-mounted displays) i) Navigation systems, sound playback devices (car audio, digital audio players) Layers, etc.), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 34. show.

[0334] Figure 34(A) shows a display device, which includes a housing 5001, a display unit 5002, a support base 5003, etc. A semiconductor device according to one aspect of the present invention is used in a display unit 5002 or other circuits. It is possible. Furthermore, the display device can be used for personal computers, TV broadcast reception, and advertising. This includes all information display devices, such as those used for display purposes.

[0335] Figure 34(B) shows a portable information terminal, consisting of a housing 5101, a display unit 5102, and operation keys 5103. The semiconductor device according to one aspect of the present invention has a display unit 5102 or other circuits. It can be used.

[0336] Figure 34(C) shows a display device, which has a curved housing 5701, a display unit 5702, etc. By using a flexible substrate in a semiconductor device according to one aspect of the present invention, a curved surface is obtained. The semiconductor device can be used in the display unit 5702 supported by the housing 5701.

[0337] Figure 34(D) shows a portable game console, comprising a casing 5301, casing 5302, display unit 5303, Display unit 5304, microphone 5305, speaker 5306, operation keys 5307, stand It has illustration 5308, etc. A semiconductor device according to one aspect of the present invention has a display unit 5303, display It can be used in part 5304 or other circuits. The band-type game console has two display units 5303 and 5304, but the portable game The number of display units in the device is not limited to this.

[0338] Figure 34(E) is an e-book, which has a housing 5601, a display unit 5602, etc. One of the present inventions The semiconductor device according to this embodiment can be used in the display unit 5602 or other circuits. By using a flexible substrate, the semiconductor device can be made flexible. .

[0339] Figure 34(F) shows a mobile phone, with a housing 5901 containing a display unit 5902, a microphone 5907, and a microphone. The speaker 5904, camera 5903, external connection unit 5906, and operation buttons 5905 are provided. It is installed. The display unit 5902 or other circuit is connected to a semiconductor device according to one aspect of the present invention. It can be used. Furthermore, a semiconductor device according to one aspect of the present invention can be made on a flexible substrate. When formed, the display section 5902 having a curved surface as shown in Figure 34(F) will be the semiconductor device. It is possible to apply this. [Examples]

[0340] Next, a transistor was fabricated using a CAAC-OS film, and the gate voltage VG(V) was... This section explains the results of measuring the drain current ID(A) value.

[0341] The fabricated transistor had the same layered structure as transistor 10 shown in Figure 3. The fabricated transistor has a channel length L of 6 μm and a channel width W of 3 μm, The length was 10 cm, and the Lov length was 2 μm. Also, in the channel width direction, the opening 23 Alternatively, the distance ΔW between the edge of the opening 24 and the edge of the oxide semiconductor film 14 was set to 1.5 μm. Note that the channel width W is the opening 23 or in the direction perpendicular to the channel length. This corresponds to the width of the opening 24. Furthermore, the Lov length refers to the function of the source or drain. The distance in the channel length direction in the region where the conductive film and the conductive film that functions as a gate overlap. It means separation.

[0342] Furthermore, the conductive film 12 consists of a titanium film with a thickness of 35 nm and a copper film with a thickness of 200 nm, which are laminated together. A conductive film obtained by this process was used. As the insulating film 13, a silicon nitride film with a thickness of 400 nm and a film An insulating film obtained by sequentially stacking a 50 nm thick silicon oxide nitride film was used. As the semiconductor film 14, a metal oxide with an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used. A target composed of the above was used to form an InGa-Zn acid with a film thickness of 35 nm. A crystalline semiconductor film was used. Conductive film 16 and conductive film 17 consisted of a titanium film with a thickness of 35 nm and A conductive film was used, obtained by sequentially stacking a copper film with a thickness of 200 nm. Insulating film 20a A silicon oxide nitride film with a thickness of 50 nm was used as the insulating film 20b, with a thickness of 400 nm. A silicon oxide nitride film was used. A silicon nitride film with a thickness of 100 nm was used as the insulating film 21.

[0343] The value of the drain current ID(A) for the gate voltage VG(V) of the fabricated transistor. The measurement results are shown in Figure 35.

[0344] Furthermore, by forming a nitride insulating film in contact with the oxide semiconductor film, the oxide semiconductor The resistivity of metal oxide films obtained by reducing the resistance of the film was investigated. As the body membrane, a target composed of a metal oxide with In:Ga:Zn=1:1:1 is used. Using an In-Ga-Zn oxide semiconductor film formed by this process, a silicon nitride film is used as the nitride insulating film. When used, it is obtained by reducing the resistance of the In-Ga-Zn oxide semiconductor film. The resistivity of the film is approximately 7.0 × 10⁻⁶. -3 It was estimated to be [Ω·cm].

[0345] Furthermore, the transmittance of the above metal oxide film was investigated. Figure 36 shows the In-G The transmittance of a sample obtained by sequentially stacking an a-Zn oxide semiconductor film and a silicon nitride film is It exhibits wavelength dependence. Note that the In-Ga-Zn oxide semiconductor film has an In:Ga:Zn ratio of 1: It is formed using a target composed of a 1:1 metal oxide, and its film thickness is 35n m was used. The silicon nitride film was deposited at a substrate temperature of 350°C, and its film thickness was 100 nm. As shown in Figure 36, the transmission of the above sample in the visible light region, from 380 nm to 770 nm, is as follows: The rate was found to be over 70%.

[0346] Furthermore, a prototype liquid crystal display having the pixels 30 shown in Figure 5 was fabricated. However, the prototype liquid crystal display The pixel 30 of the device has the same structure as shown in the cross-sectional view in Figure 9(A). See Table 1 below. The specifications of the prototype liquid crystal display device are shown below.

[0347] [Table 1]

[0348] Figure 37 shows a photograph of an image displayed on the prototype liquid crystal display device. [Explanation of symbols]

[0349] C1 Capacitive element C2 Capacitive element CLK1 signal CLK2 signal CLK3 signal CLK4 signal GL1 Wiring M1 Transistor M2 Transistor M3 Transistor M4 Transistor M5 Transistor M6 Transistor M7 Transistor M8 Transistor M9 Transistor M10 Transistor M11 Transistor M12 Transistor M13 Transistor M14 Transistor M15 Transistor PWC1 signal SL1 Wiring T1 Wiring T2 Wiring T3 Wiring T4 wiring T5 Wiring T6 wiring T7 Wiring T8 Wiring T9 Wiring 10 transistors 10A Transistor 10B Transistor 10D Transistor 10P Transistor 11 circuit boards 12 Conductive film 12A conductive film 12B conductive film 13 Insulating Film 14 Oxide semiconductor film 14A Oxide Semiconductor Film 14B Oxide Semiconductor Film 15 Insulating film 15a insulating film 15b Insulating film 16. Conductive film 16A conductive film 16B Conductive film 17 Conductive film 17A conductive film 17B Conductive film 18 areas 19 End 20 Insulating film 20a insulating film 20b insulating film 21 Insulating film 22 Conductive film 22A conductive film 23 Opening 23A opening 23B opening 24 openings 24A opening 24B opening 25 Opening 30 pixels 31 Capacitive elements 32 Metal oxide film 32a Oxide semiconductor film 33 Conductive film 34 Opening 35 Opening 36 Opening 37 Conductive film 38. Orientation film 40 circuit boards 41 Shielding membrane 42 Colored layer 43 Resin film 44 Conductive film 45 Orientation film 46 liquid crystal layers 50 Conductive film 51 Conductive film 52 Opening 53 Opening 54 Conductive film 55 Opening 60 opening 61 Insulating film 70 Display device 71 pixel section 72 Drive Circuit 73 Drive Circuit 74 liquid crystal elements 76 transistors 77 transistors 78 Capacitive elements 79 Light-emitting element 360 connecting electrodes 380 Anisotropic conductive film 400 display device 401 circuit board 405 circuit board 410-element layer 411-element layer 412 Adhesive layer 418 Adhesive layer 420 Insulating film 432 Sealing layer 440 insulating film 462 circuit boards 463 Delamination layer 464 Release Adhesive 466 Temporary support board 468 Laser light 4001 circuit board 4002 pixel section 4003 Drive Circuit 4004 Drive Circuit 4005 Sealing material 4006 circuit board 4010 Transistor 4018 FPC 4020 Insulating film 4021 Insulating film 4022 Pixel Electrodes 4023 Liquid crystal element 4028 Liquid Crystal Layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 enclosure 5002 Display section 5003 Support stand 5101 enclosure 5102 Display section 5103 Operation Keys 5301 enclosure 5302 enclosure 5303 Display section 5304 Display section 5305 Microphone 5306 Speaker 5307 Operation Keys 5308 Stylus 5601 enclosure 5602 Display section 5701 enclosure 5702 Display section 5901 enclosure 5902 Display section 5903 Camera 5904 Speaker 5905 button 5906 External connection section 5907 Mike 6100 pellets 6100a pellets 6100b pellets 6101 Aeon 6102 Zinc oxide layer 6103 particles 6105a Pellet 6105a1 area 6105a2 pellets 6105b Pellet 6105c pellets 6105d Pellet 6105d1 area 6105e Pellets 6120 circuit board 6130 Target 6161 area

Claims

1. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having a region positioned above the insulating surface and functioning as the gate electrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A second conductive film having a region positioned above the first insulating film, functioning as the other electrode of the capacitive element, and being light-transmitting, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the second conductive film, and containing silicon oxide, A third conductive film is electrically connected to the oxide semiconductor film and to the first electrode, A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a region that is electrically connected to the second conductive film, functions as a second wiring that supplies potential to the second conductive film, and extends in the first direction across the pixel and adjacent pixels, A third insulating film having a region positioned above the second conductive film, a region positioned above the third conductive film, and a region positioned above the fourth conductive film, The display element has a second electrode having a region positioned above the first electrode, The first electrode has a region positioned above the third insulating film, The second conductive film has a first region that does not overlap with the fifth conductive film and does not overlap with the second insulating film. The upper surface of the first region has a region in contact with the third insulating film, The fifth conductive film does not overlap with the fourth conductive film. Display device.

2. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having a region positioned above the insulating surface and functioning as the gate electrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A second conductive film having a region positioned above the first insulating film, functioning as the other electrode of the capacitive element, and being light-transmitting, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the second conductive film, and containing silicon oxide, A third conductive film is electrically connected to the oxide semiconductor film and to the first electrode, A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a region that is electrically connected to the second conductive film, functions as a second wiring that supplies potential to the second conductive film, and extends in the first direction across the pixel and adjacent pixels, A third insulating film having a region positioned above the second conductive film, a region positioned above the third conductive film, and a region positioned above the fourth conductive film, The display element has a second electrode having a region positioned above the first electrode, The first electrode has a region positioned above the third insulating film, The second conductive film has a first region that does not overlap with the fifth conductive film and does not overlap with the second insulating film. The upper surface of the first region has a region in contact with the third insulating film, The fifth conductive film does not overlap with the fourth conductive film. The second conductive film does not overlap with the third conductive film. Display device.

3. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having a region positioned above the insulating surface and functioning as the gate electrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A second conductive film having a region positioned above the first insulating film, functioning as the other electrode of the capacitive element, and being light-transmitting, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the second conductive film, and containing silicon oxide, A third conductive film is electrically connected to the oxide semiconductor film and to the first electrode, A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a region that is electrically connected to the second conductive film, functions as a second wiring that supplies potential to the second conductive film, and extends in the first direction across the pixel and adjacent pixels, A third insulating film having a region positioned above the second conductive film, a region positioned above the third conductive film, and a region positioned above the fourth conductive film, The display element has a second electrode having a region positioned above the first electrode, The first electrode has a region positioned above the third insulating film, The second conductive film has a first region that does not overlap with the fifth conductive film and does not overlap with the second insulating film. The upper surface of the first region has a region in contact with the third insulating film, The fifth conductive film does not overlap with the fourth conductive film. The second conductive film does not overlap with the fourth conductive film. Display device.

4. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having a region positioned above the insulating surface and functioning as the gate electrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A second conductive film having a region positioned above the first insulating film, functioning as the other electrode of the capacitive element, and being light-transmitting, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the second conductive film, and containing silicon oxide, A third conductive film is electrically connected to the oxide semiconductor film and to the first electrode, A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a region that is electrically connected to the second conductive film, functions as a second wiring that supplies potential to the second conductive film, and extends in the first direction across the pixel and adjacent pixels, A third insulating film having a region positioned above the second conductive film, a region positioned above the third conductive film, and a region positioned above the fourth conductive film, The display element has a second electrode having a region positioned above the first electrode, The first electrode has a region positioned above the third insulating film, The second conductive film has a first region that does not overlap with the fifth conductive film and does not overlap with the second insulating film. The upper surface of the first region has a region in contact with the third insulating film, The fifth conductive film does not overlap with the fourth conductive film. The second conductive film does not overlap with the third conductive film. The second conductive film does not overlap with the fourth conductive film. Display device.

5. In any one of claims 1 to 4, The oxide semiconductor film comprises In, Ga, and Zn. Display device.

Images