Joint defect distribution estimation device, joint defect distribution estimation method, and joint defect distribution estimation program

Abstract

To accurately estimate defect distribution in a junction section in a power module in which a power element and a substrate are joined by the junction section.SOLUTION: A device 100 for estimating bonding defect distribution includes a control device 10. The control device 10 acquires stress waveform distribution indicated by a waveform signal output from each of a plurality of stress sensors 21 of a power module in which a chip structure 20 integrally having a plurality of stress sensors 21 and a power element 22, and a substrate is joined by a junction section to estimate junction defect distribution indicating defect distribution of the junction section in contact with the chip structure 20 according to the acquired stress waveform distribution.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a joint defect distribution estimation device, a joint defect distribution estimation method, and a joint defect distribution estimation program. [Background technology]

[0002] For example, Patent Document 1 describes a technique for predicting failures of solder joints in electronic components soldered to a printed circuit board by attaching strain gauges to the back surface of the printed circuit board. This technique detects vibrations generated during use using strain gauges and analyzes the detected vibration waveforms using machine learning. This makes it possible to determine whether or not a failure will occur within one week after the analysis period (one month).

[0003] Furthermore, as shown in Figure 21, there is a power module on which power elements used in inverters and the like are mounted. Figure 21 is a cross-sectional view showing the structure of power module 400.

[0004] The power module 400 shown in Figure 21 has a substrate 42 mounted on a cooler 43. The substrate 42 is a mounting substrate, and for example, it has a structure in which copper foil (Cu) is stacked on top of a silicon nitride film (SiN). Power elements 200 are mounted on the substrate 42 as bare chips via solder 41. The heat generated by the power elements 200 is removed by the cooler 43, thereby controlling the element temperature. In this type of mounting structure for power module 400, an upper limit is set for the element temperature, and the power elements 200 are operated within a range that does not exceed this upper limit. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-170738 [Overview of the project] [Problems that the invention aims to solve]

[0006] The power element 200 described above is relatively large, approximately 10 mm square, and the heat generated by the power element itself can exceed 100 W. Defects in the solder joints 41 that contact the power element 200 (hereinafter referred to as "joint defects") depend on the stress on the power element 200, the mounting structure, the mounting material, etc., but can be broadly divided into two cases: those that occur at the edges of the element and those that occur in the center of the element. Joint defects include, for example, cracks and peeling. When a joint defect occurs at the edge of the element, the effect on the element temperature is relatively small, while when a joint defect occurs in the center of the element, the effect on the element temperature is relatively large. In this case, even if the area of ​​the region with a joint defect in the center of the element is the same as the area of ​​the region with a joint defect at the edge of the element, the temperature rise tends to be greater in the center of the element compared to the edge of the element.

[0007] Figure 22 illustrates the effect of thermal resistance on the junction defect distribution of the power module 400. Figure 22(A) shows the case where the junction defect is at the end of the element, and Figure 22(B) shows the case where the junction defect is in the center of the element. Note that "junction surface condition" refers to the condition of the junction surface of the solder 41 in contact with the power element 200.

[0008] In the example in Figure 22(A), a junction defect occurs at the edge of the power element 200 when stress is applied due to heat generation. On the other hand, in the example in Figure 22(B), a junction defect occurs in the center of the power element 200 when stress is applied due to heat generation. Comparing the examples in Figure 22(A) and Figure 22(B), it can be seen that the effect on the element temperature when a junction defect occurs in the center of the element (Figure 22(B)) is greater than the effect on the element temperature when a junction defect occurs at the edge of the element (Figure 22(A)). In other words, the rise in element temperature depends on the location of the junction defect (edge ​​or center).

[0009] In contrast, one could consider measuring the strain by placing strain gauges on the power module 400, as in conventional technology.

[0010] Figure 23 is a cross-sectional view showing the structure of a power module to which strain gauges are applied. Figure 23(A) shows the case where strain gauges are placed on the back surface of the power module substrate, and Figure 23(B) shows the case where strain gauges are placed on the upper surface of the element electrodes of the power module.

[0011] In the power module 400A shown in Figure 23(A), the strain gauge 201 is located on the back surface of the substrate 42. However, in this structure, the strain gauge 201 is located between the substrate 42 and the cooler 43, which is undesirable in terms of cooling performance. Also, in the power module 400B shown in Figure 23(B), the element upper electrode 202 is located on the upper surface of the power element 200, and the strain gauge 201 is located on the upper surface of the element upper electrode 202. However, although this structure avoids the cooling problem, the size of the strain gauge 201 is generally 3 to 5 mm, making it difficult to place multiple strain gauges 201 within the element surface of the power element 200. Therefore, even if the strain gauge 201 is applied, the stress distribution of the power element 200 cannot be obtained, and thus it is not possible to accurately estimate the bonding defects, i.e., the defect distribution at the bonding point.

[0012] This disclosure is made in view of the above circumstances and aims to provide a joint defect distribution estimation device, a joint defect distribution estimation method, and a joint defect distribution estimation program that can accurately estimate the defect distribution at a joint in a power module in which a power element and a substrate are joined by a joint. [Means for solving the problem]

[0013] To achieve the above objective, the joint defect distribution estimation device according to the first embodiment comprises: an acquisition unit that acquires a stress waveform distribution indicated by waveform signals output from each of the plurality of stress sensors of a power module in which a chip structure having a plurality of stress sensors and a power element integrally is joined to a substrate by a joint; and an estimation unit that estimates a joint defect distribution indicating the defect distribution of the joint in contact with the chip structure according to the stress waveform distribution acquired by the acquisition unit.

[0014] Furthermore, in the joint defect distribution estimation device according to the second embodiment, the stress waveform distribution is indicated by the waveform signals output from each of the plurality of stress sensors when a predetermined pulse waveform is applied to the power element and current is supplied.

[0015] Furthermore, the joint defect distribution estimation device according to the third embodiment is a joint defect distribution estimation device according to the second embodiment, wherein the chip structure includes a power element region which is the region of the power element and a stress sensor region which is the region of the stress sensor, and further comprises a pulse generation circuit for generating the pulse waveform, a gate drive circuit for applying the pulse waveform to the gate of the power element while controlling the on and off timing of the pulse waveform generated by the pulse generation circuit, a power element power supply for supplying power to the power element, and a stress sensor power supply for supplying power to each of the stress sensors.

[0016] Furthermore, the joint defect distribution estimation device according to the fourth embodiment further comprises, in the joint defect distribution estimation device according to the third embodiment, an analog-to-digital converter that converts waveform signals output from each of the plurality of stress sensors into digital signals, and a generation unit that generates the stress waveform distribution from the digital signals converted by the analog-to-digital converter.

[0017] Furthermore, the joint defect distribution estimation device according to the fifth embodiment further includes a storage unit that stores a trained model generated by machine learning a group of training data obtained by associating each of a plurality of previously acquired stress waveform distributions with each of a plurality of previously acquired joint defect distributions, in addition to the joint defect distribution estimation device according to any one of the first to fourth embodiments. The estimation unit inputs the stress waveform distribution acquired by the acquisition unit to the trained model and outputs the joint defect distribution from the trained model, thereby estimating the joint defect distribution corresponding to the stress waveform distribution.

[0018] Further, the bonding defect distribution estimation device according to the sixth aspect is the bonding defect distribution estimation device according to any one of the first aspect to the fifth aspect, wherein the power element has a rectangular surface defined by a side extending in the X-axis direction and a side extending in the Y-axis direction, the stress sensor is a stress sensor having sensitivity in the X-axis direction, and when the center of the power element is the origin (0, 0) and one vertex is (a, a), the centroid of the plurality of stress sensors arranged in the range surrounded by the four points (0, 0), (a, 0), (0, a), and (a, a) is included in the range surrounded by the four points (0, 0), (a / 2, 0), (0, a), and (a / 2, a).

[0019] Further, the bonding defect distribution estimation device according to the seventh aspect is the bonding defect distribution estimation device according to the sixth aspect, wherein the plurality of stress sensors arranged in the range surrounded by the four points (0, 0), (a, 0), (0, a), and (a, a) are two stress sensors, the distance between the centroid of the sensors and the origin is 0.2a or more and 0.7a or less, the angle between the straight line connecting the centroid of the sensors and the origin and the X-axis direction is 22° or more and 90° or less, the distance between the sensors is 0.14a or more and 0.91a or less, and the angle between the straight line connecting the sensor positions and the X-axis direction is 22° to 90°.

[0020] Further, the bonding defect distribution estimation device according to the eighth aspect is the bonding defect distribution estimation device according to the sixth aspect, wherein the plurality of stress sensors arranged in the range surrounded by the four points (0, 0), (a, 0), (0, a), and (a, a) are three stress sensors, the distance between the centroid of the sensors and the origin is 0.27a or more and 0.61a or less, the angle between the straight line connecting the centroid of the sensors and the origin and the X-axis direction is 27° or more and 81° or less, and the area surrounded by the straight line connecting the sensor positions is 2 as follows.

[0021] Furthermore, in order to achieve the above object, the bonding defect distribution estimation method according to the ninth aspect acquires a stress waveform distribution indicated by waveform signals output from each of the plurality of stress sensors of a power module in which a chip structure integrally having a plurality of stress sensors and a power element is bonded to a substrate by a bonding portion, and estimates a bonding defect distribution indicating a defect distribution of the bonding portion in contact with the chip structure according to the acquired stress waveform distribution.

[0022] Furthermore, in order to achieve the above object, the bonding defect distribution estimation program according to the tenth aspect causes a computer to acquire a stress waveform distribution indicated by waveform signals output from each of the plurality of stress sensors of a power module in which a chip structure integrally having a plurality of stress sensors and a power element is bonded to a substrate by a bonding portion, and estimate a bonding defect distribution indicating a defect distribution of the bonding portion in contact with the chip structure according to the acquired stress waveform distribution.

Advantages of the Invention

[0023] According to the technology of the present disclosure, in a power module in which a power element and a substrate are bonded by a bonding portion, there is an effect that a defect distribution in the bonding portion can be accurately estimated.

Brief Description of the Drawings

[0024] [Figure 1] It is a diagram showing an example of the configuration of a bonding defect distribution estimation device according to an embodiment. [Figure 2] It is a cross-sectional view showing an example of a power module according to an embodiment. [Figure 3] It is a diagram showing an example of a pulse waveform according to an embodiment. [Figure 4] It is a diagram showing an example of a stress waveform distribution according to an embodiment. [Figure 5] It is a block diagram showing an example of the electrical configuration of a control device according to an embodiment. [Figure 6] It is a block diagram showing an example of the functional configuration of a control device according to an embodiment. [Figure 7]This figure shows an example of a junction defect distribution according to the embodiment. [Figure 8] This figure shows an example of a binarized junction defect distribution according to the embodiment. [Figure 9] This figure illustrates the bonding defect distribution estimation process by the estimation unit according to the embodiment. [Figure 10] This flowchart shows an example of the processing flow by the bonding defect distribution estimation program according to the embodiment. [Figure 11] This is a cross-sectional view showing an example of the process for creating a chip structure according to the embodiment. [Figure 12] This is a cross-sectional view showing an example of the manufacturing process for a chip structure according to the embodiment, and is a continuation of the manufacturing process shown in Figure 11. [Figure 13] This figure shows an example of a set of training data according to the embodiment. [Figure 14] This is a conceptual diagram showing an example of a neural network according to the embodiment. [Figure 15] This block diagram shows another example of the functional configuration of the control device according to the embodiment. [Figure 16] This flowchart shows an example of the processing flow by the junction defect distribution learning program according to the embodiment. [Figure 17] This figure shows an example of how the stress waveform changes when a junction defect occurs at the end of an element. [Figure 18] This figure shows an example of how the temperature waveform changes when a junction defect occurs at the edge of the element. [Figure 19] This figure shows an example of how the stress waveform changes when a junction defect occurs in the center of the element. [Figure 20] This figure shows an example of how the temperature waveform changes when a junction defect occurs in the center of the element. [Figure 21] This is a cross-sectional view showing the structure of the power module. [Figure 22] This figure illustrates the effect of thermal resistance on the junction defect distribution of a power module. [Figure 23] This is a cross-sectional view showing the structure of a power module to which strain gauges have been applied. [Figure 24] This is an exploded view showing the structure of the power module. [Figure 25] This diagram illustrates the range of the sensor's center of gravity. [Figure 26] This figure shows an example of a junction defect distribution. [Figure 27] This figure shows the stress waveform distribution in joint defect distributions 1 and 2. [Figure 28] This figure shows the in-plane distribution of stress waveform changes with respect to the joint defect distribution. [Figure 29] This diagram explains how to obtain the input data. [Figure 30] This is a conceptual diagram showing an example of a neural network according to the second embodiment. [Figure 31] This diagram illustrates the defect location, which is the output of the neural network. [Figure 32] This is a conceptual diagram showing an example of a neural network according to the second embodiment. [Figure 33] This figure shows an example of a junction defect distribution. [Figure 34] This diagram shows the top 10 sensor configurations based on accuracy. [Figure 35] This diagram shows the sensor configurations for the bottom 10 in terms of accuracy. [Figure 36] This graph shows the accuracy rate of sensor placement in the data ranking for the accuracy rate of defect count, and also shows the accuracy rate for defect location. [Figure 37] This graph shows the sensor centroid radius r, sensor centroid angle θ, distance L between sensors, and angle Φ between sensors for each ranking in the data ranking. [Figure 38] This graph shows the accuracy rate for the number of defects and the accuracy rate for the location of defects in a conventional symmetrical arrangement. [Figure 39] This diagram shows the top 10 sensor configurations based on accuracy. [Figure 40] This diagram shows the sensor configurations for the bottom 10 in terms of accuracy. [Figure 41]This graph shows the accuracy rate of sensor placement in the data ranking for the accuracy rate of defect count, and also shows the accuracy rate for defect location. [Figure 42] This graph shows the sensor centroid radius r, sensor centroid angle θ, and sensor area S for each ranking in the data ranking. [Figure 43] This graph shows the accuracy rate for the number of defects and the accuracy rate for the location of defects in a conventional symmetrical arrangement. [Modes for carrying out the invention]

[0025] Hereinafter, an example of an embodiment for carrying out the technology of this disclosure will be described in detail with reference to the drawings. Components and processes that perform the same operation, action, or function are given the same reference numerals throughout the drawings, and redundant explanations may be omitted as appropriate. Each drawing is only a schematic representation to the extent that the technology of this disclosure can be fully understood. Therefore, the technology of this disclosure is not limited to the illustrated examples. Furthermore, in this embodiment, explanations of configurations not directly related to the technology of this disclosure or well-known configurations may be omitted.

[0026] The bonding defect distribution estimation device according to this embodiment acquires the stress waveform distribution shown by the waveform signals output from each of the multiple stress sensors of a power module in which a chip structure having multiple stress sensors and power elements as an integrated unit is joined to a substrate by a bonding portion. Based on the acquired stress waveform distribution, it estimates the bonding defect distribution showing the defect distribution of the bonding portion in contact with the chip structure. This allows the bonding defect distribution in the power module to be evaluated while it is mounted on a power control unit (PCU), DC-DC converter, etc., and the severity of the deterioration of the bonding portion can be estimated, making it possible to determine the need for component replacement, etc. The bonding defect distribution estimation is performed, for example, during inspection, startup, etc.

[0027] [First Embodiment] Figure 1 shows an example of the configuration of the bonding defect distribution estimation device 100 according to this embodiment.

[0028] As shown in Figure 1, the junction defect distribution estimation device 100 according to this embodiment includes a control device 10, a chip structure 20 (power module 40), a stress sensor power supply 30, a pulse generation circuit 31, a gate drive circuit 32, a power element power supply 33, an A / D (analog / digital) converter 34, and a data processing unit 35. The chip structure 20 integrally includes a plurality of stress sensors 21 and power elements 22. As an example, the chip structure 20 is provided on the power module 40 shown in Figure 2.

[0029] Figure 2 is a cross-sectional view showing an example of a power module 40 according to this embodiment.

[0030] As shown in Figure 2, the power module 40 according to this embodiment has a substrate 42 provided on a cooler 43. The substrate 42 is a mounting substrate and has a structure in which copper foil (Cu) is stacked vertically with a silicon nitride film (SiN) in between. The chip structure 20 is mounted on the substrate 42 as a bare chip via solder 41. The heat generated by the power element 22 is removed by the cooler 43, thereby controlling the element temperature. The solder 41 material is, for example, a solder material containing Sn (tin), but it may also be a sintered material such as Ag (silver) or Cu (copper), or a brazing material such as AuSi (gold-silicon alloy) or AuSn (gold-tin alloy). Solder 41 is an example of a joint. The chip structure 20 has a plurality of stress sensors 21 integrated with the power element 22, and in the example in Figure 2, nine stress sensors 21 are arranged on the chip structure 20. The circled numbers 1 to 9 on the chip structure 20 indicate the placement positions of the stress sensors 21, which are arranged diagonally in the example shown in Figure 2. The stress sensors 21 can be made of materials such as a thin metal film or a polysilicon (high-purity polycrystalline silicon) film.

[0031] The stress sensor power supply 30 supplies a constant current (power) to each of the multiple stress sensors 21. Meanwhile, the pulse generation circuit 31 generates a pulse waveform, for example, as shown in Figure 3.

[0032] Figure 3 shows an example of a pulse waveform according to this embodiment. The pulse waveform shown in Figure 3 is a predetermined rectangular wave waveform. However, the pulse waveform is not limited to a rectangular wave shape; any waveform of a certain shape is acceptable. In the example in Figure 3, the energizing period is, for example, 5 seconds or more and 10 seconds or less, and the amount of heat generated by the energizing is, for example, about 100W.

[0033] The gate drive circuit 32 applies the pulse waveform generated by the pulse generation circuit 31 to the gate of the power element 22 while controlling the on and off timing of the pulse waveform. The power element power supply 33 supplies power to the power element 22. In other words, the power element 22 is switched according to the on and off timing of the gate drive circuit 32, and a rectangular wave-shaped pulse waveform, as shown in Figure 3 as an example, is applied to the power element 22.

[0034] Each of the multiple stress sensors 21 outputs a waveform signal (analog signal) indicating resistance change to the A / D converter 34. The A / D converter 34 converts the waveform signals (analog signals) from each of the multiple stress sensors 21 into digital signals and outputs the converted digital signals to the data processing unit 35. The data processing unit 35 generates a stress waveform distribution from the digital signals converted by the A / D converter 34. The data processing unit 35 is an example of a generation unit. In other words, by applying a pulse waveform to the power element 22, the power element 22 is heated, and the stress waveform distribution at that time is obtained from the multiple stress sensors 21. The stress waveform distribution is shown by the waveform signals output from each of the multiple stress sensors 21 when the power element 22 is energized by applying a pulse waveform.

[0035] Figure 4 shows an example of the stress waveform distribution according to this embodiment. For each waveform signal graph, the vertical axis represents stress and the horizontal axis represents time. The stress waveform distribution shown in Figure 4 shows the distribution of waveform signals obtained from each of the nine stress sensors 21, corresponding to the placement positions 1 to 9 of the chip structure 20 shown in Figure 2 above.

[0036] As described above, the stress waveform distribution generated by the data processing unit 35 is input to the control device 10. The control device 10 estimates a joint defect distribution, which indicates the defect distribution of the solder 41 in contact with the chip structure 20, according to the input stress waveform distribution.

[0037] Figure 5 is a block diagram showing an example of the electrical configuration of the control device 10 according to this embodiment. The control device 10 may be, for example, a general-purpose computer device such as a personal computer (PC), or an in-vehicle computer device.

[0038] As shown in Figure 5, the control device 10 according to this embodiment includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, an input / output interface (I / O) 14, a storage unit 15, a display unit 16, an operation unit 17, and a communication unit 18. Note that the CPU 11 may be a GPU (Graphics Processing Unit), or a combination of a CPU and a GPU.

[0039] The CPU 11, ROM 12, RAM 13, and I / O 14 are connected to each other via a bus. The I / O 14 is connected to various functional units, including a storage unit 15, a display unit 16, an operation unit 17, and a communication unit 18. These functional units are capable of communicating with the CPU 11 via the I / O 14.

[0040] The control unit is comprised of a CPU 11, ROM 12, RAM 13, and I / O 14. The control unit may be configured as a sub-control unit that controls the operation of a part of the control device 10, or as part of the main control unit that controls the operation of the entire control device 10. Some or all of the blocks of the control unit may use integrated circuits such as LSIs (Large Scale Integration) or ICs (Integrated Circuit) chipsets. Individual circuits may be used for each of the above blocks, or circuits that integrate some or all of them may be used. The above blocks may be provided as a single unit, or some of the blocks may be provided separately. Furthermore, parts of each of the above blocks may be provided separately. For the integration of the control unit, dedicated circuits or general-purpose processors may be used, not just LSIs.

[0041] For example, the storage unit 15 can be an HDD (Hard Disk Drive), an SSD (Solid State Drive), or flash memory. The storage unit 15 stores the junction defect distribution estimation program 15A according to this embodiment. This junction defect distribution estimation program 15A may also be stored in the ROM 12.

[0042] The junction defect distribution estimation program 15A may, for example, be pre-installed on the control device 10. The junction defect distribution estimation program 15A may also be implemented by storing it on a non-volatile storage medium or distributing it via a network and installing it on the control device 10 as appropriate. Examples of non-volatile storage mediums include CD-ROMs (Compact Disc Read Only Memory), magneto-optical disks, HDDs, DVD-ROMs (Digital Versatile Disc Read Only Memory), flash memory, and memory cards.

[0043] The display unit 16 may be, for example, a liquid crystal display (LCD), an organic EL (Electro-Luminescence) display, or the like. The display unit 16 may also have an integrated touch panel. The operation unit 17 is provided with an interface for operation input. The display unit 16 and the operation unit 17 receive various instructions from the user of the control device 10. The display unit 16 displays various information such as the results of processing performed in response to instructions received from the user, and notifications regarding processing.

[0044] The communication unit 18 is connected to a network such as the Internet, LAN (Local Area Network), or WAN (Wide Area Network), and is capable of communicating with external devices via the network.

[0045] The CPU 11 of the control device 10 according to this embodiment functions as the various parts shown in Figure 6 by writing the junction defect distribution estimation program 15A stored in the memory unit 15 to the RAM 13 and executing it.

[0046] Figure 6 is a block diagram showing an example of the functional configuration of the control device 10 according to this embodiment.

[0047] As shown in Figure 6, the CPU 11 of the control device 10 according to this embodiment functions as an acquisition unit 11A and an estimation unit 11B.

[0048] The memory unit 15 stores stress waveform distributions acquired from the data processing unit 35, and a trained model for estimating joint defect distributions according to the stress waveform distributions. The trained model is generated by machine learning on a set of training data (map data) obtained by associating each of several pre-acquired stress waveform distributions with each of several pre-acquired joint defect distributions. For example, a neural network model is applied to the trained model, and the trained model is generated by supervised machine learning. Note that the trained model is not limited to a model that applies a nonlinear regression method such as a neural network, but may also be a model that applies a linear regression method such as multiple regression analysis.

[0049] Figure 7 shows an example of a bonding defect distribution according to this embodiment.

[0050] The bonding defect distribution shown in Figure 7 is an image obtained when a predetermined stress is applied to the power element 22 of the power module 40 shown in Figure 2 above, causing bonding defects in the solder 41. This image is obtained by non-destructive testing of the power module 40 in which bonding defects have occurred. Non-destructive testing methods such as CT (Computed Tomography) and SAT (Scanning Acoustic Tomography) are applied. The bonding defect distribution shown in Figure 7 is an image obtained by SAT testing (hereinafter referred to as the SAT image). In this SAT image, the white areas indicate ultrasonic reflection, and it can be confirmed that bonding defects have occurred in these areas. The bonding defect distribution may be analyzed as is without converting the spatial resolution of the SAT image, the gradation of the bonding state (image density), etc. However, in order to reduce the computational load of the analysis, the SAT image may be binarized as shown in Figure 8, and the defect distribution may be obtained from the binarized SAT image.

[0051] Figure 8 shows an example of a binarized junction defect distribution according to this embodiment.

[0052] As shown in Figure 8, the SAT image is binarized, and the defect distribution is obtained from the binarized SAT image. This reduces the computational load required for image analysis. Thus, the junction defect distribution can also be represented by a black and white pattern obtained from the binarized SAT image. In the example in Figure 8, the white areas represent defects.

[0053] Returning to Figure 6, the acquisition unit 11A acquires the stress waveform distribution from the storage unit 15.

[0054] The estimation unit 11B estimates the joint defect distribution according to the stress waveform distribution acquired by the acquisition unit 11A. Specifically, as an example, as shown in Figure 9, the stress waveform distribution acquired by the acquisition unit 11A is input to a trained model, and the joint defect distribution is output from the trained model, thereby estimating the joint defect distribution according to the stress waveform distribution.

[0055] Figure 9 is a diagram illustrating the bonding defect distribution estimation process by the estimation unit 11B according to this embodiment.

[0056] As shown in Figure 9, the trained model takes a stress waveform distribution as input and outputs a joint defect distribution corresponding to that stress waveform distribution. In other words, the trained model uses the stress waveform distribution as the explanatory variable and the joint defect distribution as the objective variable.

[0057] Next, the operation of the control device 10 according to this embodiment will be described with reference to Figure 10.

[0058] Figure 10 is a flowchart showing an example of the processing flow by the bonding defect distribution estimation program 15A according to this embodiment.

[0059] First, when the control device 10 receives an instruction to start the joint defect distribution estimation process, the CPU 11 starts the joint defect distribution estimation program 15A and executes the following steps.

[0060] In step S101 of Figure 10, the CPU 11 acquires from the memory unit 15 a stress waveform distribution, for example, which is represented by multiple waveform signals output from multiple stress sensors 2 as shown in Figure 4 above.

[0061] In step S102, the CPU 11 inputs the stress waveform distribution obtained in step S101 to the trained model, as an example as shown in Figure 9 above, and outputs the joint defect distribution from the trained model. This estimates the joint defect distribution corresponding to the stress waveform distribution, and the series of processes by the joint defect distribution estimation program 15A is completed. The output format of the joint defect distribution may be the image shown in Figure 8 above, or the binarized image shown in Figure 9.

[0062] Next, the process for creating the chip structure 20 according to this embodiment will be described in detail with reference to Figures 11 and 12.

[0063] Figures 11 and 12 are cross-sectional views showing an example of the manufacturing process for the chip structure 20 according to this embodiment. Figure 12 is a continuation of the manufacturing process shown in Figure 11.

[0064] In Figure 11(A), a P-type silicon substrate 51 is prepared as the substrate for the chip structure 20.

[0065] In (B), a first insulating film 52 such as SiO2 is formed on the P-type silicon substrate 51.

[0066] In (C), the first insulating film 52 is etched, and the first insulating film 52 is removed only in the region where ion implantation is performed.

[0067] In (D), ion implantation is performed in the region from which the first insulating film 52 has been removed, forming an N-type diffusion layer 53 which will be the source region and an N-type diffusion layer 54 which will be the drain region on the P-type silicon substrate 51.

[0068] In (E), a gate film 55 is formed on the first insulating film 52. The gate film 55 is formed in the region between the N-type diffusion layer 53 and the N-type diffusion layer 54. For example, polysilicon can be used for the gate film 55.

[0069] In (F), a second insulating film 56 made of SiO2 or the like is formed on the first insulating film 52 on which the gate film 55 is formed.

[0070] Moving on to Figure 12, in Figure 12(G), a sensor film 57 is formed on the second insulating film 56. The sensor film 57 is formed in a region adjacent to the region where the N-type diffusion layers 53 and 54 are formed. For example, a polysilicon or a metal thin film can be used for the sensor film 57.

[0071] In (H), a third insulating film 58 such as SiO2 is formed on the second insulating film 56 on which the sensor film 57 is formed.

[0072] In (J), etching is performed on the second insulating film 56 and the third insulating film 58, and only the regions corresponding to a part of the N-type diffusion layer 53 and a part of the N-type diffusion layer 54 are etched. The third insulating film 58 is removed, forming holes that reach a portion of the N-type diffusion layer 53 and holes that reach a portion of the N-type diffusion layer 54. In addition, the third insulating film 58 is removed only in the region corresponding to a portion of the sensor film 57, forming two holes that reach a portion of the sensor film 57.

[0073] In (K), a conductor is inserted into a hole reaching a portion of the N-type diffusion layer 53 to form a source electrode 59, and a conductor is inserted into a hole reaching a portion of the N-type diffusion layer 54 to form a drain electrode 60. The gate film 55, N-type diffusion layer 53, source electrode 59, N-type diffusion layer 54, and drain electrode 60 form a power element 22, and the region where the power element 22 is formed becomes the power element region. In addition, conductors are inserted into two holes reaching a portion of the sensor film 57 to form two electrodes 61. The sensor film 57 and the two electrodes 61 form a stress sensor 21, and the region where the stress sensor 21 is formed becomes the stress sensor region. In this way, a chip structure 20 including the power element region and the stress sensor region is created.

[0074] Next, the joint defect distribution learning process performed by the control device 10 will be described in detail. In this embodiment, the joint defect distribution estimation process and the joint defect distribution learning process are shown to be performed using the same device, but the joint defect distribution estimation process and the joint defect distribution learning process may be performed using separate devices.

[0075] For example, during the product development stage, (1) a test is performed on the power module 40 shown in Figure 2 above by applying a predetermined stress to generate bonding defects. This test is performed on multiple power modules 40. (2) After the test, the multiple power modules 40 are subjected to the non-destructive testing described above (e.g., CT inspection, SAT inspection, etc.) to obtain the bonding defect distribution from the multiple power modules 40. (3) After the test, thermal stress using the pulse waveform shown in Figure 3 above is applied to the multiple power modules 40, and the stress waveform distribution is obtained from the multiple power modules 40. The multiple stress waveform distributions obtained and the multiple bonding defect distributions are then associated to form a set of training data.

[0076] Figure 13 shows an example of a training data set according to this embodiment.

[0077] The training data set shown in Figure 13 is a dataset that associates multiple stress waveform distributions with multiple joint defect distributions. Using this training data set, for example, a trained model can be generated by machine learning a neural network model. Alternatively, the training data set used for machine learning may be acquired using CAE (Computer-Aided Engineering) techniques.

[0078] Figure 14 is a conceptual diagram showing an example of a neural network according to this embodiment.

[0079] The neural network shown in Figure 14 has an input layer x i , hidden layer (also called intermediate layer) y j It also has an output layer z.

[0080] The neural network shown in FIG. 14 has the simplest three-layer structure to simplify the explanation, but the hidden layer y j may have a multi-layer structure with two or more layers. Also, the node (also called a neuron) of the output layer z is set to one, but it may be composed of a plurality of nodes.

[0081] Here, when an input (stress waveform distribution) is given to the neural network, the calculation of the output (joint defect distribution) is performed in order from the input using the following equation (1). Note that f(·) is called an activation function, and for example, a sigmoid function or the like is used. Also, x i is the input of the input layer x i of, y j is the output of the hidden layer y j of, z is the output of the output layer z, w ij , u j is a weight coefficient. By changing these weight coefficients w ij , u j , different outputs can be obtained for the same input. That is, the learning of the model is performed by updating the weight coefficients w ij , u j so as to obtain the target output.

[0082] JPEG0007855981000001.jpg3138 ···(1)

[0083] Next, referring to FIG. 15, the functional configuration of the control device 10 that performs the joint defect distribution learning process will be described. In this case, the CPU 11 of the control device 10 writes the joint defect distribution learning program (not shown) stored in the storage unit 15 into the RAM 13 and executes it, thereby functioning as each part shown in FIG. 15.

[0084] FIG. 15 is a block diagram showing another example of the functional configuration of the control device 10 according to the present embodiment.

[0085] As shown in Figure 15, the CPU 11 of the control device 10 according to this embodiment functions as an acquisition unit 11C and a learning unit 11D.

[0086] The memory unit 15 stores the training data set and the training model. The training data set is shown as an example in Figure 13 above. The training model is shown as an example in Figure 14 above, which is a neural network model.

[0087] The acquisition unit 11C acquires a set of learning data from the storage unit 15, obtained by associating each of the previously acquired stress waveform distributions with each of the previously acquired joint defect distributions.

[0088] The learning unit 11D generates a trained model by machine learning the learning model using the training data set acquired by the acquisition unit 11C. The generated trained model is stored in the storage unit 15. The trained model takes a stress waveform distribution as input and outputs a joint defect distribution.

[0089] Figure 16 is a flowchart showing an example of the processing flow by the junction defect distribution learning program according to this embodiment.

[0090] First, when the control device 10 receives an instruction to start the joint defect distribution learning process, the CPU 11 starts the joint defect distribution learning program and executes the following steps.

[0091] In step S111 of Figure 16, the CPU 11 acquires, for example, the training data set shown in Figure 13 above from the memory unit 15.

[0092] In step S112, the CPU 11 uses the training data set acquired in step S111 to machine-learn a neural network model, as shown in Figure 14 above, as an example.

[0093] In step S113, the CPU 11 determines whether or not the predetermined termination conditions are met. If it determines that the predetermined termination conditions are not met (negative determination), the process returns to step S112 and is repeated. If it determines that the predetermined termination conditions are met (positive determination), the process proceeds to step S114. The predetermined termination conditions are, for example, whether or not a predetermined number of machine learning iterations have been performed.

[0094] In step S114, the CPU 11 stores the trained model generated by machine learning in step S112 in the memory unit 15, and terminates the series of processes by this joint defect distribution learning program. The trained model is a model in which the stress waveform distribution is the explanatory variable and the joint defect distribution is the objective variable.

[0095] Next, with reference to Figures 17 to 20, we will explain an example comparing the stress waveform change and the temperature waveform change when a joint defect occurs. Note that the solder joint surface BF shown in Figures 17 to 20 is symmetrical with respect to the x and y axes, and the figures show the joint defect distribution and stress waveform distribution for a 1 / 4 region R1 of the joint surface BF.

[0096] Figure 17 shows an example of the stress waveform change when a junction defect occurs at the edge of the element. Figure 18 shows an example of the temperature waveform change when a junction defect occurs at the edge of the element. Figure 19 shows an example of the stress waveform change when a junction defect occurs in the center of the element. Figure 20 shows an example of the temperature waveform change when a junction defect occurs in the center of the element. Here, the size of the junction surface in region R1 is assumed to be 7x7, and the defect area ratio, which indicates the percentage of the area where a junction defect occurs, is shown as 20%.

[0097] Stress changes associated with an increase in defects appear in multiple modes, including amplitude increase, amplitude decrease, and waveform inversion. On the other hand, temperature changes associated with an increase in defects appear only as an amplitude increase, and their detection range is smaller than that of stress changes. Therefore, the superiority of the stress sensor over the temperature sensor can be confirmed from the waveform data shown in Figures 17 to 20.

[0098] For example, as shown in Figures 17 and 18, if there is a bonding defect at the end of the element (white part), a stress change is observed at position A1 in Figure 17, but no temperature change is observed at position A1 in Figure 18. On the other hand, as shown in Figures 19 and 20, if there is a bonding defect in the center of the element (white part), a stress change is observed at position A1 in Figure 19, and a temperature change is also observed at position A1 in Figure 20. In other words, with a stress sensor, a stress change can be observed regardless of where the bonding defect occurs on the bonding surface. For this reason, it can be said that using a stress sensor provides higher accuracy in estimating bonding defects compared to using a temperature sensor.

[0099] Here, waveform data from a stress sensor has the following characteristics: In the case of temperature sensors, changes due to bonding defects appear only as an increase in amplitude, but in the case of stress sensors, changes due to bonding defects appear in multiple modes, including amplitude increase, amplitude decrease, and waveform inversion. • For the same joint defect, the waveform change detected by the stress sensor has a wider detection range than the waveform change detected by the temperature sensor.

[0100] Therefore, by acquiring waveform data from stress sensors placed within the chip structure and comparing and analyzing the waveform data between multiple sensors, the bonding state can be accurately estimated even at locations far from the sensors. Here, we have shown numerous stress and temperature waveforms within the chip structure from the perspective of comparing stress and temperature sensors; however, the number of sensors per chip is practically limited. For this reason, it is desirable to place multiple sensors in locations where changes are likely to occur.

[0101] Thus, according to this embodiment, while the temperature sensor shows only an increase in amplitude due to a bonding defect, the stress sensor shows multiple modes of change due to a bonding defect, including an increase in amplitude, a decrease in amplitude, and waveform inversion. Therefore, by using a stress sensor, the bonding defect distribution can be estimated with high accuracy. Furthermore, while temperature sensors only detect temperature changes directly beneath the sensor, stress sensors can detect stress changes not only directly beneath the sensor but also in the surrounding area. Therefore, they can detect a wider range of temperature changes. Therefore, by acquiring stress waveforms from multiple stress sensors placed on the chip structure and comparing and analyzing the stress waveform distributions between the multiple sensors, the bonding state can be accurately estimated even at locations far from the sensors. Furthermore, since stress sensors can detect a wider range of bonding conditions compared to temperature sensors, the severity of bonding defects can be accurately assessed.

[0102] [Second Embodiment] Next, a bonding defect distribution estimation device according to the second embodiment will be described. Since the bonding defect distribution estimation device according to the second embodiment has the same configuration as the first embodiment, the same reference numerals are used and their description is omitted.

[0103] In the second embodiment, the arrangement of the multiple stress sensors differs from that of the first embodiment. Specifically, in the first embodiment described above, nine stress sensors 21 are arranged on the chip structure 20 in a point-symmetrical manner with respect to the center of the chip structure 20.

[0104] Since a typical stress sensor 21 can only measure uniaxial stress, the symmetrical arrangement shown in Figure 2 above is not necessarily the optimal arrangement. Let's consider this using the waveform change of stress in the X-axis direction as an example. Here, in a 1 / 4 structure power module 40 shown in Figure 24, multiple stress sensors 21 are arranged on a chip structure 20. The edges defining the rectangular surface of the chip structure 20 of the power module 40 are defined as edges extending in the X-axis direction and edges extending in the Y-axis direction, and the stress sensor 21 is assumed to be a stress sensor sensitive in the X-axis direction. Furthermore, with the center of the chip structure 20 as the origin (0,0) and one vertex as (a,a), the multiple stress sensors 21 are arranged such that the centroids of the multiple stress sensors 21, which are placed in a 1 / 4 structural range enclosed by the four points (0,0), (a,0), (0,a), and (a,a), are included in the range enclosed by (0,0), (a / 2,0), (0,a), and (a / 2,a) (Figure 25). At this time, the stress waveform change was determined using thermal stress CAE for multiple joint defect distributions as shown in Figure 26. In Figure 26, the numbers in parentheses indicate the joint defect rate. In addition, the white-shaded areas in the joint defect distribution indicate joint defects, and the gray areas indicate joints that are sound.

[0105] Figure 27 shows a comparison of stress waveforms at each location in defect distribution 1 and defect distribution 2. In Figure 27, the dark-colored stress waveforms represent the stress waveforms in defect distribution 1, and the light-colored stress waveforms represent the stress waveforms in defect distribution 2. In Figure 27, areas where the amplitude change is greater than 5% are marked with a thick border. Of these, the solid thick borders represent areas where the amplitude decreased, and the dashed thick borders represent areas where the waveform reversed. An amplitude change of 5% or more was observed in 39 out of 49 locations. Thus, it can be seen that the stress waveform change is not symmetrical with respect to the origin or the X-axis and Y-axis.

[0106] Figure 28 shows the waveform changes for each joint defect distribution. The white areas in the joint defect distribution indicate joint defects, and the gray areas indicate healthy joints. The various circles indicate areas with amplitude reduction of 5% or more, areas with amplitude amplification of 5% or more, areas where the stress waveform was inverted, areas where the amplitude disappeared, and areas with amplitude change of less than 5%. The waveform changes are not symmetrical with respect to the X or Y axes. Therefore, this result supports the conclusion that a symmetrical arrangement of stress sensors is not optimal for predicting defect distributions.

[0107] Next, we will explain the results of extracting the optimal placement for stress detection. For 198 types of joint defect distributions, the stress amplitude distribution when power cycle test stress was applied was calculated using thermal stress CAE. Using this data, and the stress amplitude in a assumed sensor configuration as input, machine learning was performed to obtain two trained models (Figure 29). In this process, the output data of one trained model was the defect location (upper left, lower left, upper right, lower right, no defect) in a region divided into four parts of the solder joint (Figures 30 and 31). The output data of the other trained model was the number of defects (the number of defective locations) (Figure 32).

[0108] Figure 29 shows an example of obtaining stress at each location of a stress sensor from a stress distribution corresponding to the defect distribution and using it as input data. In other words, only the stress corresponding to the blacked-out areas indicating the location of the stress sensor is extracted from the stress distribution, and input data representing the stress corresponding to each location of the stress sensor is generated.

[0109] Figure 30 shows an example of a trained model that is a neural network model that takes the stress amplitude at each position of the stress sensor as input and outputs the probability of having a joint defect in a region divided into four parts of the solder joint (see Figure 31) (the probability of having a joint defect in each of the upper left, lower left, upper right, and lower right sections, as well as the probability of no defects).

[0110] Figure 32 shows an example of a trained model, which is a neural network model that takes the stress amplitude at each position of the stress sensor as input and outputs the number of defects (0 to 16) in the 64 divisions of the solder joint.

[0111] Figure 33 shows a portion of the 198 types of joint defect distributions. The defect arrangement in the joint defect distribution is assumed to satisfy the following four conditions.

[0112] The first condition is that the shape must be symmetrical with respect to the X and Y axes, and that there must be shapes attached to the edges. The second condition is that defects can be placed in boundary regions, but not in regions that span two regions. The third condition is that the maximum number of defects is 16. The fourth condition is that there must be a single defect, and no defects that are recessed.

[0113] Figures 34 to 42 show the estimation results of the bonding defect distribution estimation device of this embodiment for 1180 different sensor arrangements when there are two stress sensors. In this 1 / 4 structure, a high accuracy rate was achieved when the sensor centroid was placed within the area enclosed by the four points (0,0), (a / 2,0), (0,a), and (a / 2,a).

[0114] In particular, high accuracy rates (top 2%) were obtained when the sensor centroid radius r was between 1.4 and 4.9 (normalized by the side length a of 1 / 4 of the chip structure 20, this is between 0.20a and 0.70a), the sensor centroid angle θ was between 22° and 90°, the distance L between sensors was between 1 and 6.4 (0.14a and 0.91a), and the angle Φ between sensors was between 22° and 90°.

[0115] Figure 34 shows the top 10 sensor configurations in terms of accuracy. In each sensor configuration, the "1" indicates the sensor location. Figure 35 shows the sensor configurations with the lowest accuracy rates.

[0116] The upper part of Figure 36 is a graph showing the accuracy rate of sensor placements for each rank (data ranking) arranged in descending order of accuracy rate regarding the number of defects. The lower part of Figure 36 is a graph showing the accuracy rate regarding defect location for sensor placements at each rank in the above data ranking.

[0117] The upper left of Figure 37 shows a graph illustrating the sensor centroid radius r for each ranking in the data ranking. Here, the sensor centroid radius r is the distance between the sensor centroid and the origin. The upper right side of Figure 37 shows a graph illustrating the sensor centroid angle θ for each ranking in the data ranking. Here, the sensor centroid angle θ is the angle between the line connecting the sensor centroid and the origin and the X-axis direction. The lower left of Figure 37 shows a graph illustrating the inter-sensor distance L for each rank in the data ranking. Here, the inter-sensor distance L is the distance between two sensor positions. The lower right side of Figure 37 shows a graph illustrating the inter-sensor angle Φ for each rank in the data ranking. Here, the inter-sensor angle Φ is the angle between the line connecting the sensor positions and the X-axis direction.

[0118] On the other hand, Figure 38 shows examples of the accuracy rate for the number of defects and the accuracy rate for the location of defects in a conventional symmetrical arrangement.

[0119] The upper part of Figure 38 is a graph showing the accuracy rate of sensor placements for each rank (ranking) in descending order of accuracy rate regarding the number of defects. The lower part of Figure 38 is a graph showing the accuracy rate regarding defect location for each rank of sensor placement in the above ranking.

[0120] In the conventional example where stress sensors are placed at any two points on the diagonal, the estimation of defect locations is comparable to the estimation results in Figures 34 to 38 above, but the accuracy of the estimation of the number of defects is lower than in this embodiment. Therefore, in the configuration that achieved a high accuracy rate (top 2%), it surpassed the top score (0.336) of the conventional example.

[0121] Based on the above, when there are two stress sensors, and the sensor centroids are positioned within the area enclosed by the four points (0,0), (a / 2,0), (0,a), and (a / 2,a), it is preferable that the sensor centroid radius r is between 0.20a and 0.70a, the sensor centroid angle θ is between 22° and 90°, the distance L between sensors is between 1 and 6.4 (0.14a and 0.91a), and the angle Φ between sensors is between 22° and 90°.

[0122] Next, Figures 39 to 42 show the estimation results of the bonding defect distribution estimation device of this embodiment for 560 different sensor arrangements when there are three stress sensors. In this 1 / 4 structure, a high accuracy rate was obtained when the sensor centroid was placed in the area enclosed by the four points (0,0), (a / 2,0), (0,a), and (a / 2,a).

[0123] High accuracy rates (top 5%) were achieved when the sensor centroid radius r was between 1.9 and 4.3 (normalized by side length a, between 0.27a and 0.61a), the sensor centroid angle θ was between 27° and 81°, and the sensor area S was between 0 and 8 (0 to 0.16a). 2 (The following)

[0124] Figure 39 shows the top 10 sensor configurations in terms of accuracy. Figure 40 shows the sensor configurations with the lowest accuracy rates for the bottom 10 devices.

[0125] The upper part of Figure 41 is a graph showing the accuracy rate of sensor placements for each rank (data ranking) arranged in descending order of accuracy rate regarding the number of defects. The lower part of Figure 41 shows a graph illustrating the accuracy rate for defect location for each sensor configuration ranked in the above data ranking.

[0126] The upper left of Figure 42 shows a graph illustrating the sensor centroid radius r for each ranking in the data ranking. The upper right side of Figure 42 shows a graph illustrating the sensor centroid angle θ for each ranking in the data ranking. The lower right side of Figure 42 shows a graph illustrating the sensor area S for each ranking in the data ranking. Here, the sensor area S is the area enclosed by the straight line connecting the sensor positions.

[0127] On the other hand, Figure 43 shows examples of the accuracy rates for the number of defects and the location of defects in a conventional symmetrical arrangement. In this conventional example, where stress sensors are placed at three points on any three diagonals, the estimation of defect locations is comparable to the estimation results in Figures 39 to 42 above, but the estimation of the number of defects has a lower accuracy rate than in this embodiment. Consequently, the configuration that achieved a high accuracy rate (top 5%) surpassed the top score (0.407) of this conventional example.

[0128] Based on the above, when there are three stress sensors, and the sensor centroid is positioned within the area enclosed by the four points (0,0), (a / 2,0), (0,a), and (a / 2,a), the sensor centroid radius r is between 0.27a and 0.61a, the sensor centroid angle θ is between 27° and 81°, and the sensor area S is between 0 and 0.16a. 2 The following is preferable:

[0129] As explained above, according to the joint defect distribution estimation device of the second embodiment, the waveform change due to a joint defect in uniaxial stress does not have a symmetric response with respect to the solder joint. Therefore, by arranging the sensors to correspond to that response plane, the estimation accuracy of the joint defect distribution can be improved with an appropriate number of sensors. Furthermore, the severity of power module degradation can be determined from the distribution of junction defects, allowing for a more accurate assessment of the need for component replacement.

[0130] In the second embodiment described above, since the deterioration of the solder joints is symmetrical, the example of estimating joint defects for a 1 / 4 structure was used, but the method is not limited to this. Similarly, stress sensors may be placed for the remaining 3 / 4 structure to estimate joint defects. Alternatively, joint defects may be estimated only for the 1 / 4 structure.

[0131] Furthermore, in each of the above embodiments, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0132] Furthermore, the processor operations in each of the above embodiments may not be performed by a single processor, but may also be performed by multiple processors located in physically separate locations working together. Also, the order of the processor operations is not limited to the order described in each of the above embodiments, but may be changed as appropriate.

[0133] The above describes an example of a bonding defect distribution estimation device according to an embodiment. The embodiment may also be in the form of a program that causes a computer to execute the functions of each part of the bonding defect distribution estimation device. The embodiment may also be in the form of a non-temporary storage medium that is readable by a computer and stores these programs.

[0134] Furthermore, the configuration of the bonding defect distribution estimation device described in the above embodiment is merely an example, and may be modified as needed without departing from the main purpose.

[0135] Furthermore, the program processing flow described in the above embodiment is just one example, and unnecessary steps may be deleted, new steps added, or the processing order rearranged, as long as it does not deviate from the main purpose.

[0136] Furthermore, although the above embodiment describes a case in which the process according to the embodiment is realized by a software configuration using a computer by executing a program, the embodiment is not limited to this. The embodiment may also be realized by a hardware configuration or a combination of a hardware configuration and a software configuration. [Explanation of Symbols]

[0137] 10 Control device 11 CPU 11A, 11C Acquisition Department 11B Estimation part 11D Learning Department 12 ROM 13 RAM 14 I / O 15 Storage section 15A Program for Estimating Junction Defect Distribution 16 Display 17 Control section 18 Communications Department 20 Chip Structures 21 Stress Sensor 22 Power Components 30. Stress sensor power supply 31. Pulse generation circuit 32 Gate drive circuit 33 Power Element Power Supply 34 A / D converters 35 Data Processing Unit 40 Power Modules 41 Solder (joint) 42 circuit boards 43 Cooler 100 Bonding Defect Distribution Estimation Device

Claims

1. An acquisition unit that acquires a stress waveform distribution indicated by waveform signals output from each of the multiple stress sensors of a power module in which a chip structure having multiple stress sensors and power elements as an integrated unit and a substrate are joined by a joint, An estimation unit estimates a joint defect distribution that shows the defect distribution of the joint in contact with the chip structure, in accordance with the stress waveform distribution obtained by the acquisition unit. Equipped with A device for estimating the distribution of junction defects.

2. The stress waveform distribution is indicated by the waveform signals output from each of the multiple stress sensors when a predetermined pulse waveform is applied to the power element and current is passed through it. The joint defect distribution estimation device according to claim 1.

3. The chip structure includes a power element region which is the region of the power element and a stress sensor region which is the region of the stress sensor. A pulse generation circuit that generates the aforementioned pulse waveform, A gate drive circuit that applies the pulse waveform generated by the pulse generation circuit to the gate of the power element while controlling the on and off timing of the pulse waveform, A power supply for the power element that supplies power to the power element, A stress sensor power supply that supplies power to each of the aforementioned stress sensors, It also has The bonding defect distribution estimation device according to claim 2.

4. An analog-to-digital converter that converts the waveform signals output from each of the aforementioned multiple stress sensors into digital signals, A generation unit that generates the stress waveform distribution from the digital signal converted by the analog / digital converter, It also has The bonding defect distribution estimation device according to claim 3.

5. The system further includes a memory unit that stores a trained model generated by machine learning on a set of training data obtained by associating each of several previously acquired stress waveform distributions with each of several previously acquired joint defect distributions. The estimation unit inputs the stress waveform distribution acquired by the acquisition unit to the trained model and outputs the joint defect distribution from the trained model, thereby estimating the joint defect distribution corresponding to the stress waveform distribution. The bonding defect distribution estimation device according to claim 1.

6. The power element has a rectangular surface defined by an edge extending in the X-axis direction and an edge extending in the Y-axis direction. The stress sensor is a stress sensor that has sensitivity in the X-axis direction, The bonding defect distribution estimation device according to claim 1, wherein, with the center of the power element as the origin (0,0) and one vertex as (a,a), the plurality of stress sensors are arranged such that the centroids of the plurality of stress sensors, which are arranged in a range enclosed by the four points (0,0), (a,0), (0,a), (a,a), are included in the range enclosed by the four points (0,0), (a / 2,0), (0,a), (a / 2,a).

7. The plurality of stress sensors arranged in the area surrounded by the four points (0,0), (a,0), (0,a), and (a,a) are two stress sensors, The distance between the sensor's center of gravity and the origin is between 0.2a and 0.7a. The angle between the line connecting the sensor's center of gravity and the origin, and the X-axis direction, is between 22° and 90°. The distance between sensors is between 0.14a and 0.91a. The bonding defect distribution estimation device according to claim 6, wherein the angle between the line connecting the sensor positions and the X-axis direction is 22° to 90°.

8. The plurality of stress sensors arranged in the area surrounded by the four points (0,0), (a,0), (0,a), and (a,a) are three stress sensors, The distance between the sensor's center of gravity and the origin is between 0.27a and 0.61a. The angle between the line connecting the sensor's center of gravity and the origin, and the X-axis direction, is between 27° and 81°. The area enclosed by the line connecting the sensor positions is between 0 and 0.16a. ２ The bonding defect distribution estimation device according to claim 6, which is as follows:

9. The power module, which has a chip structure integrating multiple stress sensors and power elements, and a substrate joined by a joint, acquires the stress waveform distribution shown by the waveform signals output from each of the multiple stress sensors, Based on the acquired stress waveform distribution, a joint defect distribution showing the defect distribution of the joint in contact with the chip structure is estimated. Method for estimating the distribution of junction defects.

10. The power module, which has a chip structure integrating multiple stress sensors and power elements, and a substrate joined by a joint, acquires the stress waveform distribution shown by the waveform signals output from each of the multiple stress sensors, In accordance with the acquired stress waveform distribution, the bonding defect distribution showing the defect distribution of the bonding portion in contact with the chip structure is estimated. A program for estimating the distribution of junction defects, designed to be run on a computer.

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