Semiconductor structure having one or more support structures

Abstract

To provide a semiconductor structure with one or more support structures.SOLUTION: One or more semiconductor structures and / or methods for forming support structures for semiconductor structures are provided. The structures and methods include the following features. A first porosification layer is formed over a semiconductor substrate. A first epitaxial layer is formed over the first porosification layer. A second porosification layer is formed from a first portion of the first epitaxial layer and a support structure is formed from a second portion of the first epitaxial layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to the field of support structures for semiconductor wafers.

Background Art

[0002] Various types of semiconductor wafers can have various thicknesses. For example, depending on the diameter, some semiconductor wafers can have a thickness of about 700 micrometers for silicon substrates and about 370 micrometers for silicon carbide substrates. With thin wafer technology for insulated gate bipolar transistors (IGBTs) or field-effect transistors (e.g., MOSFETs), thin semiconductor wafers can have a thickness of about 200 micrometers or less for silicon substrates or about 100 micrometers or less for silicon carbide substrates.

Summary of the Invention

Means for Solving the Problems

[0003] This summary is provided to introduce, in simplified form, selected ones of the concepts that are further described in the "Detailed Description of the Invention" below. This summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a method is provided. The method can include forming a first porous layer on a semiconductor substrate. A first epitaxial layer can be formed on the first porous layer. A second porous layer can be formed from a first portion of the first epitaxial layer. A support structure can be formed from a second portion of the first epitaxial layer.

[0005] For the purposes described above and related to achieve the objectives mentioned above, the following description and accompanying drawings illustrate several exemplary embodiments and implementations. These illustrate only some of the various ways in which one or more embodiments may be employed. Other embodiments, advantages and novel features of this disclosure will become apparent from the following detailed description and in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0006] [Figure 1] This is a diagram illustrating an exemplary method for forming one or more support structures for a semiconductor structure. [Figure 2A] This is a diagram of a semiconductor substrate. [Figure 2B] This is a diagram of the first porosification layer formed on a semiconductor substrate. [Figure 2C] This is a diagram of the first epitaxial layer formed on the first porous layer. [Figure 2D] This diagram shows a second porous layer formed from a first portion of the first epitaxial layer and a support structure formed from a second portion of the first epitaxial layer. [Figure 2E] This is a diagram of a device layer formed on top of a support structure. [Figure 2F] This is a diagram of one or more device structures formed on and / or within a device layer. [Figure 2G] This is a diagram of a carrier attached to a semiconductor structure. [Figure 2H] This is a diagram of a semiconductor structure having a support structure. [Figure 2I] These are diagrams showing the semiconductor structure from below and from above. [Figure 3A] This is a diagram of a semiconductor substrate. [Figure 3B] This is a diagram of the first porous layer formed on a semiconductor substrate. [Figure 3C] This is a diagram of the first epitaxial layer formed on the first porous layer. [Figure 3D]This figure shows a second porous layer formed from a first portion of the first epitaxial layer, and a first support structure and a second support structure formed from the second and third portions of the first epitaxial layer. [Figure 3E] This is a diagram of a device layer formed on top of a support structure. [Figure 3F] This is a diagram of one or more device structures formed on and / or within a device layer. [Figure 3G] This is a diagram of a carrier attached to a semiconductor structure. [Figure 3H] This is a diagram of a semiconductor structure having a support structure. [Figure 3I] These are diagrams showing the semiconductor structure from below and from above. [Figure 4A] This is a diagram of a semiconductor substrate. [Figure 4B] This is a diagram of the first porous layer formed on a semiconductor substrate. [Figure 4C] This is a diagram of the first epitaxial layer formed on the first porous layer. [Figure 4D] This figure shows a second porous layer formed from a first portion of the first epitaxial layer, and a first support structure and a second support structure formed from one or more other portions of the first epitaxial layer. [Figure 4E] This is a diagram of a device layer formed on top of a support structure. [Figure 4F] This is a diagram of one or more device structures formed on and / or within a device layer. [Figure 4G] This is a diagram of a carrier attached to a semiconductor structure. [Figure 4H] This is a diagram of a semiconductor structure having a support structure. [Figure 4I] This is a diagram of a semiconductor structure having a support structure and metal filling the cavities between the support structures. [Figure 4J] These are diagrams showing the semiconductor structure from below and from above. [Figure 4K] These are bottom and top views of a semiconductor structure having support structures and metal filling the cavities between the support structures. **DETAILED DESCRIPTION**

[0007] The subject matter claimed herein is described with reference to the accompanying drawings, in which like reference numerals are used throughout the specification to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. It will be apparent, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and device configurations are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0008] Semiconductor wafers, such as thin semiconductor wafers, can be vulnerable to warping and mechanical breakage due to the thinness of such semiconductor wafers. For example, mechanical loading on some areas of a semiconductor wafer (e.g., near the edges) can cause hairline cracks and / or break the semiconductor wafer. This can be particularly problematic for thin semiconductor wafers (e.g., where the semiconductor wafer has a thickness of about 200 micrometers or less for a silicon substrate and about 100 micrometers or less for a silicon carbide substrate).

[0009] To strengthen a semiconductor wafer to reduce the likelihood that the semiconductor wafer will be damaged during fabrication and / or handling, a support structure can be generated for the semiconductor wafer (e.g., attached to or milled into the semiconductor wafer). For example, the support structure can be attached to the back side of the semiconductor wafer. This adds additional complexity to the semiconductor wafer manufacturing process. Further, if the support structure is generated into the back side of the semiconductor wafer using, for example, a mechanical, physical, or chemical removal process (e.g., milling, etching, electrical discharge machining), the substrate of the semiconductor wafer cannot be reused. Thus, the substrate cannot be reused, for example, due to machining of the support material during a milling process. Other issues that can arise with adding a support structure to a semiconductor wafer relate to mismatches between temperature constraints and thermal expansion rates.

[0010] Accordingly, as provided herein, one or more support structures are formed for semiconductor structures, such as thin semiconductor wafers, according to various shapes, sizes, and arrangements, to reinforce the semiconductor structure and reduce the possibility of warping or breakage. In one embodiment, the semiconductor structure includes a substrate. The substrate of the semiconductor structure may include a semiconductor wafer or the semiconductor wafer and / or an epitaxial layer. One or more support structures are formed by a porosity process applied to the substrate (such as the epitaxial layer and / or single crystal layer of the semiconductor structure). Since the support structures are not cut into or attached to the back surface of the semiconductor structure, the semiconductor substrate of the semiconductor structure can be reused. The support structures may be formed according to a process that does not introduce additional temperature constraints and / or generate thermal expansion mismatches.

[0011] This support structure provides additional support / strength to help reduce the possibility of mechanical failure, warping, or other structural problems that may arise from subsequent processing and / or handling of the semiconductor structure. These support structures may be particularly useful for thin semiconductor wafers (e.g., thin semiconductor wafers with a thickness of about 200 micrometers or less for silicon substrates and about 100 micrometers or less for silicon carbide substrates) which are otherwise vulnerable to warping and mechanical failure due to their extremely thinness.

[0012] Various shapes, sizes, arrangements, and / or numerous support structures are provided for semiconductor structures. In one or more embodiments, any number of support structures, such as a single support structure or multiple support structures, can be formed for semiconductor structures. In one or more embodiments, the support structures may have various shapes, such as loop structures (e.g., ring structures), columnar structures, grid structures including multiple structures such as columnar structures, loop structures arranged around one or more structures (e.g., around a single columnar structure or around multiple columnar structures or grid structures), cylindrical shapes, rectangular shapes, and so on.

[0013] According to several embodiments, a method is provided. The method includes forming a first porous layer on a semiconductor substrate; forming a first epitaxial layer on the first porous layer; and forming a second porous layer from a first portion of the first epitaxial layer and a support structure from a second portion of the first epitaxial layer.

[0014] According to some embodiments, forming a first porous layer includes applying a first porous process to a semiconductor substrate, and forming a second porous layer includes applying a second porous process to a first epitaxial layer. Generally, the porous process (e.g., at least one of the first or second porous process) may include an etching process (e.g., via electrochemical etching and / or plasma etching).

[0015] According to some embodiments, the support structure includes a plurality of structures. At least some of the plurality of structures may be spaced apart from each other, for example. At least some of the structures may be adjacent to each other, either individually or in combination.

[0016] According to some embodiments, the support structure includes a loop-shaped structure (e.g., a ring-shaped structure).

[0017] According to some embodiments, the support structure includes a grid-like structure having one or more structures / bridges. For example, a device structure may be aligned with openings in the grid-like structure, and groove regions may be aligned with structures / bridges in the grid-like structure.

[0018] According to some embodiments, the support structure includes a loop-shaped structure positioned around a second structure spaced apart from the loop-shaped structure. For example, the loop-shaped structure may be positioned around a device structure.

[0019] According to some embodiments, the second structure is a lattice structure.

[0020] According to some embodiments, the method includes forming a second epitaxial layer on a second porous layer. According to some embodiments, forming an epitaxial layer (e.g., a first epitaxial layer, a second epitaxial layer, etc.) on another component (e.g., a first porous layer, a first epitaxial layer, etc.) may include a deposition process (e.g., an epitaxial deposition process) for depositing the epitaxial layer onto the component. The second epitaxial layer may be formed directly on the second porous layer, or another epitaxial layer may be placed between the second epitaxial layer and the second porous layer.

[0021] According to some embodiments, the method includes forming one or more device structures on and / or within a second epitaxial layer.

[0022] According to some embodiments, the method includes separating the upper portion of the first porous layer from the lower portion of the first porous layer.

[0023] According to several embodiments, an apparatus is provided. The apparatus includes means for forming a first porous layer on a semiconductor substrate; means for forming a first epitaxial layer on the first porous layer; and means for forming a second porous layer from a first portion of the first epitaxial layer and a support structure from a second portion of the first epitaxial layer.

[0024] According to several embodiments, a method is provided. This method includes forming a support structure, which includes a porous formation process; forming a device layer on the support structure; and forming one or more device structures on and / or within the device layer.

[0025] According to some embodiments, the method includes providing a porous layer on which a support structure is formed. In some embodiments, the support structure may be directly adjacent to the porous layer. However, it may also be possible for another component to be provided between the support structure and the porous layer.

[0026] According to some embodiments, forming a support structure includes forming a first epitaxial layer to which a porous process is applied.

[0027] According to some embodiments, the porousization process porousizes only a portion of the first epitaxial layer, and the support structure includes the non-porous portion of the first epitaxial layer.

[0028] According to some embodiments, the non-porous portion includes multiple parts.

[0029] According to some embodiments, forming a device layer includes forming a second epitaxial layer.

[0030] According to several embodiments, an apparatus is provided. The apparatus includes means for forming a support structure by using a porous process; means for forming a device layer on the support structure; and means for forming one or more device structures on and / or within the device layer.

[0031] According to several embodiments, a semiconductor structure is provided. The semiconductor structure includes a support structure comprising a first epitaxial material; a device layer disposed on the support structure and comprising a second epitaxial material; and one or more device structures on and / or within the device layer.

[0032] According to some embodiments, the support structure is mainly composed of a first epitaxial material, and the device layer is mainly composed of a second epitaxial material.

[0033] According to some embodiments, the first epitaxial material and the second epitaxial material include the same material.

[0034] According to some embodiments, the support structure includes at least one of a structure / bridge consisting of multiple parts, a loop structure, or a lattice structure.

[0035] According to some embodiments, device structures are separated, for example, by dicing groove regions between neighboring device structures along the vertical direction. Dicing may include at least one of mechanical sawing, plasma dicing, and laser-assisted dicing (e.g., stealth dicing, thermal laser separation). Dicing may be carried out via a support structure (e.g., via a lattice structure / bridge). In one or more embodiments, dicing may be carried out via a metal layer.

[0036] According to several embodiments, a method is provided. The method includes: performing a first porousization process on a substrate to generate a first porous layer on the substrate; forming a first epitaxial layer (hereinafter also referred to as the "epit" layer) on the first porous layer; and performing a second porousization process on the first epitaxial layer to form a second porous layer from a first portion of the first epitaxial layer and a support structure including a second portion of the first epitaxial layer.

[0037] According to some embodiments, the method includes forming a second epitaxial layer on top of a second porous layer.

[0038] According to some embodiments, the method includes forming one or more device structures on a second epitaxial layer. The device structures may be formed on and / or within the second epitaxial layer.

[0039] According to some embodiments, the method includes attaching a reversible carrier to a second epitaxial layer.

[0040] According to some embodiments, the method includes performing a back surface treatment while the reversible carrier is attached to the second epitaxial layer.

[0041] According to some embodiments, the method includes removing the reversible carrier in response to the completion of all back-facing steps of the back-facing process or after the completion of at least some back-facing steps of the back-facing process (for example, additional back-facing steps may be performed after the reversible carrier has been removed).

[0042] According to some embodiments, the method includes removing a substrate, a first porous layer, and a second porous layer.

[0043] According to some embodiments, the method includes removing at least a portion or all of at least one porous layer of the first porous layer or the second porous layer by utilizing an etching process.

[0044] According to some embodiments, the method includes removing at least part or all of at least one porous layer of the first porous layer or the second porous layer by utilizing a mechanical process.

[0045] According to some embodiments, the method includes removing at least part or all of at least one porous layer of the first porous layer or the second porous layer by utilizing a fluid.

[0046] According to some embodiments, the support structure includes a ring structure.

[0047] According to some embodiments, the support structure is formed along the peripheral edge of the back surface of the second epitaxial layer, and the support structure has one of the following shapes: circular, square, or rectangular.

[0048] According to several embodiments, a method is provided. The method includes performing a first porosity process on a substrate to generate a first porous layer on the substrate; forming a first epitaxial layer on the first porous layer; and performing a second porosity process on the first epitaxial layer to form a second porous layer from a first portion of the first epitaxial layer, a first support structure from a second portion of the first epitaxial layer, and a second support structure from a third portion of the first epitaxial layer.

[0049] According to some embodiments, the method includes forming a second epitaxial layer on a second porous layer; and forming one or more device structures on the second epitaxial layer.

[0050] According to some embodiments, the method includes removing a substrate, a first porous layer, and a second porous layer in order to form a cavity between a first support structure and a second support structure.

[0051] According to some embodiments, the method includes filling a cavity with metal to form either a continuous or discontinuous metal layer within the cavity.

[0052] According to several embodiments, a method is provided. The method includes: performing a first porousization process on a substrate to generate a first porous layer on the substrate; forming a first epitaxial layer on the first porous layer; and performing a second porousization process on the first epitaxial layer to form a lattice support structure including a second porous layer from a first portion of the first epitaxial layer, a support structure from a second portion of the first epitaxial layer, and a plurality of support structures formed from portions of the first epitaxial layer.

[0053] According to some embodiments, the method includes forming a second epitaxial layer on a second porous layer; and forming one or more device structures on the second epitaxial layer.

[0054] According to some embodiments, the method includes removing a substrate, a first porous layer, and a second porous layer in order to form a cavity between a first support structure and a plurality of support structures of a lattice-like support structure.

[0055] According to some embodiments, the method includes filling a cavity with metal to form either a continuous or discontinuous metal layer within the cavity.

[0056] According to one or more embodiments, an exemplary method 100 for forming one or more support structures for a semiconductor structure is shown in Figure 1 and further described in conjunction with Figures 2A-2I, 3A-3I, and 4A-4I. Figures 2A-2I show a method 100 carried out to form a semiconductor structure 200. The semiconductor structure 200 includes a semiconductor substrate 202 as shown in Figure 2A. The semiconductor substrate 202 may include, for example, silicon, silicon carbide, gallium nitride, gallium arsenide, gallium oxide, indium phosphide, or any other support material that can be subjected to a porousization process. In method 102 of method 100, a first porous layer 204 is formed on the semiconductor substrate 202 as shown in Figure 2B. In one or more embodiments, the first porous layer 204 is formed by applying a first porous process (such as an edgeless or boundaryless porous process) to the semiconductor substrate 202, so that the uppermost portion of the semiconductor substrate 202 is converted into the first porous layer 204.

[0057] In method 100, 104, a first epitaxial layer 206 is formed on the first porous layer 204 as shown in Figure 2C. In one or more embodiments, the first epitaxial layer 206 is formed by a deposition process in which the first epitaxial layer 206 is deposited on the first porous layer 204. In method 100, 106, a second porous layer 208 is formed from a first portion of the first epitaxial layer 206 as shown in Figure 2D. In one or more embodiments, the second porous layer 208 is formed by applying a second porousization process to a first portion of the first epitaxial layer 206. The portion of the first epitaxial layer 206 that is not porous (the non-porous portion) remains as one or more support structures. In one or more embodiments, the support structure 206a is formed from a second portion of the first epitaxial layer 206 that is not porousd by the second porosity process, and therefore the support structure 206a includes the non-porosity portion of the first epitaxial layer 206. The support structure 206a is formed on the first porous layer 204. In one or more embodiments, the support structure 206a includes a loop-like structure (e.g., a ring structure) that is further described and shown in connection with Figure 2I. It can be understood that any number, shape, size, and / or arrangement of support structures can be formed, and that at least some of these examples are further described and shown in connection with Figures 3A-3I and 4A-4I.

[0058] In method 100, 108, a second epitaxial layer 210 is formed on the second porous layer 208 as shown in Figure 2E. In one or more embodiments, the second epitaxial layer 210 is formed on the support structure 206a. The second epitaxial layer 210 may be formed by a deposition process that deposits the second epitaxial layer 210 on the second porous layer 208 and / or the support structure 206a. In one or more embodiments, the second epitaxial layer 210 is a device layer comprising an epitaxial material which may be the same as or different from the epitaxial material of the first epitaxial layer 206 (e.g., the epitaxial material of the support structure 206a). Thus, the support structure 206a may be mainly composed of the epitaxial material of the first epitaxial layer 206, and the device layer may be mainly composed of the epitaxial material of the second epitaxial layer 210. In some embodiments, the second epitaxial layer 210 is the final epitaxial layer of the semiconductor structure 200. In some embodiments, one or more additional epitaxial layers are formed in addition to the first epitaxial layer 206 and the second epitaxial layer 210 (for example, between the first epitaxial layer 206 and the second epitaxial layer 210). It can be understood that any number of epitaxial layers may be formed.

[0059] In method 100, 110, one or more device structures 212 are formed on and / or within the second epitaxial layer 210 (e.g., on and / or within the device layer), as shown in Figure 2F. In one or more embodiments, various device formation process steps may be performed on the front surface of the semiconductor structure 200 to form one or more device structures 212. Once one or more device structures 212 are formed, a carrier 214 may be applied to the front surface of the semiconductor structure 200, as shown in Figure 2G. In one or more embodiments, the carrier 214 is a reversible carrier that can be attached to the front surface of the semiconductor structure 200. The carrier 214 supports the front surface of the semiconductor structure 200 (e.g., while one or more subsequent processing steps (e.g., back surface processing) are performed). The carrier 214 may be attached to the front surface so that it can be removed in subsequent processing steps without damaging the semiconductor structure 200. In one or more embodiments, the semiconductor substrate 202 is removed from the semiconductor structure 200 by, for example, a carrier 214 mounted on the front, as shown in Figure 2H.

[0060] In method 112, 100, at least a portion of the first porous layer 204 is removed from the semiconductor structure 200 as shown in Figure 2H. In one or more embodiments, the upper portion of the first porous layer 204 is separated from the lower portion of the first porous layer 204. In one or more embodiments, at least a portion of the second porous layer 208 is removed from the semiconductor structure 200. In one or more embodiments, a selective etching process may be used to selectively remove at least a portion of the first porous layer 204 and / or at least a portion of the second porous layer 208. In one or more embodiments, the selective etching process utilizes an etching material (such as an etching substance). The etching material may be selected to etch the porous layer with high selectivity compared to the semiconductor substrate material (e.g., silicon, hydrogen fluoride (HF), hydrogen peroxide (H2O2)), or the etching material may be selected with low selectivity (e.g., nitric acid (HNO3), acetic acid (CH3COOH), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) as the etching material) but so that the selective etching process is controlled via modifiers and / or moderators (e.g., peroxides, acetic acid) and / or surfactants. The support structure 206a is exposed by removing at least a portion of the first porous layer 204 and / or at least a portion of the second porous layer 208. For example, the support structure 206a may be a loop-shaped structure that loops along the edge of the semiconductor structure 200 (e.g., along the edge of the second epitaxial layer 210) to provide additional support and strength for the semiconductor structure 200. In particular, the loop-shaped structure may have the shape of a ring, such as a support ring.

[0061] While the carrier 214 is attached to the front surface of the semiconductor structure 200, various back-side processing steps may be performed, such as vapor deposition, etching, conditioning, lithography, implantation, annealing, and / or other processing steps. Once the back-side processing steps are complete, the carrier 214 can be removed from the semiconductor structure 200 as shown in Figure 2H.

[0062] Figure 2I shows a bottom view 250 of the semiconductor structure 200. In one or more embodiments, the support structure 206a has a ring (e.g., a surrounding circle) shape surrounding the outer edge of the semiconductor structure 200 when, for example, one or more device structures 212 are positioned on the second epitaxial layer 210 and on the internal cavity 213 of the support structure 206a, as shown in Figure 2H. In this way, the support structure 206a can be positioned near or along the outer periphery of the semiconductor structure 200. Figure 2I shows a top view 260 of the semiconductor structure 200. In one or more embodiments, one or more device structures 212 are positioned on and / or within the second epitaxial layer 210 (device layer).

[0063] Figures 3A to 3I show a method 100 implemented to form a semiconductor structure 300 including a first support structure 306a and a second support structure 306b. The semiconductor structure 300 includes a semiconductor substrate 302 as shown in Figure 3A. The semiconductor substrate 302 may include silicon, silicon carbide, or any other support material. In method 102, a first porous layer 304 is formed on the semiconductor substrate 302 as shown in Figure 3B. In one or more embodiments, the first porous layer 304 is formed by applying a first porousization process to the semiconductor substrate 302, so that the uppermost portion of the semiconductor substrate 302 is converted into the first porous layer 304. Thus, the first porous layer 304 is formed on, on, or from the semiconductor substrate 302, for example, when the first porous layer 304 is formed as part of the semiconductor substrate 302 (for example, a portion of the semiconductor substrate 302 is modified to form the first porous layer 304). In method 100, 104, the first epitaxial layer 306 is formed on the first porous layer 304 as shown in Figure 3C. In one or more embodiments, the first epitaxial layer 306 is formed by a deposition process in which the first epitaxial layer 306 is deposited on the first porous layer 304.

[0064] In method 100, 106, the second porous layer 308 is formed from a first portion of the first epitaxial layer 306, as shown in Figure 3D. In one or more embodiments, the second porous layer 308 is formed by applying the second porousization process to a first portion of the first epitaxial layer 306. In one or more embodiments, the second porousization process is performed by marginal exclusion. The portion of the first epitaxial layer 306 that is not porous (the non-porous portion of the first epitaxial layer 306) remains as one or more support structures. The non-porous portion is formed by using a hard mask or sealing ring to prevent the second porousization process from making the non-porous portion porous. In one or more embodiments, the first support structure 306a is formed from a second portion of the first epitaxial layer 306 that is not porousd by the second porosity process, and therefore the first support structure 306a includes the non-porosity portion of the first epitaxial layer 306. The first support structure 306a is formed on the first porous layer 304. In one or more embodiments, the first support structure 306a includes a loop-like structure (e.g., a ring structure) which is further described and shown in connection with Figure 3I.

[0065] In one or more embodiments, the second support structure 306b is formed from a third portion of the first epitaxial layer 306 that is not porousd by the second porosity process, and therefore the second support structure 306b includes the non-porosity portion of the first epitaxial layer 306. The second support structure 306b is formed on top of the first porous layer 304. In one or more embodiments, the second support structure 306b includes a structure such as a column structure in which the first support structure 306a (loop structure) is positioned and spaced apart by the second porous layer 308, which is further explained and shown in connection with Figure 3I. It can be understood that any number, shape, size, and / or arrangement of support structures can be formed. In one or more embodiments, both the first support structure 306a and the second support structure 306b are formed as shown in Figure 3D. In one or more embodiments, only the second support structure 306b may be formed, instead of the first support structure 306a.

[0066] In method 100, 108, a second epitaxial layer 310 is formed on the second porous layer 308 as shown in Figure 3E. In one or more embodiments, the second epitaxial layer 310 is formed on the first support structure 306a and / or the second support structure 306b. The second epitaxial layer 310 may be formed by a deposition process that deposits the second epitaxial layer 310 on the second porous layer 308, the first support structure 306a and / or the second support structure 306b. In one or more embodiments, the second epitaxial layer 310 is a device layer comprising an epitaxial material which may be the same as or different from the epitaxial material of the first epitaxial layer 306 (e.g., the epitaxial material of the first support structure 306a and / or the second support structure 306b). In this way, the first support structure 306a and / or the second support structure 306b are mainly composed of the epitaxial material of the first epitaxial layer 306, and the device layer is mainly composed of the epitaxial material of the second epitaxial layer 310.

[0067] In method 100, 110, one or more device structures 312 are formed on and / or within the second epitaxial layer 310 (e.g., on and / or within the device layer), as shown in Figure 3F. In one or more embodiments, various device formation process steps may be performed on the front surface of the semiconductor structure 300 to form one or more device structures 312. Once one or more device structures 312 are formed, a carrier 314 may be coated onto the front surface of the semiconductor structure 300, as shown in Figure 3G. In one or more embodiments, the carrier 314 is a reversible carrier that can be attached to the front surface of the semiconductor structure 300. The carrier 314 supports the front surface of the semiconductor structure 300 (e.g., while one or more subsequent processing steps are performed). In one or more embodiments, the semiconductor substrate 302 is removed from the semiconductor structure 300, as shown in Figure 3H.

[0068] In method 112, 100, at least a portion of the first porous layer 304 is removed from the semiconductor structure 300 as shown in Figure 3H. In one or more embodiments, the upper portion of the first porous layer 304 is separated from the lower portion of the first porous layer 304. In one or more embodiments, at least a portion of the second porous layer 308 is removed from the semiconductor structure 300. In one or more embodiments, a selective etching process may be used to selectively remove at least a portion of the first porous layer 304 and / or at least a portion of the second porous layer 308. In one or more embodiments, the selective etching process utilizes an etching material (such as an etching substance). The etching material may be selected to etch the porous layer with high selectivity compared to the semiconductor substrate material (e.g., silicon, hydrogen fluoride (HF), hydrogen peroxide (H2O2)), or the etching material may be selected with low selectivity (e.g., nitric acid (HNO3), acetic acid (CH3COOH), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) as the etching material) but the selective etching process may be controlled via modifiers and / or moderators (e.g., peroxides, acetic acid) and / or surfactants. By removing at least a portion of the first porous layer 304 and / or at least a portion of the second porous layer 308, a first support structure 306a, such as a loop-shaped structure looping along the edge of the semiconductor structure 300, and a second support structure 306b, such as a columnar structure, are exposed to provide additional support and strength to the semiconductor structure 300.

[0069] While the carrier 314 is mounted to the front surface of the semiconductor structure 300, various back surface treatment processes such as lithography, implantation, annealing, and / or other processing steps may be performed. In one or more embodiments, back surface metallization may be performed on the back surface of the semiconductor structure 300. In one or more embodiments, back surface metallization may fill the cavity 340 between the first support structure 306a and the second support structure 306b. The resulting metal layer may be a continuous metal layer in which the metal is filled within the cavity 340 but above the uppermost surfaces 342 of the first support structure 306a and the second support structure 306b (e.g., the metal is filled up to the dotted line 344), or a discontinuous metal layer in which the metal is filled within the cavity 340 but below the uppermost surfaces 342 of the first support structure 306a and the second support structure 306b (e.g., the metal is filled up to the dotted line 346). Once the back surface treatment process is complete, the carrier 314 can be removed from the semiconductor structure 300 as shown in Figure 3H.

[0070] Figure 3I shows a bottom view 350 of the semiconductor structure 300. In one or more embodiments, the first support structure 306a is loop-shaped so that the first support structure 306a loops around the edge of the semiconductor structure 300 (for example, around the edge of the second epitaxial layer 310 (device layer)). In one or more embodiments, the second support structure 306b has a columnar shape, and the second epitaxial layer 310 separates the first support structure 306a from the first support structure 306a so that the first support structure 306a loops around the second support structure 306b. Figure 3I shows a top view 360 of the semiconductor structure 300. In one or more embodiments, one or more device structures 312 are positioned on and / or within the second epitaxial layer 310 (device layer).

[0071] Figures 4A to 4I show a method 100 carried out to form a semiconductor structure 400, which includes a first support structure 406a and a second support structure including a plurality of structures (including a first structure 406b, a second structure 406c, a third structure 406d, a fourth structure 406e, and a fifth structure 406f, etc.). The semiconductor structure 400 includes a semiconductor substrate 402 as shown in Figure 4A. The semiconductor substrate 402 may include silicon, silicon carbide, or any other support material. In method 102, a first porous layer 404 is formed on the semiconductor substrate 402 as shown in Figure 4B. In one or more embodiments, the first porous layer 404 is formed by applying a first porousization process to the semiconductor substrate 402, so that the uppermost portion of the semiconductor substrate 402 is converted into the first porous layer 404. In method 100, in 104, the first epitaxial layer 406 is formed on the first porous layer 404 as shown in Figure 4C. In one or more embodiments, the first epitaxial layer 406 is formed by a deposition process in which the first epitaxial layer 406 is deposited on the first porous layer 404.

[0072] In method 100, 106, the second porous layer 408 is formed from a first portion of the first epitaxial layer 406, as shown in Figure 4D. In one or more embodiments, the second porous layer 408 is formed by applying the second porousization process to a first portion of the first epitaxial layer 406. In one or more embodiments, the second porousization process is performed with peripheral exclusion. The portion of the first epitaxial layer 406 that is not porous (the non-porous portion) remains as one or more support structures (such as the first support structure 406a and / or the second support structure). The non-porous portion is formed by utilizing a hard mask or sealing ring to prevent the second porousization process from making the non-porous portion porous. In one or more embodiments, the first support structure 406a is formed from a second portion of the first epitaxial layer 406 that is not porousd by the second porosity process, and therefore the first support structure 406a includes the non-porosity portion of the first epitaxial layer 406. The first support structure 406a is formed on the first porous layer 404. In one or more embodiments, the first support structure 406a includes a loop-like structure (e.g., a ring structure) which is further described and shown in connection with Figure 4I.

[0073] In one or more embodiments, the second support structure is formed from one or more portions of the first epitaxial layer 406 that are not porousd by the second porosizing process, and therefore the second support structure includes one or more non-porosized portions of the first epitaxial layer 406. The second support structure is formed on the first porous layer 404. In one or more embodiments, the second support structure includes a grid-like structure that includes multiple structures (e.g., support regions), such as the first structure 406b, the second structure 406c, the third structure 406d, the fourth structure 406e, and the fifth structure 406f, which are further described and shown in connection with Figure 4I. Thus, the second support structure includes multiple structures separated from the first support structure 406a (loop-like structure) by the second porous layer 408. It can be understood that the second support structure may include any number, shape, size, and / or arrangement of structures. In one or more embodiments, both the first support structure 406a and the second support structure are formed as shown in Figure 4D. In one or more embodiments, only the second support structure may be formed instead of the first support structure 406a.

[0074] In method 100, 108, a second epitaxial layer 410 is formed on the second porous layer 408 as shown in Figure 4E. In one or more embodiments, the second epitaxial layer 410 is formed on the first support structure 406a and / or the second support structure. The second epitaxial layer 410 may be formed by a deposition process that deposits the second epitaxial layer 410 on the second porous layer 408, the first support structure 406a and / or the second support structure. In one or more embodiments, the second epitaxial layer 410 is a device layer comprising an epitaxial material which may be the same as or different from the epitaxial material of the first epitaxial layer 406 (e.g., the epitaxial material of the first support structure 406a and / or the second support structure). In this way, the first support structure 406a and / or the second support structure are mainly composed of the epitaxial material of the first epitaxial layer 406, and the device layer is mainly composed of the epitaxial material of the second epitaxial layer 410.

[0075] In method 100, 110, one or more device structures 412 are formed on and / or within the second epitaxial layer 410 (e.g., on and / or within the device layer), as shown in Figure 4F. In one or more embodiments, various device formation process steps may be performed on the front surface of the semiconductor structure 400 to form one or more device structures 412. In one or more embodiments, one or more device structures 412 may be formed on the second porous layer 408. In one or more embodiments, one or more device structures 412 may be formed between the structures of the second support structure (e.g., between the first structure 406b and the second structure 406c, between the second structure 406c and the third structure 406d, between the third structure 406d and the fourth structure 406e, and between the fourth structure 406e and the fifth structure 406f). In one or more embodiments, the width 405 of the device structure may be the same as or similar to the width 407 of the porous region of the second porous layer 408 on which the device structure is formed, as shown in Figure 4F. In one or more embodiments, the width 405 of the device structure may be smaller than the width 407 of the porous region of the second porous layer 408. In one or more embodiments, the width 405 of the device structure may be larger than the width 407 of the porous region of the second porous layer 408, and therefore the device structure may be formed on at least a portion of one or more structures of the second support structure. In one or more embodiments, the width 405 of the device structure may be larger than the width 409 of the structure of the second support structure (e.g., a fifth structure 406f), as shown in Figure 4F. In one or more embodiments, the width 405 of the device structure may be smaller than the width 409 of the structure of the second support structure. In one or more embodiments, the width 405 of the device structure may be the same as or similar to the width 409 of the structure of the second support structure.

[0076] Once one or more device structures 412 are formed, a carrier 414 is applied to the front surface of the semiconductor structure 400 as shown in Figure 4G. In one or more embodiments, the carrier 414 is a reversible carrier that can be attached to the front surface of the semiconductor structure 400. The carrier 414 supports the front surface of the semiconductor structure 400 (for example, while one or more subsequent processing steps are performed). In one or more embodiments, the semiconductor substrate 402 is removed / detached from the semiconductor structure 400 as shown in Figure 4H.

[0077] In method 112, 100, at least a portion of the first porous layer 404 is removed from the semiconductor structure 400 as shown in Figure 4H. In one or more embodiments, the upper portion of the first porous layer 404 is separated from the lower portion of the first porous layer 404. In one or more embodiments, at least a portion of the second porous layer 408 is removed from the semiconductor structure 400. In one or more embodiments, a selective etching process may be used to selectively remove at least a portion of the first porous layer 404 and / or at least a portion of the second porous layer 408. In one or more embodiments, the selective etching process utilizes an etching material such as hydrogen fluoride (HF), hydrogen peroxide (H2O2), or other etching material. By removing at least a portion of the first porous layer 404 and / or at least a portion of the second porous layer 408, a first support structure 406a, such as a loop-shaped structure that loops along the edge of the semiconductor structure 400, and second support structures such as the first structure 406b, the second structure 406c, the third structure 406d, the fourth structure 406e, and the fifth structure 406f are exposed, providing additional support and strength to the semiconductor structure 400.

[0078] While the carrier 414 is mounted to the front surface of the semiconductor structure 400, various back surface treatment processes such as lithography, implantation, annealing, and / or other processing steps may be performed. In one or more embodiments, back surface metallization may be performed on the back surface of the semiconductor structure 400. In one or more embodiments, back surface metallization may fill the cavities 440 between the first support structure 406a, the first structure 406b, the second structure 406c, the third structure 406d, the fourth structure 406e, and / or the fifth structure 406f. The resulting metal layer may be a continuous metal layer in which the metal is filled within the cavity 440 but on top of the top surface 442 of the first support structure 406a, first structure 406b, second structure 406c, third structure 406d, fourth structure 406e, and / or fifth structure 406f (e.g., the metal is filled up to the dotted line 444), or a discontinuous metal layer in which the metal is filled within the cavity 440 but below the top surface 442 of the first support structure 406a, first structure 406b, second structure 406c, third structure 406d, fourth structure 406e, and / or fifth structure 406f (e.g., the metal is filled up to the dotted line 446). Once the back surface treatment process is complete, the carrier 414 can be removed from the semiconductor structure 400 as shown in Figure 4H.

[0079] In one or more embodiments, the dicing process may be performed to separate one or more device structures 412 by dicing 435 regions between neighboring device structures, as shown in Figure 4H. In one or more embodiments, dicing 435 may involve the removal of material represented / indicated by dotted lines 437 as opposed to cutting along lines (e.g., a certain thickness of material may be removed). In one or more embodiments, dicing 435 may be performed via one type of material, for example, if dicing 435 is performed via the epitaxial material (e.g., semiconductor material) of the second support structure, which includes the epitaxial material (e.g., semiconductor material) of the second epitaxial layer 410 and the epitaxial material (e.g., semiconductor material) from the first epitaxial layer 406. Thus, in one or more embodiments, dicing 435 may be performed via only semiconductor material. Since dicing 435 may be performed via one type of material, the dicing process and dicing tools may be selected based on the type of material.

[0080] It can be understood that Figure 4H shows a first embodiment of one or more support structures formed for a semiconductor structure, and Figure 4I shows a second embodiment of one or more support structures formed for a semiconductor structure (for example, distinct from the first embodiment in Figure 4H). However, it can be understood that at least some of the processing steps described in relation to Figures 4A to 4G can be applied to both the first embodiment in Figure 4H and / or the second embodiment in Figure 4I.

[0081] In one or more embodiments in which the cavity (e.g., cavity 440) between the first support structure 406a and the second support structure is optionally filled with metal 411, dicing 435 may be performed via two materials, for example, an epitaxial material (e.g., the epitaxial material of the second epitaxial layer 410) and metal 411, as shown in the second embodiment of Figure 4I.

[0082] Figure 4J shows a bottom view 450 of a semiconductor structure 400 having dicing lines / regions. In one or more embodiments, the semiconductor structure 400 optionally includes a first support structure 406a that can loop around the edges of the semiconductor structure 400 (e.g., around the edges of a second epitaxial layer 410 (device layer) and around a second support structure 477). In one or more embodiments, the semiconductor structure 400 includes a second support structure 477. In one or more embodiments, the second support structure 477 is separated from the first support structure 406a by a second epitaxial layer 410 such that the first support structure 406a loops around the second support structure 477. Figure 4J shows a top view 460 of a semiconductor structure 400 having dicing lines / regions. In one or more embodiments, one or more device structures 412 are positioned on and / or within a second epitaxial layer 410 (device layer).

[0083] It can be understood that Figure 4J shows bottom and top views of a first embodiment of one or more support structures formed for a semiconductor structure, and Figure 4K shows bottom and top views of a second embodiment of one or more support structures formed for a semiconductor structure (which is, for example, separate from the first embodiment in Figure 4J). However, it can be understood that at least some of the processing steps described in relation to Figures 4A to 4G can be applied to both the first embodiment in Figure 4J and / or the second embodiment in Figure 4K.

[0084] Figure 4K shows a bottom view 490 of a semiconductor structure 400 in which metal 411 is filled in a cavity between support structures. In one or more embodiments, the semiconductor structure 400 optionally includes porous regions 479 (e.g., optional openings) in which metallic material can be optionally filled. Figure 4K shows a top view 495 of a semiconductor structure 400 in which metal 411 is filled in a cavity between support structures.

[0085] While the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the attached claims is not necessarily limited to the aforementioned specific features or actions. Rather, the aforementioned specific features and actions are disclosed as exemplary forms for implementing the claims.

[0086] As used in this application, terms such as “component,” “module,” “system,” and “interface” are generally intended to refer to computer-related entities (either hardware, a combination of hardware and software, software, or running software). One or more components may be localized on one computer and / or distributed across two or more computers.

[0087] Furthermore, the claimed subject matter may be realized as a method, apparatus, or product by using standard programming and / or engineering techniques to generate software, firmware, hardware, or any combination thereof to control a computer and realize the disclosed subject matter. The term “product” as used herein is intended to encompass computer programs accessible from any computer-readable device, carrier, or medium. Naturally, those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope or spirit of the claimed subject matter.

[0088] Various operations of embodiments are provided herein. In one embodiment, one or more of the operations described may constitute a computer-readable instruction (which causes a computer device to perform the operations described) stored on one or more computer-readable materials. The order in which some or all of the operations are described should not be interpreted as meaning that these operations are necessarily order-dependent. Alternative orderings will be understood by those skilled in the art who have the advantages of this specification. Furthermore, it will be understood that not all operations are necessarily present in each embodiment provided herein.

[0089] Any aspect or design described herein as “example” is not necessarily to be considered more advantageous than other aspects or designs. Rather, the use of the word “example” is intended to present one possible aspect and / or implementation that may relate to the technology presented herein. Such examples are not intended to be unnecessary or limiting for such technology. Various embodiments of such technology may include and / or vary such examples, either alone or in combination with other features, and / or omit the examples shown.

[0090] As used in this application, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” That is, unless otherwise specified or evident from the context, “X adopts A or B” is intended to mean any of the natural inclusive permutations. That is, if X adopts A; if X adopts B; or if X adopts both A and B, “X adopts A or B” is satisfied under the condition of any of the above cases. In addition, articles used in this application and in the attached claims can generally be interpreted as meaning “one or more” unless otherwise specified or evident from the context that they are directed to the singular form. Also, unless otherwise specified, “first,” “second,” etc., are not intended to mean temporal aspect, spatial aspect, ordering, etc. Rather, such terms are used only as identifiers, features, names, etc., of elements, items, etc. For example, the first element and the second element generally correspond to elements A and B or two different or two identical or the same element.

[0091] Furthermore, although this disclosure is shown and described for one or more implementations, equivalent alternatives and modifications will be conceivable to those skilled in the art based on reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and alternatives and is limited only to the scope of the following claims. In particular, with respect to the various functions performed by the parts (elements, resources, etc.) described above, the terminology used to describe such parts is intended to correspond to any part or structure that performs a defining function of the described part (e.g., functionally equivalent) even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations shown in this disclosure. In addition, although certain features of this disclosure may be disclosed for only one of several implementations, such features may be combined with other features of one or more other implementations as they may be desirable or advantageous for a given or particular application. Furthermore, to the extent that the terms “include,” “have,” “equip,” or variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a similar manner to the term “include.” [Explanation of Symbols]

[0092] 100 ways 200, 300, 400 Semiconductor Structures 202, 302, 402 Semiconductor Substrates 204, 304, 404 First porous layer 206, 306, 406 First epitaxial layer 206a Support structure 208, 308, 408 Second porous layer 210, 310, 410 Second epitaxial layer 212, 312, 412 Device Structures 213 Internal cavity 214, 314, 414 Carrier 250 Bottom view 260 Top view 306a, 406a First support structure 306b, 406b Second support structure 340 Cavity 342 Top surface 344 dotted line 346 dotted line 350 Bottom view 405 width 406b First structure 406c Second structure 406d Third structure 406e Fourth structure 406f Fifth Structure 407 width 409 width 411 Metal 412 Device Structure 435 Dicing 437 dotted line 440 Cavity 442 Top surface 444 dotted line 446 dotted line 477 Second support structure 479 Porous region 490 Bottom view 495 Top view

Claims

1. Forming a first porous layer on a semiconductor substrate, Forming a first epitaxial layer on the first porous layer, and A method comprising forming a second porous layer from a first portion of the first epitaxial layer, and a support structure from a second portion of the first epitaxial layer.

2. The method according to claim 1, wherein forming the first porous layer includes applying a first porous process to the semiconductor substrate, and forming the second porous layer includes applying a second porous process to the first epitaxial layer.

3. The method according to claim 1, wherein the support structure includes a plurality of parts.

4. The method according to claim 1, wherein the support structure includes a loop-shaped structure.

5. The method according to claim 1, wherein the support structure includes a lattice structure.

6. The method according to claim 1, wherein the support structure includes a loop-shaped structure arranged around a second structure spaced apart from the loop-shaped structure.

7. The method according to claim 6, wherein the second structure is a lattice structure.

8. The method according to claim 1, further comprising forming a second epitaxial layer on the second porous layer.

9. The method according to claim 8, further comprising forming one or more device structures on and / or within the second epitaxial layer.

10. The method according to claim 1, further comprising separating the upper portion of the first porous layer from the lower portion of the first porous layer.

11. Forming a support structure, including a porous structure process. Forming the device layer on the support structure, A method comprising forming one or more device structures on and / or within the device layer, Forming the support structure includes forming a first epitaxial layer to which the porous process is applied. The method wherein the porous formation process porous forms only a portion of the first epitaxial layer, and the support structure includes the non-porous portion of the first epitaxial layer.

12. The method according to claim 11, further comprising providing a porous layer, wherein the support structure is formed on the porous layer.

13. The method according to claim 11 or 12, wherein the non-porous portion includes a plurality of parts.

14. The method according to any one of claims 11 to 13, wherein forming the device layer includes forming a second epitaxial layer.

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