Information processing device, information processing method, and program

Abstract

To accurately analyze the efficiency of access to a DRAM.SOLUTION: An information processor has: detection means for detecting an event for changing states of at least one or more banks constituting a DRAM; and classification means for classifying the states of at least one or more banks into an operating state, an inoperable state, or a resting state on the basis of the event detected by the detection means. When the detection means detects a first control command to a predetermined bank and a second control command subsequent to the first control command, the classification means sets a second operating state section classified into the operating state on the basis of the second control command, on the basis of a first operating state section classified into the operating state on the basis of the first control command.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an information processing apparatus, an information processing method, and a program for analyzing the state of a DRAM.

Background Art

[0002] Techniques for analyzing the performance of DRAM in system LSIs have been widely used for a long time. Before explaining performance analysis techniques, let's explain DRAM. DRAM stands for Dynamic Random Access Memory and is one of the memory devices used in many modern digital devices such as PCs (Personal Computers), smartphones, digital televisions, and digital cameras. SRAM (Static Random Access Memory) is a memory device that is often compared to DRAM. Compared to SRAM, DRAM requires a periodic memory retention operation called a refresh, so it generally consumes more power. On the other hand, its structure makes it easy to achieve high integration, and it has the advantage of being able to provide large capacity at a low cost, so it has been used as a large-capacity memory device for a long time. With the recent increase in pixel counts such as 4K (image size of approximately 4000 pixels vertically and 2000 pixels horizontally) and 8K (image size of approximately 8000 pixels vertically and 4000 pixels horizontally), the size of digital data for still and moving images continues to increase, and the application range of DRAM shows no signs of waning. As DRAM is the main memory device for digital devices, there is a high demand for improving its access speed. In response to this, DRAM has addressed these demands through structural advancements such as SDRAM (Synchronous DRAM) and RDRAM (Rambus DRAM), speed improvements through increased clock frequencies within the same structure, and various functions that enable higher speeds. Here, we will explain using SDRAM as an example. SDRAM evolved from SDR (Single Data Rate), which operates only on the rising edge of the clock signal, to DDR (Dual Data Rate), which operates on both the rising and falling edges of the clock signal, theoretically doubling its access rate. Furthermore, DDR, DDR2, DDR3, and DDR4 have evolved, mainly through improvements in clock frequency and capacity, along with the definition of the standards. In addition, LP (Low Power) versions such as LPDDR2, LPDDR3, LPDDR4, and LPDDR5 have also been standardized.The standards are defined and standardized by the JEDEC Solid State Technology Association, and have evolved to prevent companies involved in DRAM manufacturing from using their own proprietary standards.

[0003] As mentioned above, SDRAM access performance has evolved, but the control method remains fundamentally the same for all types, including SDR, DDR, and LPDDR, and is controlled by control signals called commands. The command-based control method will be explained using DDR3 as an example. However, as previously stated, the control method does not differ significantly between SDR, DDR, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. Figure 5 shows a list of DDR3 commands. In Figure 5, 501 and 502 indicate the meaning and command notation of the corresponding command when the signals 503 through 513 match that state. The ACT command is used to select the row address of the DRAM. This operation is called activation, and since the memory space at the same row address is treated as a page and preparation for access to the page is made, it is called page open. After selecting the row address with the ACT command, the column address is selected with the RD command and WR command to read and write data to the DRAM memory elements. There are two addresses for selecting the DRAM memory elements: row address and column address. Basic read and write operations involve first selecting a row address with the ACT command, then selecting a column address with the RD and WR commands to determine the address of the target memory element. In SDRAM, a method called page mode has been devised to speed up data access, where data with different column addresses but the same row address are read and written sequentially. This allows for high-speed access even if the column address is different, as long as the row address is the same. On the other hand, if the row address is different, the activated row address must be returned to a deselected state by an operation called precharge using the PRE command, and then re-activated. This precharge is called page close, in contrast to page open for activation. Due to the structure of DRAM, it is difficult to shorten the time for this series of page close (precharge) and page open (activate) operations, and this has not been significantly shortened even with advancements in standards. Generally, this series of operations is called a page miss. Page misses always occur when the row address changes, so they cannot be avoided.However, a structure has been devised to conceal this page error and improve access efficiency. The mechanism is simple: the entire memory space selected by row address and column address is constructed in units called banks, and by implementing multiple banks, page errors are concealed. In other words, during the period when a page error occurs in one bank and access is impossible, access to other banks is performed in parallel, effectively concealing all or part of the page error. However, since banks share row addresses, column addresses, and signal lines through which data flows, functional expansion can be achieved without expanding the DRAM's circuit board wiring. Figure 10 shows the penalty due to a page error and the operation of other banks to conceal it. In Figure 10, 1001 is an RD command to bank 0. According to the DDR3-SDRAM standard, there are 4-beat access, which accesses data four times consecutively, and 8-beat access, which accesses data eight times consecutively. Since consecutive accesses are performed once on the rising and falling edges of the clock, 4-beat access consumes 2 clock cycles, and 8-beat access consumes 4 clock cycles. In this example, assuming only 8-beat access is issued, the next RD command can be issued 4 clock cycles after the previous RD command is issued. RD command 1002 is issued to bank 0, 4 clock cycles after 1001, and is issued at the shortest possible timing considering 8-beat access. Subsequently, a page miss occurs in bank 0, and the PRE command 1003 and the ACT command 1004 are issued consecutively, followed by the issuance of RD command 1005 to a different page. That is, it can be determined that the period from 4 clock cycles after RD command 1002 to RD command 1005 is a penalty due to a page miss. On the other hand, RD command 1006 is issued in bank 1 4 clock cycles after RD command 1002. Regardless of the bank, 4 clock cycles is the shortest possible timing, meaning that RD commands 1002 to 1006 are accessed at the shortest possible timing. Similarly, RD commands 1007, 1008, and 1009 are also issued at 4-clock cycle intervals, and are accessed at the shortest possible timing during this period as well.As a result, the next RD command can only be issued 4 clock cycles after RD command 1009. Looking at this only in bank 0, the 18 clock cycles from 4 clock cycles after RD command 1002 to RD command 1005 are penalized due to page misses. On the other hand, looking at the DRAM as a whole, RD commands 1002, 1006, 1007, 1008, and 1009 are all issued at the fastest possible timing, so there is no penalty. In other words, the 16 clock cycles from 4 clock cycles after RD command 1002 to 4 clock cycles after RD command 1009 can be considered to have concealed the penalty due to page misses. Consequently, in the DRAM as a whole, only the 2 clock cycles from 4 clock cycles after RD command 1009 to RD command 1005 are considered to be penalized due to page misses.

[0004] Another typical control operation for DRAM is called refresh, a memory retention operation performed by the REF command. DRAM memory elements represent their values ​​by the stored charge. This stored charge is gradually lost due to leakage current within the memory element, making it difficult to distinguish between a state with no charge and a state with no charge. Therefore, it is necessary to periodically replenish the charge. This is refresh. Refresh is basically performed on a bank-by-bank basis, but the target bank must have a non-selected row address and must be closed beforehand. Also, due to its structure, the refresh operation takes a certain amount of time, and there is a period during which access is unavailable after the refresh command is issued.

[0005] In addition, DRAM also has a calibration function (periodically adjusting the phase relationship between signal lines and the clock), and this function is also achieved by issuing commands. Similar to penalties for page errors and refreshes, there is a period of time during which access is unavailable after issuing these commands.

[0006] In DRAM, it is common to use a common data signal line for transferring read and write data. Therefore, commands that perform data transfer, such as RD commands and WR commands (hereinafter referred to collectively as transfer commands), need to be issued at a time that avoids overlapping data transfer periods on the data signal line. Figure 11 illustrates this point. RD command 1101 is issued in the 4th clock cycle, and the transfer of read data 1102 begins on the data signal line in the 7th clock cycle, 3 clock cycles after issuance. The period from issuance of RD command 1101 to the start of the transfer, i.e., the read latency, is 3 clock cycles. Assuming this transfer is an 8-beat access, the transfer consumes 4 clock cycles and is completed in the 11th clock cycle. If another RD command is issued afterward, the timing of issuance must be adjusted so that the next data is transferred after the 11th clock cycle, when the transfer of read data 1102 is completed on the data signal line. Since the period from the issuance of an RD command to the start of read data transfer on the data signal line is 3 clock cycles, the next RD command must be issued after the 8th clock cycle, counting backward from the 11th clock cycle. Therefore, in this example, the next RD command 1103 is issued in the 8th clock cycle, and the read data 1104 corresponding to RD command 1103 is transferred between the 11th and 15th clock cycles. Next, we will explain an example in which an RD command is issued after a WR command. Normally, there will be at least one clock cycle between write data and read data, or between read data and write data, on the data signal line due to the processing required for switching the transfer direction. However, in the following example, for the sake of simplicity, we will explain it as if write data and read data can be transferred without any gap on the data signal line. The WR command 1105 is issued in the 104th clock cycle. Here, the period from the issuance of an RD command to the start of read data transfer is generally shorter than the period from the issuance of a write command to the start of write data transfer.In this example, the period from the issuance of the WR command to the start of the transfer of the write data is assumed to be 1 clock cycle, and the write data 1106 corresponding to the WR command 1105 begins to transfer on the data signal line at the 105th clock cycle. In this transfer, the period from the issuance of the WR command 1105 to the start of the transfer, i.e., the write latency, is 1 clock cycle. Assuming this transfer is an 8-beat access, the transfer consumes 4 clock cycles and is completed at the 109th clock cycle. That is, the write latency is 5 clock cycles. When issuing an RD command thereafter, the timing of issuance must be adjusted so that the next data is transferred after the 109th clock cycle, when the transfer of the write data 1106 on the data signal line is completed. Since the period from the issuance of the RD command to the start of the transfer of the read data is 3 clock cycles, the next RD command must be issued after the 106th clock cycle, working backward from the 109th clock cycle. Therefore, in this example, the next RD command 1107 is issued at the 106th clock cycle, and the read data 1108 corresponding to the RD command 1107 is transferred between the 109th and 113th clock cycles. Thus, data transfer commands need to be issued at a time that avoids overlapping data transfer periods on the data signal line. However, because RD commands and WR commands have different latencies, if a command with a longer latency (generally an RD command) is issued after a command with a shorter latency (generally a WR command), the interval between command issuances can be shorter.

[0007] Patent Document 1 describes a method for analyzing and displaying the performance of the DRAM described above, i.e., access efficiency. Patent Document 1 discloses a technique for classifying the state of each bank of DRAM based on the control commands into one of three categories: an operational state in which data is being transferred, an operational state in which data cannot be transferred due to predetermined constraints, or a dormant state in which there are no constraints but data is not being transferred. Some DRAM control commands have constraints on the issuance interval defined in the DRAM standard. For example, there are constraints on the interval from the ACT command to the RD command, the interval from the refresh command to the next command, and the interval between transfer commands. In Patent Document 1, if the issuance interval of two control commands that have constraints on the command issuance interval matches the constraint defined in the standard, it is determined that the command issuance has been delayed due to the constraint on the command issuance interval. If it is determined that the command issuance has been delayed, the control commands are classified as an operational state. In addition, Patent Document 1 classifies the time taken for data transfer, or 4 clock cycles in the case of 8-burst access, from the timing when the transfer command is detected into an operational state. For example, as explained in Figure 11, since RD command 1101 is detected in the fourth clock cycle, the operating state is classified for the four clock cycles starting from the fourth clock cycle. By classifying the state of the DRAM in this way, it is possible to analyze how efficiently the DRAM is being accessed. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Patent Application No. 2019-083241 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] However, the method of classifying operating states as shown in Patent Document 1 has problems. Let's explain the problems using Figure 12 as an example. The WR command 1201 is issued in the 4th clock cycle. Assuming that the transfer for the WR command 1201 is an 8-beat access, the transfer consumes 4 clock cycles, so the section 1202 enclosed by the diagonal lines from the 4th clock cycle to the 8th clock cycle becomes the operating state section. Next, the RD command 1203 is issued in the 6th clock cycle. Assuming that the transfer for the RD command 1203 is an 8-beat access, the transfer consumes 4 clock cycles, so the section 1204 enclosed by the thick line from the 6th clock cycle to the 10th clock cycle becomes the operating state section. As a result, 2 clock cycles from the 6th clock cycle overlap between the operating state section 2102 and the operating state section 2104. Therefore, although the period during which data is actually transferred on the data signal line is a total of 8 clock cycles, only 6 clock cycles can be classified as operating states. Thus, if the end of the operational state interval for a preceding transfer command occurs after the detection timing of the subsequent transfer command, the period classified as an operational state becomes shorter than the period during which data is actually transferred on the DRAM data signal line. Therefore, it is not possible to accurately analyze the efficiency of access to the DRAM. [Means for solving the problem]

[0010] The information processing apparatus of the present invention comprises a detection means for detecting an event that causes a transition in the state of at least one bank constituting a DRAM, and a classification means for classifying the state of the at least one bank into an operating state, an inoperable state, and a paused state based on the event detected by the detection means, wherein the classification means sets a second operating state interval for which the state is classified into an operating state based on the second control command, based on a first operating state interval for which the state is classified into an operating state based on the first control command, when a first control command for a predetermined bank and a second control command following the first control command are detected by the detection means. [Effects of the Invention]

[0011] According to the present invention, the efficiency of accessing DRAM can be analyzed with high accuracy. [Brief explanation of the drawing]

[0012] [Figure 1] This is a conceptual diagram illustrating the entire performance analysis process of the present invention. [Figure 2] This is a diagram showing the configuration of the test bench being simulated. [Figure 3] This is a diagram showing the configuration of a computer system that performs performance analysis. [Figure 4] These are the signal lines that make up the DDR3-SDRAM interface. [Figure 5] This is a list of commands for DDR3-SDRAM. [Figure 6] This is an example of the output result of the detection means 101 in the first embodiment. [Figure 7] This is a flowchart illustrating the processing of the bank state classification means 103 in the first embodiment. [Figure 8] This is a table showing the constraints between commands in the first embodiment. [Figure 9] This shows the processing results of the bank state classification means 103 on the output results of Figure 6. [Figure 10] This diagram illustrates the penalty for page errors in DDR3-SDRAM and the actions taken to conceal them. [Figure 11] This diagram illustrates the constraints between transfer commands. [Figure 12] This diagram illustrates the problem of overlapping operating state intervals in Patent Document 1. [Modes for carrying out the invention]

[0013] (First embodiment) The display device (information processing device) of the first embodiment will be described using Figures 1 to 9.

[0014] Figure 2 is a diagram of the test bench configuration including the system LSI and peripheral modules to be simulated in this embodiment. In Figure 2, 200 is the system LSI. The CPU 201 is for executing various controls of the system LSI 200. The image processing unit 202 performs image processing of still images and moving image data handled within the system LSI 200. The audio processing unit 203 performs audio processing of audio data handled within the system LSI 200. The network processing unit 204 transmits and receives data between the system LSI 200 and an external network. The ROM 210 stores the boot program executed when the CPU 201 starts up and various data, and is accessed via the ROMC 206. The DRAM 209 mainly stores control programs for processing by the CPU 201 and provides a workspace for when the CPU 201 executes various controls. In addition, it stores still images and moving image data handled by the image processing unit 202, audio data handled by the audio processing unit 203, and external communication data handled by the network processing unit 204. The DRAM 209 has eight banks 220 to 227 that constitute it. The bank numbers correspond to banks 220 through 227, with banks 0 through 7 corresponding to banks 220 through 227. The image processing unit 202, audio processing unit 203, and network processing unit 204 access their respective data via DMA (Dynamic Memory Access). Access to the DRAM 209 is performed by the memory controller 205 receiving an access request, converting it into a control command, which is then converted into an analog signal by the PHY 207 and issued externally. The specific access method is as described in the background information and will be omitted here. The same applies when the image processing unit 202, audio processing unit 203, and network processing unit 204 access the DRAM. The bus 208 interconnects the CPU 201, image processing unit 202, audio processing unit 203, and network processing unit 204, which issue access requests, with the memory controller 205 and ROMC 206, which receive these access requests. In this embodiment, the DRAM 209 is assumed to be an SDRAM compliant with the DDR3-SDRAM standard.A monitor 211 is connected to the control signal between the system LSI 200 and the DRAM 209, and has a function of monitoring the commands generated on the control signal during the execution of the simulation. The system LSI 200, DRAM 209, ROM 210, and monitor 211 are arranged in the test bench 212 and are connected by signals respectively.

[0015] Figure 3 is a configuration diagram of a computer device that performs performance analysis processing and analysis result display processing including the simulation processing of the test bench 212. In Figure 3, the CPU 301 is for executing various controls in the computer device. The ROM 302 is for storing a boot program and various data that are executed when the computer device is started up. The RAM 303 stores a control program for the CPU 301 to process and provides a working area when the CPU 301 executes various controls. The keyboard 304 and mouse 305 are for providing various input operation environments by the user. 306 is an HDD (hard disk) that stores various data.

[0016] 307 is a display that displays processing results and the like to the user. In this embodiment, in particular, the simulation results, waveforms, and performance analysis processing results are displayed. The network interface 308 enables communication with an external network via a LAN cable. The bus 309 is for connecting the above components. Note that the CPU, ROM, and bus also exist in the system LSI 200, but it is noted that these are separate entities.

[0017] The performance analysis process of this embodiment will now be described. The performance analysis process is performed on the computer device. Figure 1 is a conceptual diagram of the overall performance analysis process. In Figure 1, 101 is a detection means that detects events that cause state transitions in banks 220 to 227 that constitute the DRAM 209, which is the target of performance analysis. More specifically, the events are commands issued by the memory controller 205 in the system LSI 200 to control the DRAM 209. The event information 102 detected by the detection means is temporarily stored in the HDD 306 and input to the next bank state classification means 103. The bank state classification means 103 transitions the state of banks 220 to 227 based on the events that have occurred. This determines the state of banks 220 to 227 in chronological order. The bank state information 104 of banks 220 to 227 classified by the bank state classification means 103 is stored in the HDD 306 in the same way as the event information 102. The above is the overall flow of the performance analysis process of this embodiment. The following provides a detailed explanation of each element in the performance analysis process shown in Figure 1.

[0018] The detection means 101 is implemented by the monitor 211 in the simulation processing of the test bench 212 by the computer device. The simulation processing by the computer device is implemented by the CPU 301 using RAM 303 as a work area and executing simulation software stored in HDD 306. As described in the prior art, typical simulation software includes Incisive (registered trademark of Cadence), VCS (registered trademark of Synopsys), and Questasim (registered trademark of Mentor). These simulation software programs simulate the same operation as the system LSI 200 actually operates, and the results are stored in HDD 306. Specifically, these include simulation log files and waveform files output by the simulation software, and event information output by monitor 211.

[0019] The monitoring of signal lines between the system LSI 200 and DRAM 209 by the monitor 211, i.e., the detection means 101 of this embodiment, will now be described. The monitor 211 monitors the signal lines between the system LSI 200 and DRAM 209 during the simulation process. Specifically, these are the signal lines that constitute the DDR3-SDRAM interface shown in Figure 4. 401 is the clock and serves as the reference for all signals. That is, at the rising edge timing of the clock 401 (change from 0 to 1), the state of signals other than the clock 401 is evaluated and it is detected which command is being issued. Specifically, the command is detected based on the table shown in Figure 5. In Figure 5, 503 to 513 indicate the values ​​of the signal lines shown in Figure 4. 504 to 513 indicate the state of each signal at a predetermined rising edge timing of the clock 401, but it is important to note that only 503 indicates the state at the rising edge timing of the clock 401 one timing prior to that timing. In Figure 5, L means Low=0 and H means High=1. X is Don't Care and can be either 0 or 1. RFU stands for Reserved for Future Use and, like X, can be any value. V is Valid, meaning that the corresponding signal has the desired meaning for the target command. The specific meaning is omitted as it is not relevant to the explanation of this invention. BA, RA, and CA mean bank address, row address, and column address, respectively, and when a command is detected by a signal other than these, it is determined to be an address. 501 and 502 indicate the meaning and command notation of the corresponding command when the signals 503 to 513 match that state. The detection means will be explained using the ACT command as an example. Based on 503, it is determined whether the CKE signal is H at the rising edge timing of the previous clock 401. Next, based on 504, it is determined whether the CKE signal is H at the rising edge timing of the current clock 401. Similarly, it is determined that CS=L, RAS=L, CAS=H, and WE=H, and the ACT command is detected when all of these conditions are met. In this case, the BA signal means bank address, and the A signal means RA, i.e., column address.Commands other than ACT are also determined based on the values ​​of the signal lines according to the table in Figure 5, and the issued commands are detected. The special command NOP command 540 will be explained further. The NOP command 540 is detected when CKE=H→H (meaning the rising edge of the previous clock was H and the rising edge of the current clock is H), CS=L, and RAS / CAS / WE are all H. The NOP command 540 is an abbreviation for No Operation and means that no command has been generated. In this embodiment, NOP commands are excluded from detection, and other commands are the target of detection. This concludes the explanation of the detection means 101. In this embodiment, the detection means was explained using the detection of commands based on the DDR3-SDRAM standard as an example, but it is not limited to the type of standard. That is, even with other DDR2, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4, and LPDDR5, commands are similarly defined based on the values ​​of the signal lines, so the detection means can be implemented as events. Furthermore, the events detected by the detection means are not limited to commands. The detection method involves monitoring the signal line between the system LSI 200 and the DRAM 209 to detect events. Regardless of whether the value of the monitored signal is defined in the standard, any change in the signal line can be defined as an event.

[0020] The monitor 211, which implements the detection means 101, outputs the commands detected during the simulation period as log information, which becomes the event information 102. Figure 6 shows an example of the contents of the event information 102 output by the monitor 211. In Figure 6, 601 is the occurrence time, which is the elapsed time in the simulation. In this embodiment, the unit is ps (picosecond = 0.000000000001 seconds). 602 is the command, which indicates the command detected by the detection means. 603, 604, and 605 are the bank address, row address, and column address, respectively, and are indicated by the BA and A signals when each command is detected. Depending on the command, the bank address, row address, and column address may or may not be indicated, and are therefore displayed in the event information 102 accordingly.

[0021] Before describing the processing details of the bank state classification means 103 itself, we will first explain the types of bank states of banks 220 to 227 that are classified by the bank state classification means 103. In this embodiment, the following three bank states are defined. State 1: Operating state State 2: Hibernation State 3: Unable to operate

[0022] The operating state is the state in which read or write data access is being performed to the target bank. According to the DDR3-SDRAM standard, there are 4-beat access, which accesses data four times consecutively, and 8-beat access, which accesses data eight times consecutively. Since consecutive accesses are performed once on the rising and falling edges of the clock, 4-beat access consumes 2 clock cycles, and 8-beat access consumes 4 clock cycles. In this embodiment, it is assumed that only 8-beat accesses are issued, and 4 clock cycles are set as the operating state for each RD or WR command. Here, the interval for setting the 4-clock cycle operating state, that is, the start timing and end timing for setting the operating state, will be explained. First, when a transfer command is detected for the first time, the timing at which the command is detected is set as the start timing of the operating state for the target command. The end timing is the start timing plus 4 clock cycles. The interval between this start and end timing is classified as the operating state. Subsequently, when a new transfer command (hereinafter referred to as the current command) is detected, it is determined whether the end timing of the operating state for the previously detected transfer command (hereinafter referred to as the preceding command) is before or after the detection timing of the current command. In the former case, the detection timing of the current command is set as the start timing of the operational state for the current command, and the end timing is set by adding 4 clock cycles to the start timing. If the end timing of the operational state for the preceding command is later than the detection timing of the current command, setting the detection timing of the current command as the start timing of the operational state would result in an overlap in the operational state intervals of the preceding command and the current command. Therefore, in such cases, the end timing of the operational state for the preceding command is set as the start timing of the operational state for the current command, and the end timing is similarly set by adding 4 clock cycles to the start timing. This prevents the operational state intervals of the preceding command and the current command from overlapping.A key feature of this proposal is that, each time a transfer command is detected, the start and end timings of the operational state for that command are recorded, allowing for classification so that the operational state intervals do not overlap. A detailed explanation of this feature will follow later.

[0023] An unoperable state is a state in which data access to a bank cannot be performed due to predetermined constraints and the system is waiting. For example, in the DDR3-SDRAM standard, no commands can be issued for a period of time defined by the tREF parameter after the issuance of a REF (refresh) command. As explained in the prior art, this is a constraint that inevitably occurs with refresh operations and applies regardless of the type of DRAM. In this embodiment, the period of the tREF parameter after the issuance of a REF command is defined as one of the unoperable states. The tREF parameter in this case is assumed to be 500 clock cycles. However, it is also possible to define an unoperable state only when the REF command is made to wait for the issuance of an RD or WR command. That is, an unoperable state is defined only when an ACT command is issued immediately after the tREF parameter period following the issuance of a REF command. In this embodiment, an unoperable state is defined regardless of the presence or absence of an ACT command, but it goes without saying that the present invention can also be applied when an unoperable state is defined only when an ACT command occurs. Furthermore, in the DDR3-SDRAM standard, a period of time defined by the tRCD parameter must be left between the issuance of an ACT command and the issuance of an RD or WR command. Similarly, it is assumed that there are constraints between the ACT, PRE, RD, and WR commands that commonly occur during normal data access, as defined in the table in Figure 8. The DDR3-SDRAM standard has many other commands, as shown in Figure 5, and there are also constraints between these commands. However, in this embodiment, it is assumed that only the constraints shown in the table in Figure 8 exist, and if there is a gap of a certain number of clock cycles between each command, this period is defined as one of the periods during which operation is impossible. However, this premise does not limit the scope of application of the present invention; it goes without saying that even if there are constraints other than those between the commands shown in Figure 8, the present invention can be applied if those constraints are defined as a certain period after the issuance of a predetermined command, and a certain period between predetermined commands. Furthermore, although not shown in Figure 8, even if there are constraints defined by a predetermined sequence of three or more commands, the present invention can be applied as long as these constraints can be determined by conditional branching.For example, if the PRE, ACT, and RD commands occur in sequence, the period from the PRE command to the RD command can be determined as a constraint period due to a page miss. Similarly, if the REF, ACT, and WR commands occur in sequence, the period from the REF command to the WR command can be determined as a constraint period due to refresh and page open. However, when two predetermined commands occur consecutively, the subsequent command may be issued beyond the constraint period shown in Figure 8. For example, when an RD command is issued after an ACT command, a clock cycle interval equal to the constraint period shown in Figure 8 is required, but in this case, the command is issued after more clock cycles than the constraint period. In this case, the RD command is not considered to have been delayed due to a constraint, but rather not issued because there was no subsequent access request, and in this embodiment, it is not considered an inoperable state. However, similar to the REF (refresh) command described above, it is also possible to define the period after the ACT command is issued as an inoperable state, regardless of whether an RD or WR command is issued or not. In any case, the present invention can be applied if the conditional branch can be clearly defined. The above defines the non-operational state, but how to define the non-operational state for a certain period after any command, between any two commands, or in any command sequence three positions above is not a prerequisite for the present invention. If the non-operational state can be defined by the number of cycles (or a numerical constraint that can be converted to that) based on the occurrence of an event detected by the detection means, it goes without saying that the present invention can be applied regardless of the content of that definition. Furthermore, in this embodiment, the period during which commands cannot be issued for a certain period after a REF command was defined by the tREF parameter, but the memory controller 205 can control the period during which commands are not issued after a REF command regardless of the tREF parameter. For example, setting it to less than the tREF parameter is a violation of the standard and therefore cannot be done, but it is possible to control it to leave a gap of clock cycles equal to or greater than the tREF parameter. In this case, it is also possible to define the non-operational state based on the number of cycles set in the memory controller 205.

[0024] Finally, let's explain the dormant state. The dormant state is defined as a state that is neither the operating state nor the inoperable state described above. In this embodiment, the operating state and inoperable state were defined first, followed by the dormant state, but this correlation can be reversed. That is, the operating state and dormant state can be defined first, and everything else can be defined as the inoperable state.

[0025] The bank state classification means 103 will now be explained using Figure 7. The bank state classification means 103 takes event information 102 as input and is executed on the computer device as a separate process after the simulation process. The bank state classification means 103 may determine an inoperable state by checking the number of clock cycles between two events. Therefore, instead of determining the state after an event occurs, the mechanism determines the state from the previous event to the current event when an event occurs. Figure 7 is a flowchart for classifying the states of banks 220 to 227. However, this flowchart is executed independently for each bank. That is, the process shown in the flowchart of Figure 7 is executed on the computer device for eight times, corresponding to the number of banks. Since the flowchart can be used for any bank, the bank number is received in the argument input of step 701, thereby identifying the target bank. In Figure 7, the bank number is received as an argument in step 701. In steps 702 and 703, the variables used in this process are initialized. In step 702, the state confirmation time (FIX_TIME) is reset. Specifically, FIX_TIME is set to 0. The usage of the state confirmation time FIX_TIME will be explained later, but this value means that the state of the bank has been determined up to that time. In step 703, the occurrence time and type of the current event information entry and the occurrence time and type of the previous command are reset. Specifically, regardless of the bank number in the argument, CURE_TIME, which indicates the occurrence time of the currently detected command, is set to 0, and CURE_CMD, which indicates the same type, is set to UNDEF, meaning undefined. In addition, SAME_PRE_TIME, which indicates the occurrence time of the previous command for the bank indicated by the bank number in the argument, is set to 0, and SAME_PRE_CMD, which indicates the same type, is set to UNDEF, meaning undefined. Furthermore, DIFF_PRE_TIME, which indicates the occurrence time of the previous command for banks other than the bank number in the argument, is set to 0, and DIFF_PRE_CMD, which indicates the same type, is set to UNDEF, meaning undefined.Next, in step 704, SAME_TRAN_START_TIME, which indicates the start timing for classifying the next operating state for the bank indicated by the argument bank number, is reset to 0. Furthermore, regardless of the argument bank number, TRAN_END_TIME, which indicates how far the operating state will be set by the commands detected so far, is reset to 0. As mentioned above, this flowchart is executed independently for each bank, so the start timing for setting the next operating state is updated independently for each target bank, and only the information for the target bank needs to be retained. On the other hand, regardless of the bank, the information on how far the operating state will be classified by the commands detected so far is necessary to determine the start timing for classifying the target bank's operating state next, so it is updated in the same way regardless of the bank. Next, in step 705, one event information entry is read from the input event information 102. This corresponds to one line in the example of event information 102 in Figure 6. From here, steps 706 to 736 classify the bank state. As mentioned above, the bank states to be classified are the three states: operating state, inoperable state, and dormant state. First, in step 706, CURE_TIME is updated based on the occurrence time of the current event information entry, and CURE_CMD is updated based on the command of the current event information entry. Next, in step 707, it is determined whether the bank address 603 of the current event information entry matches the bank number in the argument. If they do not match, no state transition occurs for the target bank in the current event information entry. Therefore, the process proceeds to step 732. In step 732, it is determined whether CURE_CMD is a transfer command. If CURE_CMD is a transfer command, in step 733, TRAN_END_TIME is updated to the time obtained by adding 4 clock cycles to the larger of CUR_TIME or TRAN_END_TIME. The process in step 733 is to update TRAN_END_TIME at the end of the interval for classifying the operational state for a transfer command to a bank other than the target bank when such a command is detected. 4 clock cycles is the time it takes to transfer data.Here, if CUR_TIME is greater than or equal to TRAN_END_TIME, it means that the end time of the operational state interval for a previously issued transfer command is before the time the current transfer command was detected. On the other hand, if TRAN_END_TIME is greater than CUR_TIME, it means that the end time of the operational state interval for a previously issued transfer command is after the time the transfer command for the current event information entry was generated. Therefore, by adding 4 clock cycles to TRAN_END_TIME instead of CUR_TIME, the operational state intervals do not overlap. In this way, when the end time of the operational state interval for a previously issued transfer command is after the time the transfer command for the current event information entry was generated, we will refer to this as an overlap between the operational state interval and the command interval. Next, in step 734, DIFF_PRE_CMD and DIFF_PRE_TIME are updated based on the command 602 and generation time 601 of the current event information entry. That is, DIFF_PRE_CMD is set to the command 602 of the current event information entry, and DIFF_PRE_TIME is set to the generation time 601 of the current event information entry. On the other hand, if the bank address 603 of the current event information entry matches the bank number in the argument, the process proceeds to step 708. In step 708, it is determined whether the previous command for the target bank, i.e., SAME_PRE_CMD, is an RD command or a WR command. If this is the first time the determination is made at the branch in step 708, SAME_PRE_CMD is set to UNDEF, so it will always be determined to be No. If SAME_PRE_CMD was a transfer command, in step 709 it is determined whether SAME_TRANS_START_TIME is greater than FIX_TIME. The meaning of this step is explained below. If SAME_TRANS_START_TIME is greater than FIX_TIME, it indicates that the state of the interval between FIX_TIME and SAME_TRANS_START_TIME is still undefined.This situation occurs when, in a preceding process, a transfer command from a bank other than the target bank causes an overlap between the operational state interval and the command interval, and SAME_TRANS_START_TIME is set to a time later than FIX_TIME. Since this flowchart is executed independently for each bank, FIX_TIME is not updated by transfer commands from banks other than the target bank. Therefore, the interval between FIX_TIME and SAME_TRANS_START_TIME where the state is still undefined is the interval classified as the operational state of a bank other than the target bank. On the other hand, if a transfer command from the target bank causes an overlap between the operational state interval and the command interval, SAME_TRANS_START_TIME and FIX_TIME become the same. As mentioned above, in order to determine the state of the interval where the state is still undefined, the process proceeds to step 710 only if it is determined in step 709 that SAME_TRANS_START_TIME is greater than FIX_TIME. In step 710, the bank state is classified into a paused state by the difference between SAME_TRANS_START_TIME and FIX_TIME, and in the next step 711, the amount classified into a paused state is added to FIX_TIME, updating the time when the state was determined. Here, the difference between SAME_TRANS_START_TIME and FIX_TIME is classified as a dormant state. However, this interval is an interval in which banks other than the target bank are operational, and can also be considered an inoperable state for the target bank. In that case, it should be classified as an inoperable state in step 710. The result of the classification in step 710 is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and the occurrence cycle, which is the difference between SAME_TRANS_START_TIME and FIX_TIME. Next, in step 709, the processing merges depending on whether SAME_TRANS_START_TIME is determined to be greater than FIX_TIME or not, and in step 712, the period of 4 clock cycles from FIX_TIME is classified as an operational state. The result of the classification is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and the occurrence cycle of 4 cycles.Then, in step 713, 4 clock cycles are added to FIX_TIME to update the time when the state was determined. On the other hand, if it is determined to be No in step 708, in step 714 it is determined whether the previous command for the target bank, i.e., SAME_PRE_CMD, is a REF command. When the determination is made at the branch in step 714 for the first time, SAME_PRE_CMD is set to UNDEF, so it will always be determined to be No. If SAME_PRE_CMD is a REF command, in step 715 it is classified as an inoperable state for 500 clock cycles from FIX_TIME. The result of the classification is output as bank state information 104, along with the time of occurrence (FIX_TIME at this time) and the occurrence cycle of 500 cycles. Then, in step 716 it is added to FIX_TIME by 500 clock cycles to update the time when the state was determined. If steps 713 and 716 have been processed, or if it is determined to be No in step 714, proceed to step 717. In step 717, the previous command for the target bank, i.e., SAME_PRE_CMD, and the command 602 of the current event information entry are used to determine if they match the cycle set in the conditions that match the table in Figure 8. For example, if the command 602 of the current event information entry is an ACT command and SAME_PRE_CMD is a PRE command, then according to the table in Figure 8, 40 cycles are set. In this case, it is determined whether the period from the occurrence time of the previous PRE command, SAME_PRE_TIME, to the occurrence time of the target ACT command, i.e., the occurrence time of the current event information entry, 601, matches 40 cycles. The same determination is made for other commands based on the table in Figure 8. If the number of clock cycles is not set in the table in Figure 8, it means there is no constraint, so it is determined as No. If the result of the determination is Yes, in step 715, the period from FIX_TIME to the occurrence time of the current event information entry, 601, is classified as an inoperable state. The classification result is output as bank status information 104 along with the occurrence time (FIX_TIME at this time) and occurrence cycle.It is important to note that this is not the period from SAME_PRE_TIME, which is the time of the previous command for the target bank, to the time of the current event information entry, 601. The reason for this will be explained using the example where the command 602 of the current event information entry is a PRE command and SAME_PRE_CMD is an RD command. In this example, 15 cycles are set based on the table in Figure 8. Therefore, we determine whether the period from SAME_PRE_TIME, which is the time of the RD command, to the time of the current PRE command, 601, is 15 cycles. In this case, FIX_TIME and SAME_PRE_TIME do not match. This is because, since SAME_PRE_CMD is an RD command, FIX_TIME may have already had cycles added in step 714, depending on the determinations in steps 710 and 709. Therefore, if we classify the 15 cycles from SAME_PRE_TIME to the current event information entry occurrence time 601 as an inoperable state, we will double-classify the amount that FIX_TIME has advanced. To avoid this, we classify the cycles remaining after subtracting the amount that FIX_TIME has advanced as an inoperable state. Here, assuming that FIX_TIME was increased by 4 cycles only in step 710, we classify 11 clock cycles (15 minus 4) as an inoperable state. Also, at this point, FIX_TIME may have advanced beyond the current event information entry occurrence time 601. For example, let's consider the case where the command 602 in the current event information entry is an RD command and SAME_PRE_CMD is a WR command. In this example, based on the table in Figure 8, 2 cycles are set. Therefore, we determine whether the period from SAME_PRE_TIME, the occurrence time of the WR command, to the current RD command occurrence time 601 is 2 cycles. However, if the start timing of the operational state interval for a WR command that is SAME_PRE_CMD is the timing of the WR command detection, then if 4 cycles are set as the operational state interval, FIX_TIME will be in the future compared to the time the current RD command occurred. In such cases, the system is not set to an inoperable state in step 718. After classifying the system as inoperable in step 715, in the following step 716, FIX_TIME is increased by the number of cycles for which the bank state was determined in step 715, and the time for which the state was determined is updated. On the other hand, if no constraints are set in the table in Figure 8 in step 717, or if the set constraints do not match the period from SAME_PRE_TIME to the occurrence time 601 of the current event information entry, the system proceeds to step 720. From step 720 onwards, constraints from the previous command for banks other than the target bank are checked, similar to how constraints from the previous command for the target bank were checked from step 717 to step 719. Before checking the constraints, it is checked that the occurrence time of the previous command for banks other than the target bank, i.e., DIFF_PRE_TIME, is not later than FIX_TIME.In this flowchart, only when the command 602 of the current event information entry branches at step 707 and is for the target bank, the state transition of the bank is checked and the state of the bank is classified. As a result, for SAME_PRE_TIME which is the occurrence time of the command for the target bank, FIX_TIME>=SAME_PRE_TIME always holds. However, when the command 602 of the current event information entry is the previous command for a bank other than the target bank, it branches at step 707 and no state transition occurs. As a result, FIX_TIME<DIFF_PRE_TIME can occur. When the condition (FIX_TIME<DIFF_PRE_TIME) holds, before analyzing the constraints from the previous command for a bank other than the target bank, it is necessary to set the period until that command to a pause state. At step 721, the period from FIX_TIME to the occurrence time of the previous command for a bank other than the target bank, that is, DIFF_PRE_TIME, is classified as a pause state. The classified result is output as bank state information 104 together with the occurrence time (FIX_TIME at this time) and the occurrence cycle. Subsequently, at step 722, the difference from FIX_TIME to DIFF_PRE_TIME is added to advance the time when the state is determined. Now, when FIX_TIME<DIFF_PRE_TIME does not hold at step 720, and after processing step 722, it proceeds to step 723. At step 723, it is determined whether it matches the cycle set for the condition that matches the table in FIG. 8, using the previous command for a bank other than the target bank, that is, DIFF_PRE_CMD, and the command 602 of the current event information entry. For example, when the command 602 of the current event information entry is a WR command and DIFF_PRE_CMD is an RD command, based on the table in FIG. 8, 6 cycles are set. In this case, it is determined whether the period from DIFF_PRE_TIME which is the occurrence time of the RD command to the occurrence time of the target WR command, that is, the occurrence time 601 of the current event information entry, matches 6 cycles. Other commands are also determined based on the table in FIG. 8 in the same way.If no clock cycle count is set in the table in Figure 8, it means there is no constraint, and the result is determined to be No. If the result of the determination is Yes, in step 724, the period from FIX_TIME to the occurrence time of the current event information entry 601 is classified as an inoperable state. The classification result is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and occurrence cycle. It is important to note that this is not the period from DIFF_PRE_TIME, which is the occurrence time of the previous command for a bank other than the target bank, to the occurrence time of the current event information entry 601. The reason for this is the same as explained in step 715. After classifying the state as inoperable in step 724, in the following step 725, the difference from the occurrence time of the current event information entry 601 is added to FIX_TIME, and the time when the state was determined is updated. On the other hand, if no constraint is set in the table in Figure 8 in step 723, or if the set constraint does not match the period from DIFF_PRE_TIME to the occurrence time of the current event information entry 601, the process proceeds to step 726. In step 726, the period from FIX_TIME to the current event information entry's occurrence time 601 is classified as a dormant state. The classification result, along with the occurrence time (FIX_TIME at this time) and occurrence cycle, is output as bank status information 104. In the following step 727, the difference from the current event information entry's occurrence time 601 is added to FIX_TIME, updating the time when the state was determined.

[0026] Now, if steps 719, 725, or 727 have been processed, proceed to step 728. In step 728, determine whether the command in the current event information entry, i.e., CUR_CMD, is a transfer command. If it is a transfer command, proceed to step 729. In step 729, update SAME_TRAN_START_TIME, which indicates where the start timing should be when classifying the operational state interval for a transfer command that is CUR_CMD. As already explained, the actual classification of the operational state interval for a transfer command that is CUR_CMD is done after reading the next command for the target bank from the event information entry. At that time, update SAME_TRAN_START_TIME so that it is clear where the start timing of the interval to be classified into operational state should be. Specifically, update SAME_TRAN_START_TIME to the larger of CUR_TIME or TRAN_END_TIME. Here, if there is an overlap between the operational state interval and the command interval due to a transfer command issued earlier, TRAN_END_TIME will indicate a later time than CURE_TIME. Therefore, by updating the time of TRAN_END_TIME to SAME_TRAN_START_TIME, the system prevents the operating state from overlapping due to the overlap of the operating state section and the command section. On the other hand, if there is no overlap between the operating state section and the command section, the time of CUR_TIME is updated to SAME_TRAN_START_TIME. Next, in step 730, TRAN_END_TIME is updated. Here, the time required for data transfer (4 clock cycles) is simply added to SAME_TRAN_START_TIME set in step 729. After the processing of step 730 is completed, and if it is determined in step 728 that CUR_CMD is not a transfer command, the system proceeds to step 731. In step 731, SAME_PRE_CMD and SAME_PRE_TIME are updated based on the command 602 and occurrence time 601 of the current event information entry. That is, SAME_PRE_CMD is set to the command 602 of the current event information entry, and SAME_PRE_TIME is set to the occurrence time 601 of the current event information entry.Finally, in step 735, it is determined whether there is a next event information entry in the input event information 102. If there is, the process returns to step 705 and is repeated. On the other hand, if there is no event information entry, the process is terminated. The above describes the contents of the bank state classification means 103 in this embodiment. In this embodiment, the explanation was given on the premise that no multiple constraints occur simultaneously between commands. However, in reality, it is possible that a command indicated by the event information entry to be processed may be simultaneously constrained by multiple commands issued before it. For example, suppose an ACT command, an RD command, and a PRE command are issued in order. In this case, when processing the last PRE command, there is a constraint defined by the tRAS parameter between the ACT commands. Similarly, there is another constraint between the RD command and the ACT command. In most cases, the timing of the PRE command is determined by one of the constraints, but in some cases, constraints may be applied simultaneously. In any case, the bank state classification means 103 in this embodiment only retains information about the one command issued immediately before as history (SAME_PRE_TIME and SAME_PRE_CMD). Therefore, in the above example, it is not possible to determine the constraint from the ACT command. However, this premise does not limit the present invention in any way. That is, the above example can be addressed by having at least two histories and determining each constraint in step 717. In addition, by listing the constraints that may arise due to the specifications of the SDRAM being analyzed and the constraints of the memory controller 205, and modifying the system to retain enough history to address all of them, there will be no constraints that cannot be addressed.

[0027] The following describes the processing of the bank state classification means 103 in detail, using the example of using event information entries 610 to 617 in Figure 6 as the actual input for bank 220, i.e., bank number 0. In this example, we assume that 1 clock cycle = 1000 ps. Figure 9 shows the processing results when event information entries 610 to 617 are the actual inputs. 901 represents the passage of time in clock cycles. 902 represents the command detection time for bank 0, and 903 represents the command detection time for bank 1. 904 represents the state change of bank 0. 905 to 913 show the changes in the values ​​of each variable in chronological order when bank 0 is received as an argument in the flow of Figure 7. For convenience, the variables that store time are displayed after converting the time to clock cycles. The processing of event information entries 610 to 638 will be described below with reference to the processing results in Figure 9.

[0028] First, before entering the event information entry, bank number 0 is entered in step 701. In step 702, FIX_TIME is reset to 0. Next, in step 703, CURE_TIME=0, CURE_CMD=UNDEF, SAME_PRE_TIME=0, SAME_PRE_CMD=UNDEF, DIFF_PRE_TIME=0, DIFF_PRE_CMD=UNDEF. Next, in step 704, SAME_TRAN_START_TIME=0, TRAN_END_TIME=0. In steps 702 to 704, each variable is reset as shown in Figures 920 to 928.

[0029] Next, in step 705, event information entry 610 is read. Then, in step 706, CURE_TIME and CURE_CMD are updated with the read event information entry 610. CURE_TIME is set to 2000, which is the time 610 occurred, and CURE_CMD is updated with the command ACT of 610. Here, the bank address 603 of the event information entry is 0, which matches the bank number in the argument. Therefore, in step 707, it is determined to be Yes. At this point, SAME_PRE_CMD is UNDEF, so in steps 708, 714, and 717, it is determined to be No. Furthermore, at this point, FIX_TIME=0, DIFF_PRE_TIME=0, and DIFF_PRE_CMD=UNDEF, so in steps 720 and 723, it is determined to be No. As a result, in step 726, the two clock cycles from FIX_TIME=0 to the current event information entry 610's occurrence time of 2000 are classified as a hibernation state. Next, in step 727, FIX_TIME is set to 2000. In Figure 9, this confirms that 980 has entered a two-cycle pause state. Then, in step 728, since CUR_CMD is ACT, the process proceeds to step 731. After that, in step 731, SAME_PRE_CMD=ACT and SAME_PRE_TIME=2000 are set, and the process returns to step 705 via step 735. As a result of the processing from reading event information entry 610 up to this point, each variable is updated as shown in 929 to 933.

[0030] Next, event information entry 611 is read and its processing begins. The bank address 603 of event information entry 611 is 1, which does not match the bank number in the argument. Therefore, it is determined to be No in step 707. Next, in step 732, CUR_CMD is ACT, so it is determined to be No. In this case, in step 734, DIFF_PRE_CMD=ACT and DIFF_PRE_TIME=6000 are set, and the process returns to step 705 via step 735. Through the processing from reading event information entry 611 up to this point, each variable is updated as shown in 934 to 937.

[0031] Next, in the processing of event information entry 612, step 706 first updates CUR_TIME=32000 and CUR_CMD=WR. The bank address 603 of event information entry 612 is 0, which matches the bank number in the argument. Therefore, step 707 determines it as Yes. At this point, SAME_PRE_CMD is the ACT command, so steps 708 and 714 both determine it as No. In step 717, in the table in Figure 8, SAME_PRE_CMD=ACT command, and the command 602 of the current event information entry 612 is the WR command, so 30 cycles are applicable. On the other hand, the occurrence time 601 of the current event information entry 612 is 32000, so the period from SAME_PRE_TIME is 32000-2000=30000, which is 30 clock cycles. Since the results match, the determination in step 717 is Yes, and in step 718, the 30 clock cycles from FIX_TIME=2000 to 32000, the occurrence time 601 of the current event information entry 612, are classified as an inoperable state. Next, in step 719, FIX_TIME is set to 32000. In Figure 9, the inoperable state of 981 and 30 cycles are confirmed. Next, in step 728, CUR_CMD is WR, so it is determined to be Yes. Next, in step 729, the current TRAN_END_TIME is 0 and CUR_TIME is 32000, and since CUR_TIME is larger, SAME_TRAN_START_TIME is updated to 32000. This means that the next time a command for the target bank is read in the event information entry, the start timing of the operational state interval for the WR command in the current event information entry 612 will be 32000. Next, in step 730, TRAN_END_TIME is updated to 36000, which is SAME_TRAN_START_TIME plus 4 cycles, or 4000. Then, in step 731, SAME_PRE_CMD=WR and SAME_PRE_TIME=32000 are set, and the process returns to step 705 via step 735. As a result of the processing from reading event information entry 612 up to this point, each variable is updated as shown in 938 to 944.

[0032] In processing event information entry 613, first in step 706, CUR_TIME=34000 and CUR_CMD=RD are updated. The bank address 603 of event information entry 613 is 0, which matches the bank number in the argument. Therefore, in step 707, it is determined to be Yes. At this point, the command is SAME_PRE_CMD=WR, so in step 708, it is determined to be Yes. Next, in step 709, both SAME_TARN_START_TIME and FIX_TIME are 32000, so it is determined to be Yes.

[0033] Accordingly, in step 712, the period from FIX_TIME 32000 to the occurrence time of the current event information entry 613 is classified as an operational state for 4 clock cycles. Next, in step 713, FIX_TIME is set to 36000. In Figure 9, the operational state of 982 and 4 cycles are determined. In step 717, in the table in Figure 8, SAME_PRE_CMD=WR command, and the command 602 of the current event information entry 612 is an RD command, so 2 cycles are applicable. On the other hand, the occurrence time 601 of the current event information entry 612 is 34000, so the period from SAME_PRE_TIME is 34000-32000=2000, which is 2 clock cycles. The results match, so the determination in step 717 is Yes. Next, in step 718, an attempt is made to classify the period from FIX_TIME to the occurrence time of the current event information entry 613 as an inoperable state. However, since FIX_TIME (=36000) is greater than the occurrence time of the current event information entry 613, 34000, no classification is performed. In the following step 719, FIX_TIME is not added. Next, in step 728, CUR_CMD is determined to be Yes because it is RD. Next, in step 729, the current TRAN_END_TIME is 36000 and CUR_TIME is 34000, so TRAN_END_TIME is larger. Therefore, SAME_TRAN_START_TIME is updated to 36000. This means that when the next command for the target bank is read in the event information entry, the start timing for classifying the operational status for the RD command in the current event information entry 613 is 36000. Next, in step 730, TRAN_END_TIME is updated to 40000 by adding 4 cycles, i.e., 4000, to SAME_TRAN_START_TIME. After that, in step 731, SAME_PRE_CMD=RD and SAME_PRE_TIME=34000 are set, and the process returns to step 705 via step 735. After reading event information entry 613 and processing up to this point, each variable is updated as shown in 945 through 951.

[0034] In processing event information entry 614, first in step 706, CUR_TIME=4000 and CUR_CMD=WR are updated. The bank address 603 of event information entry 613 is 1, which does not match the bank number in the argument. Therefore, in step 707, it is determined to be No. Next, in step 732, since CUR_CMD is WR, it is determined to be Yes. Next, in step 733, since CUR_TIME is 40000 and TRAN_END_TIME is 40000, TRAN_END_TIME is updated from 40000 to 44000 by adding 4 clock cycles, i.e., 4000. Next, in step 734, DIFF_PRE_CMD=WR and DIFF_PRE_TIME=4000 are set, and the process returns to step 705 via step 735. Through the processing from reading event information entry 614 up to this point, each variable is updated as shown in 952 to 956.

[0035] In processing event information entry 615, first in step 706, CUR_TIME=42000 and CUR_CMD=RD are updated. The bank address 603 of event information entry 615 is 0, which matches the bank number in the argument. Therefore, in step 707, it is determined to be Yes. At this point, the command is SAME_PRE_CMD=RD, so in step 708, it is determined to be Yes. Next, in step 709, both SAME_TARN_START_TIME and FIX_TIME are 36000, so it is determined to be Yes.

[0036] Accordingly, in step 712, the operating state is classified as 4 clock cycles from FIX_TIME 36000. Next, in step 713, FIX_TIME is set to 40000. In Figure 9, the operating state of 983, 4 cycles, is determined. In step 717, in the table in Figure 8, SAME_PRE_CMD=RD command, and command 602 of the current event information entry 615 is an RD command, so there are no applicable constraints and it is determined to be No. Next, in step 720, FIX_TIME=40000 and DIFF_PRE_TIME=40000, so it is determined to be No. In step 723, in the table in Figure 8, DIFF_PRE_CMD=WR command, and command 602 of the current event information entry 615 is an RD command, so 2 cycles are applicable. On the other hand, the occurrence time 601 of the current event information entry 615 is 42000, so the period from DIFF_PRE_TIME is 42000-40000=2000, which is 2 clock cycles. Since the results match, the determination in step 723 is Yes. Next, in step 724, the period from FIX_TIME=40000 to the occurrence time 601 of the current event information entry 615 at 42000 is classified as an inoperable state. Subsequently, in step 725, FIX_TIME is set to 42000. In Figure 9, the inoperable state of 984 and 2 cycles are confirmed. Next, in step 728, CUR_CMD is RD, so it is determined to be Yes. Next, in step 729, the current TRAN_END_TIME is 44000 and CUR_TIME is 42000, and TRAN_END_TIME is larger, so SAME_TRAN_START_TIME is updated to 44000. This means that the next time a command for the target bank is read in the event information entry, the start time for classifying the operational status for the RD command in the current event information entry 615 is 44000. Next, step 730 updates TRAN_END_TIME to 48000, which is SAME_TRAN_START_TIME plus 4 cycles, or 4000.Then, in step 731, SAME_PRE_CMD=RD and SAME_PRE_TIME=42000 are set, and the process returns to step 705 via step 735. As a result of the processing from reading event information entry 615 up to this point, each variable is updated as shown in 957 to 963.

[0037] In processing event information entry 616, first in step 706, CUR_TIME=57000 and CUR_CMD=PRE are updated. The bank address 603 of event information entry 616 is 0, which matches the bank number in the argument. Therefore, in step 707, it is determined to be Yes. At this point, the command is SAME_PRE_CMD=RD, so in step 708, it is determined to be Yes. Next, in step 709, SAME_TARN_START_TIME is 44000 and FIX_TIME is 42000, so it is determined to be No. Therefore, in the next steps 710 and 711, it is necessary to determine the state between SAME_TARN_START_TIME and FIX_TIME. In step 710, the difference between SAME_TARN_START_TIME and FIX_TIME is 2000, so 2 cycles from FIX_TIME are classified as a pause state. Subsequently, in step 711, FIX_TIME is set to 44000. In Figure 9, the pause state of 985, 2 cycles, is confirmed. Next, in step 712, the period from FIX_TIME=44000 to 4 clock cycles is classified as an operational state. Then, in step 713, FIX_TIME is set to 48000. In Figure 9, the operational state of 986 and 4 cycles are confirmed. In step 717, in the table in Figure 8, SAME_PRE_CMD=RD command, and the command 602 of the current event information entry 616 is a PRE command, so 15 cycles are applicable. On the other hand, the occurrence time 601 of the current event information entry 616 is 57000, so the period from SAME_PRE_TIME is 57000-42000=15000, which is 15 clock cycles. The results match, so the judgment in step 717 is Yes. Next, in step 718, the period from FIX_TIME=48000 to the occurrence time 601 of the current event information entry 612 at 57000 is classified as an inoperable state. Then, in step 719, FIX_TIME is set to 57000. In Figure 9, the inoperable state of 987 and 9 cycles are confirmed. Next, in step 728, CUR_CMD is determined to be No because it is PRE.Then, in step 731, SAME_PRE_CMD=PRE and SAME_PRE_TIME=57000 are set, and the process returns to step 705 via step 735. The processing from reading event information entry 616 up to this point updates each variable as shown in 964 through 970.

[0038] In processing event information entry 617, first in step 706, CUR_TIME=60000 and CUR_CMD=PRE are updated. The bank address 603 of event information entry 617 is 1, which does not match the bank number in the argument. Therefore, in step 707, it is determined to be No. Next, in step 732, CUR_CMD is PRE, so it is determined to be No. Next, in step 734, DIFF_PRE_CMD=PRE and DIFF_PRE_TIME=60000 are set. Then, the process returns to step 705 via step 735. Through the processing from reading event information entry 614 up to this point, each variable is updated as shown in 952 to 956. Furthermore, in step 735, there are no more event information entries, so the process ends.

[0039] The above describes the state classification process for bank 220 of bank number 0 by the bank state classification means 103. The processing for bank number 1 is carried out in the same way as described above. As a result, the state is determined as shown in Figure 9, from 990 to 993. For banks 222 to 227, since no control commands have been generated in the event information 102 in Figure 6, they are all considered to be in a dormant state.

[0040] The bank status classified in each step is output to the bank status information 104 along with the occurrence time (FIX_TIME) and the number of cycles. The bank status information 104 stores information for eight banks, 220 to 227, separately. The bank status information obtained in this way is statistically processed to make it easier to analyze, and then displayed to the user on the display 307. An example of processing is to extract the total period of operating state, non-operating state, and idle state for each unit of time in clock units and display it using a pie chart or bar graph, but the method of statistical processing does not limit the scope of application of the present invention.

[0041] As described above, even if the end time of the section classified as an operational state for a preceding transfer command is later than the detection timing of the subsequent transfer command, the operational state sections can be classified without overlap. Furthermore, the period for classifying the operational state can be made to be the same as the period during which data is actually transferred on the DRAM data signal line. Therefore, it is possible to accurately analyze how efficiently the DRAM is being accessed.

[0042] (Other embodiments) The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions. [Explanation of Symbols]

[0043] 101 Detection means 102 Event Information 103 Bank status classification means 104 Bank Status Information

Claims

1. A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that classifies the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected by the detection means, The classification means is characterized in that, when the detection means detects a first control command for a predetermined bank and a second control command following the first control command, it sets a second operating state interval for which the operating state is classified based on the second control command, based on a first operating state interval for which the operating state is classified based on the first control command.

2. The information processing apparatus according to claim 1, characterized in that, if the end timing of the first operating state interval is later than the detection timing of the second control command, the classification means sets the end timing of the first operating state interval or a time after the end timing of the first operating state interval as the start timing of the second operating state interval.

3. The information processing apparatus according to any one of claims 1 to 2, characterized in that the aforementioned operating state is a state in which read or write data access is being performed to the target bank.

4. The information processing device according to any one of claims 1 to 3, characterized in that the aforementioned inoperable state is a state in which the device is waiting because it cannot perform read or write data access to the bank due to predetermined constraints.

5. The information processing apparatus according to any one of claims 1 to 4, characterized in that the paused state is neither the operating state nor the non-operating state.

6. The information processing apparatus according to any one of claims 1 to 5, further comprising control means for displaying the results classified by the classification means on a display means.

7. The information processing apparatus according to any one of claims 1 to 6, characterized in that the first control command and the second control command are transfer commands.

8. A detection step in which the detection means detects an event that causes a transition in the state of at least one bank constituting the DRAM, The classification means includes a classification step of classifying the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected in the detection step, The information processing method is characterized in that, in the classification step, when a first control command for a predetermined bank and a second control command following the first control command are detected by the detection means, a second operating state interval is set based on a first operating state interval classified into an operating state based on the first control command, and a second operating state interval is set based on the second control command.

9. Computers, A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that classifies the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected by the detection means, A computer program for causing the classification means to function as an information processing device, characterized in that when a first control command for a predetermined bank and a second control command following the first control command are detected by the detection means, a second operating state interval is set based on a first operating state interval that is classified into an operating state based on the first control command, and the second operating state interval is set based on the second control command.

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