High-speed overcurrent detection in battery management systems

Abstract

To provide an improved overcurrent detection for BMS, a mitigation system, a method, and a technique.SOLUTION: A BMS monitor can detect an overcurrent using two different technologies. A first technique can detect an overcurrent on the basis of the average power over different, overlapping periods. A second technique can detect an overcurrent on the basis of determining a modeled junction temperature of a switching device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to safety technologies and mechanisms for a battery management system (BMS), such as overcurrent detection.

Background Art

[0002] As smart grid and electric vehicle (EV) technologies have evolved rapidly, rechargeable batteries have emerged as large-scale energy storage devices. A BMS monitors a rechargeable battery and provides related data, such as the battery's charge level, to a control system. The BMS can have various applications, from grid energy storage to other consumer products such as electric vehicles, electric bicycles, and electric scooters.

[0003] Rechargeable batteries are inherently electrochemical and can exhibit various undesirable operating characteristics, such as outgassing, electrolyte leakage, or thermal problems such as overheating or heat dissipation reactions with oxygen. One such undesirable condition is an overcurrent state where a current larger than intended is supplied or sunk by individual cells or a battery cell stack. Overcurrent can even lead to overheating and thermal runaway.

[0004] When the battery malfunctions, a switching mechanism, such as a mechanical relay, can be provided to selectively connect and disconnect the battery from the corresponding load (e.g., an electric vehicle (EV) traction motor or related control circuit). However, mechanical relays can be expensive, slow, and bulky.

Summary of the Invention

Means for Solving the Problems

[0005] The present invention provides a battery monitor for protecting a switching device used to supply power to a load, comprising: a converter circuit including an input for receiving a voltage; an oscillator that generates a pulse sequence based on the voltage; and a digital circuit including a first detector that detects the occurrence or non-occurrence of a first fault event with respect to the switching device based on determined characteristics of the pulse sequence measured over at least two different time windows; and a second detector that detects the occurrence or non-occurrence of a second fault event with respect to the switching device by determining a modeled junction temperature of the switching device based on the pulse sequence. [Brief explanation of the drawing]

[0006] The various drawings attached to this disclosure are merely illustrative embodiments and should not be considered to limit its scope. [Figure 1] This is a block diagram of an example section of the BMS. [Figure 2A] An example of a current spike in a system is shown. [Figure 2B] An example of a current spike in a system is shown. [Figure 3] An example section of the BMS monitor is shown. [Figure 4] An example of a time window is shown. [Figure 5A] The thermal impedance profile of the sample MOSFET is shown. [Figure 5B] The circuit representation of the sample MOSFET in the Cowell model is shown. [Figure 6A] A sample binary RC system is shown. [Figure 6B] This shows a graph of current flow in a binary RC system. [Figure 6C] The circuit diagram of the Cowell model for the sample MOSFET is shown. [Figure 6D] This shows a set of binary RC pairs. [Figure 6E] This shows a network with switched resistors. [Figure 6F] This shows the switch timing method. [Figure 7] An example section of the BMS monitor is shown. [Modes for carrying out the invention]

[0007] Embodiments of this disclosure provide improved overcurrent detection and mitigation systems, methods, and techniques for use in a battery management system (BMS). The BMS may be provided for an electric vehicle (EV). The BMS monitor may use two different techniques to detect overcurrent, providing redundancy and improving reliability. The first technique may detect overcurrent based on average power over different, overlapping periods. The second technique may detect overcurrent based on determining a modeled junction temperature of a switching device, such as a semiconductor element, and coupling the battery to a load. Both techniques may take into account historical information of circuit performance, such as past current glitches. If an overcurrent is detected by either technique, the switching device may be quickly disabled, preventing the switching device from failing. Thus, the overcurrent detection techniques described herein improve the safety and reliability of the BMS while reducing costs.

[0008] This document describes a battery monitor for protecting a switching device used to supply power to a load. The battery monitor may include a converter circuit having an input for receiving a voltage and an oscillator for generating a pulse sequence based on the voltage. The battery monitor may further include a digital circuit having a first detector for detecting the occurrence or absence of a first fault event with respect to the switching device based on determined characteristics of the pulse sequence measured over at least two different time windows, and a second detector for detecting the occurrence or absence of a second fault event with respect to the switching device by determining a modeled junction temperature of the switching device based on the pulse sequence.

[0009] This document also describes a method for protecting switching devices used to supply power to a load. The method may include detecting an input voltage, generating a pulse sequence based on the input voltage, determining whether a first fault event has occurred or not for the switching device based on determined characteristics of the pulse sequence measured over at least two different time windows, determining whether a second fault event has occurred or not for the switching device by determining a modeled junction temperature of the switching device based on the pulse sequence, and disabling the operation of the switching device in response to determining whether a first or second fault event has occurred.

[0010] This paper further describes a device for protecting a switching device used to supply power to a load. The device may include a converter circuit having a voltage input and an oscillator that generates a pulse sequence based on the voltage. The device may also include a fault detector including a plurality of timing filters and comparators that determines the power dissipated over a plurality of time windows based on the pulse sequence, and for each of the plurality of time windows, compares the power dissipated in that time window with the respective power threshold for that window, detects an overcurrent event based on the comparison, and disables the switching device in response to the detection of an overcurrent event.

[0011] Figure 1 shows a block diagram of an exemplary portion of the BMS100. The BMS100 may include a plurality of battery cells 102.1-102.N, a BMS monitor 104, a fuse 106, a load 108, a switching device 110, a shunt resistor 112, an OR logic gate 114, and a drive circuit 116.

[0012] Battery cells 102.1 to 102.N may be provided as battery modules for a battery pack. For example, the battery pack may provide a stack or other assembly of battery cells, such as one using lithium-ion chemistry and providing a nominal output of 48 volts or other desired output. Batteries of different specifications, sizes, and shapes can be used. Battery cells 102.1 to 102.N may be monitored by a BMS monitor 104. For example, the BMS monitor 104 may include multiple voltage measurement channels, e.g., 16 channels.

[0013] For example, the BMS monitor 104 may be provided as an integrated circuit, which may include a monolithic integrated circuit or an integrated module containing multiple integrated circuit dies or other circuit elements in a common shared integrated circuit device package. The BMS monitor 104 may include hardware and software for measuring the voltage, current, and / or temperature levels of battery cells 102.1 to 102.N. The BMS monitor 104 may store these measurements in memory such as an EEPROM. The BMS monitor 104 may also communicate these measurements to a master controller (not shown) via a communication interface using a wired network, a wireless network, or a combination thereof.

[0014] The battery cells 102.1-102.N may also be coupled to a fuse 106, a load 108, a switching device 110, and a shunt resistor 112. The load 108 may be a component that receives power from the battery cells 102.1-102.N, such as an EV towing motor. The load 108 may be fully or partially powered by the battery cells 102.1-102.N. The fuse 106 may be provided for emergencies where the battery cells 102.1-102.N need to be permanently disconnected from the load 108 (e.g., extreme overheating).

[0015] The switching device 110 can selectively connect and disconnect the battery cells 102.1 to 102.N to the load 108. The switching device 110 may be provided as a metal oxide-semiconductor field effect transistor (MOSFET). For example, the switching device 110 may be provided as a silicon carbide (SiC) MOSFET configured to operate at a high voltage. MOSFETs have advantages over mechanical relays because they are low cost and have a fast response time. However, MOSFETs may have lower fault tolerance and thus can be more easily damaged by battery malfunction events such as overcurrent. Also, MOSFETs can be one of the first devices to fail in the circuit when used as the switching device 110. When a MOSFET fails, it often fails as a short. This fail-short characteristic can cause a short circuit between the battery cells 102.1 to 102.N and the load 108, resulting in catastrophic failure of one or more cells. The fuse 106 can blow before significant damage occurs, but when the fuse 106 blows, the embedded device (e.g., the load) can become inoperable. In the example of an EV, the EV can become inoperable and may have to be taken to a service station for expensive repairs.

[0016] Therefore, the BMS monitor 104 can disable (e.g., turn off, limit the operation of) the switching device 110 (e.g., a MOSFET) in certain situations, such as overcurrent conditions. The BMS monitor 104 may also detect a voltage across the shunt resistor 112. From the detected voltage, an overcurrent event can be detected, and then the switching device 110 (e.g., a MOSFET) can be turned off in a relatively short time before it fails. In this example, the BMS monitor 104 may detect an overcurrent event by using two different techniques (OC1 and OC2), as will be described in more detail below. If either of the OC detection techniques indicates an overcurrent event, the output of the OR logic gate 114 may trigger the driver circuit 116 to disable the switching device 110. The OR logic gate 114 and / or the driver circuit 116 may be integrated with the BMS monitor 104.

[0017] Some overcurrent detection techniques may not be able to accurately detect overcurrent events in the switching device 110. The current flow may include transients resulting from the switching of the load 108 (e.g., an EV traction motor), and therefore, simply defining an overcurrent event as "a current exceeding a threshold over a period of time" may not be effective in protecting the switching device 110.

[0018] Figures 2A - 2B show examples of current spikes in a system. Figure 2A shows two spikes (or glitches): a first spike 202 of magnitude 2000A over a duration of 1 microsecond and a second spike 204 of magnitude 500A over a duration of 2 microseconds. Assume that a threshold for detecting an overcurrent event is set for a current spike exceeding 400A over a duration of at least 2 microseconds. Here, the second spike 204 (500A over a duration of 2 microseconds) is detected as an overcurrent event, while the first spike 202 (2000A over a duration of 1 microsecond) is not detected as an overcurrent event. This can be a problem because the first spike 202 can dissipate eight times the energy in a switching device (e.g., a MOSFET) compared to the wider second spike 204.

[0019] Furthermore, a failure of a switching device (e.g., a MOSFET) can depend on the history of the current (and dissipated power and heat) in the system rather than the current at a single point in time. Figure 2B shows a first set of current spikes 206 each having a magnitude of 2000A over a duration of 1 microsecond and a second set of current spikes 208 each having a magnitude of 500A over a duration of 2 microseconds. Assume that a threshold for detecting an overcurrent event is set for a current spike exceeding 600A over a duration of at least 2 microseconds. Here, none of the spikes in either the first set or the second set of spikes 206, 208 can trigger the detection of an overcurrent event. This can be a problem because each spike can generate a certain amount of heat within the switching device (e.g., a MOSFET), and the continuous nature of the spikes can lead to overheating of the switching device and potentially cause failure of the switching device. Thus, an overcurrent in a switching device such as a MOSFET may be based not only on the amount of current at a particular time but also on the history of circuit performance.

[0020] Figure 3 shows an exemplary portion of the BMS monitor 300. The BMS monitor 300 may detect a voltage across a shunt resistor R (e.g., shunt resistor 112 in Figure 1). Based on the detected voltage, the BMS monitor 300 may detect overcurrent events based on two different detection techniques, detecting overcurrent event 1 (OC1) and event 2 (OC2), respectively. As described above with reference to Figure 1, the occurrence of either overcurrent event (OC1 and / or OC2) may trigger the deactivation of a switching device, such as a MOSFET (e.g., switching device 110 in Figure 1).

[0021] The BMS monitor 300 may include two processing chains 310, 350 corresponding to two different fault detection technologies. The first processing chain 310 may include a first analog front-end circuit 312, a first counter 314, and a first digital engine 316. The first analog front-end circuit 312 may receive or detect a voltage across a shunt resistor and convert the detected voltage into a pulse sequence (or periodic pulses).

[0022] The first analog front-end circuit 312 may include a first voltage-to-power converter 312.1 and a first current-controlled oscillator (CCO) 312.2. The first voltage-to-power converter 312.1 can convert a detected voltage into a power signal. The first voltage-to-power converter 312.1 may convert a detected voltage into a current signal using, for example, a device having a specific transconductance characteristic. The current signal can then be squared to generate a power signal, and since the square of the current can represent power, p(t) = i(t) 2R is the current, and I is the resistance. The first CCO312.2 can convert a power signal into a pulse sequence. Thus, the pulse sequence can be current-controlled. Each pulse can correspond to a "unit of energy". The frequency of the pulse sequence can be proportional to the square of the detected voltage. For example, if a detected voltage of 1V generates a pulse sequence with a frequency of 1Hz, then a detected voltage of 2V can generate a pulse sequence with a frequency of 4Hz (2V squared).

[0023] The first counter 314 may count the number of pulses in the generated pulse sequence. The first counter 314 may be a rotary counter or other reset counter that, after reaching a maximum count, rolls over and restarts counting. For example, if the count is between 1 and 12, after reaching 12, the count restarts from 1 again. The first counter 314 may be provided as a gray counter, such as a 4-bit gray counter.

[0024] The first counter 314 may be coupled to the first digital engine 316. The first digital engine 316 may be implemented using a combination of hardware and software. The first digital engine 316 may include a processor, a microprocessor, a digital state machine, and / or other preferred components.

[0025] The first digital engine 314 may receive pulse sequences and, based on the received pulse sequences, may detect first fault events, such as a first overcurrent event (OC1). The pulse sequences generated by the first counter 314 may be generated asynchronously, as they represent currents that may include spikes (or glitches), as described above. Therefore, the first digital engine 314 may synchronize the pulse sequences with its system clock (SCLK). For each clock cycle of the system clock (e.g., 125 nanoseconds) or set of clock cycles, the first digital engine 314 may store a previously acquired value of the pulse sequence in register 316.1 and use a subtractor 316.2 to subtract it from the currently acquired value of the pulse sequence to generate an energy sequence (also called a power sequence) for that clock cycle (or set of clock cycles). The energy sequence may correspond to the energy / power dissipated in the last cycle (or set of clock cycles). The first counter 314 may be large enough so that it does not complete a full rotation of its count within a clock cycle of the system clock.

[0026] The first digital engine 316 may include an OC1 detector 316.3 to detect overcurrent events based on the generated energy sequence. The OC1 detector 316.3 may detect OC1 based on the average of energy over different periods. The OC1 detector 316.3 may use multiple exponential moving average (EMA) windows.

[0027] Figure 4 shows an example of time windows. Figure 4 shows five time windows W1 to W5. Time windows W1 to W5 can be measured backward based on the current time. Time window W1 may be the shortest window backward from the current time to a first time, e.g., 1 microsecond. Time window W2 may be longer than W1, to a second time, e.g., 10 microseconds. Time window W3 may be longer than W2, to a third time, e.g., 100 microseconds. Time window W4 may be longer than W3, to a current time, e.g., 1000 microseconds. Time window W5 may be longer than W4, to a fifth time, e.g., 10000 microseconds. Time windows can be implemented using timing filters. The duration of the timing window may be configurable. The duration may be configured based on the duration of the MOSFET's thermal ladder, as will be discussed in more detail below.

[0028] For each time window, the average dissipated power can be determined simultaneously. The average power can be a function of the energy sequence observed during each period. Thus, in the example in Figure 4, the average power for time windows W1 to W5 may represent the power dissipated in the last 1 microsecond, 10 microseconds, 100 microseconds, 1000 microseconds, and 10000 microseconds, respectively.

[0029] Each time window may also be associated with a power threshold. The average power of each window can be compared to its respective power threshold. The individual thresholds for each window may be configurable. For example, the thresholds may be obtained based on a simulation of a switching device (MOSFET). The simulation may assume maximum allowable case temperature and junction temperature, as will be described in more detail below.

[0030] If the average power determined for any given time window exceeds its respective power threshold, the BMS monitor 300 (e.g., the OC1 detector 316.3) may determine that an overcurrent event OC1 has occurred. Determining the digital estimate of dissipated power using different time windows can eliminate or reduce false detections of overcurrent events resulting from current spikes (glitches), while still responding to a large number of short spikes.

[0031] Referring back to Figure 3, the second processing chain 350 is described next. The second processing chain 350 may include a second analog front-end circuit 352, a first counter 354, and a first digital engine 356. The second analog front-end circuit 352 may be similar to, or substantially the same as, the first analog front-end circuit 312. Thus, the second analog front-end circuit 352 may receive or detect a voltage across a shunt resistor and convert the detected voltage into a pulse sequence (or periodic pulses).

[0032] The second analog front-end circuit 352 may include, as described above, a second voltage-to-power converter 352.1 and a second current-controlled oscillator (CCO) 352.2, and these components may operate in the same manner as their counterparts in the first analog front-end circuit 312. The second voltage-to-power converter 352.1 may convert the detected voltage into a power signal. The second voltage-to-power converter 352.1 may convert the detected voltage into a current signal using, for example, a transconductor device. The current signal may then be squared to generate a power signal. The second CCO 352.2 may convert the power signal into a pulse sequence. Thus, the pulse sequence may be current-controlled. Each pulse may correspond to a "unit of energy". The frequency of the pulse sequence may be proportional to the square of the detected voltage.

[0033] The second counter 354 may operate in the same manner as the first counter 314 described above. The second counter 354 may be a rotary counter that, after reaching its maximum count, rolls over the count and restarts counting. For example, if the count is 1 to 12, after reaching 12, the count restarts from 1 again. The second counter 354 may be provided as a gray counter, such as a 4-bit gray counter.

[0034] In one example, one or more analog and counter components (e.g., 312 and 315, 314 and 354) of the first processing chain 310 and the second processing chain 350 may be combined or integrated. For example, a single analog front-end circuit and / or counter may be provided.

[0035] The second counter 354 may be coupled to the second digital engine 356. The second digital engine 356 may be implemented using a combination of hardware and software. The second digital engine 356 may include a processor, a microprocessor, a digital state machine, and / or other suitable components.

[0036] The second digital engine 354 may receive pulse sequences and, based on the received pulse sequences, may detect a second fault event, such as a second overcurrent event (OC2). The pulse sequences generated by the second counter 354 may be generated asynchronously, as they represent currents that may include spikes (or glitches), as described above. Therefore, the second digital engine 354 may synchronize the pulse sequences with its system clock (SCLK). For each clock cycle (e.g., 125 nanoseconds) or set of clock cycles of the system clock, the second digital engine 354 may store a previously acquired value of the pulse sequence in register 356.1 and use a subtractor 356.2 to subtract it from the currently acquired value of the pulse sequence to generate an energy sequence (also called a power sequence) for that clock cycle (or set of clock cycles). The energy sequence may correspond to the energy / power dissipated in the last cycle (or set of clock cycles). The second counter 354 may be large enough so that it does not complete a full rotation of its count within a clock cycle of the system clock.

[0037] A second digital engine 356 may include an OC2 detector 356.3 to detect an overcurrent event based on the generated energy sequence. The OC2 detector 356.3 may determine a modeled (e.g., virtual) junction temperature of a switching device (e.g., a MOSFET junction), compare the determined modeled junction temperature with a temperature threshold, and based on the comparison, detect the occurrence of an overcurrent event OC2.

[0038] The junction temperature of a MOSFET can be a reliable indicator of its safe and proper operation. For example, certain MOSFETs may function safely and properly as long as their junction temperature is below 175°C, but may fail if their junction temperature exceeds 175°C for a certain period of time. Therefore, overcurrent conditions may be detected based on the junction temperature of a switching MOSFET.

[0039] Actual (or real) junction temperature can be difficult to measure. However, junction temperature is related to the power dissipated by the MOSFET, and is related not only to the instantaneous power dissipated at a selected point in time, but also to the history of power dissipated over a period of time. Therefore, the OC2 detector 356.3 can determine the modeled junction temperature based on the power dissipated by the MOSFET and a digital representation of the MOSFET's thermal characteristics, as detected by the energy sequence.

[0040] Figure 5A shows the thermal impedance profile of the sample MOSFET, and Figure 5B shows the Cowell model circuit representation of the sample MOSFET. In Figure 5A, the x-axis represents the time scale, and the y-axis represents the thermal resistance (or impedance) of the sample MOSFET. The thermal resistance can correspond to the temperature difference between the junction and the MOSFET case divided by the energy.

[0041] A MOSFET can be modeled as a cascaded network of resistors and capacitors, known as a Cowell thermal ladder, as shown in Figure 5B. The Cowell model may include a linear network of resistors and capacitors having input ports provided as a current proportional to power, and other-end terminal ports provided as a known thermal potential, e.g., case temperature Tcase. The junction temperature Tj may correspond to a node between a first capacitor (Cj1) and a first resistor (RTj13) in the Cowell model. The values ​​of the resistors and capacitors in the Cowell model are based on the intrinsic characteristics of the MOSFET and may therefore be obtained from a digital model of the MOSFET, e.g., a SPICE (Simulation Enhanced Spectrum) model. In one example, the digital representation may be characterized as ΔT / (RiCi).

[0042] Referring back to Figure 3, the OC2 detector 356.3 may, for example, obtain values ​​from the Cowell model of a switching device (e.g., a MOSFET) from a digital model of the switching device and convert them to digital register values. Thus, these digital register values ​​for resistors and capacitors in the Cowell model may be configurable. Based on the energy sequence and the digital Cowell model register values, the OC2 detector 356.3 may calculate the virtual junction temperature Tj of the switching device. The OC2 detector 353.3 may then compare the virtual junction temperature Tj to a temperature threshold, for example, 175°C. If the determined virtual junction temperature Tj exceeds the temperature threshold, the BMS monitor 300 (e.g., the OC2 detector 356.3) may determine that an overcurrent event OC2 has occurred.

[0043] In response to the detection of either (or both) of the overcurrent events OC1 and OC2, the switching device may be disabled. These detection techniques described herein can quickly detect the overcurrent event and disable the switching device relatively quickly before it fails.

[0044] Figures 6A to 6F are used to illustrate the calculation technique for modeled (e.g., virtual) junction temperatures. Figure 6A shows a sample binary RC system, where two capacitors C1 and C2 are connected in parallel with a resistor R between them to create a binary RC system. Figure 6B shows a graph of the current flow in the binary RC system of Figure 6A. A first potential V1 exists between C1 and R, and a second potential V2 exists between C2 and R.

[0045] V1 and V2 can be characterized as follows:

number

[0046] V1 and V2 may also be characterized as follows:

number

[0047] As described above, the MOSFET may be modeled as a network of resistors and capacitors, for example, as a Cowell model. Therefore, the virtual junction temperature may be calculated using the computational techniques for V1[n+1] and V2[n+1] described above. Figure 6C shows the circuit diagram of a Cowell model of a sample MOSFET. As shown, the circuit diagram of the model includes a network of resistors (R1, R2, R3, R4, R5, R6) and capacitors (C0, C1, C2, C3, C4, C5). This network of resistors and capacitors can be converted into a set of binary pairs. Figure 6D shows a set of binary RC pairs. Two computing elements (computing element 1 and computing element 2) can be used to solve the values ​​of the thermal ladder when divided into binary elements using switching and timing schemes. The first computing element may be dedicated to solving the first RC time constant, while the second computing element may be shared by the other RC element.

[0048] Figure 6E shows a network with switched resistors. Here, resistors in a linear network may be replaced with switched resistors, and their resistance values ​​may be adjusted accordingly based on their binary positions. For example, R1 remains R1 / 1, R2 becomes R2 / 2, R3 becomes R3 / 4, R4 becomes R / 8, R5 becomes R5 / 16, R6 becomes R6 / 32, and so on. Figure 6F shows a switch timing scheme. As shown, the switch timing may be set so that the resistor connection timings are mutually exclusive; that is, only one resistor switch is closed at a time.

[0049] Therefore, one binary pair can be solved per cycle. The two computing elements may have mutually exclusive time slots for the second computing element, such as 2Δt, 4Δt, 8Δt, 16Δt, 32Δt, and 64Δt. The first computing element may be dedicated to solving the first binary pair. The time constant of the first binary pair may be comparable to Δt. The second computing element may be shared by other binary pairs based on their mutually exclusive time slots. The two computing elements can then solve the values ​​of a thermal ladder representing the MOSFET. The value of the first capacitor C0 may correspond to the junction temperature with a proportionality constant, and the capacitor value may correspond to historical data.

[0050] Figure 7 shows an exemplary portion of the BMS monitor 700. The BMS monitor 700 may detect a voltage across a shunt resistor R (e.g., shunt resistor 112 in Figure 1). Based on the detected voltage, the BMS monitor 300 may detect overcurrent events using two different detection techniques to detect overcurrent events 1 (OC1) and 2 (OC2), respectively. As described above with reference to Figure 1, the generation of either or both of the overcurrent events (OC1 and / or OC2) may trigger the deactivation of a switching device, such as a MOSFET (e.g., switching device 110 in Figure 1).

[0051] The BMS monitor 700 may include two processing chains 710 and 750 corresponding to two different overcurrent detection technologies. The first processing chain 710 may include analog components: a level shifter 712, a polarity comparator 714, a polarity switch 716, a transconductor 718, a current signal square device 720, and a CCO 722.

[0052] The level shifter 712, polarity comparator 714, and polarity switch 716 can detect and adjust the voltage across the shunt resistor. The transconductor 718 can convert the detected (and adjusted) voltage into a current signal. The transconductor 718 can also apply a gain that may be adjustable. The current signal squaring device 720 can square the current signal to generate a squared current signal representing a power signal. The CCO 722 can convert the squared current signal into a pulse sequence. Thus, the pulse sequence can be current-controlled. Each pulse may correspond to a "unit of energy". The frequency of the pulse sequence may be proportional to the square of the detected voltage.

[0053] Counter 724 can count the number of pulses in the generated pulse sequence. Counter 724 may be provided as a rotary counter, such as a Gary counter.

[0054] Next, the pulse count may be received by a digital engine. Here, based on the system clock (SCLK), the previous value of the pulse count may be subtracted from the current value of the pulse count using a delay unit 726 and a subtractor 728 to generate an energy sequence (or power sequence) for a given clock cycle (or set of clock cycles). The energy sequence may then be sent to a plurality of EMA filters 730. The EMA filters 730 may be defined over different time periods, as described above. Each EMA filter 730 may determine the power dissipated within its respective time window. A digital comparator 732 may compare the average power from each EMA filter 730 to its respective power threshold. The power thresholds for different windows may be configurable and may be set based on register values ​​from the main register file 734. The output of the digital comparator 732 may be fed to an OR gate 736. Thus, if the average power determined for any time window exceeds its respective power threshold, the BMS monitor 700 may detect the occurrence of an overcurrent event OC1.

[0055] The second processing chain 750 may include analog components: a level shifter 752, a polarity comparator 754, a polarity switch 756, a current signal squared device 760, and a CCO 762. These components may operate in the same or similar manner as their counterparts in the first processing chain 710. One or more of these components in the second processing chain 750 may be combined with or integrated with their counterparts in the first processing chain 710.

[0056] The second processing chain may also include a counter 764, a delay unit 766, and a subtractor 768 for generating an energy sequence. These components may operate in the same or similar manner as their counterparts in the first processing chain 710. One or more of these components in the second processing chain 750 may be combined with or integrated with their counterparts in the first processing chain 710.

[0057] In the second processing chain 750, the Cowell thermal filter 770 may receive an energy sequence. As described herein, the Cowell thermal filter 770 may also receive a switching device, for example, T case The BMS monitor 700 may receive a digital register value of the Cowell model and calculate the virtual junction temperature Tj of the switching device (e.g., a MOSFET). The digital register value may be configurable and may be set based on a register value from a redundant register file 772 (or the main register file 734). The digital comparator 774 may compare the virtual junction temperature to a temperature threshold. The temperature threshold may be configurable and may be set based on a register value from a redundant register file 772 (or the main register file 734). If the determined virtual junction temperature exceeds the temperature threshold, the BMS monitor 700 may detect the occurrence of an overcurrent event OC1. In response to the detection of at least one of the overcurrent events OC1 and OC2, the switching device may be disabled.

[0058] Various notes Each of the above non-limiting aspects may stand alone, or it may be combined in various permutations or combinations with one or more of the other aspects or subjects described in this document.

[0059] The above detailed description includes references to accompanying drawings, which form part of the detailed description. The drawings illustrate, for illustrative purposes, specific implementations in which the present invention can be carried out. These implementations are also commonly referred to as “examples.” Such examples may include elements in addition to those shown or described. However, the inventors also conceive of examples in which only the shown or described elements are provided. Furthermore, the inventors also conceive of examples using any combination or permutation of those elements (or one or more embodiments thereof) shown or described in any particular example (or one or more embodiments thereof) shown or described herein, or in any other example (or one or more embodiments thereof).

[0060] In the event of any inconsistent usage between this document and any document incorporated by reference, the usage in this document shall prevail.

[0061] In this document, singular terms are used to include one or more, regardless of other examples or uses of “at least one” or “one or more,” as is common in patent literature. In this document, the term “or” is used to refer to non-exclusive “or,” such that “A or B” includes “A but not B,” “B but not A,” and “A and B.” In this document, the terms “include” and “in” are used as plain English equivalents of the terms “equipped with” and “therefore.” Furthermore, in the following claims, the terms “include” and “equipped with” are unrestrictive; that is, systems, devices, articles, compositions, formulations, or processes containing elements in addition to those enumerated after such terms in the claims are still considered to be within the scope of those claims. In addition, in the following claims, terms such as “first,” “second,” and “third” are used merely as labels and are not intended to impose numerical requirements on their subject matter.

[0062] Examples of methods described herein can be implemented in machine or computer at least in part. Some examples may include computer-readable or machine-readable media coded with instructions that can be operated to configure an electronic device to perform the methods of the examples above. Implementations of such methods may include code such as microcode, assembly language code, or high-level language code. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored in one or more volatile, non-temporary, or non-volatile tangible computer-readable media, at execution or at other points in time. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0063] The above description is intended to be illustrative and not limiting. For example, the above examples (or one or more embodiments thereof) can be used in combination with one another. Those skilled in the art can use other implementations by considering the above description. The abstract is provided to enable readers to quickly confirm the nature of the technical disclosure. The abstract is submitted with the understanding that it is not to be used to interpret or limit the claims or meaning. Also, in the forms for carrying out the above invention, various features can be grouped together to streamline the disclosure. This should not be interpreted as meaning that any disclosed feature not claimed is essential to any claim. Rather, the subject matter of the invention may not be present in all features of a particular disclosed implementation. Therefore, it is conceivable that the following claims are incorporated into the forms for carrying out the invention as examples or implementations, and that each claim stands on its own as a distinct implementation, and that such implementations can be combined with one another in various combinations or permutations. The scope of the present invention should be determined by referring to the appended claims, together with the entire scope of equivalents to which such claims are granted. [Explanation of Symbols]

[0064] 104 BMS Monitor 106 fuses 108 load 110 Switching Devices 112 Shunt Resistors 114 OR logic gates 116 Drive Circuit

Claims

1. A battery monitor for protecting a switching device used to supply power to a load, A converter circuit including an input for receiving the voltage across a shunt resistor connected to a switching device, An oscillator that generates a pulse sequence based on the aforementioned voltage, It is a digital circuit, A first detector for detecting the occurrence or non-occurrence of a first fault event for the switching device based on the determined characteristics of the pulse sequence measured over at least two different time windows, and A second detector for detecting the occurrence or non-occurrence of a second fault event for the switching device by determining the modeled junction temperature of the switching device based on the pulse sequence, Digital circuits including, A battery monitor equipped with this feature.

2. The system further comprises a resettable counter for counting pulses in the pulse sequence, The battery monitor according to claim 1, wherein the digital circuit is configured to determine the count of pulses counted by the resettable counter and to determine the number of pulses received over a certain period of time.

3. The battery monitor according to claim 1, wherein the first and second failure events include an overcurrent condition.

4. The battery monitor according to claim 1, wherein the battery monitor is configured to disable the switching device in response to the detection of at least one of the first or second failure events.

5. The battery monitor according to claim 1, wherein the switching device is a metal oxide semiconductor field effect transistor (MOSFET).

6. The first detector, Based on the pulse sequence, the power dissipated over the different time windows is determined. For each time window, compare the power dissipated during that time window with the respective power threshold for that time window. The battery monitor according to claim 1, configured to detect the first fault event in response to the power dissipated over at least one of the time windows exceeding the respective power thresholds for that window.

7. The second detector, The digital representation of the resistance and capacitance values ​​of a linear network of resistors and capacitors representing the thermal characteristics of the switching device is obtained. The battery monitor according to claim 1, configured to determine the modeled junction temperature based on the resistance value, the capacitance value, and the pulse sequence.

8. The second detector, The resistors and capacitors are grouped into sets of binary pairs, A first computing element is assigned to the first set of the binary pairs. The battery monitor according to claim 7, further configured to assign a second computing element to the remaining set of the binary pairs.

9. The aforementioned converter circuit The system further includes a voltage-to-power converter for converting the aforementioned voltage into a squared current signal, The monitor according to claim 1, wherein the oscillator is configured to convert the squared current signal into the pulse sequence.

10. A method for protecting a switching device used to supply power to a load, The device detects the input voltage across a shunt resistor connected to a switching device, The device generates a pulse sequence based on the input voltage, The apparatus determines whether a first fault event occurs or not for the switching device based on the determined characteristics of the pulse sequence measured over at least two different time windows. The apparatus determines whether a second fault event occurs or not for the switching device by determining the modeled junction temperature of the switching device based on the pulse sequence. A method comprising the apparatus disabling the operation of the switching device in response to determining the occurrence of the first or second fault event.

11. The apparatus counts the pulses in the pulse sequence to generate a resettable count, The method according to claim 10, further comprising determining the number of pulses received within a certain period of time based on the resettable count.

12. The method according to claim 10, wherein the first and second fault events include an overcurrent condition.

13. The method according to claim 10, wherein the switching device is a metal oxide semiconductor field-effect transistor (MOSFET).

14. The apparatus determines whether the first failure event occurs or not. The device determines the power to be dissipated over the different time windows based on the pulse sequence, For each time window, the device compares the power dissipated in that time window with the respective power threshold for that time window. The method according to claim 10, wherein the apparatus detects the first fault event in response to the power dissipated over at least one of the time windows exceeding the respective power thresholds for that window.

15. The apparatus determines whether the second failure event occurs or not. The apparatus acquires a digital representation of the resistance and capacitance values ​​of a linear network of resistors and capacitors representing the thermal characteristics of the switching device. The method according to claim 10, wherein the apparatus determines the modeled junction temperature based on the resistance value and the capacitance value and the pulse sequence.

16. The apparatus groups the resistor and the capacitor into sets of binary pairs, The device assigns a first computing element to a first set of binary pairs, The method according to claim 15, further comprising the device assigning a second computing element to the remaining set of binary pairs.

17. A device for protecting a switching device used to supply power to a load, A converter circuit including an input for receiving the voltage across a shunt resistor connected to a switching device, An oscillator that generates a pulse sequence based on the aforementioned voltage, A fault detector comprising multiple timing filters and comparators, Based on the pulse sequence, the power dissipated over multiple time windows is determined. For each of the aforementioned multiple time windows, the power dissipated in that time window is compared with the respective power threshold for that window. Based on the above comparison, an overcurrent event is detected. In response to the detection of the overcurrent event, the switching device is disabled. Fault detector and A device equipped with the following features.

18. The system further comprises a resettable counter for counting pulses in the pulse sequence, The apparatus according to claim 17, wherein the fault detector is configured to determine the count of pulses counted by the resettable counter and to determine the number of pulses received within a certain period of time.

19. The apparatus according to claim 17, wherein the switching device is a metal oxide semiconductor field-effect transistor (MOSFET).

20. The apparatus according to claim 17, further comprising a different fault detector for detecting the occurrence or non-occurrence of a second fault event with respect to the switching device by determining a modeled junction temperature of the switching device based on the pulse sequence.

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