Doherty amplifier

Abstract

In this Doherty amplifier in which a plurality of Doherty amplifier cells (11), (12) are arranged in parallel, each Doherty amplifier cell (11), (12) comprises: a carrier amplifier (111), (112) that has an input node electrically connected to a carrier input pad and an output node electrically connected to a carrier output pad; a peak amplifier (121), (122) that has an input node electrically connected to a peak input pad and an output node electrically connected to a peak output pad; an in-cell input distribution circuit (231), (232) that has a cell input terminal to which an input signal is inputted, a carrier output terminal electrically connected to the carrier input pad, and a peak output terminal electrically connected to the peak input pad, and that distributes and outputs the input signal inputted to the cell input terminal to the carrier output terminal and the peak output terminal; and an in-cell output combining circuit (241), (242) that has a carrier input terminal electrically connected to the carrier output pad, a peak input terminal electrically connected to the peak output pad, and a cell output terminal, combines a carrier amplified output signal outputted to the carrier output pad and a peak amplified output signal outputted to the peak output pad, and outputs a cell output signal to the cell output terminal.

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplifier having a carrier amplifier and a peak amplifier.

Background Art

[0002] In recent years, in wireless communication systems such as mobile phones, signals with a large peak-to-average power ratio (Peak to Average Power Ratio, hereinafter referred to as PAPR) are used to improve communication speed. A Doherty amplifier is known as an amplifier that can amplify a signal with a large PAPR with high efficiency. Patent Document 1 shows a Doherty amplifier with higher power efficiency. The Doherty amplifier shown in Patent Document 1 is formed by arranging a plurality of Doherty cells each consisting of a carrier sub-amplifier and a peaking sub-amplifier in parallel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the Doherty amplifier shown in Patent Document 1, all carrier input terminals for the Doherty cells are electrically coupled to a carrier input signal manifold having an elongated conductor structure to which a power splitter is electrically coupled, all peaking input terminals for the Doherty cells are electrically coupled to a peaking input signal manifold having an elongated conductor structure to which a power splitter is electrically coupled, and all carrier output terminals and peaking output terminals for the Doherty cells are electrically coupled to an output signal coupling manifold having an elongated conductor structure to which output nodes are electrically coupled.

[0005] However, in the Doherty amplifier shown in Patent Document 1, the electrical length from the input node to the power splitter to the carrier input terminal for each Doherty cell is different, the electrical length from the input node to the power splitter to the peaking input terminal for each Doherty cell is different, and the electrical length from the carrier output terminal and peaking output terminal to the output node for each Doherty cell is different. As a result, there is a problem in that performance (efficiency) decreases due to differences in electrical length.

[0006] This disclosure is made in view of the above-mentioned points, and aims to provide a Doherty amplifier in which a plurality of Doherty amplifier cells having a carrier amplifier and a peaking amplifier are arranged in parallel, thereby eliminating path differences caused by the positions of the carrier amplifier and the peaking amplifier in the Doherty amplifier cell, and improving performance (efficiency). [Means for solving the problem]

[0007] The Doherty amplifier relating to this disclosure consists of multiple Doherty amplifier cells arranged in parallel. And so,Each Doherty amplifier cell comprises a carrier amplifier whose input node is electrically connected to a carrier input pad and whose output node is electrically connected to a carrier output pad; a peak amplifier whose input node is electrically connected to a peak input pad and whose output node is electrically connected to a peak output pad; an internal cell input distribution circuit having a cell input terminal into which an input signal is input, a carrier output terminal electrically connected to a carrier input pad, and a peak output terminal electrically connected to a peak input pad, which distributes the input signal input to the cell input terminal to the carrier output terminal and the peak output terminal for output; and an internal cell output combining circuit having a carrier input terminal electrically connected to a carrier output pad, a peak input terminal electrically connected to a peak output pad, and a cell output terminal, which combines the carrier amplified output signal output to the carrier output pad and the peak amplified output signal output to the peak output pad to output a cell output signal to the cell output terminal. The internal cell input distribution circuit has a carrier gate bias terminal AC-connected between the cell input terminal and the carrier output terminal, to which a gate bias voltage is applied to the carrier amplifier. The gate bias voltage applied to the carrier gate bias terminal is then transmitted to the carrier output terminal. It has a carrier-side input circuit and a peak gate bias terminal which is AC-connected between the cell input terminal and the peak output terminal, and to which a gate bias voltage is applied to the peak amplifier. The gate bias voltage applied to the peak gate bias terminal is then transmitted to the peak output terminal. A peak-side input circuit and the cell input terminal Electrical It is connected to the carrier-side input circuit and the peak-side input circuit, which are AC short-circuited and DC open-circuited. DC A blocking capacitance is provided, and a first input terminal is input to the input signal and the gate bias voltage to the carrier amplifier, and TheThe system includes: an input distribution circuit electrically connected to a second input terminal to which the input signal and a gate bias voltage for the peak amplifier are input, and electrically connected to the cell input terminal in each of the multiple Doherty amplifier cells, which distributes and outputs the input signals input to the first input terminal and the second input terminal to the cell input terminal in each of the multiple Doherty amplifier cells; a carrier gate bias application circuit electrically connected to the first input terminal and the carrier-side input circuit of the cell input distribution circuit in each of the multiple Doherty amplifier cells, which applies the gate bias voltage for the carrier amplifier applied to the first input terminal to the carrier-side input circuit of the cell input distribution circuit in each of the multiple Doherty amplifier cells; and a peak gate bias application circuit electrically connected to the second input terminal and the peak-side input circuit of the cell input distribution circuit in each of the multiple Doherty amplifier cells, which applies the gate bias voltage for the peak amplifier applied to the second input terminal to the peak-side input circuit of the cell input distribution circuit in each of the multiple Doherty amplifier cells. [Effects of the Invention]

[0008] According to this disclosure, each Doherty amplifier cell has a carrier amplifier and a peaking amplifier, as well as an in-cell input distribution circuit and an in-cell output combining circuit. Therefore, there is no difference in electrical length during distribution and combining among multiple Doherty amplifier cells, and performance (efficiency) can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example configuration of a Doherty amplifier according to Embodiment 1. [Figure 2] This figure shows an example configuration of a Doherty amplifier according to Embodiment 2. [Figure 3] This is a plan view showing an example of the structure around the DC blocking capacitor in a Doherty amplifier according to Embodiment 2. [Figure 4] This is a cross-sectional view showing an example of the structure around the DC blocking capacitor in a Doherty amplifier according to Embodiment 2. [Figure 5] This is a plan view showing an example of the structure around the DC blocking capacitor in a Doherty amplifier according to Embodiment 2. [Modes for carrying out the invention]

[0010] Embodiment 1. The Doherty amplifier according to Embodiment 1 will be explained with reference to Figure 1. The Doherty amplifier according to Embodiment 1 is a Doherty amplifier in which a plurality of Doherty amplifier cells 1, each having a carrier amplifier (carrier amp) 11 and a peak amplifier (peaking amplifier) ​​12, are arranged in parallel. Each Doherty amplifier cell 1 further has an in-cell input distribution circuit 13 that distributes the input signal to the input side of the carrier amplifier 11 and the peak amplifier 12, and an in-cell output combining circuit 14 that combines the carrier amplified output signal from the carrier amplifier 11 and the peak amplified output signal from the peak amplifier 12 on the output side of the carrier amplifier 11 and the peak amplifier 12.

[0011] Figure 1 shows two Doherty amplifier cells 1, with the first Doherty amplifier cell 1 denoted by the subscript 1 and the second Doherty amplifier cell 1 denoted by the subscript 2. The first Doherty amplifier cell 11 and the second Doherty amplifier cell 12 have the same circuit configuration and size. Therefore, in the description of the first Doherty amplifier cell 11 and the second Doherty amplifier cell 12, subscripts will be omitted and they will be described as having a common configuration in order to avoid complexity in the explanation.

[0012] Furthermore, there may be three or more Doherty amplifier cells 1. Even if there are three or more Doherty amplifier cells 1, each Doherty amplifier cell 1 n (n≧3) represents circuits with the same configuration and size. The number of Doherty amplifier cells 1 is determined by the desired output power of the Doherty amplifier.

[0013] The input signal, which is a high-frequency signal to be amplified, is input to the input terminal 100. A Doherty amplified signal in which cell output signals output from each of a plurality of Doherty amplifier cells 11 and 12 are combined is output to an output terminal 200.

[0014] A carrier amplifier 11 has an input node electrically connected to a carrier input pad 11a and an output node electrically connected to a carrier output pad 11b. The carrier amplifier 11 operates in class AB or class B. The carrier amplifier 11 is provided with a signal amplification element (a carrier transistor), and the carrier transistor 11 is a high-breakdown-voltage transistor having a source field plate of a GaN HEMT (High Electron Mobility Transistor) using gallium nitride (GaN).

[0015] Note that the carrier transistor 11 may use a transistor such as a field effect transistor (FET), a heterojunction bipolar transistor (HBT), or a high electron mobility transistor (HEMT).

[0016] In the carrier transistor 11, a gate electrode is electrically connected to the carrier input pad 11a as an input node, a drain electrode is electrically connected to the carrier output pad 11b as an output node, and a source electrode is connected to a ground node. The carrier output pad 11b is connected to a drain voltage supply node, and a drain voltage is supplied from the drain voltage supply node to the drain electrode of the carrier transistor 11 via the carrier output pad 11b.

[0017] The carrier input pad, to which the gate electrode of the carrier transistor 11 is connected, is connected to a carrier gate voltage application node, and a gate voltage is applied from the carrier gate voltage application node to the gate electrode of the carrier transistor 11 via the carrier input pad, so that the carrier transistor 11 can operate in class AB or class B. The size of the carrier transistor 11 is determined in conjunction with the number of Doherty amplifier cells 1 set, based on the output power to be obtained as a Doherty amplifier.

[0018] The peak amplifier 12 has its input node electrically connected to the peak input pad 12a, and its output node electrically connected to the peak output pad 12b. The peak amplifier 12 operates in Class C mode. The peak amplifier 12 is equipped with a signal amplification element (peak transistor), and the peak transistor 12 is a high-voltage transistor made of GaNHEMT. The peak transistor 12 may be a field-effect transistor, a heterojunction bipolar transistor, a high electron mobility transistor, or other types of transistors.

[0019] In the peak transistor 12, the gate electrode is electrically connected to the peak input pad 12a as an input node, the drain electrode is electrically connected to the peak output pad 12b as an output node, and the source electrode is connected to the ground node. The peak output pad 12b is connected to the drain voltage supply node, and the drain voltage is supplied from the drain voltage supply node to the drain electrode of the peak transistor 12 via the peak output pad 12b.

[0020] The peak input pad to which the gate electrode of the peak transistor 12 is connected is connected to the peak gate voltage application node, and a gate voltage is applied to the gate electrode of the peak transistor 12 from the peak gate voltage application node via the peak input pad so that the peak transistor 12 operates in class C.

[0021] The size of the peak transistor 12 is determined in conjunction with the number of Doherty amplifier cells 1 set, based on the output power to be obtained as a Doherty amplifier. The carrier transistor 11 and the peak transistor 12 are each mounted as GaNHEMTs on a GanmMIC (Monolithic Microwave Integrated Circuit) and integrated, forming on the same chip.

[0022] All of the carrier transistors 11 and peak transistors 12 in multiple Doherty amplifier cells 1 may be formed on the same chip. When all of the carrier transistors 11 and peak transistors 12 in multiple Doherty amplifier cells 1 are formed on the same chip, the carrier transistors 11 and peak transistors 12 are arranged alternately in parallel.

[0023] The cell input distribution circuit 13 has a cell input terminal 13a that is electrically connected to the input terminal 100 and receives the input signal input to the input terminal 100, a carrier output terminal 13b that is electrically connected to the carrier input pad 11a, and a peak output terminal 13c that is electrically connected to the peak input pad 12a. The cell input distribution circuit 13 distributes the input signal input to the cell input terminal 13a to the carrier output terminal 13b and the peak output terminal 13c and outputs them.

[0024] The cell input distribution circuit 13 has the functions of a matching circuit and a phase adjustment line, and also has the function of distributing the input signal input to the cell input terminal 13a to the carrier input pad 11a and the peak input pad 12a and outputting them. The cell input distribution circuit 13 is implemented in the GaNMMIC.

[0025] The cell input distribution circuit 13 may be formed on the same chip as the carrier transistor 11 and the peak transistor 12. The input distribution circuits 13, carrier transistors 11, and peak transistors 12 within each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier output terminal 13b and the carrier input pad 11a, and the electrical connection between the peak output terminal 13c and the peak input pad 12a are each made by a conductive layer formed on the same chip.

[0026] Furthermore, if the cell input distribution circuit 13 and the carrier transistor 11 and peak transistor 12 are formed on different chips, the electrical connection between the carrier output terminal 13b and the carrier input pad 11a, and the electrical connection between the peak output terminal 13c and the peak input pad 12a are performed by bonding wires, respectively. The electrical connection between the input terminal 100 and the cell input terminal 13a is made by a conductive layer or bonding wire.

[0027] Since all of the Doherty amplifier cells 1 have the same circuit configuration and size, the electrical length from the cell input terminal 13a to the carrier input pad 11a of the cell input distribution circuit 13 in each Doherty amplifier cell 1 is equal for all of the Doherty amplifier cells 1. Furthermore, the electrical length from the cell input terminal 13a to the peak input pad 12a of the cell input distribution circuit 13 in each Doherty amplifier cell 1 is equal for all of the multiple Doherty amplifier cells 1.

[0028] The cell output synthesis circuit 14 has a carrier input terminal 14b electrically connected to the carrier output pad 11b, a peak input terminal 14c electrically connected to the peak output pad 12b, and a cell output terminal 14a electrically connected to the output terminal 200 from which the Doherty amplified signal is output. The cell output synthesis circuit 14 synthesizes the carrier amplified output signal output to the carrier output pad 11b and the peak amplified output signal output to the peak output pad 12b to output the cell output signal to the cell output terminal 14a.

[0029] The cell output synthesis circuit 14 has the functions of a matching circuit and a phase adjustment line, and the function of synthesizing the carrier amplified output signal output to the carrier output pad 11b and the peak amplified output signal output to the peak output pad 12b to output the cell output signal to the cell output terminal 14a. The in-cell output synthesis circuit 14 is implemented in the Ganmmic Microcontroller (GaNMMIC).

[0030] The cell output synthesis circuit 14 may be formed on the same chip as the carrier transistor 11 and the peak transistor 12. The output combining circuit 14, carrier transistor 11, peak transistor 12, and input distribution circuit 13 within each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier input terminal 14b and the carrier output pad 11b, and the electrical connection between the peak input terminal 14c and the peak output pad 12b are each made by a conductive layer formed on the same chip.

[0031] Furthermore, if the cell output synthesis circuit 14 and the carrier transistor 11 and peak transistor 12 are formed on different chips, the electrical connection between the carrier input terminal 14b and the carrier output pad 11b, and the electrical connection between the peak input terminal 14c and the peak output pad 12b are performed by bonding wires, respectively. The electrical connection between output terminal 200 and cell output terminal 14a is made by a conductive layer or bonding wire.

[0032] Since all of the Doherty amplifier cells 1 have the same circuit configuration and size, the electrical length from the carrier output pad 11b to the cell output terminal 14a of the intra-cell output combining circuit 14 in each Doherty amplifier cell 1 is equal for all of the Doherty amplifier cells 1. Furthermore, the electrical length from the peak output pad 12b in each Doherty amplifier cell 1 to the cell output terminal 14a of the cell output summing circuit 14 is equal for all of the Doherty amplifier cells 1.

[0033] Next, the operation of the Doherty amplifier according to Embodiment 1 will be described. The operating principle of the Doherty amplifier will be omitted as it is assumed to be known. The input signal input to input terminal 100 is input to the cell input terminals 13a1 and 13a2 in the cell-specific input distribution circuits 131 and 132 of the multiple Doherty amplifier cells 11 and 12. In each Doherty amplifier cell 11, 12, the input signals input to the cell input terminals 13a1, 13a2 are distributed by the cell input distribution circuits 131, 132 and output from the carrier output terminals 13b1, 13b2 and the peak output terminals 13c1, 13c2.

[0034] In each Doherty amplifier cell 11, 12, the input signals output from the carrier output terminals 13b1, 13b2 are input to the input node (gate electrode) of the carrier transistor 11 via the carrier input pads 11a1, 11a2. Furthermore, in each Doherty amplifier cell 11 and 12, the input signals output from the peak output terminals 13c1 and 13c2 are input to the input node (gate electrode) of the peak transistor 12 via the peak input pads 12a1 and 12a2.

[0035] The electrical length from the cell input terminal 13a1 of the cell input distribution circuit 131 in Doherty amplifier cell 11 to the carrier input pad 11a1 is equal to the electrical length from the cell input terminal 13a2 of the cell input distribution circuit 132 in Doherty amplifier cell 12 to the carrier input pad 11a2. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, for all Doherty amplifier cells 1, the electrical length from the cell input terminal 13a of the cell input distribution circuit 13 to the carrier input pad 11a is the same.

[0036] The electrical length from the cell input terminal 13a1 to the peak input pad 12a1 of the cell input distribution circuit 131 in Doherty amplifier cell 11 is equal to the electrical length from the cell input terminal 13a2 to the peak input pad 12a2 of the cell input distribution circuit 132 in Doherty amplifier cell 12. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, for all Doherty amplifier cells 1, the electrical length from the cell input terminal 13a of the cell input distribution circuit 13 to the peak input pad 12a is the same. Therefore, there is no difference in the distribution path for the input signal at the input side of multiple Doherty amplifier cells 1, and there is no decrease in the performance (efficiency) of the Doherty amplifier.

[0037] In each Doherty amplifier cell 11, 12, the input signal input to the input nodes of the carrier transistors 111, 112 is amplified by the carrier transistors 111, 112, and the amplified carrier output signal is input from the output nodes (drain electrodes) of the carrier transistors 111, 112 to the carrier input terminals 14b1, 14b2 of the cell output combining circuits 141, 142 via the carrier output pads 11b1, 11b2.

[0038] Meanwhile, in each Doherty amplifier cell 11, 12, the input signal input to the input nodes of the peak transistors 121, 122 is amplified by the peak transistors 121, 122, and the peak amplified output signal is input from the output nodes (drain electrodes) of the peak transistors 121, 122 to the peak input terminals 14c1, 14c2 of the cell output combining circuits 141, 142 via the peak output pads 12b1, 12b2.

[0039] In each Doherty amplifier cell 11, 12, the carrier amplified output signal input to the carrier input terminals 14b1, 14b2 and the peak amplified output signal input to the peak input terminals 14c1, 14c2 are combined by the cell output combining circuits 141, 142 and output as a cell output signal to the cell output terminals 14a1, 14a2. The cell output signals output from the respective cell output terminals 14a1 and 14a2 of each Doherty amplifier cell 11 and 12 are combined and output from output terminal 200.

[0040] The electrical length from the carrier output pad 11b1 in Doherty amplifier cell 11 to the cell output terminal 14a1 of the cell output combining circuit 141 is equal to the electrical length from the carrier output pad 11b2 in Doherty amplifier cell 12 to the cell output terminal 14a2 of the cell output combining circuit 142. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, the electrical length from the carrier output pad 11b to the cell output terminal 14a of the intra-cell output combining circuit 14 is the same for all Doherty amplifier cells 1.

[0041] The electrical length from the peak output pad 12b1 in Doherty amplifier cell 11 to the cell output terminal 14a1 of the cell output combining circuit 141 is equal to the electrical length from the peak output pad 12b2 in Doherty amplifier cell 12 to the cell output terminal 14a2 of the cell output combining circuit 142. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, for all Doherty amplifier cells 1, the electrical length from the peak output pad 12b to the cell output terminal 14a of the cell output combining circuit 14 is the same. Therefore, at the output side of multiple Doherty amplifier cells 1, there is no difference in the paths for combining the carrier amplified output signal and the peak amplified output signal, and there is no decrease in the performance (efficiency) of the Doherty amplifier.

[0042] The Doherty amplifier according to Embodiment 1 has multiple Doherty amplifier cells 11 and 12 arranged in parallel. Each Doherty amplifier cell 11 and 12 includes carrier amplifiers 111 and 112 and peak amplifiers 121 and 122, as well as intra-cell input distribution circuits 131 and 132 that distribute the input signal to the carrier amplifiers 111 and 112 and the peak amplifiers 121 and 122, and intra-cell output combining circuits 141 and 142 that combine the carrier amplified output signals from the carrier amplifiers 111 and 112 and the peak amplified output signals from the peak amplifiers 121 and 122 and output them as a cell output signal. As a result, there is no difference in electrical length between the input and output sides of the multiple Doherty amplifier cells 11 and 12, there is no decrease in the performance (efficiency) of the Doherty amplifier, and power efficiency is improved.

[0043] Furthermore, the Doherty amplifier according to Embodiment 1 is configured to house multiple Doherty amplifier cells 11 and 12 in a single package and has an input terminal 100 and an output terminal 200, thereby providing a Doherty amplifier that is easy to handle.

[0044] Embodiment 2. The Doherty amplifier according to Embodiment 2 will be described with reference to Figures 2 to 5.

[0045] The Doherty amplifier according to Embodiment 2 differs from the Doherty amplifier according to Embodiment 1 in that the bias circuits for applying gate bias to the respective input nodes (gate electrodes) of the carrier amplifiers 111 and 112 and peak amplifiers 121 and 122 of the Doherty amplifier cells 11 and 12 are configured independently, but all other aspects are the same. Therefore, the explanation will focus on the bias circuit used to provide gate bias. In Figures 2 to 5, the same reference numerals as those used in Figure 1 indicate the same or equivalent parts.

[0046] The Doherty amplifier according to Embodiment 2, as shown in Figure 2, is a Doherty amplifier in which a plurality of Doherty amplifier cells 1, each having a carrier amplifier 11 and a peak amplifier 12, are arranged in parallel. Each Doherty amplifier cell 1 further includes an in-cell input distribution circuit 23 that distributes the input signal to the input side of the carrier amplifier 11 and the peak amplifier 12, an in-cell output combining circuit 24 that combines the carrier amplified output signal from the carrier amplifier 11 and the peak amplified output signal from the peak amplifier 12 to the output side of the carrier amplifier 11 and the peak amplifier 12, an input distribution circuit 31, a carrier gate bias application circuit 32, a peak gate bias application circuit 33, and an output combining circuit 40.

[0047] Figure 2 shows two Doherty amplifier cells 1, with the first Doherty amplifier cell 1 denoted by the subscript 1 and the second Doherty amplifier cell 1 denoted by the subscript 2. The first Doherty amplifier cell 11 and the second Doherty amplifier cell 12 have the same circuit configuration and size. Therefore, in the description of the first Doherty amplifier cell 11 and the second Doherty amplifier cell 12, subscripts will be omitted and they will be described as having a common configuration in order to avoid complexity in the explanation.

[0048] Furthermore, there may be three or more Doherty amplifier cells 1. Even if there are three or more Doherty amplifier cells 1, each Doherty amplifier cell 1 n (n≧3) represents circuits with the same configuration and size. The number of Doherty amplifier cells 1 is determined by the desired output power of the Doherty amplifier.

[0049] The first input terminal 101 receives the input signal, which is a high-frequency signal to be amplified, and the gate bias voltage Vgc for the carrier transistor 11 that constitutes the carrier amplifier 11. The second input terminal 102 receives the input signal and the gate bias voltage Vgp for the peak transistor 12 that constitutes the peak amplifier 12. The Doherty amplified signal, which is a composite of the cell output signals output from each of the multiple Doherty amplifier cells 11 and 12, is output to output terminals 201 and 202.

[0050] The cell input distribution circuit 23 has a carrier-side input circuit 231, a peak-side input circuit 232, and a DC blocking capacitor 233. A DC blocking capacitor 233 is electrically connected between the cell input terminal 23a and the carrier-side input circuit 231 and the peak-side input circuit 232. For example, as shown in Figures 3 and 4, the DC blocking capacitor 233 is configured as a capacitor with one end of the carrier-side input circuit 231 as one electrode, and a dielectric material between it and the other end of the peak-side input circuit 232, with the other electrode being the other electrode. One electrode of the DC blocking capacitor 233 is electrically connected to the cell input terminal 23a.

[0051] Furthermore, the DC blocking capacitance 233 may have a capacitor 233a connected between the cell input terminal 23a and one end of the carrier-side input circuit 231, and a capacitor 233b connected between the cell input terminal 23a and one end of the peak-side input circuit 232, as shown in Figure 5. In any case, the DC blocking capacitor 233 is short-circuited to the input signal, which is a high-frequency signal input to the cell input terminal 23a, and distributes the input signal input to the cell input terminal 23a to both the carrier-side input circuit 231 and the peak-side input circuit 232. On the other hand, the DC blocking capacitor 233 blocks (opens DC-wise) the connection between the carrier-side input circuit 231 and the peak-side input circuit 232 with respect to DC. In other words, the cell input terminal 23a has the function of being open in terms of DC.

[0052] The carrier-side input circuit 231 is AC-connected between the cell input terminal 23a and the carrier output terminal 23b, and has a carrier gate bias terminal 23d to which the gate bias voltage Vgc is applied to the carrier transistor 11. The peak input circuit 232 is AC-connected between the cell input terminal 23a and the peak output terminal 23c, and has a peak gate bias terminal 23e to which the gate bias voltage Vgp is applied to the peak transistor 12.

[0053] The carrier-side input circuit 231 and the peak-side input circuit 232 each have the functions of a matching circuit and a phase adjustment line. The carrier-side input circuit 231, the peak-side input circuit 232, and the DC blocking capacitor 233 are each implemented in the GaNMMIC.

[0054] The cell input distribution circuit 23 may be formed on the same chip as the carrier transistor 11 and the peak transistor 12. In multiple Doherty amplifier cells 1, the input distribution circuits 23 within each cell, the carrier transistor 11, and the peak transistor 12 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier output terminal 23b and the carrier input pad 11a, and the electrical connection between the peak output terminal 23c and the peak input pad 12a are each made by a conductive layer formed on the same chip.

[0055] Furthermore, if the cell input distribution circuit 23 and the carrier transistor 11 and peak transistor 12 are formed on different chips, the electrical connection between the carrier output terminal 23b and the carrier input pad 11a, and the electrical connection between the peak output terminal 23c and the peak input pad 12a are made by bonding wires.

[0056] Since all of the Doherty amplifier cells 1 have the same circuit configuration and size, the electrical length from the cell input terminal 13a to the carrier input pad 11a of the cell input distribution circuit 13 in each Doherty amplifier cell 1 is equal for all of the Doherty amplifier cells 1. Furthermore, the electrical length from the cell input terminal 13a to the peak input pad 12a of the cell input distribution circuit 13 in each Doherty amplifier cell 1 is equal for all of the multiple Doherty amplifier cells 1.

[0057] The cell output synthesis circuit 24 is composed of matching circuits. The cell output combining circuit 24 has a carrier input terminal 24b electrically connected to the carrier output pad 11b, a peak input terminal 24c electrically connected to the peak output pad 12b, and a cell output terminal 24a. The cell output synthesis circuit 24 synthesizes the carrier amplified output signal output to the carrier output pad 11b and the peak amplified output signal output to the peak output pad 12b to output the cell output signal to the cell output terminal 24a.

[0058] The in-cell output synthesis circuit 24 is implemented in the Ganmmic Microcontroller (GaNMMIC). The in-cell output synthesis circuit 24 may be formed on the same chip as the carrier transistor 11 and the peak transistor 12. The output combining circuit 24, carrier transistor 11, peak transistor 12, and input distribution circuit 23 within each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier input terminal 24b and the carrier output pad 11b, and the electrical connection between the peak input terminal 24c and the peak output pad 12b are each made by a conductive layer formed on the same chip.

[0059] Furthermore, if the cell output synthesis circuit 24 and the carrier transistor 11 and peak transistor 12 are formed on different chips, the electrical connection between the carrier input terminal 24b and the carrier output pad 11b, and the electrical connection between the peak input terminal 24c and the peak output pad 12b are performed by bonding wires, respectively.

[0060] Since all of the Doherty amplifier cells 1 have the same circuit configuration and size, the electrical length from the carrier output pad 11b to the cell output terminal 24a of the cell output combining circuit 24 in each Doherty amplifier cell 1 is equal for all of the Doherty amplifier cells 1. Furthermore, the electrical length from the peak output pad 12b in each Doherty amplifier cell 1 to the cell output terminal 24a of the cell output summing circuit 24 is equal for all of the Doherty amplifier cells 1.

[0061] The input distribution circuit 31 is connected to the first input terminal 101 and the second input terminal 102, and is connected to the cell input terminals 23a1 and 23a2. The input distribution circuit 31 has the function of being DC-open to the first input terminal 101 and the second input terminal 102. The input distribution circuit 31 distributes the input signal input to the first input terminal 101 and the input signal input to the second input terminal 102 to the cell input terminals 23a1 and 23a2 and outputs them.

[0062] Since the input distribution circuit 31 has the function of being DC-open with respect to the first input terminal 101, the gate bias voltage Vgc input to the first input terminal 101 is not transmitted to the cell input terminal 23a. Furthermore, since the input distribution circuit 31 has the function of being DC-open to the second input terminal 102, the gate bias voltage Vgp input to the second input terminal 102 is not transmitted to the cell input terminal 23a. The input distribution circuit 31 uses either a Wilkinson combiner / distributor or a 90° hybrid circuit.

[0063] The electrical connections between the input distribution circuit 31 and the first input terminal 101 and the second input terminal 102 are made by bonding wires. The electrical connections between the input distribution circuit 31 and the cell input terminals 23a1 and 23a2 are made by bonding wires. The input distribution circuit 31 is implemented in the Ganmmic microphone. The input distribution circuit 31 may be formed on the same chip as the multiple Doherty amplifier cells 11 and 12.

[0064] The carrier gate bias application circuit 32 is connected to the first input terminal 101 and to the carrier-side input circuits 2311 and 2312 in the cell input distribution circuits 231 and 232, respectively. The carrier gate bias application circuit 32 applies the gate bias voltage Vgc applied to the carrier amplifiers 111 and 112, which are applied to the first input terminal 101, to the carrier-side input circuits 2311 and 2312 of the intra-cell input distribution circuits 231 and 232 in each of the multiple Doherty amplifier cells 11 and 12.

[0065] In Embodiment 2, the carrier gate bias application circuit 32 is a capacitance, with one electrode electrically connected to the first input terminal 101, the carrier-side input circuit 2311 (carrier gate bias terminal 23d1), and the carrier-side input circuit 2312 (carrier gate bias terminal 23d2) by bonding wires, and the other electrode being grounded.

[0066] A low-pass filter is formed by a bonding wire connecting the first input terminal 101 and the carrier gate bias application circuit 32, a capacitance in the carrier gate bias application circuit 32, and a bonding wire connecting the carrier gate bias application circuit 32 and the carrier-side input circuit 2311. As a result, the input signal input to the first input terminal 101 is AC-open due to the carrier gate bias application circuit 32, and therefore is not transmitted to the carrier-side input circuit 2311. The gate bias voltage Vgc applied to the first input terminal 101 is transmitted to the carrier-side input circuit 2311 via the carrier gate bias application circuit 32 and applied to the gate electrode of the carrier amplifier 111.

[0067] Similarly, a low-pass filter is formed by a bonding wire connecting the first input terminal 101 and the carrier gate bias application circuit 32, a capacitance in the carrier gate bias application circuit 32, and a bonding wire connecting the carrier gate bias application circuit 32 and the carrier-side input circuit 2312. As a result, the input signal input to the first input terminal 101 is AC-open due to the carrier gate bias application circuit 32, and therefore is not transmitted to the carrier-side input circuit 2312. The gate bias voltage Vgc applied to the first input terminal 101 is transmitted to the carrier-side input circuit 2312 via the carrier gate bias application circuit 32 and applied to the gate electrode of the carrier amplifier 112.

[0068] The carrier gate bias application circuit 32 is implemented in the GaNMMIC. The carrier gate bias application circuit 32 may be formed on the same chip as the multiple Doherty amplifier cells 11 and 12.

[0069] The peak gate bias application circuit 33 is connected to the second input terminal 102 and to the peak-side input circuits 2321 and 2322 in the cell's input distribution circuits 231 and 232, respectively. The peak gate bias application circuit 33 applies the gate bias voltage Vgp applied to the peak amplifiers 121 and 122, which are applied to the second input terminal 102, to the peak-side input circuits 2321 and 2322 of the intra-cell input distribution circuits 231 and 232 in each of the multiple Doherty amplifier cells 11 and 12.

[0070] In Embodiment 2, the peak gate bias application circuit 33 is a capacitance, with one electrode electrically connected to the second input terminal 102, the peak-side input circuit 2321 (peak gate bias terminal 23e1), and the peak-side input circuit 2322 (peak gate bias terminal 23e2) by bonding wires, and the other electrode being grounded.

[0071] A low-pass filter is formed by a bonding wire connecting the second input terminal 102 and the peak gate bias application circuit 33, a capacitance in the peak gate bias application circuit 33, and a bonding wire connecting the peak gate bias application circuit 33 and the peak-side input circuit 2321. As a result, the input signal input to the second input terminal 102 is AC-open due to the peak gate bias application circuit 33, and therefore is not transmitted to the peak-side input circuit 2321. The gate bias voltage Vgp applied to the second input terminal 102 is transmitted to the peak-side input circuit 2321 via the peak gate bias application circuit 33 and applied to the gate electrode of the peak amplifier 121.

[0072] Similarly, a low-pass filter is formed by a bonding wire connecting the second input terminal 102 and the peak gate bias application circuit 33, a capacitance in the peak gate bias application circuit 33, and a bonding wire connecting the peak gate bias application circuit 33 and the peak-side input circuit 2322. As a result, the input signal input to the second input terminal 102 is AC-open due to the peak gate bias application circuit 33, and therefore is not transmitted to the peak-side input circuit 2322. The gate bias voltage Vgp applied to the second input terminal 102 is transmitted to the peak-side input circuit 2322 via the peak gate bias application circuit 33 and applied to the gate electrode of the peak amplifier 122.

[0073] The peak gate bias application circuit 33 is implemented in the GaNMMIC. The peak gate bias application circuit 33 may be formed on the same chip as the multiple Doherty amplifier cells 11 and 12.

[0074] The output combining circuit 40 is electrically connected to the cell output terminals 24a1 and 24a2, and to the output terminals 201 and 202. The output combining circuit 40 combines the cell output signal from the cell output terminal 24a1 of the Doherty amplifier cell 11 and the cell output signal from the cell output terminal 24a2 of the Doherty amplifier cell 12, and outputs the resulting Doherty amplified signal to output terminals 201 and 202. The output combining circuit 40 uses either a Wilkinson combiner / distributor or a 90° hybrid circuit.

[0075] Next, the operation of the Doherty amplifier according to Embodiment 2 will be described. The operating principle of the Doherty amplifier will be omitted as it is assumed to be known. The input signal and gate bias voltage Vgc input to the first input terminal 101 are input to the input distribution circuit 31 and the carrier gate bias application circuit 32. The input signal and gate bias voltage Vgp input to the second input terminal 102 are input to the input distribution circuit 31 and the peak gate bias application circuit 33.

[0076] In the input distribution circuit 31, the input signal input to the first input terminal 101 and the input signal input to the second input terminal 102 are combined and input to the cell input terminals 23a1 and 232 in the cell-specific input distribution circuits 131 and 132 of the multiple Doherty amplifier cells 11 and 12.

[0077] Since the input distribution circuit 31 has the function of being DC-open to the first input terminal 101 and the second input terminal 102, the gate bias voltage Vgc input to the first input terminal 101 and the gate bias voltage Vgp input to the second input terminal 102 are not transmitted to the cell input terminal 23a.

[0078] Furthermore, DC blocking capacitors 2331 and 2332 are connected to the cell input terminals 23a1 and 23a2, and the cell input terminals 23a1 and 23a2 have the function of being DC-open. As a result, the gate bias voltage Vgc and gate bias voltage Vgp are blocked by the DC blocking capacitors 2331 and 2332 and are not transmitted to the carrier-side input circuits 2311 and 2312 and the peak-side input circuits 2321 and 2322.

[0079] In other words, the gate bias voltage Vgc input to the first input terminal 101 is not transmitted to the input nodes (gate electrodes) of the peak transistors 121 and 122 via the input distribution circuit 31, the cell input terminals 23a1 and 23a2, and the peak input circuits 2321 and 2322. Furthermore, the gate bias voltage Vgp input to the second input terminal 102 is not transmitted to the input nodes (gate electrodes) of the carrier transistors 111 and 112 via the input distribution circuit 31, the cell input terminals 23a1 and 23a2, and the carrier-side input circuits 2311 and 2312.

[0080] In each Doherty amplifier cell 11, 12, the input signals, which are combined by the input distribution circuit 31 and input to the cell input terminals 23a1, 232, are distributed by the cell's internal input distribution circuits 231, 232 and output from the carrier output terminals 23b1, 23b2 and the peak output terminals 23c1, 23c2.

[0081] In each Doherty amplifier cell 11, 12, the input signals output from the carrier output terminals 23b1, 23b2 are input to the input nodes (gate electrodes) of the carrier transistors 111, 112 via the carrier input pads 11a1, 11a2. Furthermore, in each Doherty amplifier cell 11, 12, the input signals output from the peak output terminals 23c1, 23c2 are input to the input nodes (gate electrodes) of the peak transistors 121, 122 via the peak input pads 12a1, 12a2.

[0082] In the carrier gate bias application circuit 32, the input signal and gate bias voltage Vgc input to the first input terminal 101 are AC-open by the carrier gate bias application circuit 32. Therefore, the input signal is not transmitted to the carrier-side input circuits 2311 and 2312 in the respective cell-internal input distribution circuits 131 and 132 of the multiple Doherty amplifier cells 11 and 12, and the gate bias voltage Vgc is transmitted to the carrier-side input circuits 2311 and 2312.

[0083] In each Doherty amplifier cell 11, 12, the gate bias voltage Vgc transmitted to the carrier-side input circuits 2311, 2312 is applied from the carrier output terminals 23b1, 23b2 to the input nodes (gate electrodes) of the carrier transistors 111, 112 via the carrier input pads 11a1, 11a2. The gate bias voltage Vgc is blocked by DC blocking capacitors 2331 and 2332, which are connected to the cell input terminals 23a1 and 232, and is therefore not transmitted to the peak-side input circuits 2321 and 2322.

[0084] In the peak gate bias application circuit 33, the input signal and gate bias voltage Vgp input to the second input terminal 102 are AC-open by the peak gate bias application circuit 33. Therefore, the input signal is not transmitted to the peak-side input circuits 2321 and 2322 in the respective cell-internal input distribution circuits 131 and 132 of the multiple Doherty amplifier cells 11 and 12, and the gate bias voltage Vgp is transmitted to the peak-side input circuits 2321 and 2322.

[0085] In each Doherty amplifier cell 11, 12, the gate bias voltage Vgp transmitted to the peak input circuits 2321, 2322 is applied from the peak output terminals 23c1, 23c2 to the input nodes (gate electrodes) of the peak transistors 121, 122 via the peak input pads 12a1, 12a2. The gate bias voltage Vgp is blocked by DC blocking capacitors 2331 and 2332, which are connected to the cell input terminals 23a1 and 232, and is therefore not transmitted to the carrier side input circuits 2311 and 2312.

[0086] The carrier transistors 111 and 112 have a gate bias voltage Vgc applied to them and operate in class AB or class B, amplifying the input signal and outputting the amplified carrier output signal to the carrier output pads 11b1 and 11b2. The peak transistors 121 and 122 have a gate bias voltage Vgp applied to them and operate in class C, amplifying the input signal and outputting the peak amplified output signal to the peak output pads 12b1 and 12b2.

[0087] The electrical length from the cell input terminal 23a1 of the cell input distribution circuit 231 in Doherty amplifier cell 11 to the carrier input pad 11a1 is equal to the electrical length from the cell input terminal 13a2 of the cell input distribution circuit 232 in Doherty amplifier cell 12 to the carrier input pad 11a2. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, for all of the Doherty amplifier cells 1, the electrical length from the cell input terminal 23a of the cell input distribution circuit 23 to the carrier input pad 11a is the same.

[0088] The electrical length from the cell input terminal 23a1 of the cell input distribution circuit 231 in Doherty amplifier cell 11 to the peak input pad 12a1 is equal to the electrical length from the cell input terminal 23a2 of the cell input distribution circuit 232 in Doherty amplifier cell 12 to the peak input pad 12a2. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, for all Doherty amplifier cells 1, the electrical length from the cell input terminal 23a of the cell input distribution circuit 23 to the peak input pad 12a is the same. Therefore, there is no difference in the distribution path for the input signal at the input side of multiple Doherty amplifier cells 1, and there is no decrease in the performance (efficiency) of the Doherty amplifier.

[0089] In each Doherty amplifier cell 11, 12, the input signal input to the input nodes of the carrier transistors 111, 112 is amplified by the carrier transistors 111, 112, and the amplified carrier output signal is input from the output nodes (drain electrodes) of the carrier transistors 111, 112 to the carrier input terminals 24b1, 24b2 of the cell output combining circuits 241, 242 via the carrier output pads 11b1, 11b2.

[0090] Meanwhile, in each Doherty amplifier cell 11, 12, the input signal input to the input node of the peak transistors 121, 122 is amplified by the peak transistors 121, 122, and the peak amplified output signal is sent from the output node (drain electrode) of the peak transistors 121, 122 via the peak output pads 12b1, 12b2 to the cell output combining circuit 241, 2 The signal is input to the peak input terminals 24c1 and 24c2 of the 42.

[0091] In each Doherty amplifier cell 11, 12, the carrier amplified output signal input to the carrier input terminals 24b1, 24b2 and the peak amplified output signal input to the peak input terminals 24c1, 24c2 are combined by the cell output combining circuits 241, 242 and output as a cell output signal to the cell output terminals 24a1, 24a2.

[0092] The cell output signals output from the respective cell output terminals 24a1 and 24a2 of each Doherty amplifier cell 11 and 12 are combined by the output combining circuit 40 and output as a Doherty amplified signal from output terminals 201 and 202. Although two output terminals, 201 and 202, are shown, one output terminal may be used, as in Embodiment 1.

[0093] The electrical length from the carrier output pad 11b1 in Doherty amplifier cell 11 to the cell output terminal 24a1 of the cell output combining circuit 241 is equal to the electrical length from the carrier output pad 11b2 in Doherty amplifier cell 12 to the cell output terminal 24a2 of the cell output combining circuit 242. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, the electrical length from the carrier output pad 11b to the cell output terminal 24a of the cell output combining circuit 24 is the same for all Doherty amplifier cells 1.

[0094] The electrical length from the peak output pad 12b1 in Doherty amplifier cell 11 to the cell output terminal 24a1 of the cell output combining circuit 241 is equal to the electrical length from the peak output pad 12b2 in Doherty amplifier cell 12 to the cell output terminal 24a2 of the cell output combining circuit 242. Although Doherty amplifier cell 11 and Doherty amplifier cell 12 have been described as examples, the electrical length from the peak output pad 12b to the cell output terminal 24a of the cell output combining circuit 24 is the same for all Doherty amplifier cells 1. Therefore, at the output side of multiple Doherty amplifier cells 1, there is no difference in the paths for combining the carrier amplified output signal and the peak amplified output signal, and there is no decrease in the performance (efficiency) of the Doherty amplifier.

[0095] The Doherty amplifier according to Embodiment 2 has multiple Doherty amplifier cells 11 and 12 arranged in parallel. Each Doherty amplifier cell 11 and 12 includes carrier amplifiers 111 and 112 and peak amplifiers 121 and 122, as well as intra-cell input distribution circuits 231 and 232 that distribute the input signal to the carrier amplifiers 111 and 112 and the peak amplifiers 121 and 122, and intra-cell output combining circuits 241 and 242 that combine the carrier amplified output signals from the carrier amplifiers 111 and 112 and the peak amplified output signals from the peak amplifiers 121 and 122 and output them as a cell output signal. As a result, there is no difference in electrical length between the input and output sides of the multiple Doherty amplifier cells 11 and 12, there is no decrease in the performance (efficiency) of the Doherty amplifier, and power efficiency is improved.

[0096] Furthermore, the Doherty amplifier according to Embodiment 2 has cell input distribution circuits 231 and 232 having carrier-side input circuits 2311 and 2312 and peak-side input circuits 2321 and 2322, and DC blocking capacitors 2331 and 2332 to AC short-circuit and DC open-circuit between the carrier-side input circuits 2311 and 2312 and the peak-side input circuits 2321 and 2322, and the input signal and the gate bias voltage Vgc for carrier transistors 111 and 112 and the gate bias voltage Vgp for peak transistors 121 and 122 are input to the cell input terminal 2, to which the DC blocking capacitors 2331 and 2332 are connected. The system includes an input distribution circuit 31 that outputs to 3a1 and 232, a carrier gate bias application circuit 32 that receives the input signal and gate bias voltage Vgc and applies the gate bias voltage Vgc to the carrier-side input circuits 2311 and 2312, and a peak gate bias application circuit 33 that receives the input signal and gate bias voltage Vgp and applies the gate bias voltage Vgp to the peak-side input circuits 2321 and 2322. As such, independent gate bias voltages Vgc and Vgp can be applied to the carrier amplifiers 111 and 112 and the peak amplifiers 121 and 122 in multiple Doherty amplifier cells 11 and 12.

[0097] Furthermore, the Doherty amplifier according to Embodiment 2 houses a plurality of Doherty amplifier cells 11, 12, an input distribution circuit 31, a carrier gate bias application circuit 32, a peak gate bias application circuit 33, and an output combining circuit 40 in a single package, and has a configuration with two input terminals, a first input terminal 101 and a second input terminal 102, and one output terminal, thereby providing a Doherty amplifier that is easy to handle.

[0098] Furthermore, it is possible to freely combine the embodiments, modify any component of each embodiment, or omit any component of each embodiment. [Industrial applicability]

[0099] The Doherty amplifier of this disclosure is suitable as an amplifier for communications in mobile radio terminals and mobile base stations in mobile communication infrastructure. [Explanation of Symbols]

[0100] 11, 12 Doherty amplifier cells, 111, 112 carrier amplifiers, 121, 122 peak amplifiers, 131, 132, 231, 232 cell input distribution circuits, 141, 142, 241, 242 cell output combining circuits, 2311, 2312 carrier-side input circuits, 2321, 2322 peak-side input circuits, 2331, 2332 DC blocking capacitors, 31 input distribution circuit, 32 carrier gate bias application circuit, 33 peak gate bias application circuit, 40 output combining circuit.

Claims

1. Multiple Doherty amplifier cells are arranged in parallel. Each Doherty amplifier cell is: A carrier amplifier in which the input node is electrically connected to a carrier input pad and the output node is electrically connected to a carrier output pad, A peak amplifier in which the input node is electrically connected to a peak input pad and the output node is electrically connected to a peak output pad, An in-cell input distribution circuit has a cell input terminal into which an input signal is input, a carrier output terminal electrically connected to the carrier input pad, and a peak output terminal electrically connected to the peak input pad, and distributes the input signal input to the cell input terminal to the carrier output terminal and the peak output terminal for output. The cell comprises an in-cell output combining circuit having a carrier input terminal electrically connected to the carrier output pad, a peak input terminal electrically connected to the peak output pad, and a cell output terminal, which combines the carrier amplified output signal output to the carrier output pad and the peak amplified output signal output to the peak output pad to output a cell output signal to the cell output terminal, The cell-internal input distribution circuit comprises: a carrier-side input circuit AC-connected between the cell input terminal and the carrier output terminal, having a carrier gate bias terminal to which a gate bias voltage is applied to the carrier amplifier, and the gate bias voltage applied to the carrier gate bias terminal is transmitted to the carrier output terminal; a peak-side input circuit AC-connected between the cell input terminal and the peak output terminal, having a peak gate bias terminal to which a gate bias voltage is applied to the peak amplifier, and the gate bias voltage applied to the peak gate bias terminal is transmitted to the peak output terminal; and a DC blocking capacitor electrically connected between the cell input terminal, the carrier-side input circuit and the peak-side input circuit, AC-short-circuiting and DC-open-circuiting the space between the carrier-side input circuit and the peak-side input circuit. An input distribution circuit is electrically connected to a first input terminal to which an input signal and a gate bias voltage for the carrier amplifier are input, and to a second input terminal to which the input signal and a gate bias voltage for the peak amplifier are input, and is electrically connected to the cell input terminal in each of the plurality of Doherty amplifier cells, and distributes and outputs the input signals input to the first input terminal and the second input terminal to the cell input terminal in each of the plurality of Doherty amplifier cells, A carrier gate bias application circuit is electrically connected to the first input terminal and the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and applies the gate bias voltage applied to the carrier amplifier applied to the first input terminal to the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, A peak gate bias application circuit is electrically connected to the second input terminal and the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and applies the gate bias voltage applied to the second input terminal for the peak amplifier to the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells. Doherty amplifier equipped with

2. The cell-internal input distribution circuit has the functions of a matching circuit and a phase adjustment line, and the function of distributing and outputting the input signal input to the cell input terminal to the carrier input pad and the peak input pad. The cell output combining circuit has the functions of a matching circuit and a phase adjustment line, and the function of combining the carrier amplified output signal output to the carrier output pad and the peak amplified output signal output to the peak output pad to output a cell output signal to the cell output terminal. The Doherty amplifier according to claim 1.

3. The carrier gate bias application circuit has a capacitance where one electrode is electrically connected to the first input terminal and the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and the other electrode is grounded. The peak gate bias application circuit has a capacitance where one electrode is electrically connected to the second input terminal and the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and the other electrode is grounded. The Doherty amplifier according to claim 1.

4. The carrier gate bias application circuit has a capacitance where one electrode is electrically connected to the first input terminal and the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and the other electrode is grounded. The peak gate bias application circuit has a capacitance where one electrode is electrically connected to the second input terminal and the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and the other electrode is grounded. The Doherty amplifier according to claim 2.

5. The Doherty amplifier according to any one of claims 1 to 4, wherein in each Doherty amplifier cell, the carrier amplifier, the peak amplifier, the in-cell input distribution circuit, and the in-cell output combining circuit are configured on the same chip.

6. A Doherty amplifier according to any one of claims 1 to 4, wherein the plurality of Doherty amplifier cells, the input distribution circuit, the carrier gate bias application circuit, and the peak gate bias application circuit are housed in a package having the first input terminal, the second input terminal, and the output terminal.

7. The Doherty amplifier according to any one of claims 1 to 4, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.

8. The Doherty amplifier according to claim 5, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.

9. The Doherty amplifier according to claim 6, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.

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