A method for operating a memory device that extends the synchronization of data clock signals, and a method for operating an electronic device including a memory device.

Abstract

To provide a method for operating a memory device for extending synchronization of a data clock signal and a method for operating an electronic device including the memory device.SOLUTION: A method for operating a memory device which communicates with a memory controller according to the present invention includes the steps of: receiving a first command from the memory controller, in which the first command indicates the start of the synchronization of a data clock signal and defines a first clock section corresponding to the synchronization; preparing toggling of the data clock signal in a preparation time section; processing a first data stream based on the data clock signal to be toggled with a reference frequency; and processing a second data stream based on the data clock signal to be toggled with the reference frequency and the defined first clock section.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an operation method of a memory device, and more particularly, to an operation method of a memory device that extends synchronization of a data clock signal and an operation method of an electronic device including the memory device.

Background Art

[0002] A memory device may include various circuits for creating, processing, or storing data. For example, a memory device may include various circuits for storing or outputting data based on electrical signals such as commands, addresses, clocks, data clock signals, data, etc. A data clock signal may be a signal directly involved in storing or outputting data, and the frequency of the data clock signal may be higher than the frequency of the clock.

[0003] Recently, as the amount of data processed by a memory device increases, the frequency of the data clock signal has been increasing, which increases the power consumption of the memory device. To reduce power consumption, the memory device can selectively synchronize the data clock signal when data processing is required. On the other hand, when data processing is completed, the synchronization of the data clock signal may be turned off, and the memory device needs to synchronize the data clock signal again to process the next data. However, since it takes time to synchronize the data clock signal again, there is a problem that data processing is delayed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0005] The present invention has been made in view of the problems of the prior art described above, and the object of the present invention is to provide a method for operating a memory device that extends the synchronization of data clock signals, and a method for operating an electronic device including a memory device. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a method is provided for operating a memory device that communicates with a memory controller, the method comprising the process of receiving a first command from the memory controller, the first command indicating the initiation of synchronization of a data clock signal and defining a first clock interval corresponding to the synchronization; preparing for toggling of the data clock signal within a preparation time interval; processing a first data stream based on the data clock signal toggling at a reference frequency; and processing a second data stream based on the data clock signal toggling at the reference frequency and the defined first clock interval.

[0007] According to one embodiment of the present invention, a method for operating a memory device that communicates with a memory controller is provided. The method includes, as a process of receiving a first command and a second command from the memory controller, the first command including setting information for a mode register and the second command indicating the start of synchronization (initiation) of a data clock signal; the step of changing the setting of the mode register based on the setting information for the mode register; the step of preparing for toggling of the data clock signal within a preparation time interval; the step of processing a first data stream based on the data clock signal toggling at a reference frequency and the setting information for the mode register, and as a process of processing a second data stream, the step of the data clock signal toggling a reference number of times.

[0008] According to one embodiment of the present invention, a method for operating an electronic device including a memory device and a memory controller for controlling the memory device is provided. The method includes the steps of: providing a command by the memory controller, the command being for extending the synchronization of a data clock signal; preparing the memory device toggling the data clock signal within a preparation time interval; processing a first data stream based on the data clock signal toggling at a reference frequency by the memory device; and processing a second data stream based on the data clock signal toggling at the reference frequency by the memory device, wherein the synchronization of the data clock signal is extended based on the command.

[0009] According to one embodiment of the present invention, a method for operating an electronic device including a memory device and a memory controller for controlling the memory device is provided. The method includes the steps of: the memory controller determining whether the processing interval between a first processing command and a second processing command is shorter than a reference interval; if the memory controller determines that the processing interval is shorter than the reference interval, generating an extension command to extend the synchronization of a data clock signal; the memory device preparing toggling the data clock signal within a preparation time zone based on the extension command; the memory device processing a first data stream corresponding to the first processing command based on the data clock signal toggling at a reference frequency; and the memory device processing a second data stream corresponding to a second processing command based on the data clock signal toggling at a reference frequency, wherein the synchronization of the data clock signal is extended based on the extension command. [Effects of the Invention]

[0010] According to some embodiments of the present invention, a method for operating a memory device that extends the synchronization of a data clock signal, and a method for operating an electronic device including a memory device are provided.

[0011] Furthermore, according to some embodiments of the present invention, a memory device is provided in which the synchronization of the data clock signal is extended based on a defined command or a change in the setting of a mode register, thereby eliminating the need for additional data clock signal synchronization and improving data processing speed. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram showing an electronic device according to one embodiment of the present invention. [Figure 2] This is a block diagram illustrating the memory controller shown in Figure 1, based on several embodiments of the present invention. [Figure 3]Based on some embodiments of the present invention, it is a block diagram embodying the memory device of FIG. 1. [Figure 4A] Based on some embodiments of the present invention, it is a timing diagram showing the synchronization of the data clock signal of FIG. 3. [Figure 4B] Based on some embodiments of the present invention, it is a timing diagram showing the synchronization of the data clock signal of FIG. 3. [Figure 4C] Based on some embodiments of the present invention, it is a timing diagram showing the synchronization of the data clock signal of FIG. 3. [Figure 5] It is a block diagram showing an electronic device according to some embodiments of the present invention. [Figure 6] Based on some embodiments of the present invention, it is a timing diagram showing a data clock signal with extended synchronization in FIG. 5. [Figure 7] It is a block diagram showing an electronic device according to some embodiments of the present invention. [Figure 8] Based on some embodiments of the present invention, it is a timing diagram showing a data clock signal with extended synchronization in FIG. 7. [Figure 9] Based on some embodiments of the present invention, it is a timing diagram showing a data stream processed based on a data clock signal with extended synchronization. [Figure 10] It is a block diagram showing an electronic device according to some embodiments of the present invention. [Figure 11A] Based on some embodiments of the present invention, it is a timing diagram showing a data stream to be processed. [Figure 11B] Based on some embodiments of the present invention, it is a timing diagram showing a data stream processed based on a data clock signal with extended synchronization. [Figure 12A] It is a block diagram showing a memory device according to some embodiments of the present invention. [Figure 12B] Based on some embodiments of the present invention, it is a timing diagram showing the data clock signal and the data signal in FIG. 12A. [Figure 13]Figure 13 is a timing diagram showing a data stream processed based on a selectively extended data clock signal according to several embodiments of the present invention. [Figure 14] This flowchart shows how to operate a memory device according to several embodiments of the present invention. [Figure 15] This flowchart shows how to operate a memory device according to several embodiments of the present invention. [Figure 16] This flowchart shows the operation method of an electronic device according to several embodiments of the present invention. [Figure 17] This flowchart shows the operation method of an electronic device according to several embodiments of the present invention. [Figure 18] This is a block diagram showing an electronic system according to several embodiments of the present invention. [Modes for carrying out the invention]

[0013] Hereafter, embodiments of the present invention are described clearly and in detail to such an extent that a person with ordinary skill in the art to which the present invention pertains can easily implement the embodiments of the present invention. Hereafter, for the convenience of explanation, similar components are denoted by the same or similar reference numerals.

[0014] Figure 1 is a block diagram showing an electronic device according to one embodiment of the present invention. Referring to Figure 1, the electronic device 10 may include a memory controller 100 (e.g., a control circuit) and a memory device 200. The electronic device 10 may be a device that stores data or outputs stored data. For example, the electronic device 10 may be used to store data in computers, tablets, laptops, notebook computers, PDAs (personal digital assistants), mobile computing devices, smartphones, internet-connected home appliances, etc.

[0015] The memory controller 100 can communicate with the memory device 200. The memory controller 100 can control the memory device 200. The memory controller 100 can store data in the memory device 200 or read data stored in the memory device 200. The memory controller 100 may include a command generator 110. The command generator 110 (e.g., a command generation circuit) can generate a command CMD.

[0016] The memory controller 100 can generate the command CMD, address ADD, clock signal CK, and data clock signal WCK. The memory controller 100 can output the command CMD, address ADD, clock signal CK, and data clock signal WCK to the memory device 200. The memory controller 100 can output data to the memory device 200 or receive data from the memory device 200.

[0017] The memory device 200 can receive commands CMD, addresses ADD, clock signals CK and data clock signals WCK from the memory controller 100. The memory device 200 can output data to the memory controller 100 or receive data from the memory controller 100. In other words, the memory device 200 is a device that stores data. For example, the memory device 200 may be a volatile memory such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), or SRAM (Static Random Access Memory), but the present invention is not limited thereto.

[0018] The memory device 200 may include a synchronization circuit 220. The synchronization circuit 220 can control the synchronization of the data clock signal WCK. Synchronization of the data clock signal WCK means that the data clock signal WCK for reading and writing data toggles at a timing synchronized with the clock signal CK. Toggle means that the logical state changes from low to high or from high to low.

[0019] A command CMD can be a signal representing an operation to be performed by the memory device 200. For example, a command CMD may include, but is not limited to, read, write, refresh, precharge, mode register, CAS (Column Address Strobe), deselect DES, etc., and the specific type of command CMD may differ depending on the specification applied to the memory device 200.

[0020] In some embodiments, CAS is a command that precedes a read or write command and may be a command to initiate synchronization of the data clock signal WCK in LPDDR5 (Low Power Double Data Rate 5). In some embodiments, DES may be a command indicating that the memory device 200 is not performing an operation.

[0021] In some embodiments, the memory controller 100 may be connected to the memory device 200 via a command / address bus (CA bus) having multiple command pins. The memory controller 100 can output command / address signals CA to multiple command pins on the CA bus, and combinations of CA can correspond to commands CMD and addresses ADD. The memory device 200 can determine the command CMD based on the CA and command truth table (command truth value table) received via the multiple command pins.

[0022] In some embodiments, the command generator 110 can generate user-defined commands. In some embodiments, the command generator 110 can generate commands to change the settings of the memory device 200 (e.g., mode register settings). A more detailed explanation of this will be provided later with reference to Figure 2.

[0023] Address ADD may be a signal indicating the location of a memory rank, memory bank, memory cell, etc., in the memory device 200 where operations are performed. For example, Address ADD may include the row address and column address of a memory cell in a memory bank within a selected memory rank.

[0024] The clock signal CK may be a periodically toggled signal. For example, the clock signal CK may be an electrical signal having a periodically repeating logical high level or logical low level. The clock signal CK is used to communicate with the memory device 200 or to determine a reference point in the internal operation of the memory device 200. In some embodiments, the clock signal CK may include complementary CK_t and CK_c.

[0025] The data clock signal WCK may be a signal used for reading or writing data. The frequency of the data clock signal WCK may be higher than the frequency of the clock signal CK. For example, the data clock signal WCK may be a signal toggled at a high frequency for data processing. In some embodiments, the data clock signal WCK may include complementary WCK_t and WCK_c.

[0026] In some embodiments, to reduce power consumption in the memory device 200, the synchronization circuit 220 may temporarily synchronize the data clock signal WCK only at the request of the memory controller 100. After a predetermined time interval has elapsed, the synchronization of the data clock signal WCK may be turned off. When processing of the next data is required, the synchronization circuit 220 synchronizes the data clock signal WCK again at the request of the memory controller 100. A more detailed explanation of this will be provided later with reference to Figure 3.

[0027] In some embodiments, the memory controller 100 and the memory device 200 can exchange data. For example, if the command CMD is a write, the memory controller 100 can output data to the memory device 200. For example, if the command CMD is a read, the memory controller 100 can receive data from the memory device 200. The data may be at least part of a computer program or application, or at least part of user data such as images, videos, audio, or text.

[0028] In some embodiments, communication between the memory controller 100 and the memory device 200 can conform to the specifications defined in LPDDR5.

[0029] Figure 2 is a block diagram illustrating the memory controller of Figure 1 based on several embodiments of the present invention. Referring to Figures 1 and 2, the memory controller 100 can communicate with the host and the memory device 200. For example, the memory controller 100 can output the command CMD, address ADD, clock signal CK, and data clock signal WCK to the memory device 200 and communicate with the memory device 200.

[0030] The memory controller 100 may include a command generator 110, a mode register setting module 111, an address generator 112, a CMD / ADD transmitter 113, a clock generator 120, a CK transmitter 121, a WCK transmitter 122, a write data queue 130, a write data transmitter 131, a read data receiver 132, a read data queue 133, a host interface 140, and a bus 150.

[0031] The command generator 110 can generate a command CMD. The command generator 110 can output the command CMD to the CMD / ADD transmitter 113.

[0032] In some embodiments, the command generator 110 can generate a user-defined CASL (Column Address Strobe Lengthened) based on communication with the host and output a command CMD containing the CASL. While CASL is similar to CAS in that it initiates synchronization of the data clock signal WCK, it may be a command defined separately from CAS to extend the synchronization of the data clock signal WCK. A more detailed explanation of CASL will follow later, along with Figures 5 and 6.

[0033] In some embodiments, the command generator 110 can receive mode register setting information MRS from the mode register setting module 111. The command generator 110 can output a command CMD that includes the mode register setting information MRS. The mode register setting information MRS may be information for changing the mode register setting in the memory device. A more detailed explanation of the mode register setting information MRS will be provided later with reference to Figures 7 and 8.

[0034] The mode register setting module 111 can generate user-defined mode register setting information MRS based on communication with the host. The mode register setting module 111 can output the mode register setting information MRS to the command generator 110.

[0035] The address generator 112 can generate an address ADD. The address generator 112 can output the address ADD to the CMD / ADD transmitter 113. The CMD / ADD transmitter 113 can receive a command CMD from the command generator 110. The CMD / ADD transmitter 113 can receive an address ADD from the address generator 112. The CMD / ADD transmitter 113 can output the command CMD and the address ADD to the memory device 200.

[0036] The clock generator 120 can generate a clock signal CK and a data clock signal WCK. The clock generator 120 can output the clock signal CK to the CK transmitter 121. The clock generator 120 can output the data clock signal WCK to the WCK transmitter 122. The CK transmitter 121 can output the clock signal CK to the memory device 200. The WCK transmitter 122 can output the data clock signal WCK to the memory device 200.

[0037] The write data queue 130 can store data to be written to the memory device 200. For example, the write data queue 130 may contain data provided by the host. The write data queue 130 can output data to the write data transmitter 131. The write data transmitter 131 can output data to the memory device 200. For example, the write data transmitter 131 can output a data signal DQ for the write operation and a data mask inversion signal DMI to the memory device 200. DQ may be a signal representing the substantial information of the data. DMI may be a signal for the inversion of the data mask and data bus.

[0038] The data receiver 132 can receive data stored in the memory device 200. For example, the data receiver 132 can receive DQ and DMI for read operations from the memory device 200. The data receiver 132 can output data to the data queue 133. The data queue 133 can store data read from the memory device 200. The data queue 133 can output data to the host in response to a request from the host.

[0039] The host interface 140 can communicate with the host. The host interface 140 can receive mode register setting information MRS and CASL from the host and output the mode register setting information MRS and CASL to the command generator 110. The host interface 140 can receive data for write operations from the host and output the data to the write data queue 130. The host interface 140 can receive data for read operations from the read data queue 133 and output the data to the host.

[0040] Bus 150 can be electrically connected to a command generator 110, a mode register setting module 111, an address generator 112, a CMD / ADD transmitter 113, a clock generator 120, a CK transmitter 121, a WCK transmitter 122, a write data queue 130, a write data transmitter 131, a read data receiver 132, a read data queue 133, and a host interface 140.

[0041] Figure 3 is a block diagram illustrating the memory device of Figure 1 based on several embodiments of the present invention. Referring to Figures 1 and 3, the memory device 200 can communicate with the memory controller 100. For example, the memory device 200 can receive commands CMD, addresses ADD, clock signals CK and WCK from the memory controller 100 and communicate with the memory controller 100.

[0042] The memory device 200 may include a CMD / ADD receiver 210, a CMD / ADD circuit 211, a mode register 212, a row decoder 213, a column decoder 214, a synchronization circuit 220, a CK receiver 221, a WCK receiver 222, an internal clock circuit 223, an I / O (Input / Output) control circuit 230, a write data receiver 231, a read data transmitter 232, and a plurality of memory ranks 240.

[0043] The CMD / ADD receiver 210 can receive the command CMD and address ADD from the memory controller 100 via the CA bus. The CMD / ADD receiver 210 can receive the clock signal CK from the CK receiver 221. Based on the clock signal CK, the CMD / ADD receiver 210 can output the command CMD and address ADD to the CMD / ADD circuit 211.

[0044] The CMD / ADD circuit 211 may include a CMD decoder and an ADD demultiplexer. The CMD decoder can decode the command CMD. The ADD demultiplexer can demultiplex the address ADD. The CMD / ADD circuit 211 can control the mode register 212 based on the decoding of the CMD decoder.

[0045] In some embodiments, when the CMD decoder determines that the command CMD is CAS, the CMD / ADD circuit 211 can control the mode register 212 or the synchronization circuit 220 to initiate synchronization. In some embodiments, when the CMD decoder determines that the command CMD contains the mode register setting information MRS, the CMD / ADD circuit 211 can change the setting of the mode register 212.

[0046] The CMD / ADD circuit 211 can control the row decoder 213 and column decoder 214 based on the demultiplexing of the ADD demultiplexer. For example, the ADD demultiplexer can demultiplex the address ADD to obtain the row address and column address. The CMD / ADD circuit 211 can output the row address to the row decoder 213. The CMD / ADD circuit 211 can output the column address to the column decoder 214.

[0047] The mode register 212 may be connected to the CMD / ADD circuit 211. In some embodiments, the setting of the mode register 212 may be changed based on the mode register setting information MRS, which is decoded by the CMD / ADD circuit 211. In some embodiments, the mode register 212 may output a synchronization start signal SYI to the synchronization circuit 220 based on the control of the CMD / ADD circuit 211. The synchronization start signal SYI may be a signal that triggers the synchronization of the data clock signal WCK in the synchronization circuit 220.

[0048] The row decoder 213 is coupled to multiple memory ranks 240. The column decoder 214 is coupled to multiple memory ranks 240. The row decoder 213 and the column decoder 214 can determine the location of memory cells within multiple memory ranks 240. For example, the row decoder 213 can identify a row in a memory rank based on its row address, and the column decoder 214 can identify a column in a memory rank based on its column address.

[0049] The CK receiver 221 can receive the clock signal CK from the memory controller 100. The CK receiver 221 can output the clock signal CK to the CMD / ADD receiver 210 and the synchronization circuit 220. The clock signal CK can provide a reference timing for the overall operation of the memory device 200.

[0050] The WCK receiver 222 can receive the data clock signal WCK from the memory controller 100. The WCK receiver 222 can output the data clock signal WCK to the synchronization circuit 220.

[0051] The synchronization circuit 220 can receive a synchronization start signal SYI from the mode register 212. The synchronization circuit 220 can receive a clock signal CK from the CK receiver 221. The synchronization circuit 220 can receive a data clock signal WCK from the WCK receiver 222. In response to the synchronization start signal SYI, the synchronization circuit 220 can synchronize the data clock signal WCK based on the clock signal CK. The synchronization circuit 220 can output the synchronized data clock signal SWCK to the internal clock circuit 223.

[0052] Synchronization of the data clock signal WCK means toggling the data clock signal WCK at a reference frequency in time with the clock signal CK in order to process data inside the memory device 200. The reference frequency may be the steady-state frequency of the data clock signal WCK determined for reading and writing data bit by bit. The reference frequency may be higher than the frequency of the clock signal CK. A more detailed explanation of the synchronization of the data clock signal WCK will be provided later with Figures 4A to 4C.

[0053] The internal clock circuit 223 can receive a synchronized data clock signal SWCK from the synchronization circuit 220. Based on the synchronized data clock signal SWCK, the internal clock circuit 223 can output an internal clock to the I / O control circuit 230. The internal clock can be used for read and write operations in the I / O control circuit 230. In some embodiments, the internal clock circuit 223 may include a four-phase converter. A more detailed explanation of the four-phase converter will be provided later with reference to Figures 12A and 12B.

[0054] The I / O control circuit 230 may be connected to a write data receiver 231, a read data transmitter 232, an internal clock circuit 223, and multiple memory ranks 240. The I / O control circuit 230 may be a circuit that controls read and write operations with the multiple memory ranks 240. For example, the I / O control circuit 230 can receive data from the write data receiver 231. The I / O control circuit 230 can output data to the memory ranks 240 via a write driver. For example, the I / O control circuit 230 can receive data from the memory ranks 240 via a sense amplifier. The I / O control circuit 230 can output data to the read data transmitter 232.

[0055] Each of the multiple memory ranks 240 may be coupled with a corresponding low decoder 213, a corresponding column decoder 214, a corresponding write driver, and a corresponding sense amplifier. Each of the multiple memory ranks 240 may contain multiple memory banks. Each of the multiple memory banks may contain multiple memory cells. Each of the multiple memory cells may have a low address and a column address, and may store data in the form of logical high or logical low. A more detailed explanation of data processing in the multiple memory ranks 240 will be provided later with reference to Figures 10, 11A, and 11B.

[0056] Figures 4A to 4C are timing diagrams showing the synchronization of the data clock signal in Figure 3, based on several embodiments of the present invention. To understand the present invention, the unextended synchronization of the data clock signal will be explained with reference to Figures 4A to 4C, and the case where the synchronization of the data clock signal is extended will be described later with reference to Figures 5 to 16.

[0057] Figure 4A illustrates how the data stream is processed based on the CAS and write commands. Referring to Figure 4A, the waveforms of CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are shown as examples. The horizontal axis represents the time axis. CK_t and CK_c can correspond to the clock signal CK in Figure 3. The command / address signal CA can correspond to the command CMD and address ADD in Figure 3. The chip selection signal CS may be a signal to activate CA. CMD may be the signal on which CA is determined based on the command truth table. WCK_t and WCK_c can correspond to the data clock signal WCK in Figure 3. DQ and DMI can correspond to the data in Figure 3 (e.g., DQ, DMI for write operations). To understand the present invention, the timing diagram of Figure 4A will be explained with reference to Figures 3 and 4A.

[0058] At time tp1, the memory device 200 can detect a toggle of the clock signal CK. For example, the memory device 200 can detect that CK_t changes from logical low to logical high, and / or that CK_c changes from logical high to logical low. In response to the toggle of the clock signal CK, the memory device 200 can determine CA. The command CMD corresponding to the determined CA may be CAS. At time tp1, WCK_t, WCK_c, DQ, and DMI remain in the don't care state.

[0059] The memory device 200 can initiate synchronization of the data clock signal WCK in response to the command CMD being determined to be CAS. For example, time tp1 can be the starting point of the time interval tWCK_SYNC, which indicates the interval associated with the synchronization of the data clock signal WCK. For example, time tp1 can be the starting point of the preparation time interval tSYNC_Prepare, which indicates the interval for preparing for the synchronization of the data clock signal WCK.

[0060] In some embodiments, the memory device 200 can receive a write command CMD immediately after receiving a CAS. For example, the memory device 200 can receive the CAS and the write command CMD sequentially. In some embodiments, the time interval from when the write command CMD is applied until the data (DQ, DMI) is processed can be predetermined based on the specifications applied to the memory device 200.

[0061] At time tp2, the memory device 200 can determine that a time interval tENL has elapsed since time tp1 when CAS was determined. The time interval tENL can represent the period in which the data clock signal WCK is maintained in a don't care state. The memory device 200 can maintain the data clock signal WCK in a constant logical state from time tp2. For example, the memory device 200 can keep WCK_t logically low and WCK_c logically high.

[0062] At time tp3, the memory device 200 can determine that the time interval tPRE_Static has elapsed since time tp2, when the data clock signal WCK was maintained in a constant logical state. The time interval tPRE_Static can represent the interval in which the data clock signal WCK is maintained in a constant logical state. The memory device 200 can pre-toggle the data clock signal WCK after time tp3. Pre-toggling can mean toggling the data clock signal WCK at a frequency lower than or equal to the reference frequency. For example, the memory device 200 can toggle the data clock signal WCK at a frequency twice slower than the reference frequency between time tp3 and the time interval tPRE_Toggle, but the present invention is not limited thereto, and according to some embodiments, the memory device 200 can also toggle the data clock signal WCK at the reference frequency in the time interval tPRE_Toggle.

[0063] At time tp4, the memory device 200 can determine that the time interval tPRE_Toggle has elapsed since time tp3, when the data clock signal WCK pretoggled at a frequency below the reference frequency. The time interval tPRE_Toggle can represent the period in which the data clock signal WCK pretoggles at a frequency below the reference frequency. The memory device 200 can toggle the data clock signal WCK at the reference frequency after time tp4. The reference frequency is the frequency determined for reading and writing data bit by bit, and can be the frequency of the data clock signal WCK under normal conditions. For example, the reference frequency can correspond to the frequency of DQ.

[0064] At time tpd1, the memory device 200 can begin processing the data stream. The data stream can represent a set of DQs corresponding to valid data. For example, the memory device 200 can store DQs from time tpd1 based on the data clock signal WCK.

[0065] In some embodiments, the memory device 200 can process the data stream from time tpd1, after a time interval tDQI has elapsed from time tp4. The time interval tDQI may be a margin set to include a malfunction of the data clock signal WCK (e.g., the frequency of the data clock signal WCK has not yet converged to a reference frequency). In some embodiments, the time interval tDQI may be omitted, reduced, or increased.

[0066] At time tpd2, the memory device 200 can complete processing of the data stream. After time tpd2, the toggling of the data clock signal WCK may be unrelated to the processing of the data stream. Unless processing of other data streams is required, the toggling of the data clock signal WCK after time tpd2 may cause unnecessary power consumption.

[0067] At time tp5, the memory device 200 can turn off synchronization of the data clock signal WCK. Turning off synchronization can mean that the data clock signal WCK is not toggling, or that the data clock signal WCK is kept in a don't-care state without resolving any skew with the clock signal CK. After time tp5, as synchronization of the data clock signal WCK is turned off, the power consumption of the memory device 200 may be reduced. In the case of mobile devices with limited power supply, turning off synchronization of the data clock signal WCK when data processing is not required can be useful for power management.

[0068] In some embodiments, the time point tp5 at which the synchronization of the data clock signal WCK is turned off may be determined as the time interval tWCK_Toggle elapsed from the time point tp4 at which the data clock signal WCK toggles. The time interval tWCK_Toggle may depend on the setting in the mode register 212 of the memory device 200. Time point tp5 may be the end of the time interval tWCK_SYNC.

[0069] As described above, the synchronization of the CAS and the data clock signal WCK corresponding to the write command was explained with reference to Figure 4A. The time interval tWCK_SYNC associated with the synchronization of the data clock signal WCK may be the interval between time point tp1 and time point tp5. The time interval tWCK_SYNC may include the preparation time interval tSYNC_Prepare and the time interval tWCK_Toggle. The preparation time interval tSYNC_Prepare may include the time interval tENL, the time interval tPRE_Static, and the time interval tPRE_Toggle. The time interval tWCK_Toggle may mean the interval in which the data clock signal WCK toggles at a reference frequency. After the time interval tDQI for margin has elapsed from time point tp4, which is the starting point of the time interval tWCK_Toggle, the data stream is processed.

[0070] Figure 4B illustrates how the data stream is processed based on CAS and read commands. Referring to Figure 4B, the waveforms for CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are shown as examples. The horizontal axis represents the time axis. The meaning of each waveform and its correspondence with the memory device are similar to those explained in Figure 4A; therefore, for clarity of explanation, a detailed explanation is omitted. Referring to Figures 3 and 4B, the timing diagram of Figure 4B is explained.

[0071] The memory device 200 can process data based on the synchronization of the data clock signal WCK, not only when processing write commands but also when processing read commands. For example, the memory device 200 can prepare the toggling of the data clock signal WCK within the preparation time interval tSYNC_Prepare, and then process the data stream within the time interval tWCK_Toggle.

[0072] More specifically, the memory device 200 can maintain the data clock signal WCK in a don't care state within the time interval tENL, maintain the data clock signal WCK in a constant logical state within the time interval tPRE_Static, and pretoggle the data clock signal WCK at a frequency below the reference frequency within the time interval tPRE_Toggle, based on the sequentially received CAS and read commands. Subsequently, the memory device 200 can output a data stream based on a read command after the time interval tDQI for the margin has elapsed from time tp4, which is the starting point of the time interval tWCK_Toggle.

[0073] As described above, the method for processing the data stream in a write operation is illustrated with reference to Figure 4A, and the method for processing the data stream in a read operation is illustrated with reference to Figure 4B. The power consumption of the memory device 200 can be reduced by completing the synchronization of the data clock signal WCK after the data stream has been processed. However, if another read or write command is received after the synchronization of the data clock signal WCK has been turned off, the memory device 200 must synchronize the data clock signal WCK again. A more detailed explanation of this will be provided later with reference to Figure 4C.

[0074] Figure 4C illustrates how to process multiple data streams. Referring to Figure 4C, the waveforms for CK_t, CK_c, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated as examples. The horizontal axis represents the time axis. The meaning of each waveform and its correspondence with the memory device are similar to those explained in Figure 4A; therefore, for clarity of explanation, a detailed explanation is omitted. Referring to Figures 3 and 4C, the timing diagram in Figure 4C will be explained.

[0075] The memory device 200 can process multiple data streams. For example, the memory device 200 can process the first data stream within the time interval 1st tWCK_SYNC. Thereafter, the memory device 200 can process the second data stream within the time interval 2nd tWCK_SYNC.

[0076] The time interval 1st tWCK_SYNC may be the interval between time point tp1 and time point tp5. Time point tp1 may be the time when the CAS corresponding to the first write command is determined. Time point tp5 may be the time when the toggling of the data clock signal WCK for the first write operation is completed. The time interval 1st tWCK_SYNC may include the time interval 1st tValid_Data. The time interval 1st tValid_Data may be the interval between time point tp1, when the command associated with the first data stream is determined, and time point tpd2, when the processing of the first data stream is completed.

[0077] The time interval 1st tWCK_SYNC may include the preparation time interval 1st tSYNC_Prepare and the time interval 1st tWCK_Toggle. The preparation time interval 1st tSYNC_Prepare may be the interval between time tp1, when a command associated with the first data stream is received, and time tp4, when the data clock signal WCK toggles at a reference frequency. The preparation time interval 1st tSYNC_Prepare may include a time interval in which the data clock signal WCK is maintained in a don't care state, a time interval in which the data clock signal WCK is maintained in a constant logical state, and a time interval in which the data clock signal WCK pre-toggles at a frequency below the reference frequency.

[0078] The time interval 1st tWCK_Toggle may be the interval between time tp4, when the data clock signal WCK toggles at the reference frequency, and time tp5, when the synchronization of the data clock signal WCK is turned off. Within the time interval 1st tWCK_Toggle, the memory device 200 can begin processing the first data stream from time tpd1, which is after the time interval tDQI has elapsed from time tp4. At time tpd2, the memory device 200 can complete processing the first data stream.

[0079] The time interval 2nd tWCK_SYNC may be the interval between time point tp6 and time point tp10. Time point tp6 may be the time when the CAS corresponding to the second write command is determined. Time point tp10 may be the time when the toggling of the data clock signal WCK for the second write operation is completed. The time interval 2nd tWCK_SYNC may include the time interval 2nd tValid_Data. The time interval 2nd tValid_Data may be the interval between time point tp6, when the command associated with the second data stream is determined, and time point tpd4, when processing of the second data stream is completed.

[0080] The time interval 2nd tWCK_SYNC may include the preparation time interval 2nd tSYNC_Prepare and the time interval 2nd tWCK_Toggle. The preparation time interval 2nd tSYNC_Prepare may be the interval between time tp6, when a command associated with the second data stream is received, and time tp9, when the data clock signal WCK toggles at a reference frequency. The preparation time interval 2nd tSYNC_Prepare may include a time interval in which the data clock signal WCK is maintained in a don't care state, a time interval in which the data clock signal WCK is maintained in a constant logical state, and a time interval in which the data clock signal WCK pre-toggles at a frequency below the reference frequency.

[0081] The time interval 2nd tWCK_Toggle may be the interval between time tp9, when the data clock signal WCK toggles at the reference frequency, and time tp10, when the synchronization of the data clock signal WCK is turned off. Within the time interval 2nd tWCK_Toggle, the memory device 200 can begin processing the second data stream from time tpd3, when time interval tDQI has elapsed from time tp9. At time tpd4, the memory device 200 can complete processing the second data stream.

[0082] As described above, in the memory device 200, the synchronization of the data clock signal WCK can be turned off after data processing is complete in order to reduce power consumption. However, if a new write command or read command is received thereafter, the memory device 200 must synchronize the data clock signal WCK again, which may cause a delay in data processing. For this reason, a method is required to extend the synchronization of the data clock signal WCK in the memory device 200. A detailed explanation of this will be given later with reference to Figures 5 to 9.

[0083] Figure 5 is a block diagram showing an electronic device according to several embodiments of the present invention. Referring to Figure 5, the electronic device 20 may include a memory controller 100a and a memory device 200a. The memory controller 100a may include a command generator 110, an address generator 112, a CMD / ADD transmitter 113, a CK transmitter 121, a WCK transmitter 122, a write data transmitter 131, and a read data receiver 132. The memory device 200a may include a CMD / ADD receiver 210, a CMD / ADD circuit 211, a mode register 212, a synchronization circuit 220, a CK receiver 221, a WCK receiver 222, an I / O control circuit 230, a write data receiver 231, a read data transmitter 232, and a memory rank 240. Since the lower-level configuration of the electronic device 20 is similar to the configuration described with reference to Figures 1 to 3, redundant or unnecessary descriptions are omitted for clarity of explanation.

[0084] According to one embodiment of the present invention, the electronic device 20 can extend the synchronization of the data clock signal WCK based on a CASL defined by the user. The CASL may be a command defined by the user. The CASL can define a clock interval corresponding to the synchronization, representing the start of the synchronization of the data clock signal WCK. The clock interval defined by the CASL may be longer than the clock interval defined by the CAS of the LPDDR5.

[0085] According to one embodiment of the present invention, the command generator 110 may include a CASL of a defined command. The CASL may be provided by a host. The command generator 110 may output the CASL to a CMD / ADD transmitter 113 to extend synchronization. The CMD / ADD transmitter 113 may output the CASL to a CMD / ADD receiver 210 in the form of a command CMD. The CMD / ADD receiver 210 may output a command CMD containing the CASL to a CMD / ADD circuit 211. The CMD / ADD circuit 211 may decode the command CMD to obtain the CASL. The CMD / ADD circuit 211 may output the CASL to a mode register 212.

[0086] The mode register 212 can receive CASL from the CMD / ADD circuit 211. The mode register 212 can determine the clock interval for synchronization based on CASL. In this case, the determined clock interval may be longer than the clock interval corresponding to CAS. The mode register 212 can output a synchronization start signal SYIa to the synchronization circuit 220. For example, the mode register 212 can output a synchronization start signal SYIa in response to receiving CASL. The synchronization start signal SYIa may contain information about the clock interval based on CASL.

[0087] The synchronization circuit 220 can receive a synchronization start signal SYIa from the mode register 212. The synchronization circuit 220 can perform synchronization of the data clock signal WCK within a clock interval extended based on the synchronization start signal SYIa.

[0088] Figure 6 is a timing diagram showing data clock signals with extended synchronization from Figure 5, based on several embodiments of the present invention. Referring to Figure 6, timing diagrams showing synchronization when CAS is used and timing diagrams showing synchronization when CASL is used are shown. For example, when CAS is used, it can correspond to memory device 200 in Figure 1, and when CASL is used, it can correspond to memory device 200a in Figure 5. The horizontal axis represents the time axis. The meaning of each waveform and its correspondence with the memory device are the same as those described in Figure 4A, so a detailed explanation therein is omitted.

[0089] When using CAS in Figure 6 and referring to Figure 1, the memory device 200, in response to the command CMD being determined to be CAS, can toggle the data clock signal WCK within the preparation time interval tSYNC_Prepare and toggle the data clock signal WCK within the time interval tWCK_Toggle. In this case, the time interval tWCK_Toggle can correspond to a clock interval.

[0090] Referring to the use of CASL in Figure 6 and Figure 5, the memory device 200a, in response to the command CMD being determined to be CASL, can toggle the data clock signal WCK within the preparation time interval tSYNC_Prepare and toggle the data clock signal WCK within the time interval tWCK_Toggle. In this case, the time interval tWCK_Toggle can correspond to the clock interval defined in CASL.

[0091] In other words, when using CAS, the clock interval corresponding to the time interval tWCK_Toggle may be between time points tp4 and tp5. When using CASL, the clock interval corresponding to the time interval tWCK_Toggle may be between time points tp4 and tpa. As the clock interval corresponding to the time interval tWCK_Toggle is extended based on the defined CASL, the time interval tWCK_Toggle is extended by the time interval between time points tp5 and tpa.

[0092] Figure 7 is a block diagram showing an electronic device according to several embodiments of the present invention. Referring to Figure 7, the electronic device 30 may include a memory controller 100b and a memory device 200b. The memory controller 100b may include a command generator 110, a mode register setting module 111, an address generator 112, a CMD / ADD transmitter 113, a CK transmitter 121, a WCK transmitter 122, a write data transmitter 131, and a read data receiver 132. The memory device 200b may include a CMD / ADD receiver 210, a CMD / ADD circuit 211, a mode register 212, a synchronization circuit 220, a CK receiver 221, a WCK receiver 222, an I / O control circuit 230, a write data receiver 231, a read data transmitter 232, and a memory rank 240. Since the lower-level components (constituent elements) of the electronic device 30 are the same as those described with reference to Figures 1 to 3, redundant or unnecessary descriptions are omitted for clarity of explanation.

[0093] According to one embodiment of the present invention, the electronic device 30 can extend the synchronization of the data clock signal WCK by changing the setting of the mode register 212 based on a command including the setting information MRS of the mode register. The setting information MRS of the mode register may be set by the user. The setting information MRS of the mode register may include a reference count of the data clock signal WCK. The reference count may represent the number of times the data clock signal WCK toggles in the synchronization of the data clock signal WCK. For example, the reference count is a user-defined number and may be greater than the number of times the data clock signal WCK, as basically defined in the mode register 212, toggles.

[0094] According to one embodiment of the present invention, the mode register setting module 111 can determine the mode register setting information MRS. It can also receive the mode register setting information MRS from the host. The mode register setting module 111 can output the mode register setting information MRS to the command generator 110. The command generator 110 can output the mode register setting information MRS to the CMD / ADD transmitter 113. The CMD / ADD transmitter 113 can output a command CMD including the mode register setting information MRS to the CMD / ADD receiver 210. The CMD / ADD receiver 210 can output a command CMD including the mode register setting information MRS to the CMD / ADD circuit 211. The CMD / ADD circuit 211 can decode the command CMD to obtain the mode register setting information MRS. The CMD / ADD circuit 211 can output the mode register setting information MRS to the mode register 212.

[0095] The mode register 212 can change its settings based on the mode register setting information MRS. For example, the mode register 212 can determine the number of toggling cycles of the data clock signal WCK in the time interval tWCK_Toggle as a reference number based on the mode register setting information MRS. The reference number may be greater than the number of toggling cycles of the data clock signal WCK in the time interval tWCK_Toggle before the change. The mode register 212 can output a synchronization start signal SYIb to the synchronization circuit 220. For example, the mode register 212 can output a synchronization start signal SYIb in response to receiving the mode register setting information MRS.

[0096] The synchronization circuit 220 can receive a synchronization start signal SYIb from the mode register 212. Based on the synchronization start signal SYIb, the synchronization circuit 220 can extend the synchronization of the data clock signal WCK.

[0097] Figure 8 is a timing diagram showing an extended synchronization of the data clock signal in Figure 7, based on several embodiments of the present invention. Referring to Figure 8, timing diagrams showing synchronization with a typical mode register setting and timing diagrams showing synchronization with a modified mode register setting are shown. For example, the typical mode register setting corresponds to the memory device 200 in Figure 1, and the modified mode register setting corresponds to the memory device 200b in Figure 7. The horizontal axis represents the time axis. The meaning of each waveform and its correspondence with the memory device are the same as those described in Figure 4A, so a detailed explanation is omitted.

[0098] Referring to the typical mode register settings in Figure 8 and Figure 1, the memory device 200, in response to the command CMD being determined to be CAS, can toggle the data clock signal WCK within the preparation time interval tSYNC_Prepare and toggle the data clock signal WCK within the time interval tWCK_Toggle. The number of times the data clock signal WCK toggles within the time interval tWCK_Toggle can be determined according to the setting of the mode register 212. For example, within the time interval tWCK_Toggle, the data clock signal WCK can toggle a default number of times.

[0099] Referring to the modified mode register setting in Figure 8 and Figure 7, the memory device 200b can receive the mode register setting information MRS before time tp1. The mode register 212 of the memory device 200b can change its setting based on the mode register setting information MRS. For example, the mode register 212 can determine the number of togglings of the data clock signal WCK in the time interval tWCK_Toggle, instead of the base number, in the synchronization of the data clock signal WCK. At time tp1, in response to the command CMD being determined to be CASL, the memory device 200b can toggle the data clock signal WCK in the preparation time interval tSYNC_Prepare and toggle the data clock signal WCK in the time interval tWCK_Toggle. At this time, the number of togglings of the data clock signal WCK in the time interval tWCK_Toggle can follow the modified setting of the mode register 212. For example, the data clock signal WCK can toggle a reference number of times in the time interval tWCK_Toggle. The baseline number of attempts may be higher than the base number of attempts before the change.

[0100] In other words, within the time interval tWCK_Toggle, the frequency of the data clock signal WCK is constant, and the time interval tWCK_Toggle, based on the data clock signal WCK toggling a basic number of times, can be between time points tp4 and tp5. The time interval tWCK_Toggle, based on the data clock signal WCK toggling a reference number of times, can be between time points tp4 and tpb. As the number of toggling cycles of the data clock signal WCK increases within the time interval tWCK_Toggle, the time interval tWCK_Toggle can be extended by the time interval between time points tp5 and tpb.

[0101] Figure 9 is a timing diagram showing data streams processed based on a data clock signal whose synchronization is extended according to several embodiments of the present invention. Referring to Figure 9, a method for processing multiple data streams based on the extended data clock signal WCK is described. The meaning of each waveform and its correspondence with the memory device is the same as that described in Figure 4A, so for the sake of clarity of explanation, a detailed explanation of this is omitted. The timing diagram in Figure 9 can correspond to synchronization in memory device 200a in Figure 5 or synchronization in memory device 200b in Figure 7.

[0102] In some embodiments, the command at time tp1 may be determined as CASL. In some other embodiments, a command CMD for changing the mode register setting is received before time tp1, and the number of togglings of the data clock signal WCK may be determined as the reference number. The command at time tp1 may be determined as CAS.

[0103] From time tp1 within the preparation time interval tSYNC_Prepare, the memory device has the option to toggle the data clock signal WCK. From time tp4 within the time interval tWCK_Toggle, the memory device may toggle the data clock signal WCK. At this time, the time interval tWCK_Toggle may be an extended time interval based on a change in the CASL or mode register setting. For example, the time interval tWCK_Toggle may be longer than the first time interval 1st tWCK_Toggle in Figure 4C. In one embodiment, the first time interval 1st tWCK_Toggle may have a first interval, and the duration of the time interval tWCK_Toggle may be the sum of the first interval and a second interval of the clock interval indicated by a change in the CASL or setting. That is, the duration of the time interval tWCK_Toggle may be extended by the second interval.

[0104] At time point tp5, the data clock signal WCK can continue to toggle. Since the synchronization of the data clock signal WCK was not turned off, a command to start synchronization may not be necessary. For example, because the toggling of the data clock signal WCK is maintained at time point tp5, a CAS for the second write operation may not be necessary. As a result of omitting the one-cycle command CMD for CAS, the time interval 2nd tValid_Data may be shortened. This can speed up the processing of the second data stream. For example, time point tpd4c, when the processing of the second data stream is completed, may be earlier than tpd4 in Figure 4C, when the processing of the second data stream is completed.

[0105] In some embodiments, a command received immediately before a second write command may not be a CAS command in LPDDR5. For example, a CA at time tp6 may be determined to be a write command based on the command truth table, while a CA at time tp5 may be determined to be a DES (i.e., not a CAS) based on the command truth table.

[0106] As described above, the present invention provides a method for improving the data processing speed in a memory device by extending the synchronization of the data clock signal WCK.

[0107] Figure 10 is a block diagram showing an electronic device according to several embodiments of the present invention. Referring to Figure 10, the electronic device 40 may include a memory controller 100c and a memory device 200c. The memory device 200c may include an I / O control circuit 230, a first memory rank 240a, and a second memory rank 240b. The first memory rank 240a and the second memory rank 240b may each include multiple memory banks. The memory controller 100c can output a command CMD, an address ADD, a clock signal CK, and a data clock signal WCK to the memory device 200c. The memory controller 100c can communicate with the memory device 200c. The clock signal CK, the data clock signal WCK, and the data are similar to the clock signal CK, data clock signal WCK, and data in Figure 1, so a detailed explanation of them is omitted.

[0108] The memory device 200c can receive the command CMD and address ADD from the memory controller 100c. The command CMD may include CMD_R1 and CMD_R2. CMD_R1 may represent a command to be executed in the first memory rank 240a. CMD_R2 may represent a command to be executed in the second memory rank 240b. CS_R1 may be a signal indicating whether or not to select the first memory rank 240a. CS_R2 may be a signal indicating whether or not to select the second memory rank 240b.

[0109] The I / O control circuit 230 can control the first memory rank 240a based on CS_R1 and CMD_R1. For example, the I / O control circuit 230 can select the first memory rank 240a based on CS_R1, and write data to or read data from the first memory rank 240a based on CMD_R1.

[0110] The I / O control circuit 230 can control the second memory rank 240b based on CS_R2 and CMD_R2. For example, the I / O control circuit 230 can select the second memory rank 240b based on CS_R2 and write data to or read data from the second memory rank 240b based on CMD_R2.

[0111] In some embodiments, the I / O control circuit 230 can control the first memory rank 240a and the second memory rank 240b independently. For example, the I / O control circuit 230 can read data from the second memory rank 240b while writing data to the first memory rank 240a. Alternatively, the I / O control circuit 230 can read data from the first memory rank 240a while writing data to the second memory rank 240b.

[0112] Figure 11A is a timing diagram showing data streams processed based on several embodiments of the present invention. Figure 11A illustrates how to process multiple data streams in a memory device where synchronization of the data clock signal WCK is not extended.

[0113] Referring to Figure 11A, the waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated as examples. The horizontal axis represents the time axis. The meanings of CK_t, CK_c, WCK_t, WCK_c, DQ, and DMI and their correspondence with the memory device are similar to those explained in Figure 4A, and CS_R1, CMD_R1, CS_R2, and CMD_R2 are similar to those explained in Figure 10, so for the sake of clarity, a detailed explanation of these will be omitted. Referring to Figures 10 and 11A, the timing diagram in Figure 11A will be explained.

[0114] The memory device 200c can process a first data stream via the first memory rank 240a and a second data stream via the second memory rank 240b. For example, the memory device 200c can process the first data stream within the time interval 1st tWCK_SYNC. Thereafter, the memory device 200c can process the second data stream within the time interval 2nd tWCK_SYNC.

[0115] At time tp4, the memory device 200c can toggle the data clock signal WCK at the reference frequency. After the time interval 1st tWCK_Toggle has elapsed from time tp4, the synchronization of the data clock signal WCK can be turned off at time tp5. After the synchronization of the data clock signal WCK is turned off, processing of the second data stream may be requested. In order to synchronize the data clock signal WCK again, the memory device 200c must prepare to toggle the data clock signal WCK again within the preparation time interval 2nd tSYNC_Prepare based on a new CAS (e.g., the CAS determined at time tp6). This causes a delay in processing the second data stream.

[0116] Figure 11B is a timing diagram showing data streams processed based on a data clock signal with extended synchronization based on several embodiments of the present invention. Figure 11B illustrates how multiple data streams are processed in a memory device with extended synchronization of the data clock signal WCK.

[0117] Referring to Figure 11B, the waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated as examples. The meaning of each waveform and its correspondence with the memory device are the same as those explained in Figure 11A, so for the sake of clarity, a detailed explanation is omitted. The timing diagram in Figure 11B will be explained by referring to Figures 10 and 11B.

[0118] In some embodiments, the command may be determined as CASL at time tp1. In some other embodiments, a command CMD for changing the mode register setting is received before time tp1, and the number of toggles of the data clock signal WCK may be determined as a reference number (e.g., greater than the base number). The command may be determined as CAS at time tp1. This extends the synchronization of the data clock signal WCK of memory device 200c. For example, the time interval tWCK_Toggle corresponding to the synchronization of the data clock signal WCK may be between time tp4 and time tp10x, and the time interval tWCK_Toggle may be longer than the time interval (1st tWCK_Toggle) in Figure 11A.

[0119] In some embodiments, the memory device 200c can process the first and second data streams in parallel based on the extended synchronization of the data clock signal WCK. For example, the memory device 200c can process the first data stream within the time interval 1st tValid_Data. At time tp6x, before processing of the first data stream is completed, the memory device 200c can determine a write command to the second data stream. At this time, since the toggling of the data clock signal WCK is maintained, the memory device 200c can process the second data stream without a CAS for the write operation of the second data stream. At time tpd4x, the memory device 200c can complete processing of the second data stream based on the toggling of the extended data clock signal WCK.

[0120] As described above, the memory device 200c can improve data processing speed by processing the first and second data streams in parallel based on the extended synchronization of the data clock signal WCK. For example, the time tpd4x, when the processing of the second data stream is completed, may be earlier than the time tpd4, when the processing of the second data stream is completed in Figure 11A.

[0121] Figure 12A is a block diagram showing a memory device according to several embodiments of the present invention. Referring to Figure 12A, the memory device 200d may include a CMD / ADD receiver 210, a CMD / ADD circuit 211, a mode register 212, a synchronization circuit 220, a CK receiver 221, a WCK receiver 222, an internal clock circuit 223, an I / O control circuit 230, a write data receiver 231, a read data transmitter 232, and a plurality of memory ranks 240.

[0122] The CMD / ADD receiver 210, CMD / ADD circuit 211, mode register 212, synchronization circuit 220, CK receiver 221, WCK receiver 222, I / O control circuit 230, write data receiver 231, read data transmitter 232, and multiple memory ranks 240 are the same as those described in Figure 3, so a detailed explanation of them is omitted.

[0123] In some embodiments, the internal clock circuit 223 can receive a synchronized data clock signal SWCK from the synchronization circuit 220. Based on the synchronized data clock signal SWCK, the internal clock circuit 223 can output an internal clock to the I / O control circuit 230.

[0124] In some embodiments, the internal clock may be four-phase. For example, the internal clock circuit 223 may include a four-phase converter. The four-phase converter can generate a four-phase clock based on a synchronized data clock signal SWCK. The four-phase clock may include a first-phase clock signal WCK0, a second-phase clock signal WCK90, a third-phase clock signal WCK180, and a fourth-phase clock signal WCK270.

[0125] The phases of the first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) can differ from each other. For example, the first phase clock signal WCK0 may have the same phase as the synchronized data clock signal SWCK. The second phase clock signal WCK90 may lag the synchronized data clock signal SWCK by 90°. The third phase clock signal WCK180 may lag the synchronized data clock signal SWCK by 180°. The fourth phase clock signal WCK270 may lag the synchronized data clock signal SWCK by 270°.

[0126] The first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) can process different data. For example, when processing a data stream containing the first to fourth data is requested, the memory device 200d can process the first data of the data stream based on the first phase clock signal WCK0. The memory device 200d can process the second data of the data stream based on the second phase clock signal WCK90. The memory device 200d can process the third data of the data stream based on the third phase clock signal WCK180. The memory device 200d can process the fourth data of the data stream based on the fourth phase clock signal WCK270.

[0127] Figure 12B is a timing diagram showing the data clock signal and data signal in Figure 12A based on several embodiments of the present invention. Referring to Figure 12B, the waveforms of WCK_t, WCK_c, WCK0, WCK90, WCK180, WCK270 and DQ are shown. The horizontal axis represents the time axis. WCK_t and WCK_c can correspond to the data clock signal WCK or the synchronized data clock signal SWCK in Figure 12A. WCK0, WCK90, WCK180, and WCK270 can correspond to the first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) in Figure 12A. DQ can correspond to the data DQ for write operations or the data DQ for read operations in Figure 12A. DQ is sometimes also referred to as a data stream containing multiple data (D1 to D10).

[0128] Referring to Figures 12A and 12B, the memory device 200d can generate first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) based on the synchronized data clock signal SWCK. The first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) may have phase differences of 0°, 90°, 180°, and 270°, respectively, in relation to the synchronized data clock signal SWCK. The periods of the first to fourth phase clocks (WCK0, WCK90, WCK180, WCK270) may be identical to each other. For example, the periods may correspond to the time interval between time point tp1f and time point tp5f.

[0129] At time tp1f, the memory device 200d can process the first data D1 of the data stream corresponding to DQ in response to the rising edge of the first phase clock signal WCK0. The rising edge means that the logical state of the clock changes from logical low to logical high. At time tp2f, the memory device 200d can process the second data D2 of the data stream corresponding to DQ in response to the rising edge of the second phase clock signal WCK90. At time tp3f, the memory device 200d can process the third data D3 of the data stream corresponding to DQ in response to the rising edge of the third phase clock signal WCK180. At time tp4f, the memory device 200d can process the fourth data D4 of the data stream corresponding to DQ in response to the rising edge of the fourth phase clock signal WCK270.

[0130] Figure 13 is a timing diagram showing data streams processed based on a data clock signal that is selectively extended according to several embodiments of the present invention. Referring to Figure 13, a graph of the data streams processed when the processing interval is longer than or equal to the reference interval is shown. A graph of the data streams processed when the processing interval is shorter than the reference interval is also shown.

[0131] The processing interval can refer to the time interval between processing commands (e.g., read commands or write commands). The reference interval may be the time interval that serves as the basis for determining whether or not to extend the synchronization of the data clock signal. For each point in time and waveform, its meaning and correspondence in the memory device are the same as those explained in Figures 4A and 9; therefore, for the sake of clarity, a detailed explanation of this is omitted.

[0132] According to some embodiments of the present invention, the electronic device may include a memory device and a memory controller that controls the memory device. The memory controller may have information about the time interval between adjacent processing commands (i.e., processing intervals).

[0133] In some embodiments, the memory controller may determine that extending the synchronization of the data clock signal is inefficient if the processing interval is longer than or equal to the reference interval. For example, if the processing interval is longer than or equal to the reference interval, the memory controller may determine that the disadvantage of increased power consumption to maintain the synchronization of the data clock signal outweighs the advantage of improved data processing speed by omitting CAS commands as the synchronization of the data clock signal is extended.

[0134] In some embodiments, the memory controller can determine that it is efficient to extend the synchronization of the data clock signal if the processing interval is shorter than the reference interval. For example, if the processing interval is shorter than the reference interval, the memory controller can determine that the benefit of increased data processing speed as the synchronization of the data clock signal is extended outweighs the drawback of increased power consumption to maintain the synchronization of the data clock signal.

[0135] Referring to an embodiment of the first processing interval in Figure 13, the memory device can determine the first write command at time tpra1 and the second write command at time tpra2. The time interval between time tpra1, when the first write command is determined, and time tpra2, when the second write command is determined, can be referred to as the first processing interval. The memory controller may include information about the first processing interval.

[0136] In some embodiments, the memory controller can determine whether the first processing interval is longer than or equal to the reference interval. If the first processing interval is longer than or equal to the reference interval, extending the synchronization of the data clock signal may be inefficient. The memory controller may choose not to extend the synchronization of the data clock signal in the memory device. For example, at time tp5, the synchronization of the data clock signal WCK in the memory device may end. The time interval between time tp5 and time tp6r may be long. At time tp6r, the memory device can determine the CAS command. At time tp9r, the memory device can synchronize the data clock signal WCK again.

[0137] Referring to an embodiment of the second processing interval in Figure 13, the memory device can determine the first write command at time tprb1 and the second write command at time tprb2. The time interval between time tprb1, when the first write command is determined, and time tprb2, when the second write command is determined, is sometimes referred to as the second processing interval. The memory controller may include information about the second processing interval.

[0138] In some embodiments, the memory controller can determine whether the second processing interval is shorter than the reference interval. If the second processing interval is shorter than the reference interval, it may be efficient to extend the synchronization of the data clock signal. The memory controller can extend the synchronization of the data clock signal in the memory device.

[0139] For example, the memory controller can generate a command (e.g., CASL) that indicates the start of synchronization of the data clock signal and defines the clock interval corresponding to the synchronization. The memory controller can also generate a command that includes setting information for a mode register to change the number of togglings of the data clock signal to a reference number. The number of togglings of the data clock signal of the memory device can be changed to a reference number. This allows the data clock signal to toggle continuously from time tp4 to time tp5r. For the sake of understanding the present invention, the processing interval is shown between the first write command and the second write command, but the scope of the present invention is not limited thereto, and the first write command may be changed to a first read command, and the second write command may be changed to a second read command.

[0140] Figure 14 is a flowchart illustrating the operation method of a memory device according to several embodiments of the present invention. The operation method of the memory device will be explained with reference to Figure 14. The memory device can correspond to at least one of the memory device 200 in Figure 3, memory device 200a in Figure 5, memory device 200c in Figure 10, and memory device 200d in Figure 12A. The memory device can communicate with a memory controller.

[0141] In step S110, the memory device can receive a command from the memory controller. The command may indicate the start of synchronization of the data clock signal and define the clock interval corresponding to the synchronization. For example, the command may be a CASL of a defined command.

[0142] In some embodiments, the clock interval defined by the command in step S110 may be longer than the clock interval corresponding to the synchronization of the data clock signal based on the CAS command in LPDDR5.

[0143] In some embodiments, in step S110, after receiving a command indicating the start of synchronization of the data clock signal and defining a clock interval, the memory device may further receive a first processing command for processing the first data stream and a second processing command for processing the second data stream. For example, the first processing command may be a write command or a read command for the first data stream. The second processing command may be a write command or a read command for the second data stream. In some embodiments, the command received immediately before the second processing command may not be CAS and CASL.

[0144] In step S120, the memory device includes toggling the data clock signal within a preparation time interval. In some embodiments, the preparation time interval may sequentially include a first time interval for maintaining the data clock signal in a don't care state, a second time interval for maintaining the data clock signal in a constant logical state, and a third time interval for pre-toggleping the data clock signal at a frequency below the reference frequency. Pre-toggleping the data clock signal is performed by toggling the data clock signal at a frequency lower than the reference frequency.

[0145] In step S130, the memory device can process the first data stream based on a data clock signal toggled at a reference frequency. In some embodiments, the memory device can process the first data stream after toggling the data clock signal within a fourth time interval at a reference frequency. In some embodiments, the memory device can generate a four-phase clock based on the data clock signal and process the first data stream based on the four-phase clock.

[0146] In step S140, the memory device can process a second data stream based on a data clock signal toggling at a reference frequency and a defined clock interval. For example, unlike step S130, which processes the first data stream, the second data stream can be processed within a time interval in which the synchronization of the data clock signal is extended by CASL.

[0147] In some embodiments, the memory device can process a second data stream after toggling a data clock signal at a reference frequency within a fifth time interval. In some embodiments, the memory device can generate a four-phase clock based on the data clock signal and process a second data stream based on the four-phase clock. In this case, the four-phase clock can continuously toggle from the time the first data stream is processed until the second data stream is processed in step S130.

[0148] In some embodiments, a memory device can process multiple data streams through multiple memory ranks. For example, in step S130, the memory device can process a first data stream through a first memory rank. In step S140, the memory device can process a second data stream through a second memory rank. In this case, the start of processing the second data stream may be earlier than the completion of processing the first data stream.

[0149] Figure 15 is a flowchart illustrating the operation method of a memory device according to several embodiments of the present invention. The operation method of the memory device will be explained with reference to Figure 15. The memory device can correspond to at least one of the memory device 200 in Figure 3, memory device 200b in Figure 7, memory device 200c in Figure 10, and memory device 200d in Figure 12A. The memory device can communicate with a memory controller.

[0150] In step S210, the memory device can receive a first command and a second command from the memory controller. The first command may include setting information for the mode register. The second command may represent the start of synchronization of the data clock signal. For example, the first command may include setting information for the mode register to extend the synchronization of the data clock signal. The second command may be a CAS command in LPDDR5.

[0151] In some embodiments, in step S210, after receiving the first command and the second command, the memory device may further receive a first processing command for processing the first data stream and a second processing command for processing the second data stream. In some embodiments, the command received immediately before the second processing command may not be CAS and CASL.

[0152] In step S215, the memory device can change the settings of the mode register based on the setting information of the mode register. For example, the memory device can obtain the setting information of the mode register by decoding the first command received in step S210. Based on the setting information of the mode register, the memory device can determine the number of times the data clock signal toggles with respect to synchronization as a reference number. In this case, the reference number may be greater than the basic number of times the data clock signal toggles as defined in LPDDR5.

[0153] In step S220, the memory device includes toggling of the data clock signal within a preparation time interval. In some embodiments, the preparation time interval may sequentially include a first time interval in which the data clock signal is kept in a don't care state, a second time interval in which the data clock signal is kept in a constant logical state, and a third time interval in which the data clock signal is pretoggled at a frequency below the reference frequency.

[0154] In step S230, the memory device can process the first data stream based on a data clock signal toggled at a reference frequency. In some embodiments, the memory device can process the first data stream after toggling the data clock signal within a fourth time interval at a reference frequency. In some embodiments, the memory device can generate a four-phase clock based on the data clock signal and process the first data stream based on the four-phase clock.

[0155] In step S240, the memory device can process a second data stream based on a data clock signal toggling at a reference frequency and the modified mode register setting. For example, unlike step S230 which processes the first data stream, the second data stream can be processed within an extended time interval based on the modified mode register setting.

[0156] In some embodiments, the memory device can process a second data stream after toggling a data clock signal at a reference frequency within a fifth time interval. In some embodiments, the memory device can generate a four-phase clock based on the data clock signal and process the second data stream based on the four-phase clock. In some embodiments, the memory device can process multiple data streams through multiple memory ranks.

[0157] Figure 16 is a flowchart illustrating the operation method of an electronic device according to several embodiments of the present invention. The operation method of the electronic device will be explained with reference to Figure 16. The electronic device may include a memory controller and a memory device. The electronic device can correspond to at least one of the electronic devices including the electronic device 10 in Figure 1, the electronic device 20 in Figure 5, the electronic device 30 in Figure 7, the electronic device 40 in Figure 10, and the memory device 200d in Figure 12A.

[0158] In step S310, the electronic device may provide a command via the memory controller. The command can extend the synchronization of the data clock signal. For example, the command may be a CASL of a defined command. The command may also include setting information for a mode register to extend the synchronization of the data clock signal.

[0159] In step S320, the electronic device provides a data clock signal toggle by the memory device within a preparation time interval. In step S330, the electronic device can process a first data stream based on the data clock signal toggled by the memory device at a reference frequency. In step S340, the electronic device can process a second data stream based on the data clock signal toggled by the memory device at a reference frequency. The time at which the second data stream is processed may fall within the synchronization interval of the data clock signal extended based on the command in step S310.

[0160] Figure 17 is a flowchart illustrating the operation method of an electronic device according to several embodiments of the present invention. The operation method of the electronic device will be explained with reference to Figure 17. The electronic device may include a memory controller and a memory device. The electronic device can correspond to at least one of the electronic devices including electronic device 10 in Figure 1, electronic device 20 in Figure 5, electronic device 30 in Figure 7, electronic device 40 in Figure 10, and memory device 200d in Figure 12A. Similar to the embodiment in Figure 13, the electronic device can compare the processing interval and the reference interval to determine whether or not to extend the synchronization of the data clock signal.

[0161] In step S410, the electronic device can determine whether the processing interval is shorter than the reference interval. For example, the memory controller of the electronic device can determine whether the processing interval between the first processing command and the second processing command is shorter than the reference interval.

[0162] The first processing command may be a first read command or a first write command to the first data stream. The second processing command may be a second read command or a second write command to the second data stream. The reference interval may be a reference time interval used to determine whether or not to extend the synchronization of the data clock signal.

[0163] If the electronic device determines in step S410 that the processing interval is shorter than the reference interval, it may proceed to step S415. In step S415, the memory controller of the electronic device may generate an extension command to extend the synchronization of the data clock signal.

[0164] In some embodiments, extended commands may include defined commands (e.g., CASL). For example, a defined command may indicate the start of synchronization of a data clock signal and define the clock interval corresponding to the synchronization.

[0165] In some embodiments, extended commands may include mode register change commands containing setting information for the mode register, and start commands indicating the start of synchronization of the data clock signal (e.g., CAS in LPDDR5).

[0166] In step S420, the memory device of the electronic device includes toggling of the data clock signal within a preparation time interval based on an extension command. In step S430, the memory device of the electronic device can process a first data stream corresponding to a first processing command based on a data clock signal toggling at a reference frequency. In step S440, the memory device of the electronic device can process a second data stream corresponding to a second processing command based on a data clock signal toggling at a reference frequency. At this time, the toggling of the data clock signal is extended based on the extension command in step S415, and the toggling of the data clock signal can continue continuously while processing both the first and second data streams.

[0167] If the electronic device determines in step S410 that the processing interval is longer than or equal to the reference interval, it can proceed to step S450. In step S450, the memory controller of the electronic device can generate a first start command and a second start command. For example, the first start command may be a command indicating the start of synchronization of the data clock signal in order to process the first processing command. The second start command may be a command indicating the start of synchronization of the data clock signal in order to process the second processing command. In some embodiments, each of the first start command and the second start command may be a CAS command in LPDDR5.

[0168] In step S460, the memory device of the electronic device can process the first data stream based on the first start command. For example, the memory device of the electronic device can process the first data stream corresponding to the first processing command using a data clock signal toggled based on the first start command.

[0169] In some embodiments, step S460 includes the steps of: preparing the memory device to toggle a data clock signal within a preparation time interval based on a first start command; processing a first data stream based on a data clock signal toggled at a reference frequency by the memory device; and terminating the toggling of the data clock signal (i.e., terminating the synchronization of the data clock signal) after processing the first data stream by the memory device.

[0170] In step S470, the memory device of the electronic device can process the second data stream based on the second start command. For example, the memory device of the electronic device can process the second data stream corresponding to the second processing command using a data clock signal that is toggled based on the second start command. In this case, unlike when the second data stream is processed in step S440, the data clock signal in step S470 may be toggled again based on the second start command after the toggling has finished in step S460.

[0171] In some embodiments, step S470 includes the steps of: preparing the memory device to toggle a data clock signal within a preparation time interval based on a second start command; processing a second data stream based on a data clock signal toggled by the memory device at a reference frequency; and terminating the toggling of the data clock signal after processing the second data stream by the memory device.

[0172] Figure 18 is a block diagram showing an electronic system according to several embodiments of the present invention. Referring to Figure 18, the electronic system 1000 may include an electronic device 1200. The electronic device 1200 can correspond to at least one of the electronic devices including the electronic device 10 in Figure 1, the electronic device 20 in Figure 5, the electronic device 30 in Figure 7, the electronic device 40 in Figure 10, and the memory device 200d in Figure 12A. The operation method of the electronic device 1200 can correspond to the flowchart in Figure 16. The electronic device 1200 may include a memory device 200. The operation method of the memory device 200 can correspond to at least one of the flowcharts in Figure 14 and Figure 15.

[0173] The electronic system 1000 may be a mobile system such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or IoT (Internet of Things) device. However, the electronic system 1000 is not necessarily limited to a mobile system and may be a system such as a personal computer, laptop, server, media player, or automotive device such as navigation.

[0174] The electronic system 1000 may include a main processor 1100, an electronic device 1200, and storage devices (1300a, 1300b), and may further include one or more of the following: an optical input device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connecting interface 1480.

[0175] The main processor 1100 can control the overall operation of the electronic system 1000, and more specifically, the operation of other components that make up the electronic system 1000. Such a main processor 1100 can be implemented as a general-purpose processor, a dedicated processor, or an application processor, among others.

[0176] The main processor 1100 may include multiple CPU cores 1110 and may further include a controller 1120 for controlling electronic devices 1200 and / or storage devices (1300a, 1300b). In some embodiments, the main processor 1100 may further include an accelerator 1130, which is dedicated circuitry for high-speed data computation, such as AI (artificial intelligence) data computation. Such an accelerator 1130 may include a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), and / or a DPU (Data Processing Unit), and may be implemented on a separate chip that is physically independent from the other components of the main processor 1100.

[0177] The electronic device 1200 may be a volatile memory such as DRAM and / or SRAM. The electronic device 1200 may be implemented in the same package as the main processor 1100.

[0178] The storage devices (1300a, 1300b) can function as non-volatile storage devices that store data regardless of whether power is supplied, and may have a relatively larger storage capacity than the electronic device 1200. The storage devices (1300a, 1300b) may include a controller (1310a, 1310b) and flash memory (1320a, 1320b) that stores data under the control of the controller (1310a, 1310b). The non-volatile flash memory (1320a, 1302b) may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0179] The storage devices (1300a, 1300b) may be included in the electronic system 1000 in a physically separate state from the main processor 1100, or they may be implemented in the same package as the main processor 1100. Furthermore, the storage devices (1300a, 1300b) may take the form of an SSD (solid state device) or a memory card, and may be coupled to other components of the electronic system 1000 in a detachable manner via an interface such as the connecting interface 1480 described later. Such storage devices (1300a, 1300b) may be, but are not necessarily limited to, devices to which standard specifications such as UFS (universal flash storage), eMMC (embedded multi-media CArd), or NVMe (non-volatile memory express) apply.

[0180] The optical input device 1410 can capture still images and videos, and may be a camera, camcorder, and / or webcam.

[0181] The user input device 1420 can receive various types of data entered by the user of the electronic system 1000, and may be a touch pad, keypad, keyboard, mouse, and / or microphone.

[0182] The sensor 1430 can sense various types of physical quantities that can be obtained from outside the electronic system 1000 and convert the sensed physical quantities into electrical signals. Such sensors 1430 may be temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors and / or gyroscopes.

[0183] The communication device 1440 can communicate with other devices outside the electronic system 1000 based on various communication protocols. Such a communication device 1440 may be implemented as an antenna, a transceiver, and / or a modem.

[0184] The display 1450 and speaker 1460 can function as output devices that output visual and auditory information, respectively, to the user of the electronic system 1000.

[0185] The power supply device 1470 can appropriately convert power supplied from a battery (not shown) built into the electronic system 1000 and / or from an external power source and supply it to each component of the electronic system 1000.

[0186] The connecting interface 1480 can provide connectivity between the electronic system 1000 and external devices. The connecting interface 1480 can be implemented using a variety of interface methods, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), and CF (compact Flash) card interfaces.

[0187] The above-described content is a specific example for carrying out the present invention. The present invention includes not only the above-described examples, but also examples that can be simply redesigned or easily modified. Furthermore, the present invention also includes techniques that can be easily modified and implemented using the examples. Therefore, the scope of the present invention should not be limited to the above-described examples, but should be defined not only by the claims described later, but also by something equivalent to the claims of this invention. [Explanation of symbols]

[0188] 10:Electronic equipment 100: Memory Controller 110: Command Generator 111: Mode register setting module 112: Address Generator 113: CMD / ADD Transmitter 120: Clock Generator 121: CK Transmitter 122: WCK Transmitter 130: Write data queue 131: Data transmission device 132: Data Read Receiver 133: Read data queue 140: Host Interface 150: Bus 200: Memory device 210: CMD / ADD receiver 211: CMD / ADD circuit 212: Mode Register 213: Low Decoder 214: Column Decoder 220: Synchronous circuit 221: CK receiver 222: WCK receiver 223: Internal clock circuit 230: I / O control circuit 231: Data Receiver 232: Read data transmitter 240: Multiple memory ranks 1000: Electronic Systems 1100: Main Processor 1200:Electronic equipment 1300a: Storage device 1300b: Storage device 1410: Optical input device 1420: User input device 1430: Sensor 1440: Communication equipment 1450: Display 1460: Speaker 1470:Power supply equipment 1480: Connecting Interface

Claims

1. A method for operating a memory device that communicates with a memory controller, The memory controller receives a command indicating the start of synchronization between the data clock signal and the clock signal for reading or writing data. Within the preparation time interval, there is a step of preparing for the toggling of the data clock signal at the reference frequency, The step of determining whether the command is a first command associated with a first time interval, or a second command different from the first command, associated with a second time interval that is longer than the first time interval, If the command is determined to be the second command, the data clock signal is toggled at the reference frequency over the second time interval after the preparation time interval, A step of processing a first data stream based on the data clock signal that toggles at the aforementioned reference frequency, Includes, The processing step includes the step of reading or writing the first data stream.

2. The method according to claim 1, wherein the first command is a CAS (Column Address Stove) command in LPDDR5 (Low Power Double Data Rate 5).

3. The step of sequentially receiving a third command from the memory controller after the command for processing the first data stream, The process further includes the step of sequentially receiving a fourth command from the memory controller after the third command for processing the second data stream, The method according to claim 1, wherein the processing of the second data stream is to write the second data stream to the memory device or to read the second data stream from the memory device.

4. The third command is a write command corresponding to the first data stream or a read command corresponding to the first data stream, The fourth command is a write command corresponding to the second data stream or a read command corresponding to the second data stream, The method according to claim 3, wherein the second command is not a CAS command in LPDDR5.

5. The method according to claim 3, wherein the first time interval is shorter than the second time interval by a third time interval corresponding to the second command, the first time interval represents a fourth time interval from the time of receiving the fourth command to the time of completion of processing the second data stream, and the second time interval represents a fifth time interval from the time of receiving the second command to the time of completion of processing the first data stream.

6. The aforementioned preparation time interval includes, in order, the first to third sub-time intervals. Within the aforementioned preparation time interval, the step of preparing the toggling of the data clock signal at the reference frequency is: The steps include: maintaining the data clock signal in a don't care state within the first sub-time interval; The steps include maintaining the data clock signal in a constant logical state within the second sub-time interval, The method according to any one of claims 1 to 5, comprising the step of toggling the data clock signal at a frequency less than or equal to the reference frequency within the third sub-time interval.

7. The method according to claim 3, wherein the toggling of the data clock signal is maintained from the time of processing the first data stream until the time of processing the second data stream.

8. The step of processing the first data stream based on the data clock signal that toggles at the aforementioned reference frequency is: A step of generating a four-phase clock signal based on the data clock signal, wherein the four-phase clock signal includes first to fourth phase clock signals. A step of processing the first data of the first data stream based on the first phase clock signal, A step of processing the second data of the first data stream based on the second phase clock signal, A step of processing the third data of the first data stream based on the third phase clock signal, The method according to claim 3, further comprising the step of processing the fourth data of the first data stream based on the fourth phase clock signal.

9. The step of processing the second data stream is: A step of processing the fifth data of the second data stream based on the first phase clock signal, A step of processing the sixth data of the second data stream based on the second phase clock signal, A step of processing the seventh data of the second data stream based on the third phase clock signal, The process includes the step of processing the eighth data of the second data stream based on the fourth phase clock signal, The method according to claim 8, wherein the toggling of the first to fourth phase clock signals is maintained from the time of processing the first data stream until the time of processing the second data stream.

10. The memory device includes a first memory rank and a second memory rank, The step of processing the first data stream based on the data clock signal that toggles at the aforementioned reference frequency is: The process includes the step of writing the first data stream to the first memory rank or reading the first data stream stored in the first memory rank. The step of processing the second data stream is: The method according to claim 3, further comprising the steps of writing the second data stream to the second memory rank or reading the second data stream stored in the second memory rank.

11. A method for operating a memory device that communicates with a memory controller, The process of receiving a first command and a second command from the memory controller includes a step in which the first command includes setting information for the mode register, and the second command indicates the start of synchronization (initiation) of the data clock signal. A step of changing the setting of the mode register based on the setting information of the mode register, The steps include: preparing for the toggling of the data clock signal within the preparation time interval; A step of processing a first data stream based on the data clock signal that toggles at a reference frequency, Based on the data clock signal toggling at the aforementioned reference frequency and the setting of the modified mode register, the process of processing the second data stream includes the step of the data clock signal toggling a reference number of times, Methods that include...

12. The step of changing the setting of the mode register based on the setting information of the mode register is: The steps include decoding the first command and obtaining the setting information of the mode register, The step includes determining the number of times the data clock signal toggles with respect to the synchronization to the reference number based on the setting information of the mode register, The method according to claim 11, wherein the reference number is greater than the number of times the data clock signal defined by LPDDR5 (Low Power Double Data Rate 5) toggles.

13. The step of receiving the first command and the second command from the memory controller is as follows: The step of receiving the first command from the memory controller, After receiving the first command, the memory controller receives the second command, Immediately after receiving the second command, the memory controller receives a third command for processing the first data stream, The method according to claim 11 or 12, further comprising the step of receiving a fourth command from the memory controller for processing the second data stream after receiving the third command.

14. The second command mentioned above is a CAS (Column Address Strobe) command in LPDDR5, The third command is a write command corresponding to the first data stream or a read command corresponding to the first data stream, The fourth command is a write command corresponding to the second data stream or a read command corresponding to the second data stream, The method according to claim 13, wherein the command received from the memory controller immediately before receiving the fourth command is not a CAS command in LPDDR5.

15. The method according to claim 13, wherein the first time interval is shorter than the second time interval by the time interval corresponding to the second command, the first time interval includes the period from the time of receiving the fourth command to the time when processing of the second data stream is completed, and the second time interval includes the period from the time of receiving the second command to the time when processing of the first data stream is completed.

16. The aforementioned preparation time interval includes, in order, the first to third time intervals. The step of preparing the toggling of the data clock signal within the aforementioned preparation time interval is: The steps include: maintaining the data clock signal in a don't care state within the first time interval; The steps include maintaining the data clock signal in a constant logical state within the second time interval, The method according to any one of claims 11 to 15, comprising the step of pretoggling the data clock signal at a frequency less than or equal to the reference frequency within the third time interval.

17. The memory device includes a first memory rank and a second memory rank, The step of processing the first data stream based on the data clock signal that toggles at the aforementioned reference frequency is: The process includes the step of writing the first data stream to the first memory rank or reading the first data stream stored in the first memory rank. The step of processing the second data stream based on the data clock signal toggling at the aforementioned reference frequency and the setting information of the mode register is: The process includes the step of writing the second data stream to the second memory rank or reading the second data stream stored in the second memory rank, The step of receiving the first command and the second command from the memory controller is as follows: The step of receiving the first command from the memory controller, After receiving the first command, the memory controller receives the second command, Immediately after receiving the second command, the memory controller receives a third command for processing the first data stream, The method according to any one of claims 11 to 16, further comprising the step of receiving a fourth command from the memory controller for processing the second data stream after receiving the third command but before processing the first data stream is completed.

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