Memory device with a low-pin interface and corresponding method and system

Abstract

To provide a memory device interface, an integrated circuit (IC) device, and a system and a method with a high data transfer rate and low pin count.SOLUTION: In an integrated circuit device, a step for receiving a sequence of three or more command value portions on a unidirectional command address (CA) bus having four or fewer parallel inputs, a step for latching each command value portion synchronously with a rising edge of a timing clock CK, a step for determining an input command from the sequence of three or more command value portions, a step for executing the input command, and a step for outputting and inputting the sequence of data values synchronously with rising and falling edges of the timing clock on a bi-directional data bus DQ having six or fewer data inputs / outputs (IO) are included.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present disclosure generally relates to a memory device interface, and more specifically to a memory device interface having a high data transfer rate and a small number of pins.

Background Art

[0002] Memory devices are still important components in most electronic systems. From the perspective of system performance, the data rate of the memory device can be a limiting factor. From the perspective of system power consumption, it is desirable to reduce the power consumption of the memory device as much as possible. At the same time, for many systems such as automobiles, it is also desirable to minimize the system bus size. Therefore, in such systems, memory devices with a low pin count are widely used.

[0003] FIGS. 32A and 32B are diagrams showing the types and performances of conventional memory devices. FIG. 32A shows an example of a memory device 3201A having compatibility with the HyperBus (registered trademark) standard formulated by Cypress Semiconductor Corporation, that is, Infineon Technologies. The memory device 3201A can provide a high-performance solution. In some configurations, the memory device 3201A can operate at a clock speed of about 200 MHz and provide data at both the rising edge and the falling edge of the clock signal (i.e., double data rate, DDR). The device 3201A can include low-voltage CMOS (LVCMOS) signal transmission. The memory device 3201A may be a non-volatile memory device (e.g., NOR flash memory) or a volatile memory (e.g., hidden refresh DRAM).

[0004] Figure 32B shows a memory device 3201B compatible with the low-power DDR4 (LPDDR4) standard JESD209-4D developed by the Japan Semiconductor Technology Association (JEDEC). The memory device 3201B is a synchronous DRAM (SDRAM) that can provide high performance while employing a relatively large number of pins. The memory device 3201B can have differential clock inputs (CK_t / CK_c) and differential data strobes (DS_t / DS_c). Figure 32B shows a device with x8 data inputs / outputs (IO), but other LPDDR4 SDRAMs may have larger IOs (i.e., x16). The memory device 3201B can operate at clock speeds starting from approximately 800 MHz and can utilize low-voltage swing-terminated logic (LVSTL) signal transmission.

[0005] Figure 32C is a timing diagram illustrating the command processing operation of a conventional LPDDR4 device as shown in Figure 32B. In response to an active (high) chip select (CS) signal, the device can latch the first 6-bit portion of the command on the rising edge of the clock signal (CK), and then latch the second 6-bit portion of the command on the next rising edge of the clock signal (CS is inactive).

[0006] While it provides the desired high-speed signal transmission, this conventional approach may not be suitable for low-pin applications due to its high pin count. Furthermore, LPPDR4 SDRAM storage is volatile, making it unsuitable for many applications, such as storing firmware within a system. [Brief explanation of the drawing]

[0007] [Figure 1A] This figure shows the pinout of a memory device according to an embodiment. [Figure 1B] This figure shows the pinout of a memory device according to an embodiment. [Figure 1C] This figure shows the pinout of a memory device according to an embodiment. [Figure 1D] This figure shows the pinout of a memory device according to an embodiment. [Figure 2] This is a timing diagram showing the command input operation according to one embodiment. [Figure 3A] This is a timing diagram comparing the read operation using conventional methods with the operation according to one embodiment. [Figure 3B] This is a timing diagram comparing the read operation using conventional methods with the operation according to one embodiment. [Figure 4] This is a table showing the types and functions of pins in a memory device according to one embodiment. [Figure 5A] This is a timing diagram comparing conventional error correction code (ECC) data transmission with data transmission according to one embodiment. [Figure 5B] This is a timing diagram comparing conventional error correction code (ECC) data transmission with data transmission according to one embodiment. [Figure 5C] This is a timing diagram comparing conventional error correction code (ECC) data transmission with data transmission according to one embodiment. [Figure 6A] This is a timing diagram showing the command bus training operation of the memory device according to the embodiment. [Figure 6B] This is a timing diagram showing the command bus training operation of the memory device according to the embodiment. [Figure 6C] This is a timing diagram showing the command bus training operation of the memory device according to the embodiment. [Figure 7] This is a timing diagram showing the write leveling operation of a memory device according to one embodiment. [Figure 8A] This figure shows the read data bus calibration operation according to one embodiment. [Figure 8B] This figure shows the read data bus calibration operation according to one embodiment. [Figure 9A] This is a timing diagram showing the datastrobe-databus training operation according to the embodiment. [Figure 9B]A timing diagram showing a data strobe-data bus training operation according to an embodiment. [Figure 10A] A timing diagram showing a data strobe interval oscillator operation according to an embodiment. [Figure 10B] A timing diagram showing a data strobe interval oscillator operation according to an embodiment. [Figure 11] A timing diagram showing a read preamble training operation according to an embodiment. [Figure 12A] A timing diagram showing a reference voltage training operation according to an embodiment. [Figure 12B] A timing diagram showing a reference voltage training operation according to an embodiment. [Figure 13] A block diagram of a memory device according to an embodiment. [Figure 14] A block diagram of a memory device according to another embodiment. [Figure 15] A block diagram of an interface circuit according to an embodiment. [Figure 16A] A diagram showing various different interface circuits according to an embodiment. [Figure 16B] A diagram showing various different interface circuits according to an embodiment. [Figure 16C] A diagram showing various different interface circuits according to an embodiment. [Figure 16D] A diagram showing various different interface circuits according to an embodiment. [Figure 16E] [[ID=३९]]A diagram showing various different interface circuits according to an embodiment. [Figure 17A] A diagram of a memory cell array that can be included in an embodiment. [Figure 17B] A diagram of a memory cell array that can be included in an embodiment. [Figure 18] A block diagram of a memory device according to a further embodiment. [Figure 19] A block diagram of a system according to an embodiment. [Figure 20] This is a block diagram of a system according to another embodiment. [Figure 21] This is a block diagram of a memory controller according to one embodiment. [Figure 22A] This is a diagram of a memory controller circuit according to an embodiment. [Figure 22B] This is a diagram of a memory controller circuit according to an embodiment. [Figure 23] This is a diagram of an integrated circuit device according to one embodiment. [Figure 24] This is a diagram of an automobile system according to one embodiment. [Figure 25] This is a flowchart illustrating a method for operating a memory device according to an embodiment. [Figure 26] This is a flowchart of a method for providing error correction code data according to an embodiment. [Figure 27] This is a flowchart of a method for training a memory device according to one embodiment. [Figure 28] This is a flowchart of a method for showing the data output portion using a data mask inversion (DMI) signal according to one embodiment. [Figure 29] This is a flowchart illustrating a method for demonstrating a data bus configuration using DMI signals according to one embodiment. [Figure 30A] This figure compares the performance of a memory device according to one embodiment with the performance of a conventional memory device. [Figure 30B] This figure compares the performance of a memory device according to one embodiment with the performance of a conventional memory device. [Figure 30C] This figure compares the performance of a memory device according to one embodiment with the performance of a conventional memory device. [Figure 31] This figure shows the application of the memory device according to the embodiment. [Figure 32A] This diagram shows a conventional memory device, its performance, and its operation. [Figure 32B] This diagram shows a conventional memory device, its performance, and its operation. [Figure 32C]This diagram shows a conventional memory device, its performance, and its operation. [Modes for carrying out the invention]

[0008] According to the embodiment, the memory device can provide high-speed signal transmission using a relatively small number of pins. Command and address data are receivable over a relatively small command-address (CA) bus, and commands are received in multiple parts over three or more consecutive edges of the timing clock (e.g., rising edge). Data for the memory device is receivable and transmittable at double data rate (DDR) over a relatively small data bus, and as a result, data bytes are received / transmitted over three or more consecutive rising and falling edges of the timing clock.

[0009] In some embodiments, the CA bus may be 3 bits and can receive a 12-bit command as four consecutive 3-bit command portions.

[0010] In some embodiments, the data bus may be 4 bits, and DDR data can be transmitted and received in 4-bit nibbles.

[0011] In some embodiments, the memory device may include data mask inversion (DMI) input / output (IO). The DMI IO can transmit both inverted data and / or error-corrected code (ECC) data in the same single clock cycle when data is transferred on the data bus. In some embodiments, the DMI IO can indicate the upper and lower bits of a data portion when data is transferred in multiple parts on the data bus.

[0012] In some embodiments, during calibration mode, the memory device can simultaneously receive calibration setting data on both the CA bus and the data bus. In some embodiments, the calibration setting data may be reference voltage settings used in CA bus training and / or data bus training operations.

[0013] In some embodiments, the memory device may be a non-volatile memory device that provides high-speed signal transmission using a small number of pins.

[0014] Figure 1A is a block diagram of a memory device 100A according to one embodiment. The memory device 100A can provide relatively high-speed signal transmission while simultaneously having a relatively small number of pins. The main signal transmission pins for the memory device 100A may include a chip select (CS) input, a clock (CK) input, a clock enable (CKE) input, a command address (CA) input, a data strobe (DQS) IO, a data mask inversion (DMI) IO, and a data IO (DQ). The CA input may include five or fewer inputs, while the DQ IO may include six or fewer IOs. In some embodiments, the remaining inputs and IOs may be singular. Thus, the device 100A may have a total number of pins of 16 or fewer (excluding dedicated pins). According to the embodiment, the memory device 100A can store data in non-volatile memory cells, volatile memory cells, or a combination thereof.

[0015] Figure 1B is a block diagram of a memory device 100B according to another embodiment. The memory device 100B may be one implementation example of the memory device shown in Figure 1A. The memory device 100B may include the same items as in Figure 1A, but the CA input can be 3 bits and the DQ IO can be 4 bits. In such a configuration, the memory device 100B can have a relatively small number of pins, 12 pins.

[0016] Figure 1C is a block diagram of a memory device 100C according to another embodiment. The memory device 100C may be one implementation example of the memory device shown in Figure 1A. The memory device 100C may include the same items as in Figure 1B, but the clock input may include complementary clock inputs (CK / CKB). Furthermore, the data strobe I / O may be complementary (DQS / DQSB). In such a configuration, the memory device 100C can have a relatively small number of pins, 14 pins.

[0017] Figure 1D is a block diagram of a memory device 100D according to another embodiment. The memory device 100D may be one implementation example of the memory device shown in Figure 1A. The memory device 100D may include items similar to those in Figure 1B, but may be a dual-channel device providing two different interfaces. Other embodiments may include more interfaces with fewer pins.

[0018] Figure 2 is a timing diagram showing the command input operation according to one embodiment. Figure 2 shows the waveforms related to the clock input CK, the chip select input CS, and the command address input CA[2:0].

[0019] At time t0, CK can transition to high. Simultaneously, CS can go high, activating the device. On the CA bus, it can receive 3 bits of a 12-bit command (CMD1) (CMD[11:9]).

[0020] At time t1, CS can return to low. In the next three high transitions of the clock signal, the remaining 3 bits of the command (CMD[8:6], CMD[5:3], CMD[2:0]) can be received. Figure 2 shows the second command (CMD2) received immediately after the first command.

[0021] Figures 3A and 3B are timing diagrams comparing a conventional read access operation compatible with the LPDDR4 standard with a read access operation according to one embodiment. Figure 3A is a timing diagram showing the CK input and CS input, the 6-bit CA[5:0] input, the DQS IO, and the 8-bit DQ[7:0] IO.

[0022] At time t0, on the rising edge of CK, CS can be high and receive the first 6 bits of the first activation command (ACT1). CS can then return to low. On the next rising edge of the CK signal, it can receive the last 6 bits of ACT1. At time t1, it can receive the second activation command (ACT2).

[0023] At time t3, the read command pair (READ / CAS2) can be entered following the activation command (ACT1 / ACT2). The CAS2 command must be completed after the RAS-to-CAS delay (tRCD) shown at times t2-t5, which follows the last 6 bits of ACT2.

[0024] At time t6, following the read latency (RL) after the last part of the CAS2 command, the data strobe signal (DQS) can be activated to enable data output. At time t7, the DQS can transition to active over the preamble time tRPRE. At time t8, the DQS can initiate the transition synchronously with CK, and data can be output on DQ[7:0] at double the data rate in timing with the DQS. Eight bits can be output every half-clock cycle over eight clock cycles (shown as D0-D15). Following the output of the read data, the DQS can remain active over the postamble period (tRPST).

[0025] Figure 3B corresponds to Figure 3A, but is a timing diagram showing the read operation when using a device like the one in Figure 1B. Figure 3B has waveforms for the same signal set, but the CA input is 3 bits instead of 6 bits, and the DQ IO is 4 bits instead of 8 bits.

[0026] In some embodiments, the read operation in Figure 3B can execute the same commands as in Figure 3A, but the commands are received over more clock cycles and the read data is output over more clock cycles. In some embodiments, the read operation in Figure 3B can be operated under the same timing constraints as in Figure 3A, which include tRCD, RL, tDQSCK, tRPRE, and tRPST.

[0027] Referring further to Figure 3B, at time t0, on the rising edge of CK, CS becomes active and the ACT1 command is received. However, only 3 bits of the 12-bit command are received. When CS returns to low, on the three subsequent rising edges of CK, different 3-bit portions of ACT1 can be received until all 12 bits are received.

[0028] At time t1, it is possible to receive ACT2 commands that are clocked on four rising edges using the same method as ACT1.

[0029] As described in Figure 3A, READ and CAS2 commands cannot be received earlier than the tRCD period, but each of these commands can be received by dividing it into four 3-bit parts.

[0030] At time t8, the read data can be output in DDR format, but over 16 clock cycles on a 4-bit data bus (shown as D0 to D31).

[0031] In this way, memory devices with a small number of pins can execute commands that are compatible with existing standards. In some embodiments, the memory device is compatible with the LPDDR4 standard, but is also compatible with additional clock cycles for receiving command address values, inputting data values ​​in write operations, and outputting data values ​​in read operations.

[0032] Figure 4 is a table showing the types and functions of interface connections (i.e., pins) according to the embodiment. The CS, CK, and CKE inputs can function in a conventional manner, and some embodiments include differential clocks (CK_t, CK_c).

[0033] The CA[2:0] bus may be a reduced-size bus to enable a small number of pins. Optionally, the CA[2:0] bus can receive calibration data, such as a portion of a reference voltage value, in calibration mode. The functionality of the CA[2:0] bus can be established by setting the mode register.

[0034] The DQS IO can function as a data alignment signal synchronized with CK, and can optionally include differential signals (DQS_t, DQS_c).

[0035] The DMI IO can have any of several functions, including providing a data masking value in a write operation, indicating data inversion, providing ECC data, and / or indicating the upper and lower nibbles of the same byte for data output on bus DQ[3:0]. The function of the DMI signal can be established by setting the mode register.

[0036] DQ[3:0] may be a reduced-size data I / O bus.

[0037] Figure 4 also includes support inputs that can be included in the embodiment. RESET_n and ODT(ca) may have conventional functions.

[0038] Figures 5A to 5C are timing diagrams comparing conventional ECC data transmission with ECC data transmission according to one embodiment.

[0039] Figure 5A shows a conventional configuration for providing "in-band" ECC data. 64 bits of data are transmitted in bursts of 8 over DQ[7:0]. Data transmission is DDR, with 8 bits of data transmitted synchronously with the rising and falling edges of the clock (CK_t). DMI IO can indicate data inversion (e.g., DMI high) or not for each 8-bit data value. The 8-bit ECC data (ECC7:0) corresponding to the 64 bits of data is provided over DQ[7:0] after the data burst. That is, additional bus time is required to receive the ECC data.

[0040] Figure 5B shows a conventional configuration for providing "out-of-band" ECC data. Similar to Figure 5A, 64 bits of data are transmitted over DQ[7:0] by DMI values. However, ECC I / O is also included, which allows each data byte on DQ[7:0] to transmit bits of ECC data. Such a configuration requires a further increase in the number of pins.

[0041] Figure 5C illustrates "in-band" ECC data transmission according to one embodiment. Figure 5C shows waveforms relating to a timing clock CK, a reduced-size data bus DQ[3:0], and a multifunction I / O (DMI). 64 bits of data are transmitted over DQ[3:0] in 16 bursts. The data transmission is DDR, with 4 bits of data (i.e., nibbles) transmitted synchronously with the rising and falling edges of the clock (CK). The DMI signal can provide both a data mask inversion value (across two nibbles) and an ECC value within a single clock cycle. For example, the data mask inversion value DMI0 can indicate a data inversion across nibbles D3:0 and D7:4. Such a configuration can enable in-band transmission of ECC data without requiring additional data bus time.

[0042] In some embodiments, the DMI signal indicates data masking for write operations. When the DMI signal has one value (e.g., high), the data value can be masked from being written to the device. When the DMI signal has another value (e.g., low), the data can be written to the device. Referring to Figure 5C, there are no ECC values ​​in the data masking operation. As a result of the DMI value being high over nibble D3:0, such a value will not be written. If the DMI signal was low in the next half-cycle (shown as ECC0), nibble D7:4 will be written.

[0043] Figures 6A and 6B are timing diagrams of command bus training operations for a memory device according to one embodiment. Figure 6A includes waveforms for CK, CKE, CS, CA[2:0], DQS, DQ[3:0], and DMI, or their equivalents, which may be described herein. Figure 6A also includes the following other waveforms: Command, which describes the value input on CA[2:0]; VrefCA, which is the state for the calibration reference voltage; and ODT for DQ, which is the on-die termination state for the DQ bus. Figure 6B includes the same waveforms as Figure 6A, but shows DQ[2:0] and DQ[3] separately.

[0044] Referring to Figure 6A, at time t0, the memory device can receive two 12-bit commands (e.g., mode register write commands, MRW-1 / MRW-2), which can transition the memory device into command bus training mode. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein.

[0045] At time point t1, which is a predetermined time period before CKE transitions to low, DQS can transition to low. At time point t2, CKE can transition to low. Subsequently, the value of the frequency setpoint (FSP) can be updated (shown in VrefCA), switching between mode registers can be initiated (shown in ODT_CA), and transitions to ODT settings for data I / O can be initiated (shown in ODT for DQ[3:0]).

[0046] At a predetermined time point t3, a portion of the reference value Vref[3:0] can be driven on DQ[3:0]. DMI can be set low to indicate that this reference value portion includes the lower bits (i.e., less significant bits) of the Vref value.

[0047] At time point t4, DQS_t can strobe high to indicate that the Vref[3:0] value exists on DQ[3:0]. In some embodiments, DQS_t can strobe high two or more times to ensure that the reference value is captured.

[0048] At time t5, a second portion of the reference value, Vref[6:4], can be driven on DQ[3:0]. DMI can be driven high to indicate that this reference portion contains the higher bits (i.e., more significant bits) of the Vref value. At time t6, DQS_t can be driven high once or multiple times to indicate the existence of the second reference portion. In the illustrated embodiment, the reference value is 7 bits, but alternative embodiments may include more or fewer bits, including a 4-bit value that does not include the DMI transition.

[0049] At time t7, the calibration pattern (Pattern A) can be driven on CA[2:0].

[0050] Referring to Figure 6B, at time t8, following the application of the calibration pattern on CA[2:0], the pattern (pattern A) received by the memory device can be provided on DQ[2:0]. In the illustrated embodiment, DQ[3] can be driven to a predetermined level (high in this case) to signal that a captured pattern value is present. In an alternative embodiment, DMI can be used to signal that captured pattern data is present. At time t9, DQ[3] can return to its previous level (low in this case).

[0051] In the illustrated embodiment, at time t10, the second calibration pattern (pattern B) can be applied to CA[3:0], and the calibration operation can be continued.

[0052] Figure 6C is a timing diagram of a command bus training operation according to another embodiment. The training operation can be carried out by training mode commands, as shown between time points t0 and t1 in Figure 6A.

[0053] Unlike in Figure 6A, at time t3, calibration data can be provided on both the CA[2:0] bus and the DQ[3:0] bus. At time t4, DQS_t can be activated once or multiple times to indicate the presence of calibration data. In some embodiments, DMI IO can be driven low, thereby indicating that DQ[3:0] should operate as an input. The calibration operation can then proceed as shown in Figure 6B, with a calibration pattern being applied on CA[2:0], and subsequently, at time t8, such a pattern detected by the memory device can be output on DQ[3:0]. In some embodiments, DMI IO can be driven high, thereby providing pattern data, indicating that DQ[3:0] should operate as an output.

[0054] Figure 7 is a timing diagram of the write leveling operation for a memory device according to one embodiment. Figure 7 includes waveforms for CK, CKE, CS, CA[2:0], Command, DQ[3:0], and DMI as described herein. Figure 7 also includes the differential data strobe signal DQS_t / (c). However, alternative embodiments may include a single-ended DQS signal.

[0055] At time t0, the memory device can receive two 12-bit mode register write commands (MRW-1, MRW-2), which can transition the memory device into write-leveling mode. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein.

[0056] At time point t1, following the time period tWLMRD after the last part of MWR-2, the data strobe signal (DQS_t or DQS_c) can transition. The time period tWLMRD can be established by the controller device. At this time, the memory device can sample the strobe signal to generate a feedback value. In some embodiments, the clock CK can be used to sample the data strobe signal (DQS_t or DQS_c). If the sampled DQS signal has one value (e.g., high), then all data bus DQ[3:0] can have that value (e.g., high). If the sampled DQS signal has another value (e.g., low), then all data bus DQ[3:0] can have that value (e.g., low).

[0057] At time t2, the memory device can output a feedback value (e.g., the sampled clock state) following the write leveling output delay (tWLO). The first part of the feedback value can be output (Fdbk[3:0]). At time t3, the second part of the feedback value can be output (Fdbk[7:4]). The DMI value is variable and indicates a change in the nibble value (in this case, the higher bits). At time t4, the third part of the feedback value can be output (Fdbk[11:8]), followed by the fourth part (Fdbk[15:12]).

[0058] The controller can use this feedback value to adjust the placement of the DQS_t / DQS_c signals relative to the clock CK.

[0059] Figures 8A and 8B illustrate the read data bus (RD DQ) calibration operation for a memory device according to one embodiment. Figure 8A is a timing diagram including the waveforms described herein. Figure 8B includes a table showing the bit sequence outputs on the DQ IO and DMI IO during the RD DQ calibration operation.

[0060] Referring to Figure 8A, at time t0, the memory device can receive two 12-bit commands, including a multipurpose command (MPC-1) followed by a CAS-2 command. Such commands can transition the memory device into RD DQ calibration mode. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein. In RD DQ calibration mode, the memory device can access a mode register and output a pattern defined in such a register on the DQ output.

[0061] At time point t3, the test pattern can be output on the reduced-size bus DQ[3:0] following the read latency (RL) and output access time (tDQSCK).

[0062] Referring to Figure 8B, Table 802 shows the bit sequences that can be output on the DQ IO according to the values ​​stored in the mode register 804. The mode register 804 can store values ​​corresponding to test patterns and inversion masks for such test patterns. In the illustrated RD DQ calibration operation, the DMI values ​​are not inverted, and no inversion of the DQ output values ​​is instructed. The register value 804 may be programmable and can also be set to a default value.

[0063] Figures 9A and 9B are timing diagrams showing the data strobe-to-data bus (DQS-DQ) training operation for a memory device according to one embodiment. The DQS-DQ training operation can generate a test pattern to enable the data strobe signal DQS to be properly aligned with the DQ value (for example, DQS enables DQ data latching at the center of the data). Figure 9A shows the test FIFO write operation. Figure 9B shows the test FIFO read operation.

[0064] Referring to Figure 9A, at time t0, the memory device can receive two 12-bit commands, including a multipurpose command (MPC WR FIFO) followed by a CAS-2 command. Such commands can transition the memory device into write mode to the test FIFO. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein. In the illustrated embodiment, the write FIFO command is repeated at time t1.

[0065] At time t2, following write latency and other timing constraints, the write data value can be driven on DQ[3:0] (and optionally DMI). The data value can be selected by the controller device, etc. Furthermore, the data value DQ[3:0] can be provided by a data strobe value DQS_t with an initial timing. Such write data value can be stored in the entry (entry x) of the test FIFO. The test data can take any appropriate form depending on the type of training for the controller. In the illustrated embodiment, at time t3, due to the timing of the write commands to the two test FIFOs, the data for the next entry (entry x+1) can follow the data of the previous entry. In some embodiments, each write FIFO operation can write data to the next FIFO entry until the last FIFO entry is reached.

[0066] Referring to Figure 9B, after test data is written to a test FIFO with an initial DQS_t timing, such data values ​​can be read from the test FIFO to evaluate the DQS_t timing.

[0067] Referring to Figure 9B, at time t0, the memory device can receive two FIFO read commands, each consisting of an MPC RD FIFO command followed by a CAS-2 command.

[0068] At time point t1, following read latency and other delays, the data value from the first FIFO entry (entry x) can be output on DQ[3:0] (and optionally DMI). The controller can determine the performance of the current DQS_t timing from such data value and adjust such timing as needed. In the illustrated embodiment, at time point t2, due to the timing of read commands from the two test FIFOs, the data for the next entry (entry x+1) can follow the data of the previous entry. In some embodiments, each read FIFO operation can read data from the next FIFO entry until the last FIFO entry is reached.

[0069] Figures 10A and 10B are timing diagrams showing the read operation of a DQS interval oscillator for a memory device according to one embodiment. In such operation, the oscillator, including the DQS clock tree path, can be started and stopped to generate a count value. The count value can be used to detect any fluctuations in the DQS clock tree path. If such fluctuations are sufficiently large, the memory device can be retrained.

[0070] Referring to Figure 10A, at time t0, the memory device can receive a 12-bit multipurpose command to start the DQS interval oscillator. The command can be received in four 3-bit portions on the consecutive rising edges of the CK signal as described herein.

[0071] At time point t1, after a measurement period selectable by the controller, the memory device can receive a 12-bit multipurpose command to capture the count value. The command can be received in the same manner as the oscillator start command (MPC command). Upon receiving the oscillator stop command, the count value can be stored in the register.

[0072] At time t2, a read register command can be issued to read a counter value from the appropriate register. In the illustrated embodiment, this command may include two 12-bit commands, one of which is a mode register read (MRR) command followed by a CAS-2 command. In some embodiments, such a command cannot be received earlier than a predetermined delay (tOSCO).

[0073] At time point t3, the oscillator counter value from the register can be output on DQ[3:0], following the read latency and other delays. From such data values, the controller can determine whether additional training is required to account for the delay changes introduced by the DQS_t clock tree path.

[0074] Figure 10B is a timing diagram of an alternative method for obtaining the count value of the DQS interval oscillator. The operation of Figure 10B may be the same as the operation of Figure 10A, but the read register command (issued at t1) can result in both storing the count value in a register and then outputting the count value on DQ[3:0] (at time t3).

[0075] Figure 11 is a timing diagram of a read preamble training operation for a memory device according to one embodiment. Figure 11 includes waveforms as described herein. The read preamble training operation can be used to establish read preamble timing for the DQS_t signal. Although Figure 11 shows only DQS_t, other embodiments may include differential data strobe signals DQS_t / DQS_c, in which case DQS_c is driven to the opposite level of DQS_t.

[0076] At time t0, the memory device can receive 12-bit commands MRW-1 and MRW-2, which can transition the memory device into read preamble training mode. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein. After a delayed tDSO following the last 3-bit portion of MRW-2, DQS_t can be driven low at time t1. Following such a transition, the memory device will no longer lead output data with a standard preamble or follow output data with a standard postamble.

[0077] At time t2, the memory device can receive 12-bit commands MPC-1 and CAS-2 over eight rising CK transitions to initiate training. At time t3, in response to such commands, following read latency and other delays (e.g., tDQSCK), the DQS_t signal can transition synchronously to a data output on DQ[3:0]. In some embodiments, such output data may be data stored in a register (e.g., the register shown in Figure 8B). The controller can evaluate or train its DQS receiver from such data.

[0078] Figures 12A and 12B are timing diagrams illustrating the CA Vref training operation according to an embodiment. The CA Vref training operation can be used to establish a reference voltage for the CA input. However, the same process may be used to establish any other suitable reference value in the memory device. Figure 12A is a timing diagram showing a waveform as described herein. Figure 12B is a timing diagram detailing the data contained in a received command.

[0079] Referring to Figure 12A, at time t0, the memory device can receive 12-bit commands MRW-1 and MRW-2, which can initiate the memory device into a reference value setting operation. Such commands can be received in four 3-bit portions on consecutive rising edges of CK, as described herein.

[0080] Following the reception of the final portion of the MRW-2 signal, a new reference value can be established after a delay of Vref_time. In some embodiments, the delay of Vref_time can be modified depending on the magnitude of the change.

[0081] Referring to Figure 12B, the structure of a command in a reference setting operation according to one embodiment is shown in the timing diagram. The types of data included in the command may include command data CMD (i.e., bits that identify the command), address value ADD (i.e., bits that identify the register address), reference value Vref (i.e., bits that can set the reference value), and DATA (which may contain other data).

[0082] In the embodiment shown in Figure 12B, a first command (MRW-1) may contain command data in two first parts and address data in two second parts. A second command (MRW-2) may contain command data in two first parts and reference values ​​in two second parts. In one embodiment where the reference value establishes the CA reference voltage, such a reference value may contain 1 bit for a range of Vref(CA) values ​​and 6 bits for setting the Vref(CA) value.

[0083] It should be understood that the specific values ​​shown in Figure 12B are merely examples and should not be interpreted as limiting.

[0084] The command data and address data values ​​for the various operations shown in Figures 6A to 12B can take any suitable form. However, in some embodiments, the command and address values ​​can be compatible with the LPDDR4 standard (JESD209-4D) and can be transmitted on a new CA bus in the manner described herein and its equivalents.

[0085] Figure 13 is a block diagram of a memory device 1302 according to one embodiment. The memory device 1302 may include an x4 DDR interface (I / F) circuit 1304, one or more memory arrays 1306, and a control circuit 1308. The x4 DDR I / F circuit 1304 may include CK, CS, CA[2:0] inputs, as well as DQS, DQ[3:0] and DMI IO, or their equivalents, as described herein. The CK and DQS inputs are shown as single-ended, but in alternative embodiments, one or both of such inputs may be differential inputs. Since data is transmitted in parallel as nibbles over DQ[3:0] as described herein, the x4 DDR I / F 1304 may be a parallel interface. The x4 DDR I / F circuit 1304 may include a DMI control circuit 1304-0, which can provide DMI I / O with functions beyond indicating data masking during write operations or data inversion during read or write operations. Such additional functions may include, but are not limited to, providing ECC data for read and write operations, indicating upper or lower nibble indicators for read or write data on DQ[3:0] and / or indicating the state of DQ[3:0] (e.g., data reception or transmission).

[0086] In some embodiments, the x4 DDR IF 1304 may include an oscillator circuit 1304-1. The oscillator circuit 1304-1 may include at least a portion of the DQS signal path and can be used to determine a delay value for the DQS signal path. In some embodiments, the x4 DDR I / F circuit 1304 may include a training circuit 1304-2. The training circuit 1304-2 may allow data received on CA[2:0] to be provided to circuits other than the command and / or address decoding circuit. In some embodiments, the training circuit 1304-2 may allow a portion of a reference value, such as a portion that establishes a reference voltage, to be input on the DQ[3:0]IO together with another portion of the reference value.

[0087] The memory array 1306 may include one or more memory cell arrays, each capable of storing data in a write operation and outputting data in response to a read operation. The memory cell array may include any suitable type of memory cell (e.g., volatile, non-volatile) or architecture (random access, NOR, NAND). The memory array 1306 may also include corresponding decoding circuits, read path circuits and write path circuits, and in the case of non-volatile memory cells, program circuits and erase circuits.

[0088] The control circuit 1308 can control the operation of the memory device and may include logic for performing operations indicated by commands received via the x4 DDR I / F 1304. The control circuit 1308 may include registers 1308-2 (e.g., mode registers) for storing configuration values ​​and other values. All or part of such registers 1308-2 may be accessible by mode register read commands and mode register write commands.

[0089] In some embodiments, the control circuit 1308 may include a FIFO 1308-1 and / or a reference voltage generator 1308-0. The FIFO 1308-1 can store the value received by the x4 DDR IF 1304 during calibration operation for subsequent readout. The reference voltage generator 1308-0 can generate a reference voltage in response to the configured reference value received by the x4 DDR IF 1304.

[0090] Figure 14 is a block diagram of a memory device 1402 according to another embodiment. The memory device 1402 may include items similar to those in Figure 13, such items being referenced by the same reference numerals, but with the leading digit being "14" instead of "13". The memory device 1402 may differ from the memory device in Figure 13 in that the memory array is located in banks 1406-0 to -3, and the memory device 1402 may further include a serial IF 1410. The serial IF 1410 can enable serial data transactions on one or more serial data I / Os (four, indicated as S_DQ0 to S_DQ3) in synchronization with the serial clock S_CK and the serial chip select S_CS. In some embodiments, the serial IF 1410 may be compatible with the Serial Peripheral Interface (SPI) standard. However, alternative embodiments may include interfaces compatible with any other suitable serial standard.

[0091] Each bank (1406-0 to -3) can contain multiple non-volatile memory (NVM) cells. Within each bank (1406-0 to -3), one or more arrays of NVM cells can be arranged. The NVM cells can take any suitable form, and in some embodiments, they may be "flash" type NVM cells. Each bank (1406-0 to -3) is independently addressable. That is, the physical addressing of the device 1402 can have a separate bank address for each bank (1406-0 to -3). In the illustrated embodiment, all banks (1406-0 to -3) can be connected to the first bus system 1412A or the second bus system 1412B. The first bus system 1412A can connect banks (1406-0 to -3) to the x4 DDR IF 1404, and the second bus system 1412B can connect banks (1402-0 to -3) to the second I / F 1406. Figure 14 shows a device with four banks, but embodiments may include more or fewer banks.

[0092] Figure 15 is a block diagram of an interface circuit 1514 that may be included in the embodiment. The interface circuit may include a physical receive circuit 1516-0 and a physical transmit circuit 1516-1, a CA input circuit 1518, a data input path circuit 1520, a data output path circuit 1522, a training path circuit 1524, and a DMI control circuit 1504-0. In some embodiments, the receive and transmit circuits 1516-0 / 1 may be low-voltage swing-terminated logic (LVSTL) circuits.

[0093] The CA input circuit 1518 can receive a 3-bit value from the CA[2:0] input and provide a value such as CA DATA IN. In some embodiments, CA DATA IN may be a 6-bit input value formed from two 3-bit input values. In some embodiments, the CA input circuit 1518 can also provide data from CA[2:0] to the training path circuit 1524.

[0094] The data input path circuit 1520 can receive a 4-bit data value from DQ[3:0] and provide such a value as the internal data DATA_INT. The data output path circuit 1522 can receive output data from DATA_INT and provide data such as a 4-bit data value on DQ[3:0]. In some embodiments, DATA_INT may be a larger multiple of 4 bits, such as 8 bits, 16 bits, etc. The training path circuit 1524 can selectively connect the data received on the CA[2:0] input to the data output path circuit 1522, as in CA training mode.

[0095] The DMI control circuit 1504-0 can enable the DMI IO to provide a variety of functions, including, but not limited to, providing ECC data for read and write operations, indicating the upper or lower nibble value for read or write data on DQ[3:0], or indicating whether DQ[3:0] should transmit or receive data, in addition to data masking and data inversion. The DMI control circuit 1504-0 can receive output DMI values, provide DMI input values ​​(DMI IO), and provide and / or receive ECC data.

[0096] Figure 16A is a schematic diagram of a CA input circuit 1618 according to one embodiment. The CA input circuit 1618 may include an input latch 1618-0, an input demultiplexer (deMUX) 1618-1, a deMUX logic 1618-3, and a command latch 1618-2. The input latch 1618-0 can latch a 3-bit value from CA[2:0] in response to a clock signal CK', which can be generated in response to a CK input (and possibly as another input state such as CS). In response to the deMUX logic 1618-3, the deMUX 1618-2 can selectively pass the 3-bit value to multiple different positions in the command latch 1618-2. The command latch 1618-2 can form a 12-bit command, which can be processed by a command decoding circuit or the like. The DeMUX logic 1618-3 can generate a signal to clock by dividing the CA[2:0] into 3-bit portions to form a 12-bit command.

[0097] The embodiment in Figure 16A shows a configuration in which a 3-bit value is converted to a 12-bit value for processing by a command decoding circuit, etc., but such embodiments should not be interpreted as limiting. Alternative embodiments may include a device that commands a command decoding circuit that operates based on the 3-bit portion of the command.

[0098] Figure 16B is a schematic diagram of a data path 1620 / 1622 according to one embodiment. In the illustrated embodiment, the data input path 1620 may include a DQ latch 1620-0, an input data control logic 1620-1, an input deMUX 1620-2, and an input data latch 1620-3. The DQ latch 1620-0 can latch a 4-bit value from DQ[3:0] in response to a signal DQS', which can be formed in response to an input data strobe and other signals. In response to the input deMUX logic 1620-1, the input deMUX 1620-2 can selectively pass the 4-bit value to multiple different positions in the input latch 1620-3. The input data latch 1620-3 can form an 8-bit data value, which may or may not form part of a larger data value.

[0099] The data output path 1622 may include an output data latch 1622-0, output data control logic 1622-1, output MUX 1622-2, and output driver 1622-3. The output data latch 1622-0 can store an 8-bit value for output on DQ[3:0]. In response to the output MUX logic 1622-1, the output MUX 1622-2 can selectively pass a 4-bit value as output data from several different locations on the output latch 1622-0. Such data values ​​can be driven on DQ[3:0] by the output driver 1622-3.

[0100] According to the embodiment, in some operations (as shown in Figure 6C), the DMI IO can indicate the state of the DQ[3:0] IO. Figure 16C is a schematic diagram showing one such embodiment. Figure 16C includes a data output path circuit 1620B, a data input path circuit 1622B, a DMI control circuit 1604-0, and a mode control circuit 1624. The data output path circuit 1620B can provide data for output on DQ[3:0] and can be enabled or disabled by the mode control circuit 1624. The data input path circuit 1622B can receive data as input data on DQ[3:0] and can also be enabled by the mode control circuit 1624.

[0101] The DMI control circuit 1604-0 can receive an input DMI signal and provide an output DMI signal. Furthermore, in response to the mode control circuit 1624 detecting a low DMI input signal, the data input path circuit 1622B can receive input data (e.g., calibration values) on DQ[3:0] (and possibly on the CA bus). Subsequently, the DMI control circuit 1604-0 can generate a DMI output signal indicating that DQ[3:0] is providing output data (e.g., a test pattern received on the CA bus).

[0102] According to the embodiments, in some operations (as shown in Figures 6A and 7), the DMI IO can indicate the importance of the output nibble on the DQ[3:0] IO. Figure 16D is a schematic diagram of one such embodiment. Figure 16D includes a data output path circuit 1620D, a data input path circuit 1622D, and a DMI control circuit 1604-0. The data output path circuit 1620D can provide data for output on the DQ[3:0] as described with respect to Figure 16B, where the 4-bit data value is a multiplexed output in response to the NIBBLE_CTRL signal. The data input path circuit 1622B can receive data on the DQ[3:0] or its equivalent according to any embodiment of the herein.

[0103] The DMI control circuit 1604-0D may include an output unit 1604-0_Out that provides an output DMI signal and an input unit 1604-0_In that receives an input DMI signal. Furthermore, in response to a mode control signal MODE, the output unit 1604-0_Out may generate a DMI output signal indicating the nibble importance and / or nibble value change of data on the DQ[3:0]IO. Similarly, the input unit 1604-0_In may receive an input DMI signal indicating the nibble importance and / or nibble value change of data on the DQ[3:0]IO. As just two examples from many possible scenarios, in one type of calibration operation, the input DMI signal may have one value (e.g., low) to indicate that the lower bits of the input reference value are present on DQ[3:0], and then another value (e.g., high) to indicate that the higher bits of the input reference value are present on DQ[3:0]; and in another type of calibration operation, an output DMI signal may be generated that has one value (e.g., low) when the lower bits of the output value are driven on DQ[3:0], and an output DMI signal may be generated that has another value (e.g., high) when the higher bits of the output value are driven on DQ[3:0].

[0104] According to the embodiment, in some operations (as shown in Figure 6C), data received on CA[2:0] can be combined with data received on DQ[3:0] to form a reference value (e.g., Vref[5:0]). Figure 16E is a schematic diagram of one such embodiment. Figure 16E includes a CA input circuit 1618E, a data input path circuit 1620E, a data output path circuit 1622E, and a training path circuit 1624 (with a DMI control circuit 1604-0E). The data input path circuit 1620E can receive data input values ​​and their equivalents as described herein. The data output path circuit 1622E can provide data output values ​​and their equivalents as described herein.

[0105] The CA input circuit 1618E can receive 3-bit CA[2:0] values ​​and provide them to the command and / or address decoder. However, the CA input circuit 1618E may further include a circuit 1618-4 that provides the CA[2:0] input values ​​to the training path circuit 1624.

[0106] In some embodiments, the training path circuit 1624 may include a circuit 1624-1 for selectively providing data from CA[2:0] (e.g., a CA pattern) as output data on the data output path circuit 1622E. In some embodiments, the training path circuit 1624 may include a circuit 1624-0 for selectively providing data from CA[2:0] (e.g., Vref[2:0]) as part of a reference value, and DQ[3:0] provides another part of the reference value (e.g., Vref[6:4]).

[0107] The embodiments shown in Figures 16B to 16E illustrate a configuration in which a 4-bit value on DQ[3:0] is converted to an 8-bit value for transmission on the internal data bus; however, such embodiments should not be construed as limiting. Alternative embodiments may include devices having a native narrowband (e.g., 3-bit CA, 4-bit data) internal bus.

[0108] The embodiments may include any suitable memory cell array structure, but some embodiments may include a 1-transistor (1T) NOR array. Figure 17A is a schematic diagram of a 1T NOR array 1706A that may be included in the embodiments. Array 1706A may include a plurality of memory cells (one shown as 1726-0) arranged in rows and columns, where memory cells in the same row are connected to the same word line (one shown as 1726-2), and memory cells in the same column are connected to the same bit line (one shown as 1726-3). In some embodiments, the memory cell (1726-0) can be formed by a single transistor structure having a charge storage structure 1726-1 between a control gate and a channel. The charge storage structure 1726-1 can store one or more bits of data as charge (including no charge). The charge storage structure 1726-1 can take any suitable form, including, but not limited to, a floating gate, a charge storage dielectric (e.g., a replacement gate), or a combination thereof.

[0109] The embodiment may include non-volatile memory cells, but the embodiment may also include any suitable volatile array structure or volatile memory cell type. Figure 17B is a schematic diagram of a possible volatile memory cell array that may be included in the embodiment. Figure 17B shows array 1706B which may include a plurality of volatile memory cells (one shown as 1726-0V), which are arranged in rows and columns and connected to one or more bit lines (e.g., 1726-3) and word lines (e.g., 1726-2). The volatile memory cells may take any suitable form, including, but are not limited to, DRAM cells 1726-0V1 and / or SRAM cells 1726-0V2. The SRAM cell 1726-0V2 may include, but are not limited to, 4-transistor (4T), 6T and / or 8T variations.

[0110] Figure 18 is a block diagram of an NVM device 1802 according to a further embodiment. The NVM device 1802 may be any one implementation example of the NVM devices shown herein. The NVM device 1802 may include an x4 LPDDR4 IF 1804, multibanks 1806-0 to -7, a control circuit 1808, and a quad SPI (QSPI) compatible IF 1810. The x4 LPDDR4 IF may include a CS input, a CK input, a CKE input, a CA[2:0] input, a DQS IO, a DMI IO, and a DQ[3:0] IO. In some embodiments, the x4 LPDDR IF may have signaling requirements compatible with the LPDDR4 standard (JESD209-4D), but may receive commands on a reduced-size CA bus and provide data on a reduced-size DQ bus or its equivalent, as described herein. In some embodiments, the x4 LPDDR4 IF1804 may have differential signal transmission, including either differential clock inputs (CK_t, CK_c) or differential data strobes (DQS_t, DQS_c).

[0111] In some embodiments, each bank (1806-0 to -7) may contain multiple NVM cells arranged in rows and columns. Each bank (1806-0 to -7) is individually accessible via a unique bank address. In some embodiments, the NVM cells may be group erasable (e.g., flash cells). A first bank access circuit 1828-0 can enable read and write access to its corresponding bank (1802-0 to -7) from the x4 LPDDR4 IF1804 via the first bus system 1812A. A second bank access circuit 1828-1 can enable read or write access to its corresponding bank (1802-0 to -7) from the QSPI IF1810 via the second bus system 1812B. Different bank access circuits 1828-0 / 1 can enable simultaneous access to different banks via different interfaces 1804 / 1810.

[0112] The control circuit 1808 can control the operation of the device 1802 and may include any of the control circuit features described herein, including the features shown in Figure 13.

[0113] The QSPI IF1810 can include a serial chip select SPI_CS, a serial clock input SPI_CK, and four serial data I / Os SPI_DQ. These I / Os can be connected to an SPI-compatible serial bus. The QSPI IF1810 can process commands received via SPI_DQ. Such commands can include both read and write commands (e.g., program commands, erase commands).

[0114] The embodiments may include devices, circuits, and corresponding methods and operations, but the embodiments may also include systems having devices with reduced pin counts interconnected by a small, high-performance bus. Figure 19 shows one such embodiment.

[0115] Figure 19 is a block diagram of a system 1930 according to one embodiment. The system 1930 may include a host microcontroller (MCU) 1932, a first memory device 1902, and a second memory device 1934. The host memory device 1932 may include an x4 DDR4 controller (controller) 1932-0. The controller 1932 may be connected to a DDR bus 1936, which may include signal lines via one of the low-pin-count interfaces described herein. The DDR bus 1936 may include CS inputs (CS_dram, CS_nvm) for each device. Figure 19 shows a bus 13 of a size that can accommodate devices such as the device shown in Figure 1B, but alternative embodiments may include smaller or larger bus sizes.

[0116] The first memory device 1902 may be a low-pin NVM device according to any embodiment of this specification. The second memory device 1934 may be a low-pin NVM device according to any embodiment of this specification. In this way, the system 1930 can include volatile and non-volatile storage, while also including high-performance signal transmission over a reduced-size bus.

[0117] Figure 20 is a block diagram of another system 2030 according to one embodiment. System 2030 may include a host system 2032, an x4 LPDDR bus 2036, a serial bus 2040, and several other devices, three of which are shown as 2002, 2034, and 2038. The host system 2032 may include an x4 LPDDR4 memory controller (MC) 2032-0 and a serial bus MC2032-1. The x4 LPDDR4 MC2032-0 can access the devices via the x4 LPDDR4 bus 2036 by issuing commands and data according to embodiments or equivalents disclosed herein. The x4 LPDDR4 bus 2036 may include a reduced-size CA bus (i.e., 5 or fewer) and a reduced-size DQ bus (i.e., 6 or fewer) according to embodiments and equivalents disclosed herein. The serial bus MC2032-1 can access the device via the serial bus 2040, which complies with any suitable serial communication protocol.

[0118] Device 2002 may be an NVM device having an NVM array 2006, connectable to an x4 LPDDR bus 2036 via an x4 LPDDR IF2004, and connectable to a serial bus 2040 via a serial bus IF2010. Device 2002 may take the form of any of the devices described herein and their equivalents. Device 2034 may be a DRAM device, connectable to an x4 LPDDR bus 2036 via an x4 LPDDR IF2004D. Device 2038 may be a serial device 2038 connected to a serial bus 2040.

[0119] The x4 LPDDR4 MC2032-0 can issue commands (and optionally) data to the devices 2002 or 2034 or their equivalents as described herein.

[0120] The embodiments may include devices, systems, and corresponding methods, but the embodiments may also include a memory controller capable of generating commands, addresses, and data values ​​via an x4 LPDDR I / F and its equivalents as described herein. Figure 21 shows a memory controller 2132-0 according to such an embodiment.

[0121] The memory controller 2132-0 may include a command queue 2142-0, a write queue 2142-1, a read queue 2142-2, a transaction processing circuit 2142-3, an MC IF 2104, and an ECC circuit 2142-5. The command queue 2142-0, the write queue 2142-1, and the read queue 2142-2 are connectable to a controller IF, which is connectable to a controller (e.g., a host processor). The command queue 2142-0 can receive memory requests via the controller IF to access the memory device, or it can perform other operations (such as calibration or training). The write queue 2142-1 can receive write data to be written via the MC IF 2104. The read queue 2142-2 can provide read data received from the MC IF 2104.

[0122] The transaction processing circuit 2142-3 can encode requests into commands having predetermined bit values. In some embodiments, this may include encoding the command into a 12-bit command consisting of two 6-bit portions. In some embodiments, such commands may be compatible with the LPDDR4 standard (JESD209-4D). The transaction processing circuit can also format write data for output and read data received via the x4 LPDDR4 IF2104.

[0123] The MC IF2104 can generate commands and their equivalents as described herein. In some embodiments, the MC IF2104 can receive a 12-bit command and output this 12-bit command as four 3-bit values ​​on CA[2:0]. The data values ​​are receivable and transmittable in nibble units on DQ[3:0]. In addition to masking and inversion or their equivalents as described herein, the MC IF2104 can enable DMI signals on DMI IO to provide indications. This may include, but is not limited to, encoding ECC data with inverted data, indicating input or output states on DQ[3:0], or indicating upper or lower nibble of an 8-bit value on DQ[3:0].

[0124] Figure 22A is a schematic diagram of a CA output circuit 2244 for a host device according to one embodiment. The CA output circuit 2244 may include an output latch 2244-0 and an output MUX 2240-1. The output latch 2240-0 can latch a 12-bit command. The MUX 2240-1 can output such a 3-bit portion on CA[2:0]. In some embodiments, a 12-bit command value can be issued in four 3-bit portions on consecutive rising edges of a timing clock (e.g., CK).

[0125] Figure 22B is a schematic diagram showing an MC DMI circuit 2246 according to one embodiment. The MC DMI circuit 2246 can generate DMI output values ​​on DMI IO, which may include inverted data with ECC data in the same cycle of the timing clock. The MC DMI circuit 2246 may include storage 2246-1 for inverted or masked data and storage 2246-2 for storing ECC data 2246-2. Storage 2246-0 / 1 may be registers or latches, etc. MUX2246-3 can selectively output ECC data or DMI data including inverted and / or masked data. In some embodiments, such multiplexing may include providing masked / inverted data during one half of the timing clock and providing ECC data during the other half of the timing clock, as shown in Figure 5C as just one example.

[0126] Embodiments may include systems having a memory device operating with a host device, but embodiments may also include standalone devices having a reduced-pin-count interface and its equivalents as described herein. Such embodiments are shown in Figure 23. Figure 23 shows a packaged memory device 2303 in a perspective top view. The memory device 2302 can take the form of any of the memory devices or their equivalents described herein. In some embodiments, the memory device 2302 may include a single integrated circuit die. The memory device 2302 may include multiple physical connections (e.g., pins), one of which is shown as 2348. In some embodiments, the memory device 2302 can provide high-speed LVSTL signal transmission but have a relatively low pin count as described herein.

[0127] Referring to Figure 24, an automotive system 2430 according to one embodiment is illustrated. The automotive system 2430 may have a number of subsystems (two of which are shown as 2430-0 and 2430-1). Subsystems 2430-0 / 1 may operate with a host device (e.g., a CPU subsystem) that communicates with one or more memory devices. Such subsystems 2430-0 / 1 may include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, such subsystems may include a dashboard display / control subsystem and / or an infotainment subsystem, to name just two examples of many possible examples. Each subsystem 2430-0 / 1 may include a host device that can access the memory device via a reduced-size memory bus, such as the memory bus described herein. That is, the host device may have a low-pin interface, and the memory device may be a low-pin memory device. In some embodiments, the host device may be configured to execute code directly from an NVM memory device and benefit from high data transfer rates, such as one compatible with LPDDR4 signal transmission.

[0128] The described apparatus and systems disclose various methods according to the embodiments, but additional methods will be explained with reference to the flowcharts.

[0129] Figure 25 is a flowchart of a method 2550 of operation relating to a memory device according to one embodiment. Method 2550 can include receiving a 3-bit portion of a command 2550-0. In some embodiments, this can include latching multiple different command portions on the rising edge of the timing clock. The next command portion can be received 2550-2 while waiting for the last portion of the command to be received (N from 2550-1). Once the last command portion is received (Y from 2550-1), the received command can be processed 2550-4. In some embodiments, the command may be a 12-bit command, and receiving the last command portion can include receiving a fourth 3-bit portion.

[0130] If the command is a write command (WRITE from 2550-4), method 2550 may include receiving the write data as a sequence of 4-bit nibbles on a 4-bit data bus 2550-5. In some embodiments, the command portion may be receivable on the rising and falling edges of a timing clock signal, and the 4-bit value may be receivable synchronously with the rising and falling edges of the timing clock signal (i.e., DDR method). If the command is a read command (READ from 2550-4), method 2550 may output the read data as a sequence of 4-bit nibbles on a 4-bit data bus 2550-6. In some embodiments, such value may be output in DDR method. If the command is any other type of command, method 2550 may process that command 2550-7. In some embodiments, this may include processing calibration / training operations as described herein.

[0131] Figure 26 is a flowchart of method 2650 for providing ECC data with inverted data on DMI IO according to one embodiment. In some embodiments, method 2650 can be performed by a memory device. Method 2650 can include receiving commands 2650-0. Such action can include receiving commands or their equivalents according to embodiments of the invention, which include receiving multiple command portions on a reduced-size CA bus over three or more clock cycle transitions.

[0132] Method 2650 can determine whether DMI ECC is enabled 2650-1. Such actions may include, but are not limited to, causing a configuration register to be programmed to a predetermined value, having a specific device ID, or causing the received command to indicate that the DMI signal should have ECC functionality. If DMI ECC is not enabled (N from 2650-1), Method 2650 can execute a command 2650-2.

[0133] If DMI ECC is enabled (Y from 2650-1), method 2650 can determine whether the command is a read command or a write command (2650-3). If the command is a read command (READ from 2650-3), inverted data can be output on the DMI IO during one half of the data clock cycle (2650-4), and ECC data can be output during the other half of the data clock cycle (2650-5). In some embodiments, such inverted and ECC data may correspond to data being output on the data IO (e.g., DQ[3:0]). If the command is a write command (WRITE from 2650-3), inverted data can be received on the DMI IO during one half of the data clock cycle (2650-6), and ECC data can be received during the other half of the data clock cycle (2650-7). In some embodiments, such inverted and ECC data may correspond to data being received on the data IO.

[0134] Figure 27 is a flowchart of method 2750 for training the input or output of a memory device according to one embodiment. Method 2750 can include receiving a command 2750-0. Such action may include any of the actions described herein or their equivalents. Method 2750 can determine whether the received command indicates a training mode 2750-1. In some embodiments, such action may include decoding the command to determine whether the command indicates a training mode that anticipates the reception of one or more reference values. As just one of many possible actions, such action may determine whether the command is causing the memory device to enter a CA bus training mode or a DQ training mode. If the device has not entered a training mode (N from 2750-1), Method 2750 can execute the received command 2750-2.

[0135] If training mode has been entered (Y from 2750-1), method 2750 may include receiving a multi-bit reference value on both the CA bus and the DQ bus 2750-3. In some embodiments, such action may include receiving a first portion of the reference value on the CA bus and the remaining portion of the reference value on the DQ bus. According to some embodiments, different portions of the same reference value can be received simultaneously on the CA bus and the DQ bus. In some embodiments, the reference value may be a reference voltage used in the CA bus training operation.

[0136] Method 2750 may include configuring the device using a reference value 2750-4. In some embodiments, such action may include generating an analog value from bits of the reference value. In some embodiments, a reference voltage may be generated from bits of the reference value.

[0137] Method 2750 allows a training operation to be performed 2750-5. Such an action may include providing additional input to a memory device or requesting additional output from a memory device. In some embodiments, such an action may include applying a test pattern as input to the CA bus and then receiving a value such as one received by the memory device on the DQ IO bus. The training operation may continue 2750-6 until the training mode is terminated (N from 2750-6). In some embodiments, terminating the training mode may include receiving a predetermined command. However, in other embodiments, the training mode may be terminated after a predetermined period of time.

[0138] Figure 28 is a flowchart of Method 2850 for showing a portion of an output data value using a DMI signal according to an embodiment. Such a method can be performed by a memory device, a command issuing device (e.g., a memory controller), or a combination thereof. Method 2850 can include receiving a command 2850-0. Such an action can include any of the actions described herein or their equivalents. Method 2850 can determine whether the received command indicates a special DMI mode 2850-1. In some embodiments, such an action can include decoding the command. As just one of many possible actions, such an action can determine whether the command is causing the memory device to enter CA bus training mode. If it is not entering a special DMI mode (N from 2850-1), Method 2850 can perform the received command 2850-2.

[0139] If training mode has been entered (Y from 2850-1), method 2850 may include generating data 2850-3. Such action may include a memory device that generates data for output on the data bus, or a command issuing device that generates data for input to the memory device. A first portion of the data may be provided at a first level by DMI IO 2850-4, and a second portion of the data may be provided at a second level by DMI IO 2850-5. The DMI level may be established by the memory device, the command issuing device, or a combination thereof.

[0140] Figure 29 is a flowchart of method 2950 for indicating the state (i.e., input or output) of a bidirectional data bus using DMI signals according to an embodiment. Such a method can be performed by a memory device, a command issuing device, or a combination thereof. Method 2950 can include receiving a command 2950-0. Such an action can include any of the actions described herein or their equivalents. Method 2950 can determine whether the received command indicates a special DMI IO mode 2950-1. In some embodiments, such an action can include decoding the command. As just one of many possible actions, such an action can determine whether the command is causing the memory device to enter CA bus training mode. If it is not entering a special DMI IO mode (N from 2950-1), method 2950 can perform the received command 2950-2.

[0141] If a special DMI IO mode is entered (Y from 2950-1), method 2950 may include driving the DMI IO to a first level 2950-3 to indicate that the DQ should receive data. Such action may include driving a single DMI IO to a certain level to indicate that data should be received on the DQ[3:0] data bus. In some embodiments, such action may include a command issuing device that drives the DMI to a first level to indicate that a reference value exists on the DQ bus and / or the CA bus. Method 2950 may also include driving the DMI IO to a second level to indicate that the DQ is outputting data. In some embodiments, such action may include a memory device that drives the DMI to a second level to indicate that a test pattern value latched on the CA[3:0] input is available as output data on the DQ bus.

[0142] Figures 30A to 30C show a comparison of the performance of a memory device according to one embodiment with that of a conventional memory solution.

[0143] Figure 30A is a timing diagram showing a series of read operations for a conventional x8 LPDDR4 SDRAM. This operation can be considered as an "LPDDR x8" type operation. This operation is achievable at a clock speed of 800 MHz, and each read operation accesses 32 bytes of data. The read data is output at a double data rate, thus providing 2 bytes per clock cycle over 16 clocks. The SDRAM may have a tRCD value of 18 ns (i.e., 16 clocks) and an RL of 14 clocks. Figure 30A includes waveforms for CS, CA6 (i.e., a 6-bit command address bus), latency corresponding to the first read command (Lat1), latency corresponding to the second read command (Lat2), and DQ8 (i.e., an 8-bit DQ IO bus).

[0144] Continuing to refer to Figure 30A, each read command may include two activation commands (ACT1 / ACT2), followed by a read command and a CAS command (RD / CAS). The RD / CAS command is receivable after a delay of tRCD. The read data is output following RL after the CAS command. The read operation is timed to provide successive bursts of 16 clocks each, each providing 32 bytes of data.

[0145] Figure 30B is a timing diagram showing a series of read operations for a memory device according to one embodiment. This operation can be considered an "LPDDR x4" operation. The memory device may be DRAM, non-volatile memory (e.g., NOR flash), or a combination thereof. This operation may include timings such as those in Figure 30A, including a clock speed of 800 MHz, 16 clocks of tRCD, and 14 clocks of RL. However, the operation in Figure 30B includes a 3-bit reduced CA bus and a 4-bit reduced DQ bus. As a result, while each read operation accesses 32 bytes of data as shown in Figure 30A, the read operations provide 1 byte per clock cycle over 32 clocks. Figure 30B includes waveforms for CS, CA3 (i.e., the 3-bit command address bus), Lat1, Lat2, and DQ4 (i.e., the 4-bit DQ IO bus).

[0146] Continuing to refer to Figure 30B, the same command can be processed as in Figure 30A, but thanks to CA3, the command can be received over four cycles instead of two. The read operation is timed to provide successive bursts of 32 clocks each, each providing 32 bytes of data.

[0147] Figure 30C is a table comparing the performance of a conventional device with the performance of the LPDDR x4 embodiment shown in Figure 30B. Figure 30C includes parameters such as tCK (clock speed), number of pins, available bandwidth (estimated rate at which data can be transmitted), and signal transmission (type of I / O signal transmission used). This table includes parameters for the HBM x16 memory, LPDDR x8, and LPDDR x4 embodiments. As shown, the LPDDR x4 embodiment can provide high performance using a small number of pins (12).

[0148] Figure 31 shows how a high-performance memory device 3100 with reduced pin count according to an embodiment (e.g., LPDDR4 ×4 RAM) can function as a solution between conventional devices with a relatively large number of pins and / or relatively low performance.

[0149] Throughout this specification, any reference to “Embodiment” or “Embodiment” should be understood to mean that a particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment of the present invention. Therefore, it should be emphasized and understood that two or more references to “Embodiment” or “Embodiment” or “Alternative Embodiment” in different parts of this specification do not necessarily all refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be appropriately combined in one or more embodiments of the present invention.

[0150] Similarly, in the above-mentioned description of exemplary embodiments of the Invention, it should be understood that several different features of the Invention may be combined in a single embodiment, drawing, or description of the Invention for the purpose of simplifying the disclosure to aid in understanding one or more of the various different embodiments of the Invention. However, the present method of the Disclosure should not be interpreted as reflecting an intention that the claims require more features than those explicitly enumerated in each claim. Rather, the Invention is less than all the features of the single embodiment disclosed above. Accordingly, the claims following the Detailed Description are explicitly incorporated into this Detailed Description, and each claim stands independently as a separate embodiment of the Invention.

Claims

1. It is a method, The above method, in an integrated circuit device, The steps include receiving a sequence of three or more command value portions on a unidirectional command address (CA) bus having four or fewer parallel inputs, A step of latching each command value portion in synchronization with the rising edge of the timing clock, The steps include determining an input command from the sequence of three or more command value parts, The steps include: executing the input command in the integrated circuit device; The steps include outputting and inputting a sequence of data values ​​synchronized with the rising and falling edges of a data timing clock on a bidirectional data bus having six or fewer data inputs / outputs (I / O), A method that includes this.

2. The step of receiving the sequence of command value portions is: To form a 12-bit command, the process includes receiving a 3-bit command value portion in four consecutive cycles of the timing clock, The method according to claim 1.

3. The aforementioned method, In the operation of the first part of the training mode, the steps include driving the DMI signal on the data mask inversion (DMI) I / O to a predetermined value to indicate that the data bus is configured to receive input data, In the operation of the second part of the training mode, the steps include driving at least one data bus line to a predetermined value to indicate that other data bus lines are providing output data, Further including, The method according to claim 1.

4. The steps for outputting and inputting sequences of data values ​​are: The step includes receiving and transmitting data bytes as 4-bit nibbles on consecutive rising and falling edges of a data strobe clock synchronized with the timing clock, The method according to claim 1.

5. The aforementioned method, In at least the first mode of operation, in the data mask inversion (DMI) I / O, The steps include driving the DMI signal to a first value to indicate the lower nibble of the output byte, The steps include driving the DMI signal to a second value in order to indicate the upper nibble of the output byte, Further including, The method according to claim 1.

6. The aforementioned method, The process further includes receiving a test pattern value on the CA bus before driving the DMI IO, The output byte includes a test pattern captured by the integrated circuit device. The method according to claim 5.

7. The above method, in training mode, The steps include at least receiving a voltage reference value on the data I / O, After receiving the aforementioned voltage reference value, the step is to receive the input training value, Further including, The method according to claim 1.

8. The step of receiving the aforementioned voltage reference value is: The step of receiving a first portion of the voltage reference value on the data I / O, and subsequently receiving a second portion of the voltage reference value on the data I / O, The method according to claim 7.

9. The step of receiving the aforementioned voltage reference value is: The steps include receiving a first portion of the voltage reference value on the CA bus, The steps include receiving the second portion of the voltage reference value on the data bus simultaneously with the first portion, including, The method according to claim 7.

10. An integrated circuit (IC) device, The aforementioned integrated circuit (IC) device includes an interface, The aforementioned interface is A clock input configured to receive a periodic timing clock, A command address (CA) bus having four or fewer parallel inputs configured to receive sequences of three or more command value parts, At least one chip select (CS) configured to receive a chip select signal indicating the presence of valid CA data on the CA bus, A bidirectional datastrobe input / output (IO) configured to output and receive datastrobe signals derived by the timing clock, A bidirectional data bus having six or fewer parallel I / Os configured to receive and transmit data values ​​in synchronization with the rising and falling edges of the data strobe signal, A control circuit configured to execute commands received as three or more command value portions in a continuous cycle of the timing clock, A memory cell array configured to acquire and store data values ​​in response to commands received on the CA bus, An integrated circuit (IC) device that includes [a specific component].

11. The CA bus is configured to receive a 3-bit command value portion. The control circuit is configured to execute the command received as the command value portion in four consecutive cycles of the timing clock. The IC device according to claim 10.

12. The interface further includes data mask inversion (DMI) I / O, The IC device further includes a DMI control circuit, The aforementioned DMI control circuit is In the first part of the training mode, to indicate that the data bus is configured to receive input data, the DMI signal on the DMI IO is driven to a predetermined value, In the second part of the training mode, at least one data strobe I / O is driven to a predetermined value to indicate that other data strobe I / Os are providing output data. It is structured in such a way. The IC device according to claim 10.

13. The interface further includes data mask inversion (DMI) I / O, The data bus is configured to receive and transmit data bytes as 4-bit nibbles on consecutive rising and falling edges of a data strobe clock synchronized with the timing clock. The IC device further includes a DMI control circuit, The aforementioned DMI control circuit is To indicate the lower nibble of the output byte, the DMI signal on the DMI IO is driven to a first value, In order to indicate the upper nibble of the output byte, the DMI signal is driven up to a second value. It is structured in such a way. The IC device according to claim 10.

14. The IC device is A training circuit configured to receive a first portion of the reference value via the CA bus and a second portion of the reference value via the data bus, A voltage reference circuit configured to generate a reference voltage in response to the aforementioned reference value, Further including, The IC device according to claim 10.

15. The control circuit is further configured to receive a first portion of the reference value via the data strobe I / O, and subsequently receive a second portion of the reference value via the data strobe I / O. The IC device further includes a voltage reference circuit configured to generate a reference voltage in response to the reference value. The IC device according to claim 10.

16. The interface further includes data mask inversion (DMI) I / O, The IC device further includes a DMI control circuit, The aforementioned DMI control circuit is In the data mask writing operation, If the DMI signal on the DMI I / O has a first value, writing of the data value received on the data strobe I / O is prohibited. If the DMI signal has a second value, the writing of the data value received on the data strobe I / O is enabled. It is structured in such a way. The IC device according to claim 10.

17. The memory cell array includes non-volatile memory cells. The IC device according to claim 10.

18. It is a system, The system includes a first memory device, The first memory device includes a device interface, The aforementioned device interface is A clock input configured to receive a timing clock, A command address (CA) bus having four or fewer parallel inputs configured to receive a single command over three or more cycles of the timing clock, A bidirectional data bus having six or fewer parallel inputs / outputs (I / O) configured to receive and transmit data values ​​in synchronization with the rising and falling edges of a data strobe signal, Includes, The first memory device includes a memory cell array configured to acquire and store data values ​​in response to commands received on the CA bus. The system includes a system bus coupled to the clock input, the CA bus, and the data bus. system.

19. The first memory device is On the CA bus, the command is received as a sequence of 3-bit data values ​​over 4 cycles. On the aforementioned data bus, data is received and transmitted in a 4-bit nibble sequence. It is structured in such a way. The system according to claim 18.

20. The system further includes a host device, The aforementioned host device, It is connected to the aforementioned system bus, The system is configured to issue commands to at least the first memory device as a sequence of four 3-bit command value portions. The system according to claim 18.

21. In the operation of the host device in training mode, The first memory device issues test pattern data for reception on the CA bus, The test pattern data received by the first memory device is received from the first memory device, Adjust the timing for issuing data on the CA bus. It is structured in such a way. The system according to claim 20.

22. The memory cell array of the first memory device includes non-volatile memory cells. The second memory device coupled to the system bus includes a volatile memory cell array. The system according to claim 18.

23. The first memory device further includes a serial interface configured to transmit serial data over a serial data bus in synchronization with a serial clock, The host device is connected to the serial data bus. The system according to claim 20.

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