Complementary current-mode biquad with high linearity

Abstract

Some aspects of the disclosure provide methods and apparatus for processing signals using a current-mode biquad filter, which may have an adjustable bias current and / or an adjustable capacitance. One exemplary apparatus is a current-mode biquad filter circuit (402) including a first input current node (502), a first capacitive element (C1) coupled to the first input current node, a first output current node (506), a first active filter circuit (510) coupled between the first input current node and the first output current node, and a second active filter circuit (520) coupled between the first input current node and the first output current node. The second active filter circuit (520) is complementary to the first active filter circuit (510).

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims the interests and priority of U.S. Patent Application No. 17 / 136,723, filed December 29, 2020, as described below in its entirety and which is expressly incorporated herein by reference in its entirety for all applicable purposes.

[0002]

[0002] Some aspects of the present disclosure relate to electronic circuits in general, and more particularly to current-mode biquad filter circuits for processing signals. [Background technology]

[0003]

[0003] Wireless communication networks are widely deployed to provide a variety of communication services, including telephone, video, data, messaging, and broadcast. Typically being multiple access networks, such networks support communication for multiple users by sharing available network resources. For example, one network could be a 3G (third-generation mobile phone standard and technology) system that can provide network services via any one of various 3G radio access technologies (RATs), including EVDO (Evolution Data Optimized), 1xRTT (1x Radio Transmitting Technology, or simply 1x), W-CDMA (Wideband Code Division Multiple Access), UMTS-TDD (Universal Mobile Telecommunications System - Time Division Duplex), HSPA (High Speed ​​Packet Access), GPRS (General Purpose Packet Radio Service), or EDGE (Global Evolutionary High Speed ​​Data Rate). A 3G network is a wide-area cellular telephone network that has evolved to incorporate high-speed internet access and video calls in addition to voice calls. Furthermore, such multiple access networks may include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier FDMA (SC-FDMA) networks, 3G Partnership Project (3GPP®) Long-Term Evolution (LTE®) networks, and Long-Term Evolution Advanced (LTE-A) networks.

[0004]

[0004] A wireless communication network may include several base stations that can support communication for several mobile stations. A mobile station (MS) may communicate with a base station (BS) via downlink and uplink. Downlink (or forward link) refers to a communication link from a base station to a mobile station, and uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may transmit data and control information to a mobile station on the downlink and / or receive data and control information from a mobile station on the uplink.

[0005]

[0005] MS and / or BS may include, for example, a tunable active filter used as a baseband filter in the receive chain or transmit chain. The tunable active filter may be tuned to vary the center frequency (f0) of the filter over a range of frequencies. For high Q factor (Q) and high f0 filters, Q and f0 may vary due to process variations and component mismatches. [Overview of the project]

[0006]

[0006] Some aspects of the present disclosure provide current-mode biquad filter circuits. These current-mode biquad filter circuits generally include a first input current node, a first capacitive element coupled to the first input current node, a first output current node, a first active filter circuit coupled between the first input current node and the first output current node, a second active filter circuit coupled between the first input current node and the first output current node, wherein the second active filter circuit is complementary to the first active filter circuit.

[0007]

[0007] Some aspects of the present disclosure provide a radio frequency front-end including a current-mode biquad filter circuit as described herein. The radio frequency front-end may also include a low-noise amplifier having an input configured to receive a radio frequency signal. The radio frequency front-end may further include a mixer having an input coupled to the output of the low-noise amplifier and an output coupled to a first input current node of the current-mode biquad filter circuit.

[0008]

[0008] Some aspects of the present disclosure provide methods for signal processing. These methods generally involve receiving an input current signal at an input current node of a current-mode biquad filter circuit. The current-mode biquad filter circuit also includes a capacitive element coupled to an input current node, an output current node, a first active filter circuit coupled between the input current node and the output current node, and a second active filter circuit coupled between the input current node and the output current node, wherein the second active filter circuit is complementary to the first active filter circuit. The methods also include filtering the input current signal to generate an output current signal at the output current node using the current-mode biquad filter circuit.

[0009]

[0009] To enable a more detailed understanding of the features set forth above in this disclosure, a more specific description, briefly summarized above, may be obtained by referring to the manner in which a part thereof is shown in the accompanying drawings. However, it should be noted that since the description may lead to other equally effective manners, the accompanying drawings show only some exemplary manners of this disclosure and thus should not be regarded as limiting the scope of this disclosure.

Brief Description of the Drawings

[0010] [Figure 1]

[0010] Diagram of an exemplary wireless communication network according to some aspects of this disclosure. [Figure 2]

[0011] Block diagram of an exemplary access point (AP) and an exemplary user terminal according to some aspects of this disclosure. [Figure 3]

[0012] Block diagram of an exemplary transceiver front end according to some aspects of this disclosure. [Figure 4]

[0013] Block diagram of a baseband filter having a plurality of cascaded current-mode biquad filters according to some aspects of this disclosure. [Figure 5]

[0014] Schematic diagram of an exemplary current-mode biquad filter according to some aspects of this disclosure. [Figure 6]

[0015] Flow diagram of an exemplary operation for signal processing according to some aspects of this disclosure.

Modes for Carrying Out the Invention

[0011]

[0016] For ease of understanding, the same reference numbers are used, where possible, to designate the same elements common to each figure. It is contemplated that elements disclosed in one aspect may be beneficially utilized in other aspects without specific recitation.

[0012]

[0017] Some aspects of this disclosure generally relate to methods and apparatus for processing signals using a folded current-mode biquad filter. A biquad filter may have tunable transconductance (by adjusting the bias current) and / or tunable capacitance.

[0013]

[0018] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure can be implemented in many different forms and should not be construed as being limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure is thorough and complete and so as to convey the scope of this disclosure to those skilled in the art. Based on the teachings of this specification, those skilled in the art should understand that the scope of this disclosure covers any aspect of the disclosure disclosed herein, whether implemented independently of other aspects of the disclosure or in combination with other aspects of the disclosure. For example, an apparatus can be implemented or a method can be carried out using any number of the aspects described herein. Furthermore, the scope of this disclosure shall cover any such apparatus or method implemented using other structures, functions, or structures and functions in addition to or in addition to the various aspects of the disclosure described herein. It should be understood that any aspect of the disclosure disclosed herein can be carried out by one or more elements of the claims.

[0014]

[0019] The term “exemplary” is used herein to mean “acting as an example, case, or illustration.” No embodiment described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other embodiment.

[0015]

[0020] As used herein, the term “to be connected to” in various tenses of the verb “to connect” may mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term “to be connected to” may also be used herein to mean that a wire, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected between them).

[0016]

[0021] The techniques described herein can be used in combination with various wireless technologies such as Code Division Multiple Access (CDMA), Orthogonal Frequency Division Multiplexing (OFDM), Time Division Multiple Access (TDMA), Spatial Division Multiple Access (SDMA), Single Carrier Frequency Division Multiple Access (SC-FDMA), and Time Division Synchronous Code Division Multiple Access (TD-SCDMA). Multiple user terminals can concurrently transmit / receive data via different (1) orthogonal code channels for CDMA, (2) time slots for TDMA, or (3) subbands for OFDM. CDMA systems may implement IS-2000, IS-95, IS-856, Wideband CDMA (W-CDMA), or any other standard. OFDM systems may implement IEEE 802.11, IEEE 802.16, Long-Term Evolution (LTE) (e.g., in TDD and / or FDD modes), or any other standard. TDMA systems can implement the Global System for Mobile Communications (GSM®) or any other standard. These various standards are known in the art. Exemplary Wireless System

[0022] Figure 1 shows a wireless communication system 100 having an access point 110 and a user terminal 120, in which embodiments of the present disclosure may be implemented. For simplicity, only one access point 110 is shown in Figure 1. An access point (AP) is generally a fixed station that communicates with a user terminal and may also be called a base station (BS), an advanced node B (eNB), or any other term. A user terminal (UT) may be fixed or mobile and may also be called a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or any other term. A user terminal may be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet, or personal computer.

[0017]

[0023] The access point 110 can communicate with one or more user terminals 120 at a given moment over the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminal, and the uplink (i.e., reverse link) is the communication link from the user terminal to the access point. User terminals can also communicate with other user terminals peer-to-peer. The system controller 130 is coupled to the access point and performs coordination and control for the access point.

[0018]

[0024] System 100 employs multiple transmitting antennas and multiple receiving antennas for data transmission over downlink and uplink. Access point 110 uses N to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. ap It can be equipped with this many antennas. uA set of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal may transmit user-specific data to and / or receive user-specific data from the access point. Generally, each selected user terminal may be equipped with one or more antennas (i.e., N ut ≥1). N u Each selected user terminal may have the same or different number of antennas.

[0019]

[0025] The wireless system 100 may be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The system 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (for example, to reduce costs) or multiple antennas (for example, if additional costs can be supported).

[0020]

[0026] In some aspects of this disclosure, the access point 110 and / or user terminal 120 may include at least one current-mode biquad filter circuit for processing signals, as described below.

[0021]

[0027] Figure 2 shows a block diagram of the wireless system 100, including the access point 110 and two user terminals 120m and 120x. Access point 110 is N ap It is equipped with antennas 224a to 224ap. User terminal 120m is N ut,m Equipped with individual antennas 252mA~252μ, user terminal 120x is N ut,xIt is equipped with individual antennas 252xa to 252xu. The access point 110 is a transmission entity in the downlink and a reception entity in the uplink. Each user terminal 120 is a transmission entity in the uplink and a reception entity in the downlink. As used herein, a "transmission entity" is an independently operating device or apparatus capable of transmitting data via a frequency channel, and a "reception entity" is an independently operating device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates the downlink, the subscript "up" indicates the uplink, N up individual user terminals are selected for simultaneous transmission on the uplink, N dn individual user terminals are selected for simultaneous transmission on the downlink, N up is equal to or not equal to N dn and N up and N dn can be static values or may change for each scheduling interval. Beam steering or some other spatial processing technique can be used at the access point and the user terminals.

[0022]

[0028] On the uplink, in each user terminal 120 selected for uplink transmission, the TX data processor 288 receives traffic data from the data source 286 and control data from the controller 280. The TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data {d up} based on the coding and modulation scheme associated with the rate selected for the user terminal, and N ut,m a data symbol stream {s upThe transceiver front end (TX / RX) 254 (also known as the radio frequency front end (RFFE)) receives and processes each symbol stream (e.g., converts to analog, amplifies, filters, and frequency upconverts) to generate the uplink signal. The transceiver front end 254 also provides, for example, an RF switch for transmit diversity. ut,m The uplink signal can be routed to one of the antennas. The controller 280 can control the routing within the transceiver front end 254. The memory 282 can store data and program code for the user terminal 120 and interface with the controller 280.

[0023]

[0029] N up Each of these user terminals 120 can be scheduled for simultaneous transmission over the uplink. Each of these user terminals sends a set of the processed symbol streams to the access point over the uplink.

[0024]

[0030] At access point 110, N ap These antennas 224a to 224ap transmit all N on the uplink. up Uplink signals are received from individual user terminals. For receive diversity, the transceiver front end 222 may select signals received from one of the antennas 224 for processing. Signals received from multiple antennas 224 may be combined for extended receive diversity. The access point's transceiver front end 222 also performs processing that complements the processing performed by the user terminal's transceiver front end 254, providing a restored uplink data symbol stream. The restored uplink data symbol stream is the data symbol stream {s} transmitted by the user terminal. upThis is an estimate of}. The RX data processor 242 processes the stream (e.g., demodulate, deinterleave, and decode) according to the rate used for the recovered uplink data symbol stream in order to obtain the decoded data. The decoded data for each user terminal is provided to the data sink 244 for storage and / or to the controller 230 for further processing.

[0025]

[0031] The transceiver front end (TX / RX) 222 of access point 110 and / or the transceiver front end 254 of user terminal 120 may include one or more current-mode biquad filter circuits for processing signals, as described below.

[0026]

[0032] On the downlink, at access point 110, the TX data processor 210 is scheduled for downlink transmission. dn The TX data processor 210 receives traffic data for each user terminal from data source 208, control data from controller 230, and possibly other data from scheduler 234. Various types of data may be transmitted over different transport channels. The TX data processor 210 processes the traffic data for each user terminal based on the rate selected for that user terminal (e.g., encoding, interleaving, and modulation). The TX data processor 210 receives N ap N should be transmitted from one of these antennas. dn A downlink data symbol stream may be provided for one of more user terminals. The transceiver front end 222 receives and processes the symbol stream (e.g., converts to analog, amplifies, filters, and frequency upconverts) to generate the downlink signal. The transceiver front end 222 also provides, for example, an RF switch for transmit diversity. apDownlink signals can be routed to one or more of the antennas 224. The controller 230 can control the routing within the transceiver front end 222. Memory 232 can store data and program code for the access point 110 and interface with the controller 230.

[0027]

[0033] In each user terminal 120, N ut,m The antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 may select a signal received from one of the antennas 252 for processing. Signals received from multiple antennas 252 may be combined for extended receive diversity. The user terminal's transceiver front end 254 also performs processing that complements the processing performed by the access point's transceiver front end 222, providing a restored downlink data symbol stream. The RX data processor 270 processes the restored downlink data symbol stream (e.g., demodulates, deinterleaves, and decodes) to obtain decoded data for the user terminal.

[0028]

[0034] Those skilled in the art will recognize that the techniques described herein can generally be applied to systems utilizing any type of multiple access scheme, including TDMA, SDMA, orthogonal frequency division multiple access (OFDMA), CDMA, SC-FDMA, TD-SCDMA, and combinations thereof.

[0029]

[0035] Figure 3 is a block diagram of an exemplary transceiver front end 300, including transceiver front ends 222, 254 in Figure 2, in which embodiments of the present disclosure may be carried out. The transceiver front end 300 includes a transmit (TX) path 302 (also known as a transmit chain) for transmitting signals over one or more antennas, and a receive (RX) path 304 (also known as a receive chain) for receiving signals over antennas. When the TX path 302 and the RX path 304 share antenna 303, the paths may be connected to the antenna via an interface 306, which may include any of a variety of suitable RF devices such as a duplexer, switch, or diplexer.

[0030]

[0036] When receiving a common-phase (I) or quadrature-phase (Q) baseband analog signal from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, mixer 312, and DA 314 may be contained within a radio frequency integrated circuit (RFIC), while the PA 316 may be external to the RFIC. The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmitting local oscillator (LO) signal to convert the baseband signal to a different frequency (for example, upconverting from baseband to RF). This frequency conversion process generates sum and difference frequencies between the LO frequency and the frequency of the signal. These sum and difference frequencies are called beat frequencies. The beat frequency is generally within the RF range, and therefore the signal output by mixer 312 is generally an RF signal which can be amplified by DA314 and / or by PA316 before transmission by antenna 303.

[0031]

[0037] The RX path 304 includes a low-noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. In some aspects of this disclosure, the BBF 326 may include one or more current-mode biquad filter circuits for processing the signal, as described below. The LNA 322, the mixer 324, and the BBF 326 may be contained in the same or different radio frequency integrated circuit (RFIC) that includes the TX path components. An RF signal received via antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal to a different baseband frequency (i.e., down-convert it). The baseband signal output by mixer 324 may be filtered by BBF326 before being converted to a digital I or Q signal by analog-to-digital converter (ADC) 328 for digital signal processing.

[0032]

[0038] While it is desirable for the LO output to remain stable in frequency, adjusting it to different frequencies would require the use of a variable frequency oscillator, which may involve a compromise between stability and adjustability. Modern systems may employ a frequency synthesizer with a voltage-controlled oscillator (VCO) to generate a stable, adjustable LO with a specific adjustment range. Thus, the transmit LO frequency may be generated by the TX frequency synthesizer 318, and the transmit LO frequency may be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 330, and the receive LO frequency may be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324. Exemplary current-mode biquad filter circuit

[0039] Some wireless communication networks (for example, New Radio (NR), also known as 5G, the fifth generation of mobile phone standards and technologies) can support a variety of wireless communication services, such as Extended Mobile Broadband (eMBB) targeting wide bandwidths (e.g., 80 MHz or above) and millimeter wave (mmW) targeting higher carrier frequencies (e.g., 25 GHz or above). These services may support communications with lower latency and higher throughput than previous generations, such as 3G and 4G (the fourth generation of mobile phone standards and technologies). However, compared to previous generations, these 5G services may involve more stringent latency and bandwidth requirements. For reference, 5G mmW can utilize significantly larger bandwidths (e.g., 10x or more) than 4G.

[0033]

[0040] Current receiver (RX) architectures are generally insufficient to meet the bandwidth specifications associated with 5G communication services, such as 5G mmW. For example, some 4G RX architectures may use closed-loop feedback topologies, which can limit the bandwidth capability of the RX architecture (e.g., to less than 100 megahertz (MHz)). Furthermore, even in RX architectures employing open-loop architectures and / or passive components, resonant (e.g., LC) filters generally limit reconfigurability and tuning range to cover lower bandwidth modes. Therefore, it is sometimes desirable to provide an RX architecture that can meet higher bandwidth capabilities (e.g., greater than 100 MHz) and offers improved reconfigurability compared to conventional RX architectures.

[0034]

[0041] The embodiments presented herein describe an RX architecture having a baseband filter (e.g., BBF326) capable of supporting a higher bandwidth (e.g., up to 1 gigahertz (GHz)) for 5 G mmW. Figure 4 is a block diagram of an exemplary RX architecture 400 according to some embodiments of the present disclosure. The RX architecture 400 includes an LNA322, a mixer 324, and a BBF326. Here, the BBF326 can filter the baseband signal output by the mixer 324. There are many different circuit topologies for implementing filters in electronic circuits, such as a baseband filter (e.g., BBF326) in the receiving chain of a radio frequency front end. One exemplary filter topology using one or more amplifiers (e.g., an active topology) is called a biquadratic filter. A biquadratic filter is a type of linear filter for implementing a transfer function that is the ratio of two quadratic functions, hence the name "biquadratic".

[0035]

[0042] In one embodiment, the baseband filter of the RX architecture described herein may include at least one current-mode biquad filter circuit to support higher bandwidths, for example, 5 G mmW. As shown in Figure 4, for example, the BBF326 includes a current-mode biquad filter 402-1 and a current-mode biquad filter 402-2 cascaded with the current-mode biquad filter 402-1 to achieve an overall fourth-order filter. While Figure 4 shows the BBF326 with two cascaded current-mode biquad filters 402, it should be noted that in other embodiments, the BBF326 may include any number of current-mode biquad filters 402 (e.g., one, two, three, etc.).

[0036]

[0043] In one embodiment, the BBF326 may be an inductorless baseband circuit capable of supporting higher bandwidths (e.g., up to 1 GHz or more for 5 GHz mmW) than baseband filters in conventional RX architectures. The BBF326 has adjustable G over a larger bandwidth (e.g., via adjustable bias current). M and / or may have a tunable capacitor for complete reconfigurability. In some embodiments, the BBF326 may output a current signal to a current-mode ADC, while in other embodiments, a load resistor may be used to convert the output current signal to a voltage signal before it is received by an ADC (e.g., ADC328).

[0037]

[0044] Figure 5 is a schematic diagram of exemplary current-mode biquad filters 402 (e.g., current-mode biquad filter 402-1, current-mode biquad filter 402-2, etc.) according to several aspects of the present disclosure. The current-mode biquad filter 402 has an input current node 502 (e.g., I input+ ) and input current node 504 (for example, I input- ) and output current node 506 (for example, I output+ ) and output current node 508 (for example, I output- ) and active filter circuit 510, active filter circuit 520, active filter circuit 550, and active filter circuit 560. Input current nodes 502 and 504 are differential input current signal pairs (for example, I input+ / I input- ) can receive, and output current nodes 506 and 508 receive a differential output current signal pair (e.g., I) from the current-mode biquad filter 402. output+ / I output- It may output ).

[0038]

[0045] Active filter circuits 510 and 520 are complementary to each other. Each of the active filter circuits 510 and 520 is coupled between the input current node 502 and the output current node 506. Active filter circuit 510 includes a common-gate circuit 530 that drives a current mirror circuit 532. For example, transistor T1 of the common-gate circuit 530 drives the first branch (e.g., transistor T3) of the current mirror circuit 532, and the first branch of the current mirror circuit 532 controls the second branch (e.g., transistor T4) of the current mirror circuit 532.

[0039]

[0046] Similarly, the active filter circuit 520 includes a common gate circuit 540 that drives a current mirror circuit 542. For example, transistor T2 of the common gate circuit 540 drives a first branch of the current mirror circuit 542 (e.g., transistor T5), and the first branch of the current mirror circuit 542 controls a second branch of the current mirror circuit 542 (e.g., transistor T6). In the complementary active filter circuits 510 and 520, (i) the source of transistor T1 and the source of transistor T2 are coupled to the input current node 502, and (ii) the drain of transistor T4 and the drain of transistor T6 are coupled to the output current node 506.

[0040]

[0047] In some embodiments, the ratio (e.g., current Miller ratio 1:M) between the size of transistor T3 and the size of transistor T4 is tunable. In some embodiments, the ratio (e.g., current Miller ratio 1:M) between the size of transistor T5 and the size of transistor T6 is tunable. To implement tunable transistors, a switched array of parallel transistors may be used, where the gates of selected transistors are selectively coupled to a control input node, and the gates of unselected transistors are connected to a voltage rail (e.g., V) to turn off the unselected transistors. DD It is selectively coupled to (or to ground). In this way, the current Miller ratio of 1:M can be adjusted by changing the effective number of parallel transistors. In some embodiments, the ratio between the size of transistor T3 and the size of transistor T4 may be equal to the ratio between the size of transistor T5 and the size of transistor T6.

[0041]

[0048] As also shown, the active filter circuit 550 and the active filter circuit 560 are complementary to each other. Each of the active filter circuits 550 and 560 is coupled between the input current node 504 and the output current node 508. The active filter circuit 550 includes a common gate circuit 570 that drives the current mirror circuit 572. For example, transistor T7 of the common gate circuit 570 drives the first branch of the current mirror circuit 572 (e.g., transistor T9), and the first branch of the current mirror circuit 572 controls the second branch of the current mirror circuit 572 (e.g., transistor T10).

[0042]

[0049] Similarly, the active filter circuit 560 includes a common gate circuit 580 that drives a current mirror circuit 582. For example, transistor T8 of the common gate circuit 580 drives a first branch of the current mirror circuit 582 (e.g., transistor T11), and the first branch of the current mirror circuit 582 controls a second branch of the current mirror circuit 582 (e.g., transistor T12). In the complementary active filter circuits 550 and 560, (i) the source of transistor T7 and the source of transistor T8 are coupled to the input current node 504, and (ii) the drain of transistor T10 and the drain of transistor T12 are coupled to the output current node 508.

[0043]

[0050] In some embodiments, the ratio between the size of transistor T9 and the size of transistor T10 is adjustable. In some embodiments, the ratio between the size of transistor T11 and the size of transistor T12 is adjustable. In some embodiments, the ratio between the size of transistor T9 and the size of transistor T10 may be equal to the ratio between the size of transistor T11 and the size of transistor T12. In some embodiments, each of the current mirror circuits 532, 542, 572, and 582 may have the same ratio between the sizes of the transistors in their respective current mirror circuits, as shown in Figure 5 by ratio M.

[0044]

[0051] As shown in Figure 5, transistors T1 and T7 in common gate circuits 530 and 570 can be n-type field-effect transistors (NFETs), respectively. As shown in the figure, transistors T2 and T8 in common gate circuits 540 and 580 can be p-type field-effect transistors (PFETs), respectively. As shown in Figure 5, transistors T3, T4, T9, and T10 in current mirror circuits 532 and 572 can be PFETs, and transistors T5, T6, T11, and T12 in current mirror circuits 542 and 582 can be NFETs. In this way, active filter circuit 510 and active filter circuit 520 are complementary to each other. Similarly, active filter circuit 550 and active filter circuit 560 are complementary to each other.

[0045]

[0052] In some embodiments, the current-mode biquad filter 402 is (for example, G MOne or more tunable capacitors and / or tunable bias currents may be implemented to adjust the current. As shown in Figure 5, for example, the current-mode biquad filter 402 includes (i) a tunable capacitor C1 coupled between input current node 502 and input current node 504, (ii) a tunable capacitor C2 coupled between active filter circuit 510 and active filter circuit 550, and (iii) a tunable capacitor C3 coupled between active filter circuit 520 and active filter circuit 560. However, it should be noted that although Figure 5 shows three tunable capacitors C1, C2, and C3, the current-mode biquad filter 402 may include any number of tunable capacitors (for example, any combination of capacitors C1, C2, and C3 may be tunable). Furthermore, it should be understood that tunable capacitors (such as capacitors C1, C2, and / or C3) may be implemented by a switched array of capacitors (also called a “tunable capacitor bank”). In some embodiments, such a switched array of capacitors can be implemented, for example, by a binary-weighted capacitor bank.

[0046]

[0053] As also shown in Figure 5, the current-mode biquad filter 402 includes biasing nodes Vbp and Vbn configured to adjust the transconductance of one or more transistors in the current-mode biquad filter 402. For example, the positive biasing node Vbp may be configured to adjust the transconductance of transistors T1 and T7, where the gate of transistor T1 is coupled to capacitor C7 and to biasing node Vbp via resistor R1, and the gate of transistor T7 is coupled to capacitor C5 and to biasing node Vbp via resistor R2. In some embodiments, at least one of resistors R1, R2, capacitor C5, and capacitor C7 is variable.

[0047]

[0054] Similarly, the negative bias node Vbn may be configured to adjust the transconductance transistors T2 and T8, where the gate of transistor T2 is coupled to capacitor C6 and to the bias node Vbn via resistor R3, and the gate of transistor T8 is coupled to capacitor C4 and to the bias node Vbn via resistor R4. In some embodiments, at least one of resistors R3, R4, capacitor C4, and capacitor C6 is variable.

[0048]

[0055] In some embodiments, the current mirror circuit of each active filter circuit may be coupled to a common-mode gate circuit in a different active filter circuit. For example, the first branch of the current mirror circuit 532 includes a transistor T3, and the transistor T3 is V DD It has a source coupled to (e.g., a voltage rail), and a drain coupled to (i) the gate of transistor T3, (ii) the output of common gate circuit 530, and (iii) the gate of transistor T8 via capacitor C4 (e.g., Vpm+). Furthermore, the first branch of the current mirror circuit 542 includes transistor T5, which has a source coupled to (i) the gate of transistor T3, (ii) the output of common gate circuit 530, and (iii) the gate of transistor T8 via capacitor C4. SS It has a source coupled to (for example, an electrical ground for the circuit, a voltage rail), and a drain coupled to (i) the gate of transistor T5, (ii) the output of common gate circuit 540, and (iii) the gate of transistor T7 via capacitor C5 (e.g., Vnm+). Furthermore, the first branch of the current mirror circuit 572 includes transistor T9, and transistor T9 is V DD It has a source coupled to (i) the gate of transistor T9, and a drain coupled to (ii) the output of the common gate circuit 570, and (iii) the gate of transistor T2 via capacitor C6 (e.g., Vpm-). Furthermore, the first branch of the current mirror circuit 582 includes transistor T11, and transistor T11 has a source coupled to (i) the gate of transistor T9, and (ii) the output of the common gate circuit 570, and (iii) the gate of transistor T2 via capacitor C6. SSThe source is coupled to (i) the gate of transistor T11, (ii) the output of the common gate circuit 580, and (iii) the gate of transistor T1 via capacitor C7, and the drain is coupled to (i) the gate of transistor T11 (e.g., Vnm-). In this way, the gates of the transistors are cross-coupled.

[0049]

[0056] Figure 6 is a flowchart of an exemplary operation 600 for processing a signal, according to some aspects of the present disclosure. Operation 600 may be carried out by a circuit such as a current-mode biquad filter 402.

[0050]

[0057] Operation 600 begins in block 602 by receiving an input current signal at the input current node (e.g., input current node 502) of a current-mode biquad filter circuit (e.g., current-mode biquad filter 402-1). The current-mode biquad filter circuit may include (i) a capacitive element (e.g., capacitor C1) coupled to the input current node, (ii) an output current node (e.g., output current node 506), (iii) a first active filter circuit (e.g., active filter circuit 510) coupled between the input current node and the output current node, and (iv) a second active filter circuit (e.g., active filter circuit 520) coupled between the input current node and the output current node. The second active filter circuit may be complementary to the first active filter circuit.

[0051]

[0058] In block 604, the circuit filters the input current signal using a current-mode biquad filter circuit to generate an output current signal at the output current node.

[0052]

[0059] In some embodiments, a circuit (e.g., current-mode biquad filter circuit 420-1) may be cascaded with another circuit (e.g., current-mode biquad filter circuit 420-2). In some embodiments, the circuit may be contained within a radio frequency front end. In these embodiments, the radio frequency front end may also include an LNA (e.g., LNA322) having an input configured to receive radio frequency signals, and a mixer (e.g., mixer324) having an input coupled to the output of the LNA and an output coupled to the input current node of the circuit.

[0053]

[0060] The various operations of the methods described above may be carried out by any suitable means capable of performing the corresponding functions. These means may include, but are not limited to, a variety of (one or more) hardware and / or software components and / or modules, including circuits, application-specific integrated circuits (ASICs), or processors. Generally, where there are operations shown in the figures, those operations may have corresponding means-plus-function components of similar numbering.

[0054]

[0061] For example, the means for transmission may include a transmitter (e.g., the transceiver front end 254 of the user terminal 120 shown in Figure 2, the transceiver front end 222 of the access point 110 shown in Figure 2, or the transceiver front end 300 shown in Figure 3) and / or antennas (e.g., antennas 252ma~252mu of the user terminal 120m shown in Figure 2, antennas 224a~224ap of the access point 110 shown in Figure 2, or antenna 303 of the transceiver front end 300 shown in Figure 3). Means for receiving may include a receiver (for example, the transceiver front end 254 of the user terminal 120 shown in Figure 2, the transceiver front end 222 of the access point 110 shown in Figure 2, or the transceiver front end 300 shown in Figure 3) and / or antennas (for example, antennas 252ma to 252mu of the user terminal 120m shown in Figure 2, antennas 224a to 224ap of the access point 110 shown in Figure 2, or antenna 303 of the transceiver front end 300 shown in Figure 3). Means for processing, determining, and operating may include a processing system that includes one or more processors (for example, the TX data processor 210, RX data processor 242, and / or controller 230 of the access point 110 shown in Figure 2, or the RX data processor 270, TX data processor 288, and / or controller 280 of the user terminal 120 shown in Figure 2).

[0055]

[0062] As used herein, the term “deciding” encompasses a wide variety of actions. For example, “deciding” may include calculating, calculating, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or other data structure), and confirming. It may also include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and resolving, selecting, choosing, and establishing.

[0056]

[0063] As used herein, the phrase “at least one of” the list of items refers to any combination of those items that contains a single member. For example, “at least one of a, b, or c” shall include a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical elements (for example, aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0057]

[0064] Various exemplary logic blocks, modules, and circuits described in connection with this disclosure may be implemented or carried out using general-purpose processors, digital signal processors (DSPs), ASICs, field-programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration.

[0058]

[0065] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The steps and / or actions of the method may be interchangeable with one another without departing from the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of any particular steps and / or actions may be modified without departing from the claims.

[0059]

[0066] The described functions can be implemented in hardware, software, firmware, or any combination thereof. When implemented in hardware, an exemplary hardware configuration may include a processing system within a wireless node. The processing system may be implemented using a bus architecture. The bus may include any number of interconnecting buses and bridges, depending on the specific application of the processing system and the overall design constraints. The bus can link various circuits to each other, including processors, machine-readable media, and bus interfaces. Bus interfaces may be used to connect network adapters, in particular, to the processing system via the bus. Network adapters may be used to implement signal processing functions at the physical (PHY) layer. In the case of user terminals, user interfaces (e.g., keypads, displays, mice, joysticks, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, but these circuits are well known in the art and therefore will not be described further.

[0060]

[0067] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functions, all linked to each other with other support circuits via an external bus architecture, and external memory providing at least a portion of machine-readable media. Alternatively, the processing system may be implemented using an ASIC with a processor, a bus interface, a user interface (in the case of an access terminal), support circuits, and at least a portion of machine-readable media integrated on a single chip, or using one or more FPGAs, PLDs, controllers, state machines, gate logic, individual hardware components, or other suitable circuits, or any combination of circuits capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how the functions described should be best implemented for the processing system, depending on the specific application and the overall design constraints imposed on the overall system.

[0061]

[0068] It should be understood that the claims are not limited to the exact configuration and components set forth above. Various modifications, changes, and variations may be made to the configuration, operation, and details of the methods and apparatus described above without departing from the claims. The invention described in the original claims of this application is listed below. [C1] The first input current node and A first capacitive element coupled to the first input current node, The first output current node, A first active filter circuit coupled between the first input current node and the first output current node, A second active filter circuit coupled between the first input current node and the first output current node, wherein the second active filter circuit is complementary to the first active filter circuit. A current-mode biquad filter circuit equipped with [a specific feature]. [C2] The current-mode biquad filter circuit according to C1, wherein at least one of the first active filter circuit or the second active filter circuit has an adjustable transconductance. [C3] The current-mode biquad filter circuit described in C2, wherein the first capacitive element comprises an adjustable capacitor. [C4] The first active filter circuit, A first common gate circuit having an input coupled to the first input current node, A first current mirror circuit having a first branch coupled to the output of the first common gate circuit and a second branch coupled to the first output current node, Equipped with, The second active filter circuit is, A second common gate circuit having an input coupled to the first input current node, A second current mirror circuit having a first branch coupled to the output of the second common gate circuit and a second branch coupled to the first output current node, A current-mode biquad filter circuit as described in C1, comprising the above. [C5] The system further comprises a first bias node and a second bias node, and herein, The first common gate circuit comprises a first transistor, the first transistor having a source coupled to the first input current node, a drain coupled to the first branch of the first current mirror circuit, and a gate coupled to the first bias node. The second common gate circuit comprises a second transistor, the second transistor having a source coupled to the first input current node, a drain coupled to the first branch of the second current mirror circuit, and a gate coupled to the second bias node. Current-mode biquad filter circuit as described in C4. [C6] The current-mode biquad filter circuit according to C5, wherein the first bias node is configured to adjust the transconductance of the first transistor, and the second bias node is configured to adjust the transconductance of the second transistor. [C7] The first branch of the first current mirror circuit comprises a third transistor, the third transistor having a source coupled to a first voltage rail, and a drain coupled to the gate of the third transistor and the output of the first common gate circuit. The second branch of the first current mirror circuit comprises a fourth transistor, the fourth transistor having a source coupled to the first voltage rail, a drain coupled to the first output current node, and a gate coupled to the gate of the third transistor. The first branch of the second current mirror circuit comprises a fifth transistor, the fifth transistor having a source coupled to a second voltage rail, and a drain coupled to the gate of the fifth transistor and the output of the second common gate circuit. The second branch of the second current mirror circuit comprises a sixth transistor, the sixth transistor having a source coupled to the second voltage rail, a drain coupled to the first output current node, and a gate coupled to the gate of the fifth transistor. Current-mode biquad filter circuit as described in C5. [C8] The ratio between the size of the third transistor and the size of the fourth transistor is equal to the ratio between the size of the fifth transistor and the size of the sixth transistor, and the ratio between the size of the third transistor and the size of the fourth transistor is adjustable. Current-mode biquad filter circuit as described in C7. [C9] A second input current node, wherein the first capacitive element is coupled between the first input current node and the second input current node. The second output current node, A third active filter circuit coupled between the second input current node and the second output current node, A fourth active filter circuit coupled between the second input current node and the second output current node, wherein the fourth active filter circuit is complementary to the third active filter circuit. The current-mode biquad filter circuit described in C5 further includes the following: [C10] A second capacitive element coupled between the first active filter circuit and the third active filter circuit, A third capacitive element coupled between the second active filter circuit and the fourth active filter circuit and The current-mode biquad filter circuit described in C9 further includes the following: [C11] The current-mode biquad filter circuit according to C10, wherein at least one of the first capacitive element, the second capacitive element, or the third capacitive element comprises an adjustable capacitor. [C12] The third active filter circuit is A third common gate circuit having an input coupled to the second input current node, A third current mirror circuit having a first branch coupled to the output of the third common gate circuit and a second branch coupled to the second output current node, Equipped with, The fourth active filter circuit is, A fourth common gate circuit having an input coupled to the second input current node, A fourth current mirror circuit having a first branch coupled to the output of the fourth common gate circuit and a second branch coupled to the second output current node, A current-mode biquad filter circuit as described in C10, comprising the above. [C13] The second capacitive element is coupled between the output of the first common gate circuit and the output of the third common gate circuit. The third capacitive element is coupled between the output of the second common gate circuit and the output of the fourth common gate circuit. Current-mode biquad filter circuit as described in C12. [C14] The third common gate circuit comprises a third transistor, the third transistor having a source coupled to the second input current node, a drain coupled to the first branch of the third current mirror circuit, and a gate coupled to the first bias node. The fourth common gate circuit comprises a fourth transistor, the fourth transistor having a source coupled to the second input current node, a drain coupled to the first branch of the fourth current mirror circuit, and a gate coupled to the second bias node. Current-mode biquad filter circuit as described in C12. [C15] The first bias node is configured to adjust the transconductance of at least one of the first transistor or the third transistor, The second bias node is configured to adjust the transconductance of at least one of the second or fourth transistors. Current-mode biquad filter circuit as described in C14. [C16] The first branch of the first current mirror circuit comprises a fifth transistor, the fifth transistor having a source coupled to a first voltage rail, and a drain coupled to the gate of the fifth transistor, the output of the first common gate circuit, and the gate of the fourth transistor of the fourth common gate circuit. The first branch of the second current mirror circuit comprises a sixth transistor, the sixth transistor having a source coupled to a second voltage rail, and a drain coupled to the gate of the sixth transistor and the output of the second common gate circuit and the gate of the third transistor of the third common gate circuit. The first branch of the third current mirror circuit comprises a seventh transistor, the seventh transistor having a source coupled to the first voltage rail, and a drain coupled to the gate of the seventh transistor and the output of the third common gate circuit and the gate of the second transistor of the second common gate circuit. The first branch of the fourth current mirror circuit comprises an eighth transistor, the eighth transistor having a source coupled to the second voltage rail, and a drain coupled to the gate of the eighth transistor, the output of the fourth common gate circuit, and the gate of the first transistor of the first common gate circuit. Current-mode biquad filter circuit as described in C14. [C17] The second branch of the third current mirror circuit comprises a ninth transistor, the ninth transistor having a source coupled to the first voltage rail, a drain coupled to the second output current node, and a gate coupled to the gate of the seventh transistor. The second branch of the fourth current mirror circuit comprises a tenth transistor, the tenth transistor having a source coupled to the second voltage rail, a drain coupled to the second output current node, and a gate coupled to the gate of the eighth transistor. Current-mode biquad filter circuit as described in C16. [C18] A fourth capacitive element coupled between the gate of the fifth transistor and the gate of the fourth transistor of the fourth common gate circuit, A fifth capacitive element coupled between the sixth transistor and the gate of the third transistor of the third common gate circuit, A sixth capacitive element coupled between the seventh transistor and the gate of the second transistor of the second common gate circuit, A seventh capacitive element coupled between the eighth transistor and the gate of the first transistor of the first common gate circuit and The current-mode biquad filter circuit described in C16 further includes the following: [C19] A radio frequency front end comprising the current-mode biquad filter circuit described in C1, A low-noise amplifier having an input configured to receive radio frequency signals, A mixer having an input coupled to the output of the low-noise amplifier and an output coupled to the first input current node of the current-mode biquad filter circuit. A radio frequency front-end that further enhances this feature. [C20] A method for signal processing, wherein the method is The input current signal is received at the input current node of the current-mode biquad filter circuit, and the current-mode biquad filter circuit is configured to receive the input current signal at the input current node of the current-mode biquad filter circuit. A capacitive element coupled to the input current node, Output current node, A first active filter circuit coupled between the input current node and the output current node, A second active filter circuit coupled between the input current node and the output current node, wherein the second active filter circuit is complementary to the first active filter circuit. Furthermore, The input current signal is filtered using the current-mode biquad filter circuit in order to generate an output current signal at the output current node. A method that includes [a certain feature]. [C21] The radio frequency front-end described in C19 further comprises another current-mode biquad filter circuit cascaded with the aforementioned current-mode biquad filter circuit. [C22] The radio frequency front-end according to C19, further comprising an analog-to-digital converter (ADC), wherein the current-mode biquad filter circuit is included in a baseband filter (BBF), and the BBF is coupled to the ADC. [C23] The radio frequency front end according to C22, further comprising another current-mode biquad filter circuit cascaded with the aforementioned current-mode biquad filter circuit and included in the BBF. [C24] The radio frequency front end according to C22, wherein the ADC comprises a current-mode ADC, and the BBF is configured to output a current signal to the current-mode ADC. [C25] The radio frequency front end according to C22 further comprises a load resistor configured to convert a current signal output from the BBF into a voltage signal, wherein the ADC is configured to receive the voltage signal. [C26] The current-mode biquad filter circuit according to C1, further comprising a resistor coupled to the first output current node, wherein the resistor is configured to convert a current signal to a voltage signal.

Claims

1. The first input current node and A first capacitive element (C1) directly coupled to the first input current node, The first output current node and A first active filter circuit directly coupled between the first input current node and the first output current node, A second active filter circuit is directly coupled between the first input current node and the first output current node, and the second active filter circuit is complementary to the first active filter circuit in its circuit configuration. A current-mode biquad filter circuit comprising, wherein, The first active filter circuit, A first common gate circuit having an input coupled to the first input current node, A first current mirror circuit having a first branch coupled to the output of the first common gate circuit and a second branch coupled to the first output current node, Equipped with, The second active filter circuit described above, A second common gate circuit having an input coupled to the first input current node, The system comprises a second current mirror circuit having a first branch coupled to the output of the second common gate circuit and a second branch coupled to the first output current node, The current-mode biquad filter circuit further comprises a first bias node (Vbp) and a second bias node (Vbn), wherein, The first common gate circuit comprises a first transistor (T1), the first transistor having a source coupled to the first input current node, a drain coupled to the first branch of the first current mirror circuit, and a gate coupled to the first bias node. The second common gate circuit comprises a second transistor (T2), the second transistor having a source coupled to the first input current node, a drain coupled to the first branch of the second current mirror circuit, and a gate coupled to the second bias node. Current-mode biquad filter circuit.

2. The current-mode biquad filter circuit according to claim 1, wherein at least one of the first active filter circuit or the second active filter circuit comprises an adjustable transconductance, and the first capacitive element comprises an adjustable capacitor.

3. The current-mode biquad filter circuit according to claim 1, wherein the first bias node is configured to adjust the transconductance of the first transistor, and the second bias node is configured to adjust the transconductance of the second transistor.

4. The first branch of the first current mirror circuit comprises a third transistor (T3), the third transistor having a source coupled to a first voltage rail, and a drain coupled to the gate of the third transistor and the output of the first common gate circuit. The second branch of the first current mirror circuit comprises a fourth transistor (T4), the fourth transistor having a source coupled to the first voltage rail, a drain coupled to the first output current node, and a gate coupled to the gate of the third transistor, The first branch of the second current mirror circuit comprises a fifth transistor (T5), the fifth transistor having a source coupled to the second voltage rail, and a drain coupled to the gate of the fifth transistor and the output of the second common gate circuit. The second branch of the second current mirror circuit comprises a sixth transistor (T6), the sixth transistor having a source coupled to the second voltage rail, a drain coupled to the first output current node, and a gate coupled to the gate of the fifth transistor, The ratio between the size of the third transistor and the size of the fourth transistor is equal to the ratio between the size of the fifth transistor and the size of the sixth transistor. The ratio between the size of the third transistor and the size of the fourth transistor is adjustable. The current-mode biquad filter circuit according to claim 1.

5. A second input current node, wherein the first capacitive element is coupled between the first input current node and the second input current node. The second output current node, A third active filter circuit coupled between the second input current node and the second output current node, A fourth active filter circuit is coupled between the second input current node and the second output current node, and the fourth active filter circuit is complementary to the third active filter circuit. A second capacitive element (C2) is coupled between the first active filter circuit and the third active filter circuit, A third capacitive element (C3) coupled between the second active filter circuit and the fourth active filter circuit, The current-mode biquad filter circuit according to claim 1, further comprising the above.

6. The current-mode biquad filter circuit according to claim 5, wherein at least one of the first capacitive element, the second capacitive element, or the third capacitive element comprises an adjustable capacitor.

7. The third active filter circuit is A third common gate circuit having an input coupled to the second input current node, A third current mirror circuit having a first branch coupled to the output of the third common gate circuit and a second branch coupled to the second output current node, Equipped with, The fourth active filter circuit is A fourth common gate circuit having an input coupled to the second input current node, A fourth current mirror circuit having a first branch coupled to the output of the fourth common gate circuit and a second branch coupled to the second output current node, Equipped with, The second capacitive element is coupled between the output of the first common gate circuit and the output of the third common gate circuit. The third capacitive element is coupled between the output of the second common gate circuit and the output of the fourth common gate circuit. The current-mode biquad filter circuit according to claim 5.

8. The third common gate circuit comprises a third transistor (T7), the third transistor having a source coupled to the second input current node, a drain coupled to the first branch of the third current mirror circuit, and a gate coupled to the first bias node. The fourth common gate circuit comprises a fourth transistor (T8), the fourth transistor having a source coupled to the second input current node, a drain coupled to the first branch of the fourth current mirror circuit, and a gate coupled to the second bias node. The first bias node is configured to adjust the transconductance of at least one of the first transistor or the third transistor. The second bias node is configured to adjust the transconductance of at least one of the second transistor or the fourth transistor, The first branch of the first current mirror circuit comprises a fifth transistor (T3), the fifth transistor having a source coupled to a first voltage rail, and a drain coupled to the gate of the fifth transistor, the output of the first common gate circuit, and the gate of the fourth transistor of the fourth common gate circuit. The first branch of the second current mirror circuit comprises a sixth transistor (T5), the sixth transistor having a source coupled to the second voltage rail, and a drain coupled to the gate of the sixth transistor, the output of the second common gate circuit, and the gate of the third transistor of the third common gate circuit. The first branch of the third current mirror circuit comprises a seventh transistor (T9), the seventh transistor having a source coupled to the first voltage rail, and a drain coupled to the gate of the seventh transistor, the output of the third common gate circuit, and the gate of the second transistor of the second common gate circuit. The first branch of the fourth current mirror circuit comprises an eighth transistor (T11), the eighth transistor having a source coupled to the second voltage rail, and a drain coupled to the gate of the eighth transistor, the output of the fourth common gate circuit, and the gate of the first transistor of the first common gate circuit. The second branch of the third current mirror circuit comprises a ninth transistor (T10), the ninth transistor having a source coupled to the first voltage rail, a drain coupled to the second output current node, and a gate coupled to the gate of the seventh transistor. The second branch of the fourth current mirror circuit comprises a tenth transistor (T12), the tenth transistor having a source coupled to the second voltage rail, a drain coupled to the second output current node, and a gate coupled to the gate of the eighth transistor. The current-mode biquad filter circuit is, A fourth capacitive element (C4) coupled between the gate of the fifth transistor and the gate of the fourth transistor of the fourth common gate circuit, A fifth capacitive element (C5) is coupled between the sixth transistor and the gate of the third transistor of the third common gate circuit, A sixth capacitive element (C6) coupled between the seventh transistor and the gate of the second transistor of the second common gate circuit, A seventh capacitive element (C7) coupled between the eighth transistor and the gate of the first transistor of the first common gate circuit and The current-mode biquad filter circuit according to claim 7, further comprising the above.

9. A radio frequency front end comprising the current-mode biquad filter circuit described in claim 1, A low-noise amplifier having an input configured to receive radio frequency signals, A mixer having an input coupled to the output of the low-noise amplifier and an output coupled to the first input current node of the current-mode biquad filter circuit. A radio frequency front-end that further enhances this feature.

10. A method for signal processing, wherein the method is The current-mode biquad filter circuit receives an input current signal at the first and second input current nodes, and the current-mode biquad filter circuit, Capacitive elements directly coupled to the first and second input current nodes, First and second output current nodes, A first active filter circuit directly coupled between the first input current node and the first output current node, A second active filter circuit is directly coupled between the second input current node and the second output current node, and the second active filter circuit is complementary to the first active filter circuit in its circuit configuration. Furthermore, The input current signal is filtered using the current-mode biquad filter circuit to generate output current signals at the first and second output current nodes. Equipped with, The first active filter circuit, A first common gate circuit having an input coupled to the first input current node, A first current mirror circuit having a first branch coupled to the output of the first common gate circuit and a second branch coupled to the first output current node, Equipped with, The second active filter circuit described above, A second common gate circuit having an input coupled to the first input current node, A second current mirror circuit having a first branch coupled to the output of the second common gate circuit and a second branch coupled to the first output current node, Equipped with, The current-mode biquad filter circuit further comprises a first bias node (Vbp) and a second bias node (Vbn), wherein, The first common gate circuit comprises a first transistor (T1), the first transistor having a source coupled to the first input current node, a drain coupled to the first branch of the first current mirror circuit, and a gate coupled to the first bias node. The second common gate circuit comprises a second transistor (T2), the second transistor having a source coupled to the first input current node, a drain coupled to the first branch of the second current mirror circuit, and a gate coupled to the second bias node. method.

11. The radio frequency front-end according to claim 9, further comprising another current-mode biquad filter circuit cascaded with the aforementioned current-mode biquad filter circuit.

12. The present invention further comprises an analog-to-digital converter (ADC), wherein the current-mode biquad filter circuit is included in a baseband filter (BBF), the BBF is coupled to the ADC, and the radio frequency front end is cascaded with the current-mode biquad filter circuit and further comprises another current-mode biquad filter circuit included in the BBF. The ADC comprises a current-mode ADC, and the BBF is configured to output a current signal to the current-mode ADC, or The radio frequency front end according to claim 9, further comprising a load resistor configured to convert a current signal output from the BBF into a voltage signal, wherein the ADC is configured to receive the voltage signal.

13. The current-mode biquad filter circuit according to claim 1, further comprising a resistor coupled to the first output current node, wherein the resistor is configured to convert a current signal to a voltage signal.

Images