Semiconductor memory

Abstract

To reduce the circuit area of a semiconductor storage device.SOLUTION: A semiconductor storage device of an embodiment includes a first memory cell transistor, a first bit line, a first sense amplifier, and a first latch circuit. The first memory cell transistor and the first sense amplifier are connected to the first bit line. The first latch circuit is connected to the first sense amplifier. The first sense amplifier has a first node, a first transistor, a second node, and a second transistor. The first node is connected to the first bit line. The first transistor has one end electrically connected to the first latch circuit. The second node is connected to the gate of the first transistor. The second transistor is connected between the first node and the second node. In operation of transferring electric charges from the first bit line to the first node and the second node according to data of the first memory cell transistor, the second transistor is in an ON state. In operation of transferring the data at the second node to the first latch circuit, the second transistor is in an OFF state.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The embodiment relates to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Reduce the circuit area of the semiconductor memory device.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment includes a first memory cell transistor, a first bit line, a first sense amplifier, and a first latch circuit. The first bit line is electrically connected to the first memory cell transistor. The first sense amplifier is electrically connected to the first bit line. The first latch circuit is electrically connected to the first sense amplifier. The first sense amplifier has a first node, a first transistor, and a second node , the 2 transistors , first conductor, and second conductor and a second transistor. The first node is connected to the first bit line. The first transistor has one end electrically connected to the first latch circuit. The second node is connected to the gate of the first transistor. The second transistor is connected between the first node and the second node. The first conductor is It functions as the first node. The second conductor is connected to the first latch circuit and is adjacent to the first conductor, functioning as the first wiring.In the operation of transferring charge from the first bit line to the first and second nodes according to the data of the first memory cell transistor, the second transistor is in the ON state. In the operation of transferring data from the second node to the first latch circuit, the second transistor is in the OFF state. The second conductor has a first wiring capacitance between it and the first conductor. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows a block diagram of an example configuration of the semiconductor memory device 1 according to the first embodiment. [Figure 2] Figure 2 shows an example of the circuit configuration of the memory cell array provided in the semiconductor memory device 1 according to the first embodiment. [Figure 3] Figure 3 shows a block diagram illustrating an example of the configuration of the sense amplifier included in the semiconductor memory device 1 according to the first embodiment. [Figure 4] Figure 4 shows an example of the layout of the sense amplifier included in the semiconductor memory device 1 according to the first embodiment. [Figure 5] Figure 5 shows an example of the circuit configuration of the sense amplifier unit SAU included in the semiconductor memory device 1 according to the first embodiment. [Figure 6] Figure 6 shows an example of the planar structure of a transistor in the semiconductor memory device 1 according to the first embodiment. [Figure 7] Figure 7 shows an example of the cross-sectional structure of the circuit region of the semiconductor memory device 1 according to the first embodiment, along the line VI-VI in Figure 6. [Figure 8] Figure 8 shows an example of the cross-sectional structure of the circuit region of the semiconductor memory device 1 according to the first embodiment. [Figure 9] Figure 9 shows a flowchart illustrating an example of the read operation of the semiconductor memory device 1 according to the first embodiment. [Figure 10] Figure 10 shows a timing chart, which is an example of the voltages of various signals during the read operation of the semiconductor memory device 1 according to the first embodiment. [Figure 11] Figure 11 shows an example of the cross-sectional structure of a circuit region of a semiconductor memory device 1m according to a modified example of the first embodiment. [Figure 12] Figure 12 shows an example of the cross-sectional structure of the circuit region of a semiconductor memory device 1m according to a modified example of the first embodiment. [Figure 13] Figure 13 shows an example of the circuit configuration of the sense amplifier unit SAU included in the semiconductor memory device 1b according to the second embodiment. [Figure 14] Figure 14 shows an example of the cross-sectional structure of the circuit region of the semiconductor memory device 1b according to the second embodiment. [Figure 15] Figure 15 shows a timing chart, which is an example of the voltages of various signals during the read operation of the semiconductor memory device 1b according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral, and repeated descriptions may be omitted. Multiple components having substantially the same function and configuration may be denoted by additional numbers or letters at the end of their reference numerals to distinguish them from one another.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, there may be differences in the relationships and ratios of dimensions between drawings. In addition, all descriptions of one embodiment may also apply to other embodiments unless explicitly or obviously excluded.

[0009] In this specification and in the claims, “substantially the same,” “approximately the same,” and “approximately identical” mean that they are intended to be the same, but are not exactly identical due to limitations in manufacturing and / or measurement techniques, and allow for errors.

[0010] In this specification and the claims, when a first element is "connected" to a second element, it includes that the first element is connected to the second element directly or through an element that is always or selectively conductive. "Electrically connected" means that it may be through an insulator as long as it can operate in the same manner as those that are electrically connected.

[0011] Hereinafter, a rectangular coordinate system composed of an X-axis, a Y-axis, and a Z-axis is used. In the following description, the description of "down" and its derivatives and related words refer to positions with smaller coordinates on the Z-axis, and the description of "up" and its derivatives and related words refer to positions with larger coordinates on the Z-axis.

[0012] In the drawings, hatching is appropriately added to make the figures easier to view. The hatching added to the drawings is not necessarily related to the material or characteristics of the components to which the hatching is added. In the drawings, components such as insulator layers (interlayer insulating films), substrates, wirings, contacts, etc. are appropriately omitted to make the figures easier to view.

[0013] <1>First Embodiment Hereinafter, the semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is, for example, a NAND-type flash memory. The following description is based on an example where the semiconductor memory device 1 is a NAND-type flash memory.

[0014] <1-1>Configuration (Structure) <1-1-1>Overall Configuration of the Semiconductor Memory Device 1 FIG. 1 shows the elements and connections in the semiconductor memory device 1 of the first embodiment, as well as related elements. As shown in FIG. 1, the semiconductor memory device 1 is controlled by a memory controller 2. The memory controller 2 receives commands from a host device (not shown) and controls the semiconductor memory device 1 based on the received commands.

[0015] The semiconductor memory device 1 is connected to the memory controller 2 via a NAND bus. The NAND bus transmits a number of control signals and an 8-bit wide input / output signal DQ. The control signals include signals CE, CLE, BLE, WE, RE, WP, data strobe signals DQS and DQS, and the ready / busy signal RB. The symbol "￣" indicates inverted logic. The semiconductor memory device 1 receives and transmits input / output signals DQ. The input / output signals DQ include command (CMD), write data or read data (DAT), address information (ADD), and status (STA).

[0016] Signal CE enables semiconductor memory device 1. Signal CLE notifies semiconductor memory device 1 to send a command via input / output signal DQ. Signal ALE notifies semiconductor memory device 1 to send address information via input / output signal DQ. Signal WE instructs semiconductor memory device 1 to receive input / output signal DQ. Signal RE instructs semiconductor memory device 1 to output input / output signal DQ. The ready / busy signals RY / BY indicate whether semiconductor memory device 1 is ready or busy, with a low level indicating busy. When semiconductor memory device 1 is ready, it accepts commands; when busy, it does not accept commands.

[0017] The semiconductor memory device 1 includes components such as a memory cell array 10, input / output circuits 11, registers 12, a sequencer 13, a voltage generation circuit 14, a driver 15, a row decoder 16, a sense amplifier 17, and a data register (data cache) 18.

[0018] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK (BLK0, BLK1, ...). Each block BLK includes a plurality of memory cell transistors MT. The memory cell array 10 also contains word lines WL (not shown) and bit lines BL (not shown).

[0019] The input / output circuit 11 is connected to the memory controller 2 by wiring based on a NAND memory interface.

[0020] Register 12 is a circuit that holds the command CMD and address information ADD received by the memory controller 2. The command CMD instructs the sequencer 13 to perform various operations, including data read, data write, and data erase. The address information ADD includes, for example, a block address, a page address, and a column address. The block address, page address, and column address specify the block BLK, word line WL, and bit line BL, respectively.

[0021] The sequencer 13 is a circuit that controls the operation of the entire semiconductor memory device 1. Based on the command CMD received from the register 12, the sequencer 13 controls the voltage generation circuit 14, the row decoder 16, and the sense amplifier 17 to perform various operations including data reading, data writing, and data erasure.

[0022] The voltage generation circuit 14 is a circuit that generates multiple voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from outside the semiconductor memory device 1 and generates multiple voltages from the power supply voltage. The generated voltages are supplied to components such as the memory cell array 10 and the driver 15. By applying various voltages, voltages are applied to various components and wiring in the semiconductor memory device 1.

[0023] The driver 15 is a circuit that applies various voltages necessary for the operation of the semiconductor memory device 1 to several components. The driver 15 receives multiple voltages from the voltage generation circuit 14 and supplies a selected voltage from among them to the raw decoder 16.

[0024] The row decoder 16 is a circuit for selecting a block BLK. The row decoder 16 transfers the potential supplied from the driver 15 to one block BLK selected based on the block address received from the register 12.

[0025] The sense amplifier 17 is a circuit that determines the data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT and generates read data or transfers write data to the memory cell transistor MT based on the sensed state.

[0026] The data register 18 is a circuit that holds data for input and output of data by the semiconductor memory device 1. The data register 18 receives the data DAT received by the semiconductor memory device 1 and supplies data based on the received data DAT to the sense amplifier 17. The data register 18 receives data from the sense amplifier 17 and supplies data DAT based on the received data to the input / output circuit 11.

[0027] <1-1-2> Circuit configuration of the memory cell array 10 Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10 provided in the semiconductor memory device 1 according to the first embodiment. In Figure 2, one block BLK is extracted and shown from among a plurality of block BLKs included in the memory cell array 10. For example, all other block BLKs are also composed of the elements and connections shown in Figure 2. The number of block BLKs in the memory cell array 10 and the number of string units SU in one block BLK can be set to any number. The following description is based on an example in which one block BLK contains five string units SU0 to SU4.

[0028] Each string unit SU is a set of multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains multiple memory cell transistors, e.g., memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2. The following description is based on an example where each NAND string NS contains eight memory cell transistors MT0 to MT7.

[0029] The memory cell transistor MT includes a control gate and a charge storage layer, and retains data non-volatilely. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0030] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the set of memory cell transistors MT0 to MT7. The other end of the set of memory cell transistors MT0 to MT7 is connected to the drain of selection transistor ST2. The source of selection transistor ST2 is connected to the source line SL.

[0031] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of each selection transistor ST1 in string units SU0 to SU4 are connected to selection gate lines SGD0 to SGD4, respectively. The gates of multiple selection transistors ST2 are connected to the selection gate line SGS.

[0032] Column addresses are assigned to bit lines BL0 to BLm. Each bit line BL is shared by a certain NAND string NS in each of multiple block BLKs. Each of the word lines WL0 to WL7 is provided for each block BLK. Source lines SL are shared, for example, between multiple block BLKs.

[0033] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is referred to, for example, as a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0034] Furthermore, the circuit configuration of the memory cell array 10 provided in the semiconductor memory device 1 according to the first embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to any number.

[0035] <1-1-3> Configuration of SenseAmp 17 Figure 3 is a block diagram of a sense amplifier 17 included in the semiconductor memory device 1 according to the first embodiment. As shown in Figure 3, the sense amplifier 17 includes a plurality of sense amplifier units SAU and a plurality of latch circuits XDL.

[0036] A sense amplifier unit (SAU) is provided for each bit line (BL). During data read operations, the sense amplifier unit (SAU) senses data read from the connected bit line (BL), and during data write operations, it transfers the data to be written to the connected bit line (BL). In Figure 3, eight sense amplifier units (SAU) are commonly connected to a single bus (DBUS). The number of sense amplifier units (SAU) connected to a single bus (DBUS) is arbitrary. In the following explanation, when distinguishing between the eight sense amplifier units (SAU) commonly connected to a single bus (DBUS), each will be referred to as SAU. <0> ~SAU <7> This is how it is written.

[0037] A latch circuit XDL is provided for each sense amplifier unit SAU and temporarily stores data related to the connected bit line BL. Figure 3 shows the sense amplifier unit SAU <0> ~SAU <7> Eight latch circuits XDL<7:0>, each corresponding to a specific component, are connected in common to a single bus DBUS. Alternatively, each of the eight latch circuits XDL<7:0> could be connected to one of the eight bus DBUS components.

[0038] Each latch circuit XDL is connected to a data line I / O. The latch circuits XDL are used to send and receive data between the sense amplifier unit SAU and the outside world via the bus DBUS and data line I / O. That is, for example, data received from the controller is first stored in the latch circuit XDL via the data line I / O, and then transferred to the sense amplifier unit SAU via the bus DBUS. The reverse is also true.

[0039] Figure 4 shows an example of the layout of the sense amplifier 17 included in the semiconductor memory device 1 according to the first embodiment. As shown in Figure 4, the bit lines BL extend along the Y axis and are aligned along the X axis. The distance between adjacent bit lines BL along the X axis may be referred to as the "BL pitch" below.

[0040] Sense Amplifier Unit SAU <0> This is the sense amplifier unit SAU <0> They are adjacent to each other along the X-axis. The width along the X-axis for each sense amplifier unit (SAU) may be referred to as the "SAU pitch" below.

[0041] <1-1-4> Circuit configuration of the sense amplifier unit SAU The circuit configuration of the sense amplifier unit SAU will be explained with reference to Figure 5. Figure 5 is a circuit diagram of the sense amplifier unit SAU included in the semiconductor memory device 1 according to the first embodiment.

[0042] Figure 5 shows an example of the circuit configuration of a sense amplifier unit SAU, by extracting one sense amplifier unit SAU from among the multiple sense amplifier units SAU included in the sense amplifier 17. All other sense amplifier units SAU also have the configuration shown in Figure 5. The sense amplifier unit SAU includes a sense circuit SA and, for example, three latch circuits (SDL, ADL, and BDL).

[0043] The sense circuit SA senses the data read from the bit line BL during data reading and determines whether the read data is "0" or "1". During data writing, the sense circuit SA applies a voltage to the bit line BL based on the data to be written. The sense circuit SA also performs AND or OR operations using the data in the latch circuits SDL, ADL, and BDL.

[0044] The sense circuit SA is described in detail. In the following description, one of the transistor's sources or drains may be referred to as "one end of the current path," and the other source or drain may be referred to as "the other end of the current path."

[0045] The sense circuit SA includes n-channel MOS transistors 20-33, a p-channel MOS transistor 36, and capacitive elements 34 and 35.

[0046] The gate of transistor 20 receives the signal BLC. One end of the current path of transistor 20 is connected to the bit line BL, and the other end of the current path of transistor 20 is connected to node SCOM. Transistor 20 is used to clamp the connected bit line BL to a voltage corresponding to the signal BLC.

[0047] The gate of transistor 21 receives the signal BLX. One end of the current path of transistor 21 is connected to node SCOM, and the other end of the current path of transistor 21 is connected to node SSRC.

[0048] The gate of transistor 22 receives the signal NLO. One end of the current path of transistor 22 is connected to node SCOM, and the other end of the current path of transistor 22 is connected to node SRCGND. A ground voltage, for example, VSS, is applied to node SRCGND. Transistor 22 is used to charge or discharge the connected bit line BL.

[0049] The gate of transistor 23 is connected to node INV_S. One end of the current path of transistor 23 is connected to node SSRC, and the other end of the current path of transistor 23 is connected to node SRCGND.

[0050] The gate of transistor 24 receives signal XXL. One end of the current path of transistor 24 is connected to node SCOM, and the other end of the current path of transistor 24 is connected to node SEN1. Transistor 24 controls the period for sensing data from memory cell transistor MT. The function of node SEN1 will be described later.

[0051] The gate of transistor 31 receives the signal SPC. One end of the current path of transistor 31 is connected to node SEN1, and the other end of the current path of transistor 31 has a voltage VHLB applied to it. The voltage VHLB is, for example, the power supply voltage VDD. By turning on transistor 31 and transferring the voltage VHLB to node SEN1, node SEN1 is pre-charged.

[0052] The gate of transistor 33 receives the signal S2S. One end of the current path of transistor 33 is connected to node SEN1, and the other end of the current path of transistor 33 is connected to node SEN2. By turning off transistor 33, nodes SEN1 and SEN2 can be isolated.

[0053] Nodes SEN1 and SEN2 function as sense nodes for sensing data from the target memory cell transistor MT during data readout. More specifically, during readout, the pre-charged charge in nodes SEN1 and SEN2 (capacitive elements 34 and 35) is transferred to the bit line BL depending on whether the target memory cell transistor MT is on or off. Data readout is performed by sensing the voltages of nodes SEN1 and SEN2 at this time.

[0054] The gate of transistor 25 is connected to node SEN2. One end of the current path of transistor 25 is connected to one end of the current path of transistor 26, and the other end of the current path of transistor 25 is connected to node VLOP. A voltage VLOP is applied to node VLOP. The voltage VLOP will be described later.

[0055] The gate of transistor 26 receives the signal STB. The other end of the current path of transistor 26 is connected to the bus LBUS.

[0056] The gate of transistor 27 receives the signal BLQ. One end of the current path of transistor 27 is connected to node SEN2, and the other end of the current path of transistor 27 is connected to bus LBUS.

[0057] The gate of transistor 28 is connected to the bus LBUS. One end of the current path of transistor 28 is connected to one end of the current path of transistor 29, and the other end of the current path of transistor 28 is connected to node VLOP.

[0058] The gate of transistor 29 receives the signal LSL. The other end of the current path of transistor 29 is connected to node SEN2.

[0059] The gate of transistor 30 receives the signal LPC. One end of the current path of transistor 30 is connected to the bus LBUS, and the voltage VDDLT is applied to the other end of the current path of transistor 30. Voltage VDDLT is lower than, for example, voltage VHLB. By turning on transistor 30 and transferring voltage VDDLT to the bus LBUS, the bus LBUS is precharged.

[0060] The gate of transistor 32 receives the signal DSW. One end of the current path of transistor 32 is connected to bus LBUS, and the other end of the current path of transistor 32 is connected to bus DBUS. Transistor 32 is a bus switch for connecting bus LBUS and bus DBUS. This bus switch connects the sense circuit SA and the latch circuit XDL.

[0061] The gate of transistor 36 is connected to node INV_S. A voltage VHSA is applied to one end of the current path of transistor 36, and the other end of the current path of transistor 36 is connected to node SSRC. The voltage VHSA is, for example, the power supply voltage VDD.

[0062] One electrode of the capacitive element 34 is connected to node SEN1, and the other electrode of the capacitive element 34 is connected to bus LBUS.

[0063] One electrode of the capacitive element 35 is connected to node SEN2, and the other electrode of the capacitive element 35 is connected to node VLOP.

[0064] In each sense amplifier unit SAU, the sense circuit SA and the three latch circuits SDL, ADL, and BDL are connected by a bus LBUS so that they can send and receive data from one another.

[0065] The various signals in the sense amplifier unit SAU with the above configuration are provided, for example, by the sequencer 13.

[0066] The latch circuits SDL, ADL, and BDL temporarily store data. During data writing, the sense circuit SA controls the bit line BL according to the data stored in the latch circuit SDL. The other latch circuits ADL and BDL are used to temporarily store the data of each bit, for example, when individual memory cell transistors MT store two or more bits of data. The number of latch circuits can be set arbitrarily, for example, according to the amount of data (number of bits) that the memory cell transistors MT can store.

[0067] <1-2> Wiring structure Figure 6 shows an example of a planar structure of transistors in the semiconductor memory device 1 according to the first embodiment. Figure 6 is a part of the circuit region of the semiconductor memory device 1 and shows a part of the sense amplifier unit SAU shown in Figure 4 and another sense amplifier unit SAU aligned with this sense amplifier unit SAU along the X-axis. In adjacent sense amplifier units SAU along the X-axis, for example, a set of transistors that can share a power supply can have a structure as shown in Figure 6.

[0068] In adjacent sense amplifier units SAU along the X-axis, a set of transistors capable of sharing a power supply includes, for example, transistors Tr1 and Tr2 and an element isolation region STI. Transistor Tr1 may be any of transistors 20-33 and 36 included in a first sense amplifier unit SAU. Transistor Tr2 may be any of transistors 20-33 and 36 included in a sense amplifier unit SAU adjacent to the first sense amplifier unit SAU.

[0069] Transistor Tr1 has a first diffusion region NP1, a second diffusion region NP2, a first gate electrode GC1, contact CS1, and contact CS2. Contact CS1 is an electrode to which one end of the current path of transistor Tr1 is connected. Contact CS2 is an electrode to which the other end of the current path of transistor Tr1 is connected.

[0070] Transistor Tr2 has a first diffusion region NP1, a third diffusion region NP3, a second gate electrode GC2, contact CS1, and contact CS3. Contact CS1 is an electrode to which one end of the current path of transistor Tr2 is connected. Contact CS3 is an electrode to which the other end of the current path of transistor Tr2 is connected.

[0071] Transistors Tr1 and Tr2 share a first diffusion region NP1. In other words, the first diffusion region NP1 is continuously provided across transistors Tr1 and Tr2. The first contact CS1 is provided on the first diffusion region NP1. Transistors Tr1 and Tr2 share the first contact CS1.

[0072] In an XY plane view, the second diffusion region NP2 is located on the opposite side of the first diffusion region NP1 along the Y axis, with the first gate electrode GC1 in between. The first gate electrode extends along the X axis. The second contact CS2 is located on the second diffusion region NP2.

[0073] In an XY plane view, the third diffusion region NP3 is located on the opposite side of the first diffusion region NP1 along the Y axis, with the second gate electrode GC2 in between. The second gate electrode extends along the X axis. The third contact CS3 is located on the third diffusion region NP3.

[0074] The element isolation region (STI) is provided, for example, to electrically isolate transistors Tr1 and Tr2. The element isolation region (STI) electrically isolates the second diffusion region NP2 and the third diffusion region NP3, respectively, that transistors Tr1 and Tr2 have. The element isolation region (STI) is provided between the second diffusion region NP2 and the third diffusion region NP3. For example, silicon oxide is used for the element isolation region (STI).

[0075] In the semiconductor memory device 1 according to the first embodiment, the region along the X-axis of transistors Tr1 and Tr2 is shared by two sense amplifier units SAU. In other words, the SAU pitch, which is the width along the X-axis of each sense amplifier unit SAU, is approximately the same as half the width of the region along the X-axis of transistors Tr1 and Tr2.

[0076] Multiple sets of transistors capable of sharing a power supply (sets of transistors Tr1 and Tr2 and element isolation regions STI) may be arranged along the Y-axis. Multiple sets of transistors arranged along the Y-axis may be aligned along the X-axis.

[0077] In other words, the semiconductor memory device 1 may have a structure in which sets of transistors Tr1 and Tr2 and element isolation regions STI are repeatedly arranged. Figure 6 shows the structure of one such set of transistors Tr1 and Tr2 and element isolation regions STI.

[0078] Figure 7 is a cross-sectional view along the line VI-VI in Figure 6, showing an example of the cross-sectional structure of the circuit region of the semiconductor memory device 1 according to the first embodiment. As shown in Figure 7, the semiconductor memory device 1 includes, for example, a semiconductor substrate 38 and an insulating layer 39 in its circuit region. The insulating layer 39 is provided on the semiconductor substrate 38.

[0079] Although some parts are omitted in the illustration, a circuit region is provided in part of the semiconductor substrate 38 and within the insulating layer 39, and the memory cell array 10 is provided above the insulating layer 39. Circuits used, for example, a row decoder 16 and a sense amplifier 17 are provided in the circuit region.

[0080] The semiconductor substrate 38 is, for example, a P-type semiconductor substrate. The semiconductor substrate 38 includes, for example, a first diffusion region NP1 of transistors Tr1 and Tr2. The first diffusion region NP1 is provided on the upper surface (near the surface) of the semiconductor substrate 38 and is, for example, doped with phosphorus (P).

[0081] The first diffusion region NP1 is positioned apart from the second diffusion region NP2 (not shown) in the Y direction. The first diffusion region NP1 and the second diffusion region NP2 function as the source (source diffusion layer) or drain (drain diffusion layer) of the transistor Tr1.

[0082] The first diffusion region NP1 is positioned away from the third diffusion region NP3 (not shown) in the Y direction. The first diffusion region NP1 and the third diffusion region NP3 function as the source (source diffusion layer) or drain (drain diffusion layer) of the transistor Tr2.

[0083] The insulating layer 39 includes, for example, silicon oxide (SiO2). The insulating layer 39 includes, for example, conductive layers 40-46, 50-56, 60-64, and 70, and contacts CS1-CS3 and C1-C3. Each of the conductive layers 40-46, 50-56, 60-64, and 70, and contacts CS1-CS3 and C1-C3, contains, for example, a metal such as tungsten.

[0084] Contact CS1 is provided on the first diffusion region NP1. The first diffusion region NP1 and contact CS1 are electrically connected. A conductive layer 43 is provided on contact CS1. Contact C1 is provided on the conductive layer 43. A conductive layer 53 is provided on contact C1. Contact C2 is provided on the conductive layer 53. A conductive layer 62 is provided on contact C2. Contact C3 is provided on the conductive layer 62. A conductive layer 70 is provided on contact C3.

[0085] In the following, the wiring layers provided with conductive layers 43, 53, 62, and 70 may be referred to as “D0”, “D1”, “D2”, and “D3”, respectively.

[0086] In wiring layer D0, conductive layers 40 to 46 are arranged sequentially from the -X side to the +X side. In wiring layer D1, conductive layers 50 to 56 are arranged sequentially from the -X side to the +X side. Conductive layers 50 to 56 are located above conductive layers 40 to 46 along the Z axis. In wiring layer D2, conductive layers 60 to 64 are arranged sequentially from the -X side to the +X side.

[0087] Conductive layers 40-46, 50-56, and 60-64 extend, for example, along the Y-axis. Conductive layer 70 extends, for example, along the X-axis.

[0088] Contact CS2 is provided on a second diffusion region NP2 (not shown). The second diffusion region NP2 and contact CS2 are electrically connected. Contact CS2 is provided in the layer containing contact CS1. Contact CS2 is connected, for example, to a conductive layer 41 located in the wiring layer D0. Contact CS2 may also be connected to wiring other than the conductive layer 41 in the wiring layer D0.

[0089] Contact CS3 is provided on a third diffusion region NP3 (not shown). The third diffusion region NP3 and contact CS3 are electrically connected. Contact CS3 is provided in the layer containing contact CS1. Contact CS3 is connected, for example, to a conductive layer 45 located in the wiring layer D0. Contact CS3 may also be connected to wiring other than the conductive layer 45 in the wiring layer D0.

[0090] Conductive layers 50 and 54 function, for example, as node SEN1. Conductive layers 51 and 55 function, for example, as bus LBUS. Conductive layer 56 functions, for example, as bus DBUS. Conductive layers 60 and 64 function, for example, as bit line BL. Conductive layer 70 functions as a power line. Conductive layers 43, 53, and 62 connected to conductive layer 70 function as power lines. That is, conductive layers 43, 53, and 62, along with the contacts CS1 and C1-C3, function as power lines.

[0091] When the conductive layer 50, which functions as node SEN1, and the conductive layer 51, which functions as bus LBUS, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 50 and conductive layer 51 corresponds to the capacitive element 34 (see Figure 5).

[0092] Similarly, when the conductive layer 54, which functions as node SEN1, and the conductive layer 55, which functions as bus LBUS, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 54 and conductive layer 55 corresponds to the capacitive element 34.

[0093] The conductive layers 43, 53, and 62, as well as the contacts CS1 and C1-C3, are shared as the power supply for transistors Tr1 and Tr2. In this way, in adjacent sense amplifier units SAU along the X-axis, for example, transistors Tr1 and Tr2 can share a power supply.

[0094] As previously shown in Figure 6, the semiconductor memory device 1 according to the first embodiment shares the region along the X-axis of transistors Tr1 and Tr2 with two sense amplifier units SAU. In other words, the semiconductor memory device 1 shares seven wirings (conductor layers) aligned along the X-axis with two sense amplifier units SAU. To put it another way, the SAU pitch is approximately the same as the width of 3.5 wirings aligned along the X-axis.

[0095] The statement that "the SAU pitch is the width of 3.5 wires aligned along the X-axis" is sometimes referred to below as "the number of tracks in the sense amplifier unit SAU is 3.5." In other words, the number of tracks refers to the number of wires contained within the SAU pitch.

[0096] Similar to the relationship between node SEN1 and bus LBUS, the conductive layer functioning as node SEN2 and the conductive layer functioning as node VLOP are arranged adjacent to each other. Figure 8, like Figure 7, shows an example of the cross-sectional structure of the circuit region of the semiconductor memory device 1 according to the first embodiment.

[0097] As shown in Figure 8, the insulating layer 39 further includes conductive layers 80-83. Conductive layers 80-83 are located on wiring layer D0 or D1. Conductive layers 80 and 81 are located on the -X side of the contact CS1 and C1-C3 pair. Conductive layer 80 and conductive layer 81 are adjacent along the X axis.

[0098] Conductive layers 82 and 83 are located on the +X side of contact CS1 and the combination of C1-C3. Conductive layer 82 and conductive layer 83 are adjacent to each other along the X axis.

[0099] Conductive layers 80 and 82 function as node SEN2. Conductive layers 81 and 83 function as node VLOP.

[0100] When the conductive layer 80, which functions as node SEN2, and the conductive layer 81, which functions as node VLOP, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 80 and conductive layer 81 corresponds to the capacitive element 35 (see Figure 5).

[0101] Similarly, when the conductive layer 82, which functions as node SEN2, and the conductive layer 83, which functions as node VLOP, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 82 and conductive layer 83 corresponds to the capacitive element 35.

[0102] <1-3> Read operation Figure 9 is a flowchart showing an example of the read operation of the semiconductor memory device 1 according to the first embodiment. Figure 10 is a timing chart showing the voltages of various signals during the read operation of the semiconductor memory device 1 according to the first embodiment. Below, an example of the read operation of the semiconductor memory device 1 according to the first embodiment will be described with reference to Figure 9 as appropriate.

[0103] In the first embodiment, the read operation is performed by precharging nodes SEN1 and SEN2 in the sense circuit SA, transferring the precharged charge from nodes SEN1 and SEN2 to the bit line BL, and then stroving.

[0104] As shown in Figure 9, the semiconductor memory device 1 according to the first embodiment executes, for example, the processes in steps S10 to S19 in order during the read operation.

[0105] In step S10, the bit line BL is precharged. That is, when the memory cell transistor MT to be read is selected, the sense amplifier 17 precharges the bit line BL.

[0106] Specifically, as shown in Figure 10, at time t1, the sequencer 13 raises the signal BLC from Low ("L") level (VSS) to High ("H") level (VBLC) and the signal BLX from Low ("L") level (VSS) to High ("H") level (VBLX). Voltage VBLC is the voltage used to clamp the voltage of bit line BL. Voltage VBLX is the voltage that allows transistor 21 to transfer voltage VDD. Voltage VBLX is higher than voltage VBLC. As a result, transistors 20 and 21 are turned on, and bit line BL is precharged. Precharging of bit line BL takes place during the period from time t1 to time t4.

[0107] At time t1, the sequencer 13 sets the voltage of node VLOP to the "L" level (VSS).

[0108] In step S11, node SEN1 is precharged. That is, the sense amplifier 17 precharges node SEN1 while precharging bit line BL.

[0109] Specifically, as shown in Figure 10, at time t1, the sequencer 13 raises the signal SPC from "L" level (VSS) to "H" level (VX2). Voltage VX2 is the voltage that allows transistor 31 to transfer voltage VHLB. As a result, transistor 31 turns on, and node SEN1 is precharged with voltage VHLB. Bus LBUS is, for example, in a floating state during the period from time t1 to time t2, and can take any value between VSS and VDD.

[0110] In step S12, the signal S2S is raised to the "H" level (VX2). Specifically, as shown in Figure 10, at time t2, the sequencer 13 raises the signal S2S from the "L" level (VSS) to the "H" level (VX2). Voltage VX2 is the voltage that turns on transistor 33 and brings nodes SEN1 and SEN2 to the same potential. Therefore, transistor 33 is turned on. When transistor 33 is turned on, nodes SEN1 and SEN2 are linked and at the same potential. By turning transistor 33 off, the potential of node SEN2 and the potential of node SEN1 become independent of each other.

[0111] In step S13, node SEN2 is precharged. That is, sense amplifier 17 precharges node SEN2. Specifically, as shown in Figure 10, at time t2, transistor 33 is ON (step S12), so node SEN2 is precharged to the "H" level (VHLB).

[0112] Next, due to node SEN2 being precharged, transistor 25 turns ON. Also, at time t2, sequencer 13 raises signal STB from "L" level (VSS) to "H" level (VDD). As a result, transistor 26 turns ON. With transistors 25 and 26 turned ON, bus LBUS becomes at the same potential as node VLOP. That is, bus LBUS becomes "L" level (VSS).

[0113] In step S14, the potential of node SEN1 is clock-up. Specifically, as shown in Figure 10, at time t3, the sequencer 13 lowers the signal SPC from "H" level (VX2) to "L" level (VSS). Also at time t3, the sequencer 13 lowers the signal STB from "H" level (VDD) to "L" level (VSS). As a result, transistors 31 and 26 are turned off.

[0114] Furthermore, at time t3, the sequencer 13 raises the signal LPC from "L" level (VSS) to "H" level (VX2). As a result, transistor 30 turns on.

[0115] When transistor 30 is turned ON, the bus LBUS rises from the "L" level (VSS) to the "H" level (VDDLT). In other words, the bus LBUS is charged. Voltage VDDLT is lower than voltage VHLB. As a result, capacitive element 34 is charged, and the voltage at node SEN1 rises to voltage Vcu1 due to the effect of capacitive coupling. Voltage Vcu1 is the voltage at node SEN1 that has risen due to the clock up, and it is higher than voltage VHLB.

[0116] In step S15, the potential of node SEN2 is clock-up. Specifically, at time t3, the sequencer 13 raises the voltage of node VLOP from "L" level (VSS) to "H" level (VDDSA). Voltage VDDSA is, for example, the power supply voltage VDD.

[0117] As a result, the capacitive element 35 is charged, and the voltage at node SEN2 rises to voltage Vcu1 due to the effect of capacitive coupling. Voltage Vcu1 is the voltage at node SEN2 that has risen due to the clock-up. At this time, since transistor 33 is in the ON state, nodes SEN1 and SEN2 conduct and are at the same potential. That is, nodes SEN1 and SEN2 are clock-up by both the bus LBUS and node VLOP, resulting in voltage Vcu1.

[0118] In step S16, the potentials of nodes SEN1 and SEN2 are sensed. That is, after the clock is up, the sense amplifier 17 senses the voltages of nodes SEN1 and SEN2.

[0119] Specifically, as shown in Figure 10, at time t4, the sequencer 13 raises the signal XXL from "L" level (VSS) to "H" level (VXXL). Voltage VXXL is higher than voltage VBLX.

[0120] In this state, if the threshold voltage of the memory cell transistor MT to be read is equal to or greater than the read voltage, the memory cell transistor MT is considered to be in an off state (hereinafter referred to as "off-cell"). Almost no current flows from the bit line BL connected to the off-cell to the source line SL. Therefore, when reading from an off-cell, the charge stored in nodes SEN1 and SEN2 is hardly discharged. That is, at time t4, the voltages of nodes SEN1 and SEN2 hardly fluctuate.

[0121] On the other hand, if the threshold voltage of the memory cell transistor MT to be read is less than the read voltage, the memory cell transistor MT is turned on (hereinafter referred to as "on-cell"). Current flows from the bit line BL connected to the on-cell to the source line SL. Since voltage VXXL is higher than voltage VBLX, when reading from an on-cell, the charge stored in nodes SEN1 and SEN2 is discharged. That is, at time t4, the voltages of nodes SEN1 and SEN2 begin to decrease.

[0122] At time t5, the sequencer 13 drops the signal XXL from the "H" level (VXXL) to the "L" level (VSS). As shown in Figure 10, between time t4 and time t5, the voltages of nodes SEN1 and SEN2, which were connected to the off-cell, hardly change from the voltage Vcu1.

[0123] Furthermore, as shown in Figure 10, the voltages of nodes SEN1 and SEN2, which were connected to the on-cell, gradually decrease between time t4 and time t5. The voltages of nodes SEN1 and SEN2, which were connected to the on-cell, settle at voltage Vcu2 at time t5.

[0124] In step S17, the signal S2S is lowered to the "L" level (VSS). Specifically, as shown in Figure 10, at time t6, the sequencer 13 lowers the signal S2S from the "H" level (VX2) to the "L" level (VSS). This turns off transistor 33. With transistor 33 turned off, the potentials of node SEN2 and node SEN1 become independent of each other.

[0125] Furthermore, as shown in Figure 10, at time t6, the sequencer 13 lowers the signal LPC from "H" level (VX2) to "L" level (VSS). As a result, transistor 30 turns off.

[0126] Because transistors 33 and 30 are turned off, node SEN1 enters a floating state. Therefore, for example, from time t6 onward, node SEN1 can take any value between VSS and Vcu1.

[0127] In step S18, the potential of node SEN2 is clocked down. Specifically, at time t7, the sequencer 13 lowers the voltage of node VLOP from the "H" level (VDDSA) to the "L" level (VSS).

[0128] As a result, the voltage of node SEN2 decreases due to the effect of capacitive coupling. Specifically, as shown in Figure 10, the voltage of node SEN2, which was connected to an off-cell, decreases to voltage Vcu3. Voltage Vcu3 is the voltage of node SEN2 that has decreased due to clock down (in the case of an off-cell). If the threshold voltage of transistor 25 is Vth15, then voltage Vcu3 is between Vth15 and Vcu1.

[0129] Additionally, the voltage of node SEN2, which was connected on-cell, drops to voltage Vcu3'. Voltage Vcu3' is the voltage of node SEN2 (in the case of on-cell) after the clock down. Voltage Vcu3' is lower than voltage Vcu2. Voltage Vcu3' is between VSS and Vth15. The difference between voltage Vcu2 and voltage Vcu3' is approximately equal to the difference between voltage Vcu1 and voltage Vcu3.

[0130] In step S19, the sense amplifier 17 performs a strobe. First, as shown in Figure 10, at time t8, the sequencer 13 raises the signal STB from the "L" level (VSS) to the "H" level (VDD). This turns on transistor 26. As a result, transistor 25, which was connected to the off-cell, turns on based on the voltage difference between voltage Vcu3 and voltage Vth15. With transistors 25 and 26 turned on, the voltage of the bus LBUS decreases. Let the voltage of the bus LBUS at this time be Vlb1.

[0131] On the other hand, transistor 25, which was connected to the on-cell, turns off based on the voltage difference between voltage Vcu3' and voltage Vth15. Because transistor 25 is off, the bus LBUS is maintained at voltage VDDLT. Let the voltage of the bus LBUS at this time be Vlb1'.

[0132] At time t9, the sequencer 13 lowers the signal STB from the "H" level (VDD) to the "L" level (VSS). This turns off transistor 26, and the voltage of bus LBUS is maintained. As a result, the logic level of the read data is determined. If the voltage of bus LBUS is Vlb1, it is determined that bus LBUS is holding "L" level data. If the voltage of bus LBUS is Vlb1', it is determined that bus LBUS is holding "H" level data.

[0133] In other words, when the data from node SEN2 is at the "H" level (Vcu3), the bus LBUS becomes at the "L" level (Vlb1), and this "L" level is held by the latch circuit SDL. When the data from node SEN2 is at the "L" level (Vcu3'), the node LBUS is maintained at the "H" level (Vlb1'), and this "H" level is held by the latch circuit SDL.

[0134] Once the logic level of the read data is determined, a logical operation is performed using the determined logic level (for example, an AND or OR operation between the determined data and the data of latch circuit ADL, or an AND or OR operation between the determined data and the data of latch circuit BDL). The determined logic level may also be transferred to latch circuit XDL.

[0135] In the read operation flow of the first embodiment described above, none of the steps are limited to the illustrative order, and unless otherwise indicated, any of them may occur in a different order and / or in parallel with other steps.

[0136] <1-4> Advantages (Effects) of the First Embodiment According to the semiconductor memory device 1 of the first embodiment described above, the circuit area of ​​the sense amplifier 17 can be reduced. The detailed effects of the semiconductor memory device 1 of the first embodiment will be described below.

[0137] To reduce the chip size of the semiconductor memory device 1, it is required to reduce the circuit area of ​​the sense amplifier 17. Two methods are possible to reduce the circuit area of ​​the sense amplifier 17. First, wiring capacitance is used for the sense nodes (for example, nodes SEN1 and SEN2 in Figure 5), and capacitive elements are not used. This is because using capacitive elements increases the length of the sense amplifier along the Y axis.

[0138] Another point is to reduce the number of tracks per sense amplifier unit (SAU). This is because increasing the number of tracks increases the number of sense amplifier units (SAU) along the X-axis. To suppress the width of the sense amplifier units (SAU) along the X-axis, 3.5 tracks or less is desirable.

[0139] Here, as a comparative example, we consider a semiconductor memory device 1r according to a comparative example of the first embodiment. The semiconductor memory device 1r uses wiring capacitance to reduce the circuit area of ​​the sense amplifier 17, and the number of tracks per sense amplifier unit SAU is 3.5. The semiconductor memory device 1r differs from the semiconductor memory device 1 according to the first embodiment mainly in that it does not have node SEN2, capacitive element 35, and transistors 31 and 33. Node SEN1 in the semiconductor memory device 1r may be referred to as node SENr below.

[0140] Due to the reduction in the number of tracks, the semiconductor memory device 1r may have wiring that functions as a node SENr and wiring that functions as a bus LBUS arranged adjacent to each other along the X-axis. Because the node SENr and bus LBUS are adjacent, the node SENr is coupled to the bus LBUS.

[0141] In the semiconductor memory device 1r, when node SENr and bus LBUS are coupled, read operations cannot be performed accurately. This is because, for example, when sense amplifier 17 performs strobe, the voltage of bus LBUS fluctuates. When the voltage of bus LBUS fluctuates, the potential of node SENr coupled to bus LBUS also fluctuates. When the potential of node SENr fluctuates, it may become impossible to accurately control transistor 25 connected to node SENr. When the control of transistor 25 cannot be performed accurately, the voltage of bus LBUS also becomes inaccurate. In other words, it becomes impossible to accurately determine whether the memory cell transistor MT connected to node SENr was off-cell or on-cell.

[0142] Thus, although there is a demand to reduce the number of tracks, simply reducing the number of tracks, as in semiconductor memory device 1r, can lead to problems such as inaccurate read operations. Therefore, after reducing the number of tracks, it is necessary to implement measures to address the coupling between the bus LBUS and node SENr.

[0143] Therefore, the sense node of the semiconductor memory device 1 according to the first embodiment is designed such that fluctuations in the voltage of the bus LBUS do not affect the sense node when the sense amplifier 17 performs strobe.

[0144] As described above, the semiconductor memory device 1 has nodes SEN1 and SEN2, a capacitive element 35, and transistors 31 and 33. By turning on transistor 33, the semiconductor memory device 1 can make nodes SEN1 and SEN2 conduct and set them to the same potential. By turning off transistor 33, the semiconductor memory device 1 can set the potentials of node SEN1 and node SEN2 to be in a state independent of each other.

[0145] During the processing of steps S12 to S16, the semiconductor memory device 1 maintains the transistor 33 in the ON state. That is, when sensing nodes SEN1 and SEN2 during the read operation of the semiconductor memory device 1, nodes SEN1 and SEN2 are in a conductive state. In other words, the semiconductor memory device 1 makes nodes SEN1 and SEN2 conductive and senses both nodes SEN1 and SEN2. By sensing both nodes SEN1 and SEN2, the charge pre-charged in nodes SEN1 and SEN2 (capacitive elements 34 and 35) is transferred to the bit line BL. Therefore, the semiconductor memory device 1 can transfer more charge than when sensing only one of nodes SEN1 or SEN2.

[0146] During steps S17 to S19, the semiconductor memory device 1 maintains transistor 33 in the off state. That is, during the read operation of the semiconductor memory device 1, when strobe operation is performed, the potentials of node SEN1 and node SEN2 are in a state independent of each other. Specifically, the semiconductor memory device 1 makes node SEN2 independent from node SEN1 by turning off transistor 33. Only node SEN1 is coupled to bus LBUS. Because node SEN2 is independent from node SEN1, node SEN2 is no longer affected by fluctuations in the bus LBUS voltage during strobe operation.

[0147] Since SEN1 is in a floating state from time t6 onward, the effects of fluctuations in the bus LBUS voltage can be ignored. The potential of node SEN2 is maintained without being affected, so the control of transistor 25 connected to node SEN2 can be performed accurately. Because the control of transistor 25 can be performed accurately, the voltage of the bus LBUS is also accurate. In other words, it can be accurately determined whether the memory cell transistor MT connected to nodes SEN1 and SEN2 was off-cell or on-cell.

[0148] Thus, according to the semiconductor memory device 1 of the first embodiment, the number of tracks per sense amplifier unit SAU can be reduced while the read operation can be performed normally.

[0149] <2> Modified form of the first embodiment <2-1>Configuration (structure) In the semiconductor memory device 1 according to the first embodiment described above, an example was shown in which the number of tracks per sense amplifier unit SAU is 3.5. However, the number of tracks per sense amplifier unit SAU is not limited to the structure described above. A modified semiconductor memory device 1 according to the first embodiment may be referred to as semiconductor memory device 1m below.

[0150] In this modified semiconductor memory device 1m of the first embodiment, the circuit configuration of the sense amplifier unit SAU and the timing chart during read operation are the same as those of the semiconductor memory device 1.

[0151] Figure 11 shows an example of the cross-sectional structure of a circuit region of a semiconductor memory device 1m according to a modified example of the first embodiment. Figure 11 shows the same region as in Figure 7.

[0152] As shown in Figure 11, in the modified semiconductor memory device 1m, the number of tracks per sense amplifier unit SAU may be 3. The specific structure is shown below.

[0153] In the semiconductor memory device 1m, the semiconductor substrate 38, the insulating layer 39, the first diffusion region NP1, the second diffusion region NP2, the third diffusion region NP3, and the conductive layer 70 have the same structure and function as the semiconductor memory device 1 according to the first embodiment.

[0154] The insulating layer 39 includes, for example, conductive layers 40m-45m, 50m-55m, 60m-64m, and 70, as well as contacts CS1-CS3 and C1-C3. Each of the conductive layers 40m-45m, 50m-55m, 60m-64m, and 70, and contacts CS1-CS3 and C1-C3, contains a metal such as tungsten.

[0155] Contact CS1 is provided on the first diffusion region NP1. The first diffusion region NP1 and contact CS1 are electrically connected. A conductive layer 42m is provided on contact CS1. Contact C1 is provided on the conductive layer 42m. A conductive layer 52m is provided on contact C1. Contact C2 is provided on the conductive layer 52m. A conductive layer 62m is provided on contact C2. Contact C3 is provided on the conductive layer 62m. A conductive layer 70 is provided on contact C3.

[0156] In wiring layer D0, conductive layers 40m to 45m are arranged sequentially from the -X side to the +X side. In wiring layer D1, conductive layers 50m to 55m are arranged sequentially from the -X side to the +X side. Conductive layers 50m to 55m are located above conductive layers 40m to 45m along the Z axis. In wiring layer D2, conductive layers 60m to 64m are arranged sequentially from the -X side to the +X side.

[0157] The conductive layers 40m-45m, 50m-55m, and 60m-64m extend, for example, along the Y-axis.

[0158] Contact CS2 is provided on a second diffusion region NP2 (not shown). The second diffusion region NP2 and contact CS2 are electrically connected. Contact CS2 is provided in the layer containing contact CS1. Contact CS2 is connected, for example, to a conductive layer 41m located in the wiring layer D0. Contact CS2 may also be connected to wiring other than the conductive layer 41m in the wiring layer D0.

[0159] Contact CS3 is provided on a third diffusion region NP3 (not shown). The third diffusion region NP3 and contact CS3 are electrically connected. Contact CS3 is provided in the layer containing contact CS1. Contact CS3 is connected, for example, to a conductive layer 44m located in the wiring layer D0. Contact CS3 may also be connected to wiring other than the conductive layer 44m in the wiring layer D0.

[0160] Conductive layers 50m and 53m function, for example, as node SEN1. Conductive layers 51m and 54m function, for example, as bus LBUS. Conductive layers 60m and 64m function, for example, as bit line BL. Conductive layers 42m, 52m, and 62m connected to conductive layer 70 function as power lines. That is, conductive layers 42m, 52m, and 62m, along with contacts CS1 and C1-C3, function as power lines.

[0161] When the conductive layer 50m, which functions as node SEN1, and the conductive layer 51m, which functions as bus LBUS, are placed adjacent to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 50m and conductive layer 51m corresponds to the capacitive element 34 (see Figure 5).

[0162] Similarly, when the conductive layer 53m, which functions as node SEN1, and the conductive layer 54m, which functions as bus LBUS, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 53m and conductive layer 54m corresponds to the capacitive element 34.

[0163] The conductive layers 42m, 52m, and 62m, along with the contacts CS1 and C1-C3, are shared as power supplies for transistors Tr1 and Tr2. In this way, similar to semiconductor memory device 1, in semiconductor memory device 1m, adjacent sense amplifier units SAU along the X-axis, for example, transistors Tr1 and Tr2, can share a power supply.

[0164] Thus, in the semiconductor memory device 1m according to the modified version of the first embodiment, six wirings (conductive layers) aligned along the X-axis are shared by two sense amplifier units SAU. In other words, the SAU pitch is approximately the same as the width of three wirings aligned along the X-axis. That is, in the semiconductor memory device 1m according to the modified version of the first embodiment, the number of tracks per sense amplifier unit SAU is 3.

[0165] Figure 12, similar to Figure 11, shows an example of the cross-sectional structure of a circuit region of a semiconductor memory device 1m according to a modified example of the first embodiment. Similar to the relationship between node SEN1 and bus LBUS, the conductive layer functioning as node SEN2 and the conductive layer functioning as node VLOP are arranged adjacent to each other.

[0166] As shown in Figure 12, the insulating layer 39 of the semiconductor memory device 1m further includes conductive layers 80m to 83m. Conductive layers 80m to 83m are located on wiring layer D0 or D1. Conductive layers 80m and 81m are located on the -X side of the contact CS1 and C1 to C3 pair. Conductive layer 80m and conductive layer 81m are adjacent along the X axis.

[0167] Conductive layers 82m and 83m are located on the +X side of contact CS1 and the combination of C1-C3. Conductive layer 82m and conductive layer 83m are adjacent to each other along the X axis.

[0168] Conductive layers 80m and 82m function as node SEN2. Conductive layers 81m and 83m function as node VLOP.

[0169] When conductive layer 80m, which functions as node SEN2, and conductive layer 81m, which functions as node VLOP, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 80m and conductive layer 81m corresponds to the capacitive element 35 (see Figure 5).

[0170] Similarly, when the conductive layer 82m, which functions as node SEN2, and the conductive layer 83m, which functions as node VLOP, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 82m and conductive layer 83m corresponds to the capacitive element 35.

[0171] <2-2> Advantages (Effects) of 1m Semiconductor Memory Device According to the semiconductor memory device 1m, a modified version of the first embodiment described above, the read operation can be performed normally while reducing the number of tracks per sense amplifier unit SAU, similar to the semiconductor memory device 1.

[0172] Furthermore, the semiconductor memory device 1m allows for a further reduction in the circuit area of ​​the sense amplifier 17. The semiconductor memory device 1m also allows for a further reduction in the number of tracks per sense amplifier unit SAU. By reducing the number of tracks, the semiconductor memory device 1m can reduce the width of the sense amplifier unit SAU along the X-axis. By reducing the width of the sense amplifier unit SAU along the X-axis, the semiconductor memory device 1m can further reduce the circuit area of ​​the sense amplifier 17.

[0173] <3> Second Embodiment The following describes the semiconductor memory device 1 according to the second embodiment. The semiconductor memory device 1 according to the second embodiment differs from the semiconductor memory device 1 according to the first embodiment. Hereinafter, the semiconductor memory device 1 of the second embodiment may be referred to as semiconductor memory device 1b to distinguish it from the semiconductor memory device 1 of the first embodiment.

[0174] <3-1>Configuration (structure) <3-1-1> Circuit configuration of the sense amplifier unit SAU The semiconductor memory device 1b according to the second embodiment differs from the semiconductor memory device 1 according to the first embodiment mainly in the signal that clocks up the voltage of node SEN2. The clock input to node CLKSA is what clocks up the voltage of node SEN2 in the semiconductor memory device 1b. The other structures of the second embodiment are substantially the same as those of the first embodiment. The following will mainly describe the differences between the semiconductor memory device 1b according to the second embodiment and the first embodiment.

[0175] The differences from the first embodiment will be explained using Figures 13 to 15. Figure 13 is a circuit diagram of the sense amplifier unit SAU included in the semiconductor memory device 1b according to the second embodiment. Figure 13 shows the same region as in Figure 5 of the first embodiment.

[0176] As shown in Figure 13, the semiconductor memory device 1b in the second embodiment differs from the semiconductor memory device 1 in the first embodiment in that the other electrode of the capacitive element 35 is connected to node CLKSA. In other respects, Figure 13 is the same as Figure 5, so a detailed explanation is omitted.

[0177] In the semiconductor memory device 1b, one electrode of the capacitive element 35 is connected to node SEN2, and the other electrode of the capacitive element 35 is connected to node CLKSA. A clock is applied to node CLKSA. The clock is applied to clock up the voltage of node SEN2.

[0178] <3-2> Wiring Structure Figure 14 shows an example of the cross-sectional structure of a circuit region in the semiconductor memory device 1b according to the second embodiment. Figure 14 shows the same region as in Figure 8. In the semiconductor memory device 1b, the conductive layer that functions as node SEN2 and the conductive layer that functions as node CLKSA are arranged adjacent to each other.

[0179] As shown in Figure 14, the insulating layer 39 of the semiconductor memory device 1b further includes conductive layers 80b to 83b. Conductive layers 80b to 83b are located on wiring layer D0 or D1. Conductive layers 80b and 81b are located on the -X side of the contact CS1 and C1 to C3 pair. Conductive layer 80b and conductive layer 81b are adjacent along the X axis.

[0180] Conductive layers 82b and 83b are located on the +X side of contact CS1 and the combination of C1-C3. Conductive layer 82b and conductive layer 83b are adjacent to each other along the X axis.

[0181] Conductive layers 80b and 82b function as node SEN2. Conductive layers 81b and 83b function as node CLKSA.

[0182] When the conductive layer 80b, which functions as node SEN2, and the conductive layer 81b, which functions as node CLKSA, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 80b and conductive layer 81b corresponds to the capacitive element 35 (see Figure 13).

[0183] Similarly, when the conductive layer 82b, which functions as node SEN2, and the conductive layer 83b, which functions as node CLKSA, are placed next to each other, inter-wiring capacitance is generated between them. The inter-wiring capacitance between conductive layer 82b and conductive layer 83b corresponds to the capacitive element 35.

[0184] The relationship between node SEN1 and bus LBUS in semiconductor memory device 1b is the same as in semiconductor memory device 1, so the explanation is omitted.

[0185] <3-3> Read operation Figure 15 is a timing chart showing the voltages of various signals during the read operation of the semiconductor memory device 1b. As shown in Figure 15, the timing chart of the voltage at node CLKSA is the same as the timing chart of the voltage at node VLOP in the semiconductor memory device 1.

[0186] Specifically, at time t1, the sequencer 13 sets the voltage of node CLKSA to the "L" level (VSS).

[0187] At time t3, the sequencer 13 raises the voltage of node CLKSA from the "L" level (VSS) to the "H" level (VDDSA). As a result, the capacitive element 35 is charged, and the voltage of node SEN2 rises to voltage Vcu1 due to the effect of capacitive coupling.

[0188] At time t7, the sequencer 13 lowers the voltage of node CLKSA from the "H" level (VDDSA) to the "L" level (VSS). As a result, the voltage of node SEN2 decreases due to the effect of capacitive coupling. Specifically, as shown in Figure 14, the voltage of node SEN2 that was connected to the off-cell decreases to voltage Vcu3. Also, the voltage of node SEN2 that was connected to the on-cell decreases to voltage Vcu3'.

[0189] In the semiconductor memory device 1b, for example, a ground voltage VSS is applied to node VLOP. The other signals are the same as those in the timing chart of the first embodiment (see Figure 7), so their explanation is omitted.

[0190] <3-4> Advantages (Effects) of the Second Embodiment According to the semiconductor memory device 1b of the second embodiment described above, the circuit area of ​​the sense amplifier 17 can be reduced, similar to the semiconductor memory device 1.

[0191] In the semiconductor memory device 1 according to the first embodiment, an example was shown in which the voltage of node SEN2 was clock-upped using voltage VLOP. However, the voltage of node SEN2 is not limited to voltage VLOP. As in the semiconductor memory device 1b according to the second embodiment, the clock input to node CLKSA may be used to clock-up the voltage of node SEN2.

[0192] First, according to the semiconductor memory device 1b of the second embodiment, similar to the first embodiment, it is possible to reduce the number of tracks while also implementing measures against coupling between the bus LBUS and the node SEN1. That is, according to the semiconductor memory device 1b, similar to the semiconductor memory device 1, it is possible to reduce the number of tracks per sense amplifier unit SAU while performing read operations normally.

[0193] By reducing the number of tracks, the semiconductor memory device 1b can reduce the width of the sense amplifier unit SAU along the X-axis. By reducing the width of the sense amplifier unit SAU along the X-axis, the semiconductor memory device 1b can reduce the circuit area of ​​the sense amplifier 17.

[0194] <4> Modified form of the second embodiment In the semiconductor memory device 1 according to the first and second embodiments described above, an example was shown in which the voltage of node SEN1 is overclocked by bus LBUS. However, the voltage of node SEN1 is not limited to being overclocked by bus LBUS. For example, the voltage of node SEN1 may be overclocked by bus DBUS.

[0195] In this configuration, a conductive layer functioning as node SEN1 and a conductive layer functioning as bus DBUS are arranged adjacent to each other. In this case, inter-wiring capacitance occurs between the conductive layer functioning as node SEN1 and the conductive layer functioning as bus DBUS. This inter-wiring capacitance corresponds to the capacitive element 34 (see Figure 4 or Figure 13).

[0196] <5> Other variations, etc. In the first and second embodiments, the structures of the semiconductor memory devices 1 to 1b may be other structures. The structures shown in the modifications of the first and second embodiments may be applied to the first and second embodiments even if they are only a part of them or a combination of several of them.

[0197] The first and second embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. The first and second embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The first and second embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0198] 2…Memory controller, 3…Wiring, 10…Memory cell array, 11…Input / output circuit, 12…Register, 13…Sequencer, 14…Voltage generation circuit, 15…Driver, 16…Raw decoder, 17…Sense amplifier, 18…Data register, 20~33,36,Tr1,Tr2…Transistors, 34,35…Capacitor elements, 38…Semiconductor substrate, 39…Insulator layer, 40~46,50~56,60~64,70,80~83…Conductive layer, C1~C3,CS1~CS3…Contacts, GC1,GC2…Gate electrodes, BL0~BLm…Bit lines, MT0~MT7…Memory cell transistors, SAU…Sense amplifier unit, SGD0~SGD4…Selection gate lines, ST1,ST2…Selection transistors, SU0~SU4…String unit, WL0~WL7…Word lines

Claims

1. The first memory cell transistor, A first bit line electrically connected to the first memory cell transistor, A first sense amplifier electrically connected to the first bit line, A first latch circuit electrically connected to the first sense amplifier, Equipped with, The first sense amplifier is, A first node connected to the first bit line, A first transistor having one end electrically connected to the first latch circuit, A second node connected to the gate of the first transistor, A second transistor connected between the first node and the second node, A first conductor that functions as the first node, A second conductor is connected to the first latch circuit and is adjacent to the first conductor, functioning as a first wiring, It has, In the operation of transferring charge from the first bit line to the first node and the second node according to the data of the first memory cell transistor, the second transistor is in the ON state. In the operation of transferring data from the second node to the first latch circuit, the second transistor is in the off state. The second conductor has a first inter-wiring capacitance with respect to the first conductor. Semiconductor memory device.

2. The first sense amplifier is, A third conductor that functions as the second node, The present invention further comprises a fourth conductor connected to one end of the first transistor and adjacent to the third conductor, which functions as a second wiring, The fourth conductor has a second inter-wiring capacitance with respect to the third conductor. The semiconductor memory device according to claim 1.

3. The first sense amplifier is, A third conductor that functions as the second node, A fourth conductor connected to one end of the second transistor and functioning as a second wire, The present invention further comprises a fifth conductor adjacent to the third conductor and functioning as a third wiring for receiving a clock signal, The fifth conductor has a second inter-wiring capacitance with respect to the third conductor. The semiconductor memory device according to claim 1.

4. A first memory cell transistor, A first bit line electrically connected to the first memory cell transistor, A first sense amplifier electrically connected to the first bit line, A first latch circuit electrically connected to the first sense amplifier, Equipped with, The first sense amplifier is, A first node connected to the first bit line, A first transistor having one end electrically connected to the first latch circuit, A second node connected to the gate of the first transistor, A second transistor connected between the first node and the second node, A first capacitor, one end of which is connected to the first node and the other end of which is connected to the first wiring, A second capacitor, one end of which is connected to the second node and the other end of which is connected to the second wiring, It has, In the operation of transferring charge from the first bit line to the first node and the second node according to the data of the first memory cell transistor, the second transistor is in the ON state. In the operation of transferring data from the second node to the first latch circuit, the second transistor is in the off state. Semiconductor memory device.

5. The first sense amplifier is, The system further comprises a third transistor, one end of which is connected to the first node and the other end of which is connected to the first power supply. The semiconductor memory device according to claim 4.

6. A first memory cell transistor, A first bit line electrically connected to the first memory cell transistor, A first sense amplifier electrically connected to the first bit line, The first sense amplifier and the second sense amplifier adjacent in the first direction, A first latch circuit electrically connected to the first sense amplifier, Equipped with, The first sense amplifier is, A first node connected to the first bit line, A first transistor having one end electrically connected to the first latch circuit, A second node connected to the gate of the first transistor, A second transistor connected between the first node and the second node, The fourth transistor, It has, The second sense amplifier has a fifth transistor, The fourth transistor and the fifth transistor have a shared source-drain region, Semiconductor memory device.

7. The system further comprises a second sense amplifier adjacent to the first sense amplifier in a first direction, The first sense amplifier and the second sense amplifier, which are aligned in the first direction, Having seven wires aligned in the first direction, The semiconductor memory device according to claim 1.

8. At least one of the seven wires is electrically connected to the first latch circuit. The semiconductor memory device according to claim 7.

9. The width of the first sense amplifier in the first direction is This corresponds to 3.5 wires aligned in the first direction. The semiconductor memory device according to claim 1.

10. The system further comprises the first sense amplifier and a second sense amplifier adjacent to the first sense amplifier in the first direction. The width of the second sense amplifier in the first direction is This corresponds to 3.5 wires aligned in the first direction. The semiconductor memory device according to claim 9.

11. The system further comprises a second sense amplifier adjacent to the first sense amplifier in a first direction, The first sense amplifier and the second sense amplifier, which are aligned in the first direction, Having six wires aligned in the first direction, The semiconductor memory device according to claim 1.

12. The width of the first sense amplifier in the first direction is This corresponds to three wires aligned in the first direction, The semiconductor memory device according to claim 1.

13. The system further comprises the first sense amplifier and a second sense amplifier adjacent to the first sense amplifier in the first direction. The width of the second sense amplifier in the first direction is This corresponds to three wires aligned in the first direction, The semiconductor memory device according to claim 12.

14. The first sense amplifier and the second sense amplifier adjacent in the first direction, A second latch circuit electrically connected to the second sense amplifier, The second bit line electrically connected to the second sense amplifier, The system further comprises a second memory cell transistor electrically connected to the second bit line, The aforementioned second sense amplifier is A third node connected to the second bit line, A sixth transistor having one end electrically connected to the second latch circuit, The fourth node connected to the gate of the sixth transistor, It has a seventh transistor connected between the third node and the fourth node, In the operation of transferring charge from the second bit line to the third node and the fourth node according to the data of the second memory cell transistor, the seventh transistor is in the ON state. In the operation of transferring the data from the fourth node to the second latch circuit, the seventh transistor is in the off state. The semiconductor memory device according to claim 1.

15. A first memory cell transistor, A first bit line electrically connected to the first memory cell transistor, A first sense amplifier electrically connected to the first bit line, A first latch circuit electrically connected to the first sense amplifier, Equipped with, The first sense amplifier is, A first node connected to the first bit line, A first transistor having one end electrically connected to the first latch circuit, A second node connected to the gate of the first transistor, A second transistor connected between the first node and the second node, A first capacitor, one end of which is connected to the first node and the other end of which is connected to the first wiring, A second capacitor, one end of which is connected to the second node and the other end of which is connected to the third wiring, A third transistor, one end of which is connected to the first node and the other end of which is connected to the first power supply, It has, In the operation of transferring charge from the first bit line to the first node and the second node according to the data of the first memory cell transistor, the second transistor is in the ON state. In the operation of transferring data from the second node to the first latch circuit, the second transistor is in the off state. Semiconductor memory device.

16. The first memory cell transistor, A first bit line electrically connected to the first memory cell transistor, A first sense amplifier electrically connected to the first bit line, A first latch circuit electrically connected to the first sense amplifier, Equipped with, The first sense amplifier is, A first node connected to the first bit line and the first potential, A first transistor having one end electrically connected to the first latch circuit, A second node connected to the gate of the first transistor, A third node connected to the first node and the second potential, The second transistor connected to the third node, A fourth node connected to the second node and the third node, The gate has a third transistor connected to the fourth node, In the operation of transferring charge from the first bit line to the third node and the fourth node according to the data of the first memory cell transistor, the second transistor is in the ON state. In the operation of transferring data from the fourth node to the first latch circuit, the second transistor is in the off state. Semiconductor memory device.

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