Method for fabricating a composite structure including a thin layer made of single-crystal semiconductor on a carrier substrate.

Abstract

The present invention relates to a method for manufacturing a composite structure including a thin layer of a single crystal semiconductor, comprising the steps of: a) providing a donor substrate; b) implanting the donor substrate with ions of a light species, except in an annular peripheral region, to form a buried weakened surface, the implantation conditions defining a first thermal budget for blistering and a second thermal budget for splitting; c) forming a stiffening film on the donor substrate having a thickness of 0.5 microns or more, the stiffening film being performed by applying a thermal budget lower than the first thermal budget, the stiffening film leaving bare a number of regions of the front side, the regions having lateral dimensions of 50 microns or less; d) depositing a carrier substrate on the donor substrate, the thermal budget being higher than the first thermal budget; and e) cleaving to form the composite structure.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductors for microelectronic components. More specifically, the present invention relates to a method for manufacturing a composite structure comprising a thin layer made of a single-crystal semiconductor arranged on a carrier substrate, wherein the thin layer may be made of, for example, single-crystal silicon carbide, and the carrier substrate may be made of polycrystalline silicon carbide. [Background technology]

[0002] Silicon carbide (SiC) is increasingly being used to manufacture innovative power devices that meet the needs of growing electronics application areas, particularly electric vehicles.

[0003] Specifically, power devices and integrated power systems based on single-crystal silicon carbide can handle much higher power densities than conventional silicon equivalents, and can do so in a smaller active region. To further limit the dimensions of power devices on SiC, it is advantageous to manufacture vertical rather than horizontal components. To achieve this, the SiC structure must enable vertical electrical conduction between electrodes positioned on the front and back surfaces.

[0004] Nevertheless, single-crystal SiC substrates for the microelectronics industry remain expensive, and large-diameter manufacturing is difficult. Therefore, it is advantageous to use solutions for transferring thin layers to fabricate composite structures containing thin layers of single-crystal SiC on typically less expensive carrier substrates. One well-known solution for transferring thin layers is the Smart Cut™ method, based on light ion implantation and direct bonding. Such a method makes it possible to fabricate composite structures that enable perpendicular electrical conduction, for example, by directly contacting a carrier substrate made of polycrystalline SiC (p-SiC) and containing a thin layer of c-SiC exfoliated from a donor substrate made of single-crystal SiC (c-SiC). Nevertheless, achieving good quality direct bonding between two c-SiC and p-SiC substrates by molecular bonding remains challenging due to the complexity of dealing with the surface finish and roughness of the substrates.

[0005] U.S. Patent No. 8,436,363 avoids direct bonding by providing a method for manufacturing a composite structure including a thin layer made of c-SiC placed on a metal carrier substrate whose thermal expansion coefficient matches that of the thin layer. This manufacturing method involves the following steps: The steps include forming an embedded weak surface on a c-SiC donor substrate and defining a thin layer boundary between the embedded weak surface and the front surface of the donor substrate, To form a carrier substrate of sufficient thickness to serve as a reinforcing material, the steps include depositing a metal layer, for example, made of tungsten or molybdenum, on the front surface of the donor substrate, The steps include dividing along the aforementioned embedded weak surface to create a cleavage between a composite structure comprising a metal carrier substrate and a thin layer made of c-SiC on one side, and the remainder of the donor substrate made of c-SiC on the other side, Includes.

[0006] However, this manufacturing method is unsuitable when the material on which the carrier substrate is formed is p-SiC, which requires deposition at temperatures higher than 1000°C, and even above 1200°C (the normal temperature for p-SiC manufacturing). Specifically, at these high temperatures, the growth rate of cavities and microcracks present in the embedded brittle surfaces is faster than the growth rate of the p-SiC layer, and the thickness required to achieve the reinforcing effect is not reached before blistering, which is associated with the deformation of the thin layer perpendicular to the microcracks, begins.

[0007] As mentioned above with reference to composite structures made of silicon carbide, the underlying problem can occur in any type of semiconductor where thin layers are exfoliated using weakening techniques based on light seed injection, and the thermal budget that leads to blistering (blistering activation budget) is lower than the thermal budget required for carrier substrate deposition.

[0008] The thermal budgets for blistering and splitting have been extensively studied for many single-crystal semiconductors, including silicon, silicon carbide, germanium, and III-V compounds (see, for example, Aspar et al., "The generic nature of the Smart Cut® process for thin film transfer," Journal of Electronic Materials, vol. 30, no. 7, July 2001, or Bedell et al., "Investigation of surface blistering of hydrogen implanted crystals," Journal of Applied Physics, volume 90, no. 3, August 2001). The dynamics of blistering and splitting are known to depend on the properties of the embedded vulnerable surface, which are determined by the properties of the semiconductor and the ion implantation conditions applied to the donor substrate. In particular, the implantation energy of light species determines the depth of the embedded vulnerable surface, and the amount of implanted dose determines the amount of species that can form / grow microcavities and, when thermally activated, place the microcavities under pressure. Other implantation parameters, including temperature, also affect the properties of the embedded vulnerable surface, as well as the dynamics of blistering and splitting associated with it.

[0009] Blistering occurs when the free surface of the donor substrate lacks sufficient reinforcement, while splitting occurs when this free surface has sufficient reinforcement to embed microcracks and fuse them at the weak surface without deforming the upper layer, thus causing complete splitting along the embedded weak surface.

[0010] Due to these physical effects, defining a thin layer (typically less than 1.5 microns thick) on the donor substrate (through a fragile embedding surface resulting from the implantation of light species ions) and applying a thermal budget higher than the blistering thermal budget to form the carrier substrate by deposition appear to be incompatible. [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] The present invention addresses the above-mentioned problems. The present invention relates to a method for manufacturing a composite structure comprising a thin layer made of a single-crystal semiconductor placed on a low-quality carrier substrate, wherein the composite structure can further provide perpendicular electrical conductivity between the thin layer and the carrier substrate. [Means for solving the problem]

[0012] The present invention relates to a method for manufacturing a composite structure including a thin layer made of a single-crystal semiconductor, wherein the thin layer is arranged on a carrier substrate, and this method a) A step of preparing a donor substrate made of single-crystal semiconductor, b) A step of implanting light seed ions into the donor substrate under implantation conditions, excluding the annular peripheral region of the donor substrate, to form an embedded fragile surface, and defining a thin layer boundary between the embedded fragile surface and the front surface of the donor substrate, The embedded fragile surface contains lenticular microcavities that tend to develop into microcracks when thermally activated. The injection conditions specify a first thermal budget for obtaining blistering on the front surface of the donor substrate, and a second thermal budget for obtaining separation on the embedded vulnerable surface. Blistering corresponds to thin-layer deformation perpendicular to microcracks, while splitting corresponds to complete splitting in embedded weak surfaces. Steps and c) A step of forming a reinforcing film on a donor substrate, wherein this step is performed using a thermal budget lower than the first thermal budget, and the reinforcing film is formed It is perforated and takes the form of a grid with a coverage rate between 5% and 30% on the front surface, leaving multiple areas on the front exposed, and these areas have a lateral dimension of 50 microns or less. Having a thickness of 0.5 microns or more, Steps and d) A step of depositing a carrier substrate on the front surface of a donor substrate having a reinforcing film on its front surface, wherein this step is performed using a thermal budget higher than the first thermal budget. e) The step of cleaving to form a composite structure on one side and the remaining part of the donor substrate on the other side, Includes.

[0013] According to other advantageous and non-limiting features of the present invention, which can be applied individually or in any technically feasible combination, The annular peripheral region of the donor substrate, i.e., the region where ions are not implanted in step b), has a width between 1 mm and 2 cm. Step d) is performed by applying a thermal budget equal to or greater than the second thermal budget. The single-crystal semiconductor of the donor substrate is selected from silicon carbide, silicon, germanium, III-V or III-N compounds, diamond, and gallium oxide. The reinforcing film comprises a material selected from tungsten, silicon carbide, silicon, silicon nitride, boron nitride, silicon oxide, aluminum oxide, and aluminum nitride. Step c) includes one or more sequences of deposition, joining, photolithography, nanoimprint, etching, and / or thinning, The thickness of the perforated reinforcement film is between 0.5 microns and 5 microns. The carrier substrate has a single-crystal or polycrystalline structure and comprises at least one material selected from silicon carbide, silicon, diamond, III-V or III-N compounds such as gallium nitride, and gallium oxide. At the end of the deposition in step d), the carrier substrate has a thickness of 50 microns or more. The manufacturing method includes step f) of performing one or more mechanical and / or chemical and / or thermal treatments on the composite structure in order to smooth the free surface of the thin layer and / or to improve the quality of the edges of the composite structure and / or to correct the thickness uniformity of the composite structure. One (or more) of the mechanical or chemical treatments (if any) in step f) is performed before the splitting step e) in order to improve the quality of the edges of the stack obtained from step d) and / or to correct the thickness uniformity of the carrier substrate. The manufacturing method includes a step of readjusting the remainder of the donor substrate for the purpose of reusing it as a donor substrate.

[0014] The present invention also relates to a composite structure obtained from the above manufacturing method, comprising power components formed on and / or within a thin layer in whole or in part, and having a metal electrode on the back surface of the carrier substrate.

Brief Description of the Drawings

[0015] Further features and advantages of the present invention will become apparent upon reading the following detailed description of the present invention with reference to the accompanying drawings. [Figure 1] It is a diagram showing a composite structure generated using the manufacturing method according to the present invention. [Figure 2a] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2a-1] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2b] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2c] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2d] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2e] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 2f] It is a diagram showing the steps of the manufacturing method according to the present invention. [Figure 3]This figure shows an Arrhenius plot of blistering time versus temperature for a donor substrate made of SiC implanted with a dose of 6 × 10¹⁶ H / cm² and an energy of 150 keV. This substrate is used as an example in the following description.

[0016] In the diagram, elements of the same type may be designated by the same reference numeral. The diagram is a schematic representation and is not to scale for clarity. In particular, the thickness of layers along the z-axis is not to scale with respect to the lateral dimensions along the x and y axes, and the relative thickness of layers relative to each other is not necessarily considered in the diagram. [Modes for carrying out the invention]

[0017] The present invention relates to a method for manufacturing a composite structure 1, that is, a structure as shown in Figure 1, which includes a thin layer 10 made of a single-crystal semiconductor placed on a carrier substrate 200.

[0018] The method first includes step a) preparing a donor substrate 111 made of a single-crystal semiconductor on which a thin layer 10 is intended to be formed. This single-crystal semiconductor may be selected from silicon carbide, silicon, germanium, III-V or III-N compounds, diamond, gallium oxide (Ga2O3), or other materials for which thin layer exfoliation is advantageous.

[0019] The donor substrate 111 preferably takes the form of a circular wafer with a diameter of 100 mm, 150 mm, 200 mm, or actually 300 mm, or even 450 mm, and a thickness typically between 300 and 800 microns. This donor substrate has a front surface 111a and a back surface 111b (Figure 2a). The surface roughness of the front surface 111a is advantageously selected such that the Ra (mean roughness) measured by atomic force microscopy (AFM) with a 20 micron × 20 micron scan is less than 1 nm.

[0020] Next, in this method, the thin layer 10 of the composite structure is peeled off from the donor substrate 111. Therefore, the donor substrate 111 must have the mechanical, electrical, and crystallographic properties necessary for the intended application.

[0021] According to one particular embodiment, the donor substrate 111 comprises an initial substrate 11 made of a single-crystal semiconductor and a donor layer 110 also formed from this material and produced by epitaxial growth on the initial substrate 11 (Figure 2a-1). The epitaxial growth step is carried out such that the donor layer 110 has a crystal defect density lower than that of the initial substrate 11. In this case, the thin layer 10 is peeled off from the donor layer 110. Therefore, the quality of the initial substrate 11 does not need to be as high as that of the donor layer 110.

[0022] As an example of this particular embodiment, the initial substrate 11 is made of 4H or 6H polytype single crystal SiC (c-SiC), with an offcut angle of 4.0° ± 0.5° or less with respect to the <11-20> crystal axis, and 5 / cm 2 The following, or even 1 / cm 2 It has a density of less than 1 / 30 Ω·cm of through-dislocations (micropipes). In the case of N-doping (nitrogen doping), the initial substrate preferably has a resistivity that falls between 0.015 Ω·cm and 0.030 Ω·cm. Typically 3000 / cm 2 An initial substrate 11 having the following low density of basal plane dislocation defects (BPDs) may be selected, such as 1500 / cm². 2 c-SiC substrates with a certain BPD density are readily available, which simplifies the preparation of initial substrates.

[0023] If defects within the thin layer 10 expand, it could affect the performance and reliability of the component. Therefore, the c-SiC donor layer 110 should be 1 / cm 2The following BPD densities are produced. For this purpose, epitaxial growth of the donor layer 110 is carried out at temperatures higher than 1200°C, preferably between 1500°C and 1900°C. The precursors used are silane (SiH4), propane (C3H8), or ethylene (C2H4), and the carrier gas is sometimes hydrogen, optionally mixed with argon. The low density of BPDs in the donor layer 110 is obtained by promoting the conversion of BPDs present in the initial substrate 11 to through-edge dislocations (TEDs).

[0024] Returning to the general description of the manufacturing method according to the present invention, the method includes step b) implanting light seed ions into a donor substrate 111 to a predetermined depth representing a desired thickness of the thin layer 10. Note that if a donor layer 110 is present, this depth is always less than the thickness of the donor layer. This implantation creates an embedded brittle surface 12, which defines the boundary of the thin layer 10 between the embedded brittle surface 12 and the free surface 111a of the donor substrate 111 (Figure 2b).

[0025] Ion implantation is performed to form an embedded vulnerable surface 12 in the central region 12a of the donor substrate 111, but not in the annular peripheral region 12b. For this reason, during the ion implantation step, a mask is applied to the front surface 111a facing the annular peripheral region 12b, for example, to prevent ions from penetrating this peripheral region 12b of the substrate 111.

[0026] The annular peripheral region 12b preferably has a width between 1 mm and 2 cm. In other words, the embedded weak surface 12 is not present in the annular peripheral region 12b that extends from the edge of the donor substrate 111 toward the center of the substrate 111 over a distance between 1 mm and 2 cm. The importance of this annular peripheral region 12b, in which the donor substrate 11 does not contain the embedded weak surface 12, will be discussed later.

[0027] The light species to be implanted are preferably hydrogen, helium, or both of these species co-implanted. Referring to the Smart Cut™ process, as is well known, the light species form microcavities distributed in a thin layer parallel to the front face 111a of the donor substrate 111, i.e., parallel to the (x,y) plane in the figure, in the vicinity of a determined depth. This thin layer is, for the sake of simplicity, called the buried weakness plane 12.

[0028] The implantation energy of the light species is selected such that the light species reach a determined depth in the donor substrate 111 with certainty. Typically, hydrogen ions are in the energy range between 10 keV and 250 keV and are implanted with a dose between 5 E 16 / cm 2 ~1 E 17 / cm 2 and define the boundary of the thin layer 10 having a thickness between 100 and 1500 nm, which of course depends on the semiconductor properties of the donor substrate 111.

[0029] Note that prior to the ion implantation step, in some cases, a thin protective layer may be deposited on the front face 111a of the donor substrate 111. This protective layer may be made of a material such as silicon oxide or silicon nitride, for example, and may be removed at the end of step b) in some cases.

[0030] As described above, the embedded weak surface 12 contains lenticular microcavities that tend to develop into microcracks when thermally activated. In a selected single-crystal semiconductor of the donor substrate 111, the injection conditions define a first thermal budget for obtaining blistering on the front surface 111a of the donor substrate 111. This first thermal budget can be achieved by applying various temperatures over various annealing times that induce blistering (blistering activation budget). The injection conditions also define a second thermal budget for obtaining splitting at the embedded weak surface 12. This second thermal budget can be achieved by applying various temperatures over various annealing times that spontaneously induce splitting (splitting activation budget). It will be recalled that if the front surface 111a is not reinforced, blistering corresponds to deformation of the thin layer 10 perpendicular to the microcracks, and if the front surface 111a is reinforced, splitting corresponds to complete splitting at the embedded weak surface 12.

[0031] As recalled in the introduction, the dynamics of blistering and splitting have been extensively studied in many single-crystal semiconductors under various ion implantation conditions. Therefore, finding or determining information regarding the thermal budget for blistering and the thermal budget for splitting for a particular type of single-crystal semiconductor and specific ion implantation conditions is within the capabilities of those skilled in the art.

[0032] Next, the manufacturing method includes step c) forming a reinforcing film 20 on the front surface 111a of the donor substrate 111 (Figure 2c). This step is performed using a thermal budget lower than the first thermal budget. The objective here is to keep the thermal budget below the level that would otherwise cause deformation of the thin layer 10 due to blistering or partial delamination of the thin layer 10 as a result of microcrack growth in the embedded weak surface 12.

[0033] In addition, the reinforcing film 20 is perforated and takes the form of a grid with a coverage of 30% or less, preferably between 5% and 30%, in the plane of the front surface 111a. Due to its grid form, the perforated reinforcing film 20 defines a plurality of exposed areas (perforated areas of the reinforcing film 20) on the front surface 111a that form features 20' with a lateral dimension of 50 microns or less. The lateral dimension is the dimension of the feature in the (x,y) plane of the front surface 111a of the donor substrate 111. At least one dimension of the feature 20' may be 20 microns or less, 10 microns or less, or even 5 microns or less, or even 2 microns or less. The feature 20' can have the shape of a square, rectangle, triangle, circle, or other polygon. The width of the grid lines in the (x,y) plane, i.e., the width of the lines separating the features 20' defined by the reinforcing film 20, may be between 5 microns and 50 microns.

[0034] Furthermore, the reinforcing film 20 has a thickness of 0.5 microns or more, typically a thickness between 0.5 microns and 50 microns, preferably a thickness between 0.5 microns and 5 microns.

[0035] The role of the perforated reinforcing film 20 is to maintain the mechanical integrity of the thin layer 10 in step d) in which the subsequent carrier substrate 200 is deposited, which requires a thermal budget higher than the first thermal budget for blistering, or even higher than the second thermal budget for splitting.

[0036] Another advantage of the perforated reinforcing film 20 is that it allows for the formation of direct contact between the thin layer 10 and the carrier substrate 200 over an area larger than 70% of the area of ​​the thin layer 10. This is particularly advantageous with respect to perpendicular electrical conductivity in the future composite structure 1, as the deposition of the carrier substrate 200 at high temperatures is highly favorable for obtaining a good interface with the thin layer 10. For part of it, the perforated reinforcing film 20 does not need to ensure electrical conductivity between the thin layer 10 and the carrier substrate 200. Therefore, the reinforcing film can include a wide variety of materials selected from tungsten, silicon carbide, silicon, silicon nitride, boron nitride, silicon oxide, aluminum oxide, aluminum nitride, etc. The crystal quality of the perforated reinforcing film 20 and the quality of the interface with the working layer 10 are not important, and for this reason, it is possible to form the reinforcing film 20 with a low thermal budget. Nevertheless, care is taken to select a material for the reinforcing film 20 that is suitable for the temperature applied in the following steps of the method (in particular, step d) below, and typically a material is selected whose melting point is higher than the temperature at which the step is performed.

[0037] To form the film 20, step c) includes a sequence of one or more of any other techniques that enable the production of a perforated film in the form of deposition, bonding, photolithography, nanoimprinting, etching and / or thinning, or grid. For example, the perforated reinforced film 20 can be produced by depositing a continuous film, then performing lithography to define a grid, and finally etching the features 20' to create exposed areas on the front surface 111a of the donor substrate 111.

[0038] For example, an energy of 150 keV and 6 × 10⁻⁶ 16 H+ / cm 2In the case of a donor substrate 111 made of c-SiC implanted with a dose of hydrogen ions (and, if present, a donor layer 110 made of c-SiC), the embedded weak surface 12 is located at a depth of approximately 800 nm, except for a 5 mm wide annular peripheral region 12b, and the temperature in step c) is selected to be less than 800°C, or even less than 500°C. In this temperature range, blistering takes a long time to occur (see Figure 3), and for example, a reinforcing film 20 made of 2 μm thick polycrystalline silicon carbide can be formed in about 2 hours by thermal CVD at approximately 700°C. The black circles in Figure 3 represent this thermal budget, which, as can be seen, is much lower than the thermal budget for blistering.

[0039] Subsequently, conventional photolithography and etching steps can be used to complete a perforated reinforcement film 20 made of polycrystalline SiC, which defines a square feature 20' with a side length of 25 microns and a grid with a line width of 4 microns. The coverage of the grid is approximately 25%.

[0040] Next, the manufacturing method according to the present invention includes step d) depositing a carrier substrate 200 on the front surface 111a of a donor substrate 111, on which a perforated reinforcing film 20 is provided (Figure 2d). The deposition in step d) is carried out using a thermal budget higher than the first thermal budget (i.e., the thermal budget for blistering), or a thermal budget greater than or equal to the second thermal budget (for splitting).

[0041] In step d), the preferred high temperature improves the structural quality of the carrier substrate 200 and the quality of the interface with the thin layer 10. Deposition can be carried out using any known technique, in particular thermochemical vapor deposition (TCVD), plasma-excited chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0042] At the end of the deposition in step d), the stack 211 is formed, and the carrier substrate 200 will have a thickness of 50 microns or more, or even 200 microns or more, or even more than 300 microns.

[0043] As described above, the high thermal budget applied in step d) ensures that the perforated reinforcing film 20 mechanically reinforces the thin layer 10, thereby limiting blistering and preventing localized delamination of the thin layer 10, thus preventing irreparable damage to the thin layer 10.

[0044] Depending on the target composite structure 1, the carrier substrate 200 may have a single-crystal or polycrystalline structure and may contain at least one material selected from III-V or III-N compounds such as silicon carbide, silicon, diamond, gallium nitride, and gallium oxide.

[0045] The deposition in step d) is accompanied by a thermal budget higher than the first thermal budget for blistering, or a thermal budget greater than or equal to the second thermal budget for splitting, and the reinforcing film 20 limits the expansion of microcracks that form blisters and prevents the appearance of localized delamination of the thin layer 10, so that in step d), the microcracks fuse with each other and propagate through the embedded weak surface 12.

[0046] Because the annular peripheral region 12b is eliminated, the fact that the embedded fragile surface 12 does not extend to the edge of the donor substrate 111 prevents fragmentation propagating through the embedded fragile surface 12 from causing premature cleavage between the composite structure 1 (thin layer 10, reinforcing film 20, and carrier substrate 200) and the remainder 111' of the donor substrate. Specifically, if the thickness of the carrier substrate 200 is too small, the composite structure 1 is too thin overall to stand on its own and is prone to fragmentation and breakage. Since fragmentation along the embedded fragile surface 12 occurs rapidly with a high thermal budget, the annular peripheral region 12b allows the stack 211 to remain bonded until the carrier substrate 200, which is typically 50 microns or more, achieves the desired thickness.

[0047] Returning to the previous example of the donor substrate 111 made of c-SiC and the reinforcing film 20 made of p-SiC, the carrier substrate 200 made of p-SiC may be formed on the front surface 111a of the donor substrate 111, and the perforated reinforcing film 20 is provided on this surface. For this purpose, the p-SiC is deposited by thermal CVD at a temperature between 900°C and 1500°C, for example, at 1000°C for 4 hours to achieve a thickness of 400 microns. The black triangle in Figure 3 represents this thermal budget, which, as can be seen, is much higher than the first thermal budget (blistering activation budget).

[0048] Splitting along the embedded vulnerable surface 12 occurs less than one hour after the start of deposition. The thermal budget for deposition in step d) is also higher here than the splitting thermal budget. Nevertheless, stack 211 is completely maintained because of the presence of a peripheral annular region 12b without the embedded vulnerable surface 12.

[0049] Finally, the manufacturing method according to the present invention includes step e) cleaving the stack 211 to form a composite structure 1 on one side and the remaining portion 111' of the donor substrate on the other side (Figure 2e).

[0050] This cleavage can be achieved mechanically or chemically. For example, by applying mechanical stress to the edge of the stack 211 through the insertion of a tool (e.g., a blade or bevel), a crack can be induced in the annular peripheral region 12b, thereby cleaving the stack 211. Alternatively, the cleavage of step e) can also be obtained by applying chemical etching of the edge of the donor substrate 111 (of the annular peripheral region 12b) alone or in combination with mechanical stress.

[0051] Although not shown in Figure 2e, the cleavage step may generate thickness non-uniformity in the annular peripheral region 12b, substantially increasing the roughness of the thin layer 10 because the thin layer 10 is not necessarily transferred integrally in the peripheral region 12b. These defects may be addressed in subsequent steps f) of the method.

[0052] The manufacturing method according to the present invention may include step f) one or more mechanical and / or chemical and / or thermal treatments performed on the composite structure 1 in order to smooth the free surface of the thin layer 10 and / or to improve the quality of the edges of the composite structure 1 (the edges of the thin layer 10 or the edges of the carrier substrate 200) and / or to correct the uniformity of the thickness of the composite structure 1.

[0053] As is known, at the end of cleavage step e), the free surface 10a of the thin layer 10 of the composite structure 1 has a surface roughness of 5-100 nm RMS (measured with an atomic force microscope (AFM) using a 20 micron × 20 micron scan) at least in its central region 12a.

[0054] Next, step f) may include chemical mechanical polishing (CMP) of the free surface 10a of the thin layer 10, typically involving the removal of material of about 50 nm to 1000 nm, to obtain a final roughness of less than 0.5 nm RMS or even less than 0.3 nm (in a 20 × 20 μm AFM field). Step f) may also include chemical or plasma treatment (cleaning or etching), such as SC1 / SC2 cleaning (SC1 is an acronym for standard cleaning 1, SC2 is an acronym for standard cleaning 2) and / or HF cleaning (HF is an acronym for hydrofluoric acid), or treatment in N2, Ar, CF4 plasma, etc., to further improve the quality of the free surface 10a of the thin layer 10.

[0055] Furthermore, chemical mechanical polishing (CMP) and / or chemical treatment (etching or cleaning) and / or mechanical treatment (grinding) can be applied to the back surface 200b of the carrier substrate 200. Such treatments can improve the thickness uniformity of the carrier substrate 200 and the roughness of its back surface 200b. For the manufacture of vertical components in which at least one metal electrode is present on the back surface 200b of the composite substrate 1, a roughness of less than 0.5 nm RMS (measured in a 20 micron x 20 micron field using an atomic force microscope (AFM)) is desirable.

[0056] It should be noted that these treatments applied to the back surface 200b of the carrier substrate 200 may optionally be applied immediately before the cleavage step, step e), i.e., before the front surface 10a of the composite structure 1 is exposed, in order to limit contamination, particularly during contamination- or stress-inducing treatments such as chemical etching or mechanical lapping (or mechanical grinding).

[0057] The edges of the composite structure 1 may also be polished or ground in step f) if necessary, with the aim of conforming their circular contour and bevel shape to the requirements of the microelectronics manufacturing method.

[0058] Again, according to one advantageous embodiment, step f) may include a high-temperature heat treatment for about one hour to several hours (at a temperature included between 1000°C and 1900°C, depending on the material properties of the composite structure 1). The purpose of this step is to stabilize the composite structure 1 by repairing any structural or surface defects still present in and / or on the thin layer 10, and, where appropriate, by altering the crystal structure of the carrier substrate 200, thereby adapting the structure 1 to subsequent high-temperature heat treatments necessary for manufacturing components on the thin layer 10, i.e., epitaxial growth, dopant activation annealing, deposition, etc.

[0059] The method according to the present invention may include an additional step of epitaxially growing an additional layer on the thin layer 10 of the composite structure 1. Such a step is applied when a relatively large working layer thickness, i.e., typically about 5 to 50 microns, is required for the manufacture of the part. The conditions for this epitaxial growth may optionally be selected to be similar to those of step a), but preferably the temperature is kept lower to limit the stress induced in the working layer (corresponding to the assembly composed of the thin layer 10 and the additional layer) as a result of the potentially non-uniform material of the composite structure 1.

[0060] Finally, the manufacturing method may include a step of readjusting the remainder of the donor substrate 111' for the purpose of reusing the remainder of the donor substrate as the initial substrate 11 or donor substrate 111. Such a readjustment step is based on treating the surface 110'a (Figure 2e) once or more times by chemical mechanical polishing of its surface or edges, and / or by mechanical grinding, and / or by dry or wet chemical etching. The thickness of the donor layer 110 is preferably defined such that, when formed in step a), the remainder of the donor substrate 111' can be reused as donor substrate 111 at least twice.

[0061] The present invention also relates to a composite structure 1 obtained by the manufacturing method described above. The composite structure 1 is particularly suitable for power applications. A composite structure comprising a thin layer 10 made of high-crystallinity c-SiC, a reinforcing film 20 made of p-SiC, and a carrier substrate made of p-SiC, i.e., the structure described above as an example, is very preferable for the manufacture of vertical power components.

[0062] Therefore, the composite structure 1 may include one (or more) vertical power components, such as transistors, diodes, or any high-voltage and / or high-frequency components manufactured using one of the many manufacturing techniques known in the art. The composite structure 1 according to the present invention is fully compatible with the aforementioned art.

[0063] In the case of vertical power components, all or part of the component is formed on and / or within the thin layer 10, and metal electrodes are generated on the back surface 200b of the carrier substrate 200. Direct contact between the thin layer 10 and the carrier substrate 200, present in the perforated region 20' of the reinforcing film 20, ensures good vertical electrical conductivity and effective thermal conductivity. Conductivity is guaranteed regardless of the material of the film 20, thereby increasing the choice of material, with only mechanical rigidity being a requirement.

[0064] Furthermore, the lateral dimensions of the power components in question are approximately 1 square millimeter, which is significantly larger than the size of the features 20' and grid lines defined by the perforated reinforcing film 20. Therefore, it should be noted that there is always a vertical electrical contact between the thin layer 10 and the carrier substrate 200, perpendicular to each manufactured component. The shape and dimensions of the grid are, in some cases, adjusted to match the design and distribution of the components intended to be manufactured on the composite structure 1.

[0065] Other types of composite structures 1, besides the SiC-based structure given as an example, can of course be manufactured using the manufacturing method according to the present invention, using combinations of other materials. A non-limiting example is the following stack of thin single crystal layer (10) / perforated reinforcing film (20) / carrier substrate (200).

[0066] GaN / Si / Diamond GaN / W / SiC SiC / SiO2 / Diamond Si / SiO2 / Diamond Si / SiO2 / SiC Diamond / Si / Diamond.

[0067] Of course, the present invention is not limited to the embodiments and examples described, and modified embodiments can be carried out without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a composite structure (1) including a thin layer (10) made of a single crystal semiconductor, wherein the thin layer is placed on a carrier substrate (200), and the method is a) A step of preparing a donor substrate (111) made of the single crystal semiconductor, b) The step of implanting light seed ions into the donor substrate (111) under implantation conditions, excluding the annular peripheral region of the substrate (111), to form an embedded fragile surface (12), and defining the boundary of the thin layer (10) between the embedded fragile surface (12) and the front surface (111a) of the donor substrate (111), The embedded fragile surface (12) includes a lens-shaped microcavity that tends to develop into microcracks when thermally activated. The injection conditions define a first thermal budget for obtaining blistering on the front surface (111a) of the donor substrate (111), and a second thermal budget for obtaining division on the embedded vulnerable surface (12). The blistering corresponds to the deformation of the thin layer (10) perpendicular to the microcrack, and the splitting corresponds to the complete splitting of the embedded weak surface (12). Steps and c) A step of forming a reinforcing film (20) on the donor substrate (111), wherein this step is performed using a thermal budget lower than the first thermal budget, and the reinforcing film (20) is formed The surface of the front (111a) is perforated and has a grid shape with a coverage rate between 5% and 30%, leaving multiple areas of the front (111a) exposed, and these areas have a lateral dimension of 50 microns or less. Having a thickness of 0.5 microns or more, Steps and d) A step of depositing a carrier substrate (200) on the front surface (111a) of the donor substrate (111) on which the reinforcing film (20) is provided, wherein this step is performed using a thermal budget higher than the first thermal budget, e) The step of cleaving to form the composite structure (1) on one side and the remaining part (111') of the donor substrate on the other side, Methods that include...

2. The manufacturing method according to claim 1, wherein the annular peripheral region (12b) of the donor substrate (111), i.e., the region in step b) where ions are not implanted, has a width that includes between 1 mm and 2 cm.

3. The manufacturing method according to claim 1 or 2, wherein step d) is performed by applying a thermal budget equal to or greater than the second thermal budget.

4. The manufacturing method according to any one of claims 1 to 3, wherein the single-crystal semiconductor of the donor substrate (111) is selected from silicon carbide, silicon, germanium, III-V or III-N compounds, diamond, and gallium oxide.

5. The manufacturing method according to any one of claims 1 to 4, wherein the reinforcing film (20) comprises a material selected from tungsten, silicon carbide, silicon, silicon nitride, boron nitride, silicon oxide, aluminum oxide, and aluminum nitride.

6. The manufacturing method according to any one of claims 1 to 5, wherein step c) comprises one or more sequences of deposition, bonding, photolithography, nanoimprinting, etching, and / or thinning.

7. The manufacturing method according to any one of claims 1 to 6, wherein the thickness of the reinforcing film (20) is between 0.5 microns and 5 microns.

8. The manufacturing method according to any one of claims 1 to 7, wherein the carrier substrate (200) has a single crystal or polycrystalline structure and comprises at least one material selected from silicon carbide, silicon, diamond, gallium nitride, and III-V or III-N compounds, and gallium oxide.

9. The manufacturing method according to any one of claims 1 to 8, wherein at the end of the deposition in step d), the carrier substrate (200) has a thickness of 50 microns or more.

10. A manufacturing method according to any one of claims 1 to 9, comprising step f) performing one or more mechanical and / or chemical and / or thermal treatments on the composite structure (1) in order to smooth the free surface of the thin layer (10) and / or to improve the quality of the edges of the composite structure (1) and / or to correct the thickness uniformity of the composite structure (1).

11. A manufacturing method according to any one of claims 1 to 10, comprising the step of readjusting the remaining portion (111') of the donor substrate for the purpose of reusing the remaining portion of the donor substrate as a donor substrate.

12. A composite structure (1) obtained by a manufacturing method according to any one of claims 1 to 11, comprising power components which are all or part formed on and / or within the thin layer (10), and a metal electrode on the back surface of the carrier substrate (200).

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