Decoding system and physical layout for analog neural memory in deep learning artificial neural networks

Abstract

To provide a word line decoder, a control gate decoder, a bit line decoder, a low voltage row decoder, and a high voltage row decoder and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system.SOLUTION: Combined word line and control gate decoder 4100 comprises: a PMOS transistor 4102; an NMOS transistor 4103; row address signals 4104; vertical input word lines 4105; a horizontal word output line 4106 which is coupled to word lines of VMM arrays; an inverter 4107; switches 4108 and 4112; and an isolation transistor 4109, and receives a control gate input 4110 CGIN0 and outputs a control gate line 4111 CG0. The word line output 4106 WL0 and control gate output 4111 CG0 are selected or de-selected at the same times by decoding logic that controls a NAND gate 4101.SELECTED DRAWING: Figure 41

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Provisional Application No. 62 / 840,318, titled "DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK," filed on 29 April 2019, and U.S. Patent Application No. 16 / 503,355, also titled "DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK," filed on 3 July 2019.

[0002] (Field of invention) An improved decoding system and physical layout for an analog neural memory system utilizing non-volatile memory cells are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain) and are used to estimate or approximate functions that may depend on numerous inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages.

[0004] Figure 1 shows an artificial neural network, in which the circles represent input or layers of neurons. The connections (referred to as synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This enables the neural network to adapt to the input and become learnable. Typically, a neural network includes multiple input layers. Typically, there is one or more intermediate layers of neurons and an output layer of neurons that provides the output of the neural network. At each level, the neurons make decisions individually or jointly based on the data received from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of appropriate hardware technologies. In practice, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons, that is, a very high degree of parallelization of computational processing. In principle, such complexity can be realized by digital supercomputers or dedicated GPU (Graphics Processing Unit) clusters. However, in addition to high costs, these approaches are also troubled by poor energy efficiency compared to biological networks that mainly perform low-precision analog calculations and consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS implementation synapses have been too bulky assuming the required large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memories. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and then generate a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including a source region and a drain region separated within a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above a first portion of the channel region and insulated from the first portion of the channel region, and a non-floating gate disposed above a second portion of the channel region and insulated from the second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells is configured to multiply the stored weight values by the first plurality of inputs to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and accurate amount of charge, i.e., the number of electrons, on the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] One challenge in a vector matrix multiplication (VMM) system is the ability to select a particular cell or group of cells, or in some cases the entire array of cells, for erase, programming, and read operations. A related challenge is to improve the use of physical space within a semiconductor die without losing functionality.

[0009] What is needed is an improved decoding system and physical layout for analog neural memory systems that utilize non-volatile memory cells. [Overview of the project]

[0010] An improved decoding system and physical layout for an analog neural memory system utilizing non-volatile memory cells are disclosed.

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[0061] [Figure 1] This is a diagram showing an example of an artificial neural network using prior art technology. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This shows another prior art split-gate flash memory cell. [Figure 7] This shows a stacked gate flash memory cell of prior art. [Figure 8] This figure shows various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 9] Block diagram of the vector-matrix multiplication system. [Figure 10] This block diagram shows an exemplary artificial neural network that utilizes one or more vector-matrix multiplication systems. [Figure 11] Another embodiment of the vector-matrix multiplication system is shown. [Figure 12] Another embodiment of the vector-matrix multiplication system is shown. [Figure 13] Another embodiment of the vector-matrix multiplication system is shown. [Figure 14] Another embodiment of the vector-matrix multiplication system is shown. [Figure 15] Another embodiment of the vector-matrix multiplication system is shown. [Figure 16] This demonstrates prior art long- and short-term memory systems. [Figure 17] This shows an exemplary cell used in long-term and short-term memory systems. [Figure 18] Figure 17 shows one embodiment of an exemplary cell. [Figure 19] Another embodiment of the exemplary cell shown in Figure 17 is presented. [Figure 20] This shows a prior art gated regression unit system. [Figure 21] An exemplary cell used in a gated regression unit system is shown. [Figure 22] Figure 21 shows one embodiment of an exemplary cell. [Figure 23] Another embodiment of the exemplary cell shown in Figure 21 is presented. [Figure 24] Another embodiment of the vector-matrix multiplication system is shown. [Figure 25] Another embodiment of the vector-matrix multiplication system is shown. [Figure 26] Another embodiment of the vector-matrix multiplication system is shown. [Figure 27] Another embodiment of the vector-matrix multiplication system is shown. [Figure 28] Another embodiment of the vector-matrix multiplication system is shown. [Figure 29] Another embodiment of the vector-matrix multiplication system is shown. [Figure 30] Another embodiment of the vector-matrix multiplication system is shown. [Figure 31] Another embodiment of the vector-matrix multiplication system is shown. [Figure 32] Another embodiment of the vector-matrix multiplication system is shown. [Figure 33] An illustrative block diagram of a vector-matrix multiplication system is shown. [Figure 34] This shows an exemplary decoding embodiment of a vector matrix multiplication system. [Figure 35] Another exemplary decoding embodiment of a vector-matrix multiplication system is shown. [Figure 36] An exemplary row decoder is shown. [Figure 37] Another exemplary decoding embodiment of a vector-matrix multiplication system is shown. [Figure 38] Another exemplary decoding embodiment of a vector-matrix multiplication system is shown. [Figure 39] Another exemplary decoding embodiment of a vector-matrix multiplication system is shown. [Figure 40] One embodiment of a low-voltage row decoder is shown. [Figure 41] One embodiment of a combined low-voltage row decoder and control gate decoder is shown. [Figure 42] This shows one embodiment of a bit line decoder. [Figure 43] The vector-matrix multiplication system and input block are shown. [Figure 44] This shows a multiplexer that receives output from an array and provides input to one or more arrays in a multiplexed format. [Figure 45A] This shows an exemplary layout of a vector-matrix multiplication system. [Figure 45B] This shows an exemplary layout of a vector-matrix multiplication system. [Figure 46] This shows an exemplary layout of a vector-matrix multiplication system. [Figure 47] This document shows word-line decoder circuits, source-line decoder circuits, and high-voltage level shifters for use with vector multiplier matrices. [Figure 48] This document shows an erase gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high-voltage level shifter for use with a vector multiplier matrix. [Figure 49] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 50] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 51] Another exemplary decoding embodiment of a vector-matrix multiplication system is shown. [Modes for carrying out the invention]

[0062] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. Non-volatile memory cell

[0063] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("Patent No. 130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed above a first portion of the channel region 18, insulated from the first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18), and extends above a portion of the source region 14. The word line terminal 22 (typically coupled to the word line) has a first portion located above the second portion of the channel region 18 and insulated from the second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18), and a second portion extending upward over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line terminal 24 is coupled to the drain region 16.

[0064] By applying a high-voltage positive voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim tunnel.

[0065] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are applied to the floating gate). The electron current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0066] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is detected as the erased state, or the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is almost or completely turned off, and no (or very little) current flows through the channel region 18, which is detected as the programmed state, or the "0" state.

[0067] Table 1 shows typical voltage ranges that can be applied to the terminals of the memory cell 110 for performing read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 2 [Table 1] "Readout 1" is a readout mode where the cell current is the output of the bit line. "Readout 2" is a readout mode where the cell current is the output of the source line terminal.

[0068] Figure 3 shows a memory cell 310 similar to the memory cell 210 in Figure 2, with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased with a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0V / -8V) during erasing, and a low or medium voltage (e.g., 0V / 2.5V) during reading. The other terminals are biased in the same way as the terminals in Figure 2.

[0069] Figure 4 shows a four-gate memory cell 410, comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0070] Table 2 shows typical voltage ranges that can be applied to the terminals of the memory cell 310 for read, erase, and program operations. Table 2: Operation of flash memory cell 410 in Figure 4 [Table 2] "Readout 1" is a readout mode where the cell current is the output of the bit line. "Readout 2" is a readout mode where the cell current is the output of the source line terminal.

[0071] Figure 5 shows a memory cell 510 similar to the memory cell 410 in Figure 4, except that the memory cell 510 does not include an erase gate (EG) terminal. Erasure is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low voltage or a negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage. Programming and reading are the same as in Figure 4.

[0072] Figure 6 shows a different type of flash memory cell, a 3-gate memory cell 610. Memory cell 610 is identical to memory cell 410 in Figure 4, except that memory cell 610 does not have a separate control gate terminal. The erase and read operations (erasure occurs through the use of the erase gate terminal) are the same as those in Figure 4, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line terminal to compensate for the lack of control gate bias.

[0073] Table 3 shows typical voltage ranges that can be applied to the terminals of the memory cell 610 for performing read, erase, and program operations. Table 3: Operation of the flash memory cell 610 in Figure 6 [Table 3] "Readout 1" is a readout mode where the cell current is the output of the bit line. "Readout 2" is a readout mode where the cell current is the output of the source line terminal.

[0074] Figure 7 shows a different type of flash memory cell, a stacked gate memory cell 710. The memory cell 710 is similar to the memory cell 210 in Figure 2, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (coupled to the word line) is separated by an insulating layer (not shown) and extends over the floating gate 20. Erase, programming, and read operations are performed in the same manner as described above for the memory cell 210.

[0075] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 710 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 710 in Figure 7 [Table 4]

[0076] "Read 1" is a read mode in which the cell current is the output of the bit line. "Read 2" is a read mode in which the cell current is the output of the source line terminal. Optionally, in an array containing rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, the source line terminal can be shared by adjacent rows of memory cells.

[0077] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0078] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disruption to other memory cells, from a completely erased state to a completely programmed state. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disruption to other memory cells, from a completely programmed state to a completely erased state, and vice versa. This means that cell storage is analog, or at least one of a number of discontinuous values ​​(such as 16 or 64 different values) can be stored, making every cell in the memory array highly precise and individually tunable, and the memory array ideal for storage, allowing for fine-tuning of the synaptic weights of a neural network.

[0079] The methods and means described herein can be applied without limitation to other non-volatile memory technologies such as SONOS (silicon oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase-change memory), MRAM (magnetoresistive random-access memory), FeRAM (ferroelectric memory), OTP (bilevel or multilevel one-time programmable), and CeRAM (strongly correlated electron memory). The methods and means described herein can also be applied without limitation to volatile memory technologies used in neural networks such as SRAM, DRAM, and volatile synaptic cells. Neural networks using non-volatile memory cell arrays

[0080] Figure 8 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array in this embodiment. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0081] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1, going from input layer S0 to layer C1, scans the input image with an overlapping 3x3 pixel filter (kernel), applying different sets of weights to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one pixel of the layer in feature map C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different sets of weights to generate different feature maps of layer C1 until all feature maps of C1 have been computed.

[0082] In this example, layer C1 contains 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared across all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0083] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function is to average neighboring positions (or use the max function), reduce dependence on edge positions, and reduce data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2, moving from layer S1 to layer C2, scans the maps in S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification of the content of the original image.

[0084] Each layer of a synapse operates using an array or part of an array of non-volatile memory cells.

[0085] Figure 9 is a block diagram of a system usable for that purpose. The vector matrix multiplication (VMM) system 32 includes non-volatile memory cells, which are used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM system 32 includes a VMM array 33 containing non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Inputs to the VMM array 33 can be made from the erase gate and word line gate decoders 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0086] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, the VMM array 33 effectively multiplies the input by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to produce an output, which becomes the input to the next layer or the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient due to on-the-spot memory calculations.

[0087] The output of the VMM array 33 is fed to a differential adder (such as an adding operational amplifier or an adding current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of both positive and negative weight inputs and output a single value.

[0088] The summed output values ​​of the differential adder 38 are then fed to an activation function circuit 39, which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other nonlinear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in Figure 8), which are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (receiving input from the previous layer of neurons or from an input layer such as an image database), and the adder 38 and activation function circuit 39 constitute multiple neurons.

[0089] The inputs to the VMM system 32 in Figure 9 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0090] Figure 10 is a block diagram showing the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in Figure 10, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be voltage or current. The input D / A conversion of the first layer can be performed by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. Input conversion can also be performed by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s)(one or more) to the input VMM system 32a.

[0091] The output generated by input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which then generates an output provided as input to the next VMM system (hidden level 2) 32c, and so on. The various layers of VMM system 32 function as the synaptic and neuron layers of a convolutional neural network (CNN). VMM systems 32a, 32b, 32c, 32d, and 32e can each be a standalone physical non-volatile memory array, or multiple VMM systems can utilize different parts of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-multiplexed with respect to different parts of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. VMM Array

[0092] Figure 11 shows a neuron VMM array 1100, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0093] In the VMM array 1100, control gate lines such as control gate line 1103 extend in the vertical direction (therefore, the reference array 1102 in the row direction is orthogonal to the control gate line 1103), and erase gate lines such as erase gate line 1104 extend in the horizontal direction. Here, the input to the VMM array 1100 is provided to the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 1100 appears on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0 and SL1 respectively) performs a summation function of all currents from the memory cells connected to that particular source line.

[0094] As described herein for the neural network, the non-volatile memory cells of the VMM array 1100, i.e., the flash memory of the VMM array 1100, are preferably configured to operate in the subthreshold region.

[0095] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion as follows: Ids = Io * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt Where w = e (-Vth) / nVt is. Where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the Kelvin temperature, q is the electron charge, n is the slope factor = 1+(Cdep / Cox), Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, and Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n - 1) * Vt 2It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0096] When using an IV logarithmic converter that converts the input current Ids to the input voltage Vg using a memory cell (such as a reference memory cell or peripheral memory cell) or a transistor: Vg=n * Vt * log[Ids / wp * Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0097] For a memory array used as a vector matrix multiplier VMM array, the output current is as follows: Iout=wa * Io * e (Vg) / nVt That is to say Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt In the formula, wa = w for each memory cell in the memory array.

[0098] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0099] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in the linear region. Ids=β * (Vgs-Vth) * Vds;β=u * Cox * Wt / L Wα(Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0100] Word lines, control gate lines, bit lines, or source lines can be used as inputs to memory cells operating within the linear region. Bit lines or source lines can be used as outputs to memory cells.

[0101] For IV linear converters, a memory cell (such as a reference memory cell or peripheral memory cell), a transistor, or a resistor operating in the linear domain can be used to linearly convert input / output current to input / output voltage.

[0102] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 * β * (Vgs-Vth) 2 ;β=u * Cox * Wt / L Wα(Vgs-Vth) 2 That is, the weight W is (Vgs - Vth) 2 proportional to

[0103] Word lines, control gates, or erase gates can be used as inputs to memory cells operating within a saturation region. Bit lines or source lines can be used as outputs to output neurons.

[0104] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturated).

[0105] Other embodiments for the VMM array 32 shown in Figure 9 are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. As described in the above application, source lines or bit lines can be used as neuron outputs (current sum outputs).

[0106] Figure 12 shows a neuron VMM array 1200 particularly suited to the memory cell 210 shown in Figure 2, which is used as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. The reference arrays 1201 and 1202, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0107] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory cell array 1203, then adds all the results (memory cell currents) to produce the outputs of each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By having the memory array 1203 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and the outputs appear on bit lines BL0~BLN respectively during read (inference) operations. The current distributed across each bit line BL0 to BLN acts as a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0108] Table 5 shows the operating voltages of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells, with FLT indicating floating, i.e., no voltage applied. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1200 in Figure 12 [Table 5]

[0109] Figure 13 shows a neuron VMM array 1300, particularly suitable for the memory cell 210 shown in Figure 2, and used as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1300 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current applied to each source line performs a function of the sum of all currents from the memory cells connected to that particular source line.

[0110] Table 6 shows the operating voltages of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in Figure 13 [Table 6]

[0111] Figure 14 shows a neuron VMM array 1400, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexer 1412 includes a separate multiplexer 1405 and a cascoding transistor 1404 to ensure a constant voltage across the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are adjusted to a target reference level.

[0112] The memory array 1403 serves two purposes. First, it stores the weights used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1401 and 1402 and supplied to the control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory cell array, and then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current applied to each bit line is a function of the sum of all currents from the memory cells connected to that particular bit line.

[0113] The VMM array 1400 performs unidirectional adjustment of non-volatile memory cells within the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until a desired charge is reached on its floating gate. This can be done, for example, using the precision programming techniques described below. If too much charge is applied to the floating gate (e.g., an incorrect value is stored in the cell), the cell must be erased and the series of partial programming operations must be repeated. As shown, two rows sharing the same erase gate (e.g., EG0 or EG1) must be erased together (known as page erase), and then each cell is partially programmed until a desired charge is reached on its floating gate.

[0114] Table 7 shows the operating voltages of the VMM array 1400. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in Figure 14 [Table 7]

[0115] Figure 15 shows a neuron VMM array 1500, particularly suitable for the memory cell 310 shown in Figure 3, and used as part of synapses and neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 or a first non-volatile reference memory cell, and a reference array 1502 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3, as well as the SL lines WL0, WL1, WL2, and WL3, extend horizontally. The VMM array 1500 is similar to the VMM array 1400 except that the VMM array 1500 performs bidirectional adjustment, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on a floating gate by using individual EG lines. As shown, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1514), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0116] Table 8 shows the operating voltages of the VMM array 1500. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in Figure 15 [Table 8]

[0117] Figure 24 shows a neuron VMM array 2400, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2400, inputs INPUT0, ..., INPUT N These are bit lines BL0, ..., BL N Each signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0118] Figure 25 shows a neuron VMM array 2500, particularly suitable for the memory cell 210 shown in Figure 2, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3 respectively, and outputs OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0119] Figure 26 shows a neuron VMM array 2600 particularly suitable for the memory cell 210 shown in Figure 2, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0120] Figure 27 shows a neuron VMM array 2700, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL NIt is generated by [this method].

[0121] Figure 28 shows a neuron VMM array 2800 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n These are the vertical control gate lines CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0122] Figure 29 shows a neuron VMM array 2900, particularly suitable for the memory cell 410 shown in Figure 4, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N These are bit lines BL0, ..., BL N The signals are received by the gates of the bit line control gates 2901-1, 2901-2, ..., 2901-(N-1), and 2901-N, which are connected to each of the above. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0123] Figure 30 shows a neuron VMM array 3000 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Received to, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N They are generated in each respective location.

[0124] Figure 31 shows a neuron VMM array 3100 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL N Each is generated, and each source line SL i It is coupled to the source lines of all memory cells in column i.

[0125] Figure 32 shows a neuron VMM array 3200 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received by OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL N Each bit line BL is generated in its respective place. i It is coupled to the bit lines of all memory cells in column i. Long-term and short-term memory

[0126] Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0127] Figure 16 shows an exemplary LSTM1600. In this example, the LSTM1600 includes cells 1601, 1602, 1603, and 1604. Cell 1601 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1602 receives the input vector x1, the output vector (hidden state) h0 from cell 1601, and the cell state c0 from cell 1601, and generates the output vector h1 and the cell state vector c1. Cell 1603 receives the input vector x2, the output vector (hidden state) h1 from cell 1602, and the cell state c1 from cell 1602, and generates the output vector h2 and the cell state vector c2. Cell 1604 receives the input vector x3, the output vector (hidden state) h2 from cell 1603, and the cell state c2 from cell 1603, and generates the output vector h3. Additional cells can also be used, and an LSTM with four cells is just one example.

[0128] Figure 17 shows an exemplary implementation of LSTM cell 1700 that can be used for cells 1601, 1602, 1603, and 1604 in Figure 16. LSTM cell 1700 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates a cell state vector c(t) and an output vector h(t).

[0129] LSTM cell 1700 includes sigmoid function devices 1701, 1702, and 1703, each controlling the degree to which each component of the input vector contributes to the output vector by applying a number between 0 and 1. LSTM cell 1700 also includes tanh devices 1704 and 1705 for applying a hyperbolic tangent function to the input vector, multiplier devices 1706, 1707, and 1708 for multiplying two vectors, and an adder device 1709 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0130] Figure 18 shows an LSTM cell 1800, which is an example implementation of LSTM cell 1700. For the reader's convenience, the same numbering method used in LSTM cell 1700 is used in LSTM cell 1800. Sigmoid function devices 1701, 1702, and 1703, and tanh device 1704 each contain multiple VMM arrays 1801 and activation circuit block 1802. Thus, it can be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1706, 1707, and 1708, and adder device 1709 are implemented in a digital or analog manner. Activation function block 1802 can be implemented in a digital or analog manner.

[0131] Figure 19 shows an alternative example of LSTM cell 1800 (and another example of an implementation of LSTM cell 1700). In Figure 19, sigmoid function devices 1701, 1702, and 1703, and tanh device 1704 share the same physical hardware (VMM array 1901 and activation function block 1902) in a time-division multiplexed manner. LSTM cell 1900 also includes a multiplier device 1903 for multiplying two vectors, an adder device 1908 for adding two vectors, a tanh device 1705 (including the activation circuit block 1902), a register 1907 for storing the value i(t) output from the sigmoid function block 1902, and a multiplexer 1910 for storing the value f(t) output from the multiplier device 1903. * Register 1904 stores c(t-1), and the value i(t) is output from the multiplier device 1903 via the multiplexer 1910. * The register 1905 stores u(t), and the value o(t) is output from the multiplier device 1903 via the multiplexer 1910. * It includes register 1906 for storing c~(t) and multiplexer 1909.

[0132] While an LSTM cell 1800 contains multiple sets of VMM arrays 1801 and their respective activation function blocks 1802, an LSTM cell 1900 contains only one set of VMM arrays 1901 and activation function blocks 1902 used to represent multiple layers in an embodiment of the LSTM cell 1900. Compared to the LSTM cell 1800, the LSTM cell 1900 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than the LSTM cell 1800.

[0133] It is further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Gated regression unit

[0134] Analog VMM implementations can be used in gated recurrent unit (GRU) systems. A GRU is a gate mechanism within an iterative neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0135] Figure 20 shows an exemplary GRU2000. In this example, the GRU2000 includes cells 2001, 2002, 2003, and 2004. Cell 2001 receives input vector x0 and produces output vector h0. Cell 2002 receives input vector x1 and output vector h0 from cell 2001 and produces output vector h1. Cell 2003 receives input vector x2 and output vector (hidden state) h1 from cell 2002 and produces output vector h2. Cell 2004 receives input vector x3 and output vector (hidden state) h2 from cell 2003 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0136] Figure 21 shows an exemplary implementation of a GRU cell 2100 usable in cells 2001, 2002, 2003, and 2004 of Figure 20. The GRU cell 2100 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 2100 includes sigmoid function devices 2101 and 2102, each applying a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 2100 also includes a tanh device 2103 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 2104, 2105, and 2106 for multiplying two vectors, an adder device 2107 for adding two vectors, and a complementary device 2108 that subtracts the input from 1 to produce an output.

[0137] Figure 22 shows GRU cell 2200, an example implementation of GRU cell 2100. For the reader's convenience, the same numbering method used in GRU cell 2100 is used in GRU cell 2200. As can be seen from Figure 22, the sigmoid function devices 2101 and 2102, and the tanh device 2103, each contain multiple VMM arrays 2201 and activation function blocks 2202. Thus, it can be understood that VMM arrays are used specifically in GRU cells used in certain neural network systems. The multiplier devices 2104, 2105, 2106, the adder device 2107, and the complementary device 2108 are implemented in a digital or analog manner. The activation function block 2202 can be implemented in a digital or analog manner.

[0138] Figure 23 shows an alternative example of the GRU cell 2200 (and another example of an implementation of the GRU cell 2300). In Figure 23, the GRU cell 2300 uses the VMM array 2301 and the activation function block 2302, which, when configured as a sigmoid function, controls the degree to which each component of the input vector contributes to the output vector by applying a number between 0 and 1. In Figure 23, the sigmoid function devices 2101 and 2102, and the tanh device 2103, share the same physical hardware (VMM array 2301 and activation function block 2302) in a time-division multiplexed manner. The GRU cell 2300 also includes a multiplier device 2303 for multiplying two vectors, an adder device 2305 for adding two vectors, a complementary device 2309 for subtracting an input from 1 to produce an output, a multiplexer 2304, and a value h(t-1) output from the multiplier device 2303 via the multiplexer 2304. * The register 2306 holds r(t), and the value h(t-1) is output from the multiplier device 2303 via the multiplexer 2304. * The register 2307 holds the value z(t), and the value h^(t) is output from the multiplier device 2303 via the multiplexer 2304. * This includes register 2308, which holds (1-z((t)).

[0139] While a GRU cell 2200 contains multiple sets of VMM arrays 2201 and activation function blocks 2202, a GRU cell 2300 contains only one set of VMM arrays 2301 and activation function blocks 2302, which are used to represent multiple layers in embodiments of the GRU cell 2300. Compared to the GRU cell 2200, the GRU cell 2300 requires less space because it requires only one-third the space for the VMM and activation function blocks.

[0140] It is further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient.

[0141] The input to the VMM array may be analog level, binary level, or digital bits (in which case a DAC is required to convert the digital bits to an appropriate input analog level), and the output may be analog level, binary level, or digital bits (in which case an output ADC is required to convert the output analog level to a digital bit).

[0142] For each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells. Decoding System and Physical Layout Embodiments for VMM Arrays

[0143] Figures 33 to 51 disclose various decoding systems and physical layouts for VMM arrays that can be used with any of the memory cell types described above with respect to Figures 2 to 7, or with respect to other nonvolatile memory cells.

[0144] Figure 33 shows the VMM system 3300. The VMM system 3300 comprises a VMM array 3301 (which can be based on any of the aforementioned VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM designs), a low-voltage row decoder 3302, a high-voltage row decoder 3303, a column decoder 3304, a column driver 3305, control logic 3306, a bias circuit 3307, a neuron output circuit block 3308, an input VMM circuit block 3309, an algorithm controller 3310, a high-voltage generator block 3311, an analog circuit block 3315, and control logic 3316.

[0145] The input circuit block 3309 functions as an interface from the external input to the input terminals of the memory array 3301. The input circuit block 3309 may, without limitation, include a DAC (digital-to-analog converter), DPC (digital-to-pulse converter), APC (analog-to-pulse converter), IVC (current-to-voltage converter), AAC (analog-to-analog converter such as a voltage-to-voltage scaler), or FAC (frequency-to-analog converter). The neuron output block 3308 functions as an interface from the memory array output to an external interface (not shown). The neuron output block 3308 may, without limitation, include an ADC (analog-to-digital converter), APC (analog-to-pulse converter), DPC (digital-to-pulse converter), IVC (current-to-voltage converter), or IFC (current-to-frequency converter). The neuron output block 3308 may, without limitation, include an activation function, a normalization circuit, and / or a rescaling circuit.

[0146] The low-voltage row decoder 3302 provides a bias voltage for read and program operations and provides a decode signal to the high-voltage row decoder 3303. The high-voltage row decoder 3303 provides a high-voltage bias signal for program and erase operations.

[0147] The algorithm controller 3310 provides functions for controlling bit lines during program operation, verification operation, and erase operation.

[0148] The high-voltage generator block 3311 includes a charge pump 3312, a charge pump regulator 3313, and a high-voltage generation circuit 3314 that provide multiple voltages required for various program operations, erase operations, program verification operations, and read operations.

[0149] Figure 34 shows a VMM system 3400 that is particularly suitable for use with memory cells of the type shown in Figure 4 as memory cells 410. VMM system 3400 is VMM array 3401, 3402, 340 3 , and 3404 (VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000 and 310 respectively) 0、 The array comprises low-voltage row decoders 3405, 3406, 3407, and 3408, a shared high-voltage row decoder 3409, word lines or word input lines 3411, 3412, 3413, and 3414, bit lines 3421, 3422, 3423, and 3424, a control gate line 3432, a source line 3434, and an erase gate line 3434. The shared high-voltage row decoder 3409 provides the control gate line 3432, the source line 3434, and the erase gate line 3434. In this configuration, the word lines 3411, 3412, 3413, and 3414, and the bit lines 3421, 3422, 3423, and 3424 are parallel to each other. In one embodiment, the word lines and bit lines are arranged vertically. line 3434 and the erase gate line 3436 are parallel to each other and arranged horizontally, and therefore perpendicular to the word lines or word input lines 3411, 3412, 3413, and 3414, as well as the bit lines 3421, 3422, 3423, and 3424.

[0150] In the VMM system 3400, VMM arrays 3401, 3402, 3403, and 3404 have a control gate line 3432, source line 3 434, erase gate line 3436, and high-voltage row decoder 3409 are shared. However, each array has its own low-voltage row decoder, such that low-voltage row decoder 3405 is used with VMM array 3401, low-voltage row decoder 3406 is used with VMM array 3402, low-voltage row decoder 3407 is used with VMM array 3403, and low-voltage row decoder 3408 is used with VMM array 3404. An advantage of this configuration is that word lines 3411, 3412, 3413, and 3414 are arranged vertically such that word line 3411 can be routed only to VMM array 3401, word line 3412 can be routed only to VMM array 3402, word line 3413 can be routed only to VMM array 3403, and word line 3414 can be routed only to VMM array 3404. This would be extremely inefficient in conventional layouts where word lines are arranged horizontally, given that multiple VMM arrays share the same high-voltage decoder and the same high-voltage decoding lines.

[0151] Figure 35 shows a VMM system 3500 that is particularly suitable for use with a memory cell of the type shown in Figure 4 as the memory cell 410. The VMM system 3500 is similar to the VMM system 3300 in Figure 33, except that the VMM system 3500 includes separate word line and low-voltage line decoders for read and programming operations.

[0152] The VMM system 3500 includes VMM arrays 3501, 3502, 3503, and 3504 (each based on one of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), and a low-voltage read row decoder. The system comprises decoders 3505, 3506, 3507, and 3508, a shared low-voltage program line decoder 3530, a shared high-voltage line decoder 3509, read word lines or word input lines 3511, 3512, 3513, and 3514, a program pre-decode line 3515, bit lines 3521, 3522, 3523, and 3524, a control gate line 3532, a source line 3533, and an erase gate line 3535. The shared high-voltage line decoder 3509 provides the control gate line 3532, the source line 3533, and the erase gate line 3535. In this layout, the read word lines or word input lines 3511, 3512, 3513, and 3514, the program pre-decode line 3515, and the bit lines 3521, 3522, 3523, and 3524 are parallel to each other and arranged perpendicularly. The control gate line 3532, source line 3533, and erase gate line 3535 are parallel to each other and arranged horizontally, and therefore perpendicular to the read word lines or word input lines 3511, 3512, 3513, and 3514, the program pre-decode line line 3515, and the bit lines 3521, 3522, 3523, and 3524. In this VMM system 3500, the low-voltage program line decoder 3530 is shared across multiple VMM arrays.

[0153] In the VMM system 3500, VMM arrays 3501, 3502, 3503, and 3504 share a control gate line 3532, a source line 3533, an erase gate line 3535, and a high-voltage row decoder 3509. However, each VMM array has its own low-voltage read row decoder, such that the low-voltage read row decoder 3505 is used with VMM array 3501, the low-voltage read row decoder 3506 is used with VMM array 3502, the low-voltage read row decoder 3507 is used with VMM array 3503, and the low-voltage read row decoder 3508 is used with VMM array 3504. An advantage of this layout is that the read word lines or word input lines 3511, 3512, 3513, and 3514 are arranged vertically so that word line 3511 can be routed only to VMM array 3501, word line 3512 can be routed only to VMM array 3502, word line 3513 can be routed only to VMM array 3503, and word line 3514 can be routed only to VMM array 3504. This would be very inefficient in a conventional layout where the word lines are arranged horizontally for multiple arrays sharing the same high-voltage decoder and the same high-voltage decode line. In particular, the program pre-decode line 3515 can be connected to any of the VMM arrays 3501, 3502, 3503, and 3504 via the low-voltage program line decoder 3530, and as a result, one or more cells of those VMM arrays can be programmed at once.

[0154] Figure 36 shows further details of a particular embodiment of the VMM system 3500, in particular details of the low-voltage row decoders 3505, 3506, 3507, and 3508, exemplified as the low-voltage row decoder 3600. The low-voltage read row decoder 3600 comprises several switches, such as exemplary switches shown for selectively coupling row and word lines of each cell of the VMM arrays 3601, 3602, 3603, and 3604. The low-voltage program decoder 3630 includes exemplary NAND gates 3631 and 3632, PMOS transistors 3633 and 3635, and NMOS transistors 3636 and 3636, configured as shown. The NAND gates 3631 and 3632 accept the program pre-decode row line XP3615 as input. During program operation, the low-voltage read row decoders 3605, 360 6 ,360 7 The switch Sp (which may be a CMOS multiplexer or another type of switch) in 3608 is closed, and therefore the program word lines Wlp0-n are coupled to the word lines in the array to apply a voltage for programming. During read operations, the read word lines or word input lines 3611, 3612, 3613, and 3614 are selectively coupled to the word line terminals of rows in one or more arrays 3601, 3602, 3603, and 3604 using the Sr switch (closed) (which may be a CMOS multiplexer or another type of switch) in the low-voltage read row decoders 3605, 3606, 3607, and 3608 to apply a voltage.

[0155] Figure 37 shows a VMM system 3700 particularly suitable for use with memory cells of the type shown in Figure 4 as memory cells 410. The VMM system 3700 is based on VMM arrays 3701, 3702, 3702, and 3704 (each based on any of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, and 3100, or other VMM array designs), and a low-voltage row decoder. The shared global high-voltage line decoder 3730 comprises 3705, 3706, 3707, and 3708, local high-voltage line decoders 3709 and 3710, global high-voltage line decoder 3730, word lines 3711, 3712, 3713, and 3714, bit lines 3721, 3722, 3723, and 3724, high-voltage and / or low-voltage (HV / LV) pre-decode line 3732, source line 3733, and erase gate line 3734. The shared global high-voltage line decoder 3730 comprises HV / LV pre-decode line 3732, source line 3 Provides line 733 and erase gate line 3734. In this layout, word lines 3711, 3712, 3713, and 3714, and bit lines 3721, 3722, 3723, and 3724 are parallel to each other and arranged perpendicularly. HV / LV predecode line 3732, source line 3The 733 and erase gate lines 3734 are parallel to each other and arranged horizontally, and therefore perpendicular to the word lines 3711, 3712, 3713, and 3714, as well as the bit lines 3721, 3722, 3723, and 3724. The HV / LV pre-decode line 3732 is input to local high-voltage decoders 3709 and 3710. Local high-voltage decoder 3709 outputs local control gate lines for VMM arrays 3701 and 3702. Local high-voltage decoder 3710 outputs local control gate lines for VMM arrays 3703 and 3704. In another embodiment, local high-voltage decoders 3709 and 3710 can provide local source lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively. In another embodiment, local high-voltage decoders 3709 and 3710 can provide local erase gate lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively.

[0156] Here, the local high-voltage row decoder 3709 is shared by VMM arrays 3701 and 3702, and the local high-voltage row decoder 3710 is shared by VMM arrays 3703 and 3704. The global high-voltage decoder 3730 routes the high-voltage and low-voltage pre-decode signals to local high-voltage row decoders such as the local high-voltage row decoders 3709 and 3710. Thus, the high-voltage decoding function is divided between the global high-voltage row decoder 3730 and the local high-voltage decoders such as the local high-voltage decoders 3709 and 3710.

[0157] In the VMM system 3700, VMM arrays 3701, 3702, 3703, and 3704 share an HV / LV pre-decode line 3732, a source line 3733, an erase gate line 3734, and a global high-voltage row decoder 3730. However, each VMM array has its own low-voltage row decoder, such that the low-voltage row decoder 3705 is used with VMM array 3701, the low-voltage row decoder 3706 is used with VMM array 3702, the low-voltage row decoder 3707 is used with VMM array 3703, and the low-voltage row decoder 3708 is used with VMM array 3704. An advantage of this layout is that word lines 3711, 3712, 3713, and 3714 are arranged vertically, so that word line 3711 can be routed only to VMM array 3701, word line 3712 can be routed only to VMM array 3702, word line 3713 can be routed only to VMM array 3703, and word line 3714 can be routed only to VMM array 3704. This would be extremely inefficient in a conventional layout where word lines are arranged horizontally for multiple arrays sharing a single high-voltage decoder.

[0158] Figure 38 shows a VMM system 3800 that is particularly suitable for use with memory cells of the type shown in Figure 4 as memory cells 410. VMM system 3800 is a VMM array 3801, 3802, 380 33804 (each based on one of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), low-voltage row decoders 3805, 3806, 3807, and 3808, local high-voltage row decoders 3809 and 3810, global high-voltage row decoder 3830, bit lines 3821, 3822, 3823, and 3824, control gate lines or control gate input lines 3811 and 3812, HV / LV pre-decode line 3833, source line 3834, and erase gate line 3835. Shared global high voltage line decoder 3830, HV / LV pre-decode line 3833, source line 3 834 and erase gate line 3835 are provided. Local high-voltage decoders 3809 and 3810 connect control gate inputs CG3811 and 3812 to the local control gates of VMM arrays 3801, 3802 and 3803 and 3804, respectively. Low-voltage row decoders 3805, 3806, 3807 and 3808 provide local (horizontal) word lines to arrays 3801, 3802, 3803 and 3804, respectively. In this layout, the control gate lines 3811 and 3812, as well as the bit lines 3821, 3822, 3823 and 3824, are parallel to each other and arranged vertically. Source line 3834 and erase gate line 3835 are parallel to each other, arranged horizontally, and therefore perpendicular to control gate lines 3811 and 3812 and bit lines 3821, 3822, 3823, and 3824.

[0159] Similar to the VMM system 3700 in Figure 37, the local high-voltage row decoder 3809 is shared by VMM arrays 3801 and 3802, and the local high-voltage row decoder 3810 is shared by VMM arrays 3803 and 3804. The global high-voltage decoder 3830 routes signals to local high-voltage row decoders such as the local high-voltage row decoders 3809 and 3810. Therefore, the high-voltage decoding function is shared between the global high-voltage row decoder 3830 and the local high-voltage decoders such as the local high-voltage decoders 3809 and 3810 (local source influence It is divided between (and / or can provide a local erase gate line).

[0160] In VMM system 3800, VMM arrays 3801, 3802, 3803, and 3804 are HV / LV pre-decode line 3833, source line 3 834, erase gate line 3835, and global high-voltage row decoder 3830 are shared. However, each VMM array has its own low-voltage row decoder, such that low-voltage row decoder 3805 is used with VMM array 3801, low-voltage row decoder 3806 is used with VMM array 3802, low-voltage row decoder 3807 is used with VMM array 3803, and low-voltage row decoder 3808 is used with VMM array 3804. An advantage of this layout is that the control gate lines 3811 and 3812, which may be read lines or input lines, are arranged vertically such that control gate line 3811 can be routed only to VMM arrays 3801 and 3802, and control gate line 3812 can be routed only to VMM arrays 3803 and 3804. This would not be possible in a conventional layout where word lines are arranged horizontally.

[0161] Figure 39 shows a VMM system 3900 that is particularly suitable for use with memory cells of the types shown in Figure 3 as memory cell 310, Figure 4 as memory cell 410, Figure 5 as memory cell 510, or Figure 7 as memory cell 710. The VMM system 3900 comprises VMM arrays 3901 and 3902 (each based on one of the aforementioned VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), a low-voltage row decoder 3903 (used with arrays 3901 and 3902), a local high-voltage row decoder 3905, a global high-voltage row decoder 3904, control gate lines 3908 and 3909, and bit lines 3906 and 3907. In this layout, control gate line 3908 is used only by VMM array 3901, and control gate line 3909 is used only by VMM array 3902. The low-voltage row decode line 3910 is used as the decode input to the global high-voltage row decoder 3904. The global high-voltage row decode line 3911 is used as the decode input to the local high-voltage decoder 3905.

[0162] The local high-voltage row decoder 3905 is shared by VMM arrays 3901 and 3902. The global high-voltage decoder 3904 routes signals to local high-voltage row decoders in multiple VMM systems, such as the local high-voltage row decoder 3905 of VMM system 3900. Thus, the high-voltage decoding function is divided between the global high-voltage row decoder 3904 and local high-voltage decoders such as the local high-voltage decoder 3905, as described above.

[0163] In the VMM system 3900, VMM arrays 3901 and 3902 share word lines (not shown), source gate lines (not shown) if present, erase gate lines (not shown) if present, and a global high-voltage row decoder 3904. Here, VMM arrays 3901 and 3902 share a low-voltage row decoder 3903. The advantage of this layout is that VMM arrays 3901 and 3902 do not share control gate lines, allowing each array to be accessed independently using control gate lines 3908 and 3909, respectively.

[0164] Figure 51 shows a VMM system 5100 particularly suitable for use with memory cells of the type shown in Figure 4 as memory cells 410. The VMM system 5100 comprises VMM arrays 5101, 5102, 5103, and 5104 (each of which may be based on any of the aforementioned VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1510, 2400, 2510, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), a high-voltage decoder 5130, routing blocks 5151 and 5152, input word lines 5111 and 5112, bit lines 5121, 5122, 5123, and 5124, control gate line 5132, source line 5133, and erase gate line 5134. The high-voltage decoder 5130 provides a control gate line 5132, a source line 5133, and an erase gate line 5134. Routing blocks 5151 and 5152 are locations where vertically received input word lines 5111 and 5112 are routed to horizontally extending word lines of VMM arrays 5101 to 5104, respectively. Alternatively, routing blocks 5151 and 5152 may route a vertically received control gate input line 5132 to a horizontally extending control gate line 5132 of the VMM array.

[0165] Figure 40 shows a low-voltage row decoder 4000 including a NAND gate 4001, a PMOS transistor 4002, and an NMOS transistor 4003. The NAND gate 4001 receives a row address signal 4004. The PMOS transistor 4002 is coupled to a vertical word line input 4005. The output is a horizontal word line 4006, which is one of many word lines coupled to each VMM array. In this example, there are a total of 16 word lines, and therefore there are 16 instances of the row decoder 4000, each outputting one of the 16 word lines. Thus, based on the received row address signal, one word line, such as word line 4006, outputs its respective signal, such as a voltage, while the other word lines are set to ground.

[0166] Figure 41 shows a combined co-select / deselect word line and control gate decoder 4100, including a low-voltage line decoder as shown in Figure 40, which comprises a NAND gate 4101, a PMOS transistor 4102, an NMOS transistor 4103, a line address signal 4104, a vertical input word line 4105, and a horizontal word output line 4106 coupled to a word line of the VMM array. The combined word line and control gate decoder 4100 further includes an inverter 4107, switches 4108 and 4112, and an isolation transistor 4109, which receives a control gate input 4110 CGIN0 and outputs a control gate line 4111 CG0. The word line output 4106 WL0 and the control gate output CG0 4111 are simultaneously selected or deselected by a decoding logic (not shown) that controls the NAND gate 4101.

[0167] Figure 42 shows a bit line decoder 4200 operating with VMM arrays 4201 and 4202. The bit line decoder 4200 includes a column multiplexer 4203 (for selecting one or more bit lines for programming and verification, where verification is used to confirm that the cell current has reached a specific target during a tuning operation (program or erase operation)), and a sense amplifier 4204 (for performing read operations on one or more bit lines). As shown, local bit line mux 4201b and 4202b multiplex the local array bit lines into global bit lines 4220x which are coupled to the column multiplexer 4203. The sense amplifier includes an ADC or other device. Thus, the bit line decoder 4200 is shared across multiple arrays.

[0168] Figure 43 shows the VMM system 4300, which comprises VMM arrays 4301, 4302, 4303, and 4304, low-voltage row decoders 4305 and 4307, local high-voltage row decoders 4306 and 4308, global high-voltage row decoder 4309, digital bus inputs QIN[7:0] 4311 and 4312 (which are inputs to the VMM arrays), and bit lines 4321, 4322, 4323, and 4324. Each low-voltage row decoder, such as the low-voltage row decoder 4305, comprises a circuit block row decoder 4335 for each word line, such as an exemplary data input block 4331 (which may consist of eight latches or registers) and block 4332 (which may comprise a data-to-voltage converter or a data-to-pulse converter) that outputs a signal 4333 on the word line. Therefore, the input to this low-voltage row decoder is a digital bus QIN[7:0] with appropriate control logic. In each circuit block row decoder 4335, the digital inputs QIN[7:0] 4311 and 4312 are appropriately latched by synchronous timing means and methods (e.g., by a serial-to-parallel clocking interface).

[0169] Figure 44 shows a neural network array input / output bus multiplexer 4400 that receives outputs from a VMM array (such as from an ADC) and provides those outputs in a group-multiplexed manner to the input blocks of another VMM array (such as a DAC or DPC). In the example shown, the input to the input / output bus multiplexer 4400 contains 2048 bits (256 sets, each of 8 bits NEU0, ..., NEU255), and the input / output bus multiplexer 4400 provides those bits in 64 different groups of 32 bits each, and multiplexes between different groups (providing one group of 32 bits at any given time), such as by using time-division multiplexing. Control logic 4401 generates control signals 4402 that control the input / output bus multiplexer 4400.

[0170] Figures 45A and 45B show exemplary layouts of the VMM array, where the word lines are laid out horizontally (Figure 45A) in contrast to vertically (Figure 34 or 35, as in Figure 45B).

[0171] Figure 46 shows an exemplary layout of a VMM array where the word lines are laid out vertically (as in Figure 34 or 35). However, in this layout, two word lines (e.g., word lines 4601 and 4602) can occupy the same column but access different rows in the array (due to the gap between them).

[0172] Figure 47 shows a VMM high-voltage decoding circuit, which includes a word-line decoder circuit 4701, a source-line decoder circuit 4704, and a high-voltage level shifter 4708, suitable for use in the type of memory cell shown in Figure 2.

[0173] The word line decoder circuit 4701 includes a PMOS select transistor 4702 (controlled by the signal HVO_B) and an NMOS deselector transistor 4703 (controlled by the signal HVO_B), configured as shown in the figure.

[0174] The source line decoder circuit 4704 includes an NMOS monitoring transistor 4705 (controlled by signal HVO), a drive transistor 4706 (controlled by signal HVO), and a deselector transistor 4707 (controlled by signal HVO_B), configured as shown in the figure.

[0175] The high-voltage level shifter 4708 receives an enable signal EN and outputs a high-voltage signal HV and its complementary signal HVO_B.

[0176] Figure 48 shows a VMM high-voltage decoding circuit, which includes an erase gate decoder circuit 4801, a control gate decoder circuit 4804, a source line decoder circuit 4807, and a high-voltage level shifter 4811, suitable for use in the type of memory cell shown in Figure 3.

[0177] The erase gate decoder circuit 4801 and the control gate decoder circuit 4804 use the same design as the word line decoder circuit 4701 in Figure 47.

[0178] Source line decoder circuit 4807 uses the same design as source line decoder circuit 4704 in Figure 47.

[0179] The high-voltage level shifter 4811 uses the same design as the high-voltage level shifter 4708 in Figure 47.

[0180] Figure 49 shows a word line driver 4900. The word line driver 4900 selects word lines (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown herein) and provides a bias voltage to those word lines. Each word line is connected to a selection isolation transistor, such as a selection transistor 4901, which is controlled by a control line 4902. The selection transistor, such as selection transistor 4901, isolates the high voltage (e.g., 8-12V) used during the erase operation from the word line decode transistor, and the selection transistor can be implemented using an I / O transistor that operates at a low voltage (e.g., 1.8V, 3.3V). Here, during any operation, the control line 4902 is activated, and all selection transistors similar to selection transistor 4901 are turned on. Exemplary bias transistor 4903 (part of the word line decoding circuit) selectively couples word lines to a first bias voltage (e.g., 3V), and exemplary bias transistor 4904 (part of the word line decoding circuit) selectively couples word lines to a second bias voltage (lower than the first bias voltage and including ground, a bias between ground and the first bias voltage, or a negative voltage bias to reduce leakage from unused memory rows). During ANN (analog neural network) readout operation, all used word lines are selected and coupled to the first bias voltage. All unused word lines are coupled to the second bias voltage. During other operations, such as program operation, only one word line is selected, and the other word line is coupled to the second bias voltage, which may be a negative bias (e.g., -0.3 to -0.5V or higher) to reduce array leakage.

[0181] Bias transistors 4903 and 4904 are coupled to the output of stage 4906 of shift register 4905. Shift register 4905 allows each row to be controlled independently according to the input data pattern (loaded at the start of ANN operation).

[0182] Figure 50 shows the word line driver 5000. The word line driver 5000 is similar to the word line driver 4900, except that each selection transistor is further coupled to a capacitor such as capacitor 5001. Capacitor 5001 can provide a precharge or bias to the word line at the start of operation, which is enabled by transistor 5002 to sample the voltage on line 5003. Capacitor 5001 acts to sample and hold the input voltage for each word line (S / H). Transistors 5004 and 5005 are off during the ANN operation (array current adder and activation function) of the VMM array, meaning that the voltage on S / H capacitor 5001 acts as a (stray) voltage source for each word line. Alternatively, capacitor 5001 can be provided by capacitance from the word line of the VMM array (or as control gate capacitance if the input is on a control gate).

[0183] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly on” (without intermediate material, element, or gap between them) and “indirectly on” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element electrically connecting the elements together between them) and “indirectly electrically coupled to” (with intermediate material or element electrically connecting the elements together between them). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is an analog neural memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each memory cell includes a control gate terminal and a word line terminal, A plurality of word lines, each of which is coupled to the word line terminal of the row of memory cells, A plurality of control gate lines, each of which is coupled to the control gate terminal of a row of memory cells, An analog neural memory system comprising: a plurality of decoders, each decoder being selectively coupled to the plurality of word lines for providing row decoder functionality, wherein the row decoder functionality is selectively coupled to the plurality of word lines, which can be selected or deselected; and a plurality of control gate lines for providing control gate decoder functionality, wherein the control gate decoder functionality is selectively coupled to the plurality of control gate lines, which can be selected or deselected.

2. The system according to claim 1, wherein the non-volatile memory cell is a split-gate flash memory cell.

3. It is an analog neural memory system, A first vector matrix multiplication array comprising an array of nonvolatile memory cells arranged in rows and columns, wherein each memory cell comprises a bit line terminal and a control gate terminal, and the first vector matrix multiplication array A second vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each memory cell includes a bit line terminal, a word line terminal, and a control gate terminal, A high-voltage row decoder for applying a high voltage to the word line terminals of selected rows in the first vector matrix multiplication array and cells in selected rows in the second vector matrix multiplication array, A first set of control gate lines, each of which is connected to a control gate terminal of a row of cells in the first vector matrix multiplication array and not connected to the second vector matrix multiplication array, An analog neural memory system comprising: a second set of control gate lines, each of which is coupled to a control gate terminal of a row of cells in the second vector matrix multiplication array and not coupled to the first vector matrix multiplication array.

4. The system according to claim 3, wherein the non-volatile memory cell is a split-gate flash memory cell.

5. It is an analog neural memory system, A plurality of vector matrix multiplication arrays, each vector matrix multiplication array including an array of non-volatile memory cells organized in rows and columns, each memory cell including a word line terminal, and the plurality of vector matrix multiplication arrays A plurality of read row decoders, each read row decoder being coupled to one of the plurality of vector matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation, An analog neural memory system comprising: a shared program row decoder coupled to all of the plurality of vector matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector matrix multiplication arrays during program operation; and

6. The system according to claim 5, wherein the non-volatile memory cell is a split-gate flash memory cell.

7. The system according to claim 5, wherein the non-volatile memory cell is a stacked gate flash memory cell.

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