RF impedance matching network with series-connected diode switches

Abstract

In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit includes at least one electronically variable capacitor (EVC). Each EVC includes a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor into and out of the fixed capacitor to change the total capacitance of the EVC. Each switching circuit includes a switch operatively coupled to the fixed capacitor to cause switching of the fixed capacitor into and out of the fixed capacitor. The switch includes at least one string of series connected PIN or NIP diodes. For each string, at least one of the diodes in the string has a balancing capacitor in parallel with the diode.

Description

[Technical Field]

[0001] (Related applications) This application claims the interests of U.S. Provisional Application No. 63 / 193,183, filed on 26 May 2021, which is incorporated herein by reference in its entirety. [Background technology]

[0002] In the manufacture of semiconductor devices such as microprocessors, memory chips, and other integrated circuits, the semiconductor device manufacturing process utilizes plasma processing at different stages of the manufacturing process. Plasma processing involves energizing a gas mixture by introducing RF (radio frequency) energy into the gas mixture, thereby imparting energy to the gas molecules. This gas mixture is typically contained within a vacuum chamber, also known as a plasma chamber, and the RF energy is introduced into the chamber through electrodes or other means. In a typical plasma process, a high-frequency power supply generates power at the desired RF frequency and RF power, and this power is transmitted to the plasma chamber through RF cables and networks.

[0003] To provide efficient power transfer from the high-frequency power supply to the plasma chamber, an RF matching network is positioned between the high-frequency power supply and the plasma chamber. The purpose of the RF matching network is to convert the plasma impedance to a value suitable for the high-frequency power supply. Often, especially in semiconductor manufacturing processes, RF power is transmitted through 50-ohm coaxial cables, and the system impedance (output impedance) of the high-frequency power supply is also 50 ohms. On the other hand, the impedance of the plasma driven by the RF power varies based on plasma chemistry and other conditions inside the plasma chamber. This impedance must be converted to a non-reactive 50 ohms (i.e., 50+j0) for maximum power transmission. The RF matching network performs this task of continuously converting the plasma impedance to 50 ohms for the high-frequency power supply. In most cases, this conversion is performed so that the input impedance of the RF matching network is 50+j0 ohms, i.e., a purely resistive 50 ohms.

[0004] An RF matching network may comprise a variable capacitor and a microprocessor-based control circuit for controlling the capacitor. The value and size of the variable capacitor are influenced by the power handling capability, operating frequency, and impedance range of the plasma chamber. The primary variable capacitor used in RF matching networks is the vacuum variable capacitor (VVC). A VVC is an electromechanical device consisting of two concentric metal rings that move relative to each other to change capacitance. In complex semiconductor processes where impedance changes are very rapid, rapid and frequent movement stresses the VVC, leading to its failure. VVC-based RF matching networks are one of the last electromechanical components in semiconductor manufacturing processes.

[0005] However, as semiconductor devices shrink in size and become more complex, feature shapes become extremely small. As a result, the processing time required to manufacture these features also becomes extremely small, typically in the range of 5-6 seconds. Current RF matching networks take 1-2 seconds to tune the process, which leads to unstable process parameters for a significant portion of the process time. Electronically variable capacitor (EVC) technology (see, for example, U.S. Patent No. 7,251,121, which is incorporated herein by reference in its entirety) makes it possible to reduce this semiconductor processing tuning time from 1-2 seconds to less than 500 microseconds. EVC-based matching networks are a type of solid-state matching network. The reduction in tuning time significantly increases the available stable processing time, thereby improving yield and performance.

[0006] While EVC technology is publicly known, it has not yet been developed as an industry-recognized replacement for VVC. Because EVCs are purely electronic devices, they are not a one-to-one replacement for VVCs in RF-matched networks. Therefore, further advancements are needed to more fully utilize EVCs as part of RF-matched networks. [Overview of the project] [Means for solving the problem]

[0007] The disclosure may also relate to radio frequency (RF) impedance matching circuits, the matching circuit comprising: an RF input configured to be operably coupled to an RF source providing an RF signal; an RF output configured to be operably coupled to a plasma chamber; at least one electronically variable capacitor (EVC), each of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC; and a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch comprising at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and for each of the at least one string, at least one of the diodes in the string having a balanced capacitor in parallel with the diode.

[0008] In another embodiment, a method for impedance matching includes coupling the radio frequency (RF) input of a matching circuit to an RF source providing an RF signal, and coupling the RF output of the matching circuit to a plasma chamber, wherein the matching circuit comprises at least one electronically variable capacitor (EVC), each of the at least one EVCs comprises a fixed capacitor, each of the fixed capacitors comprises a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, and a control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprises a switch operably coupled to the fixed capacitor to cause the switching of the input and output of the fixed capacitor, the switch comprises at least one string of series-connected diodes, each of the diodes in the series-connected diodes is a PIN diode or a NIP diode, and for each of the at least one string, at least one of the diodes in the string has a balanced capacitor in parallel with the diode, and matching the impedance by at least one of the switching circuits of the at least one EVC to change the input and output of its corresponding fixed capacitor to change the total capacitance of the EVC.

[0009] In another embodiment, a semiconductor processing tool includes a plasma chamber configured to deposit material onto a substrate or to etch material from a substrate, and an impedance matching circuit operably coupled to the plasma chamber, the matching circuit having an RF input operably coupled to an RF source providing an RF signal, an RF output operably coupled to the plasma chamber, and at least one electronically variable capacitor (EVC), each of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, and a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch comprising at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and for each of the at least one string, at least one of the diodes in the string having a balanced capacitor in parallel with the diode.

[0010] In another embodiment, a method for manufacturing a semiconductor includes placing a substrate in a plasma chamber configured to deposit a material layer on the substrate or to etch a material layer from the substrate; energizing the plasma in the plasma chamber by connecting RF power from an RF source to the plasma chamber in order to carry out deposition or etching; and performing impedance matching by an impedance matching circuit connected between the plasma chamber and the RF source while the plasma is energized, wherein the matching circuit includes an RF input configured to be operably connected to the RF source, an RF output configured to be operably connected to the plasma chamber, and at least one electronically variable capacitor (EVC), each of which EVCs comprises a fixed capacitor, each of which is The device comprises at least one electronically variable capacitor having a corresponding switching circuit for changing the total capacitance of an EVC by switching the input and output of a fixed capacitor, and a control circuit configured to cause switching of the input and output of a fixed capacitor of each EVC to enable impedance matching, wherein each switching circuit for each fixed capacitor of each EVC comprises a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch comprises at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and for each of the at least one string, at least one of the diodes in the string is a balanced capacitor in parallel with the diode.

[0011] In yet another embodiment, the RF impedance matching circuit includes an RF input configured to be operably coupled to an RF source providing an RF signal, an RF output configured to be operably coupled to a plasma chamber, at least one electronically variable capacitor (EVC), each of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, and a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch comprising at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and each of the series-connected diodes being directly positioned on a heatsink that does not conduct electricity.

[0012] In another embodiment, a method for impedance matching includes coupling the radio frequency (RF) input of a matching circuit to an RF source providing an RF signal, and coupling the RF output of the matching circuit to a plasma chamber, wherein the matching circuit comprises at least one electronically variable capacitor (EVC), each of the at least one EVCs comprises a fixed capacitor, each fixed capacitor comprising a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, and a control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch operably coupled to the fixed capacitor to cause the switching of the input and output of the fixed capacitor, the switch comprising at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and each of the series-connected diodes being directly positioned on a non-conductive heatsink, and matching the impedance by at least one of the switching circuits of the at least one EVC to change the input and output of its corresponding fixed capacitor to change the total capacitance of the EVC.

[0013] In another embodiment, the semiconductor processing tool includes a plasma chamber configured to deposit material onto a substrate or to etch material from a substrate, and an impedance matching circuit operably coupled to the plasma chamber, the matching circuit having an RF input operably coupled to an RF source providing an RF signal, an RF output operably coupled to the plasma chamber, and at least one electronically variable capacitor (EVC), each of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, and a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch comprising at least one string of series-connected diodes, each of the diodes in the series-connected diodes being a PIN diode or a NIP diode, and each of the series-connected diodes being directly positioned on a non-conductive heatsink.

[0014] In another embodiment, a method for manufacturing a semiconductor includes: placing a substrate in a plasma chamber configured to deposit a material layer on the substrate or to etch a material layer from the substrate; energizing the plasma in the plasma chamber by connecting RF power from an RF source to the plasma chamber in order to carry out deposition or etching; and performing impedance matching by an impedance matching circuit connected between the plasma chamber and the RF source while the plasma is energized, wherein the matching circuit is at least one electronically variable capacitor (EVC), each of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors switching the input and output of the fixed capacitor The device comprises at least one electronically variable capacitor having a corresponding switching circuit for changing the total capacitance of the EVC, and a control circuit configured to cause switching of the input and output of a fixed capacitor of each EVC to enable impedance matching, wherein each switching circuit for each fixed capacitor of each EVC includes a switch operably coupled to the fixed capacitor to cause switching of the input and output of the fixed capacitor, the switch includes at least one string of series-connected diodes, each of the diodes in the series-connected diodes is a PIN diode or a NIP diode, and each of the series-connected diodes is positioned directly on a heatsink that does not conduct electricity. [Brief explanation of the drawing]

[0015] This disclosure will be better understood from the detailed description and accompanying drawings.

[0016] [Figure 1] Figure 1 is a block diagram of one embodiment of a semiconductor processing system. [Figure 2] Figure 2 is a block diagram of one embodiment of a semiconductor processing system having an L-configuration matching network. [Figure 3] Figure 3 is a block diagram of one embodiment of a semiconductor processing system having a pi-configuration matching network. [Figure 4]FIG. 4 is a block diagram of one embodiment of a circuit for providing a variable capacitance using an electronically variable capacitor. [Figure 5] FIG. 5 is a schematic diagram of a variable capacitance system for switching the inputs and outputs of individual capacitors of an electronically variable capacitor. [Figure 6] FIG. 6 is a block diagram of one embodiment of a switching circuit for an EVC. [Figure 7] FIG. 7 is a flowchart of an exemplary process for impedance matching by varying a variable capacitance. [Figure 8] FIG. 8 is a flowchart of an exemplary process for impedance matching using a parameter matrix to vary a variable capacitance. [Figure 9] FIG. 9 is a diode-based switch utilizing a balancing resistor according to one embodiment. [Figure 10] FIG. 10 is a block diagram of a diode-based switch positioned on a ceramic substrate positioned on a metal heat sink according to one embodiment. [Figure 11] [[ID=2I]]FIG. 11 is a graph of the voltage between the diodes of the diode-based switch of FIG. 9. [Figure 12] FIG. 12 is a graph of the voltage between the diodes of the diode-based switch of FIG. 9 using a floating heat sink. [Figure 13] FIG. 13 is a graph of the voltage between the diodes of the diode-based switch of FIG. 9 using un-equal valued balancing resistors. [Figure 14] FIG. 14 is a diode-based switch utilizing a balancing capacitor according to one embodiment. [Figure 15] FIG. 15 is a diode-based switch utilizing a balancing capacitor according to another embodiment. <00001OS>[[ID=3S]] [Figure 16] FIG. 16 is a schematic simulation diagram of a diode-based switch utilizing a balancing capacitor according to one embodiment. [Figure 17] Figure 17 is a graph of the voltage across the diodes in the diode-based switch of Figure 15, which utilizes a balanced capacitor, according to one embodiment. [Figure 18] Figure 18 is a block diagram of a diode-based switch positioned on a ceramic heatsink, according to another embodiment. [Modes for carrying out the invention]

[0017] The following description of preferred embodiments is essentially illustrative and is not intended to limit the invention in any way. The description of exemplary embodiments is intended to be read in conjunction with the accompanying drawings and is considered to be part of the whole written description. Any reference to direction or orientation in the description of exemplary embodiments disclosed herein is intended solely for illustrative purposes and is not intended to limit the scope of the invention in any way. The discussion herein describes and illustrates several possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term “or” as used herein should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, the word “based on” as used herein should be interpreted as “based at least partially,” and not limited to the interpretation “based entirely.”

[0018] The features of the present invention can be implemented in software, hardware, firmware, or a combination thereof. The computer programs described herein are not limited to any particular embodiment and can be implemented in an operating system, application program, foreground or background process, driver, or any combination thereof. The computer programs may run on a single computer or server processor, or on multiple computers or server processors.

[0019] The processors described herein may be any central processing unit (CPU), microprocessor, microcontroller, computing device, or programmable device or circuit configured to execute computer program instructions (e.g., code). Various processors may be embodied in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual auxiliary components necessary to form a functional data processing device, including but not limited to buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, and LAN.

[0020] The computer-executable instructions or programs (e.g., software or code) and data described herein may be programmed and tangibly embodied on non-transient computer-readable media accessible and thereby obtainable from each processor described herein, which configures and directs the processor to perform desired functions and processes by executing instructions encoded on the medium. A device that embodies such a programmable processor configured with such non-transient computer-executable instructions or programs may be referred to as a “programmable device” or “device,” and a group of programmable devices communicating with each other may be referred to as a “programmable system.” The non-temporary “computer-readable media” as described herein includes, but is not limited to, any suitable volatile or non-volatile memory, including random access memory (RAM) and various types thereof, read-only memory (ROM) and various types thereof, USB flash memory, and magnetic or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tapes, CD-ROMs, DVD-ROMs, optical discs, ZIP® drives, Blu-ray® discs, and others) that can be written to and / or read by a processor operably connected to the media.

[0021] In certain embodiments, the present invention may be embodied in the form of computer implementation processes and devices such as processor-based data processing and communication systems, or computer systems for carrying out those processes. The present invention may also be embodied in the form of software or computer program code embodied in a non-temporary computer-readable storage medium, wherein, when loaded into and executed within a data processing and communication system or computer system, the computer program code segments configure the processor to produce specific logic circuits configured to implement the processes.

[0022] In the following descriptions in which circuits are shown and described, those skilled in the art will recognize, for clarity, that not all peripheral circuits or components are shown in the diagrams or described in the description. Furthermore, the terms “connected” and “operably connected” may refer to the direct or indirect connection of two components of a circuit.

[0023] The following description of preferred embodiments is purely illustrative and is not intended to limit the invention in any way. The description of exemplary embodiments is intended to be read in conjunction with the accompanying drawings and is considered to be part of the whole written description. Any reference to direction or orientation in the description of exemplary embodiments disclosed herein is purely for illustrative purposes and is not intended to limit the scope of the invention in any way. Relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “left,” “right,” “top,” “bottom,” “front,” and “rear,” as well as their derivatives (e.g., “horizontally,” “downwardly,” “upwardly,” etc.), should be interpreted as referring to the orientation described or the orientation shown in the drawings discussed. These relative terms are for illustrative purposes only and do not imply that the device is constructed or operated in a particular orientation unless explicitly stated. Terms such as “attached,” “affixed,” “connected,” “coupled,” “interconnected,” “secured,” and other similar terms refer, unless otherwise explicitly stated, to relationships in which structures are fixed or attached to one another, either directly or indirectly, through intervening structures, as well as both movable and rigid attachments or relationships. The discussion herein describes and illustrates several possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term “or” as used herein should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, the word “based on” as used herein should be interpreted as “based at least partially,” and not limited to the interpretation “based entirely.”

[0024] The range used throughout is used as a concise expression to describe all values ​​within the range. Any value within the range can be selected as the end of the range. Furthermore, all references cited herein are incorporated herein in their entirety by reference. In the event of any conflict between the definitions in this disclosure and the definitions in the cited references, this disclosure shall prevail.

[0025] Semiconductor processing system Referring to Figure 1, a semiconductor device processing system 5 utilizing a high-frequency power supply 15 is shown. System 85 includes the high-frequency power supply 15 and a semiconductor processing tool 86. The semiconductor processing tool 86 includes a matching network 11 and a plasma chamber 19. In other embodiments, a generator 15 or other power supply may form part of the semiconductor processing tool.

[0026] The semiconductor device can be a microprocessor, a memory chip, or other type of integrated circuit or device. The substrate 27 can be placed in a plasma chamber 19, which is configured to deposit a material layer on the substrate 27 or to etch a material layer from the substrate 27. Plasma processing involves energizing a gas mixture by introducing RF energy into the gas mixture, thereby imparting energy to the gas molecules. This gas mixture is typically contained within a vacuum chamber (plasma chamber 19), and the RF energy is typically introduced into the plasma chamber 19 through electrodes. Therefore, the plasma can be energized by connecting RF power from an RF source 15 to the plasma chamber 19 to carry out deposition or etching.

[0027] In a typical plasma process, a high-frequency power supply 15 generates power at radio frequencies, typically in the range of 3 kHz to 300 GHz, which is transmitted to a plasma chamber 19 through RF cables and networks. To provide efficient power transfer from the high-frequency power supply 15 to the plasma chamber 19, an intermediate circuit is used to match the fixed impedance of the high-frequency power supply 15 with the variable impedance of the plasma chamber 19. Such intermediate circuits are commonly referred to as RF impedance matching networks, or more simply RF matching networks. The purpose of the RF matching network 11 is to convert the variable plasma impedance to a value that more closely matches the fixed impedance of the high-frequency power supply 15. Co-owned U.S. Publications 2021 / 0183623 and 2021 / 0327684, whose entire disclosures are incorporated herein by reference, provide examples of such matching networks.

[0028] Unified Network Figure 2 is a block diagram of one embodiment of a semiconductor processing system 85 having a processing tool 86 including an L-configuration RF impedance matching network 11. As will be discussed in more detail below, the exemplary matching network 11 utilizes electronically variable capacitors (EVCs) for both the shunt variable capacitor 33 and the series variable capacitor 31. It should be noted that the present invention is not limited in this way. For example, one of the EVCs (e.g., the shunt EVC 33) may be a mechanically variable VVC or may be replaced with a variable inductor.

[0029] An exemplary impedance matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 may be connected between the RF impedance matching network 11 and the RF source 15. An RF output sensor 49 may be connected between the RF impedance matching network 11 and the plasma chamber 19 so that the RF output from the impedance matching network and the plasma impedance presented by the plasma chamber 19 can be monitored. Certain embodiments may include only one of the input sensor 21 and the output sensor 49. The functions of these sensors 21, 49 are described in more detail below.

[0030] As described above, the RF impedance matching network 11 helps maximize the amount of RF power transmitted from the RF source 15 to the plasma chamber 19 by matching the impedance at the RF input 13 to the fixed impedance of the RF source 15. The matching network 11 may consist of a single module in a single housing designed for electrical connections to the RF source 15 and the plasma chamber 19. In other embodiments, the components of the matching network 11 may be located in different housings, some components may be outside the housing, and / or some components may share a housing with components outside the matching network.

[0031] As is well known in the art, the plasma in the plasma chamber 19 typically undergoes certain fluctuations outside of operational control, such that the impedance presented by the plasma chamber 19 is a variable impedance. Since it is not possible to completely control the variable impedance of the plasma chamber 19, an impedance matching network may be used to create impedance matching between the plasma chamber 19 and the RF source 15. Furthermore, the impedance of the RF source 15 may be fixed to a set value by the design of the particular RF source 15. The fixed impedance of the RF source 15 may undergo slight fluctuations during use, for example, due to temperature or other environmental fluctuations, but since the fluctuations do not significantly change the fixed impedance from the originally set impedance value, the impedance of the RF source 15 is still considered a fixed impedance for the purposes of impedance matching. Other types of RF sources 15 may be designed so that the impedance of the RF source 15 can be set at the time of use or during use. The impedance of this type of RF source 15 is still considered fixed because this impedance can be controlled by the user (or at least by a programmable controller), and the set value of the impedance may be known at any point during operation, thus effectively making the set value a fixed impedance.

[0032] The RF source 15 may be a high-frequency power supply of a type well known in the art, which generates an RF signal at a frequency and power appropriate for the process carried out in the plasma chamber 19. The RF source 15 may also be electrically connected to the RF input 13 of the RF impedance matching network 11 using a coaxial cable, which will have the same fixed impedance as the RF source 15 for impedance matching purposes.

[0033] The plasma chamber 19 includes a first electrode 23 and a second electrode 25, and in a process well known in the art, the first and second electrodes 23 and 25, together with a suitable control system (not shown) and plasma in the plasma chamber, enable either or both of the deposition of material on a substrate 27 and / or etching of material from the substrate 27.

[0034] In an exemplary embodiment, the RF impedance matching network 11 includes a series variable capacitor 31, a shunt variable capacitor 33, and a series inductor 35, forming an "L" type matching network. The shunt variable capacitor 33 is shown as having shunted to a reference potential (in this case, ground 40) between the series variable capacitor 31 and the series inductor 35, and those skilled in the art will recognize that the RF impedance matching network 11 may be configured with a shunt variable capacitor 33 that shunts to a reference potential at the RF input 13 or RF output 17.

[0035] Alternatively, the RF impedance matching network 11 may be configured in a "T" type configuration or other matching network configurations such as a "π" or "pi" type configuration, as shown in Figure 3. In certain embodiments, the variable capacitors and switching circuits described below may be included in any configuration suitable for the RF impedance matching network.

[0036] In exemplary embodiments, each of the series variable capacitor 31 and the shunt variable capacitor 33 may be an electronically variable capacitor (EVC) as described in U.S. Patent No. 7,251,121, where the EVC is effectively formed as a capacitor array consisting of a plurality of individual capacitors. The series variable capacitor 31 is connected in series between the RF input 13 and the RF output 17 (which is also in parallel between the RF source 15 and the plasma chamber 19). The shunt variable capacitor 33 is connected in parallel between the RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 may be connected in parallel between the RF output 19 and ground 40. Other configurations may also be implemented without deviating from the functionality of the RF matching network. In yet another configuration, the shunt variable capacitor 33 may be connected in parallel between a reference potential and one of the RF input 13 and RF output 19.

[0037] The series variable capacitor 31 is connected to the series RF choke and filter circuit 37 and also to the series driver circuit 39. Similarly, the shunt variable capacitor 33 is connected to the shunt RF choke and filter circuit 41 and also to the shunt driver circuit 43. Each of the series driver circuit 39 and the shunt driver circuit 43 is connected to the control circuit 45, which consists of a suitable processor and / or signal generation circuit to provide input signals for controlling the series driver circuit 39 and the shunt driver circuit 43. The power supply 47 is connected to each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45, providing operating power to each of these components at the designed current and voltage. The voltage levels provided by the power supply 47, and therefore the voltage levels employed by each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45, can be selected to suit the design in order to perform their respective specific tasks. In other embodiments, various electronic components can be used to enable the control circuit 45 to send commands to the variable capacitors. Furthermore, while the driver circuit and the RF choke and filter are shown separately from the control circuit 45, these components can also be considered as parts that form the control circuit 45.

[0038] In exemplary embodiments, the control circuit 45 includes a processor. The processor may be any type of appropriately programmed processing unit (or a set of two or more processing units working together), such as a computer or microprocessor, configured to execute computer program instructions (e.g., code). The processor may be embodied in any appropriate type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual auxiliary components necessary to form a functional data processing unit, including but not limited to buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth®, LAN. The processor in exemplary embodiments consists of specific algorithms that enable the harmonized network to perform the functions described herein.

[0039] The combination of the series variable capacitor 31 and the shunt variable capacitor 33 allows the combined impedance of the RF impedance matching network 11 and the plasma chamber 19 to be controlled, using the control circuit 45, the series driver circuit 39, and the shunt driver circuit 43, to match, or at least substantially match, the fixed impedance of the RF source 15.

[0040] The control circuit 45 is the brain of the RF impedance matching network 11. This is because, in order to create impedance matching, the control circuit 45 receives multiple inputs from sources such as the RF input sensor 21 and the series variable capacitor 31 and shunt variable capacitor 33, performs the calculations necessary to determine the changes to the series variable capacitor 31 and shunt variable capacitor 33, and sends commands to the series variable capacitor 31 and shunt variable capacitor 33. The control circuit 45 is a type of control circuit commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. The difference between the control circuit 45 and the control circuit of prior art arises in the programming differences due to the speed at which the RF impedance matching network 11 can perform the switching of the variable capacitors 31 and 33 and impedance matching.

[0041] Each of the series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 is configured such that a DC signal can pass between the series driver circuit 39 and the shunt driver circuit 43 and their respective series variable capacitors 31 and shunt variable capacitors 33, while simultaneously blocking the RF signal from the RF source 15 and preventing the RF signal from leaking to the outputs of the series driver circuit 39 and the shunt driver circuit 43 and the output of the control circuit 45. The series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 are of a type known to those skilled in the art.

[0042] Figure 3 is a block diagram of one embodiment of a semiconductor processing system 85A having a pi-configuration matched network 11A, in contrast to the L-configuration matched network of Figure 2. For ease of understanding, the RF choke and filter, driver circuit, and power supply of Figure 2 are omitted in this figure. Where the same reference numerals as in Figure 2 are used in Figure 3, it should be understood that the relevant components may have similar features to those discussed with respect to Figure 2. The most significant difference between the L configuration and the pi configuration is that the L configuration utilizes a series capacitor 31 and a shunt capacitor 33, while the pi configuration utilizes two shunt capacitors 31A and 33A. Nevertheless, the control circuit can change the capacitance of these shunt capacitors 31A and 33A to achieve impedance matching. Each of these shunt capacitors 31A and 33A can be an EVC as described above. These can be controlled by chokes, filters, and drivers similar to those described above with respect to Figure 2.

[0043] EVC Capacitor Array Figure 4 is a block diagram of one embodiment of an electronic circuit 150 for providing variable capacitance using an electronically variable capacitor 151. The circuit 150 utilizes an EVC 151 comprising two capacitor arrays 151a and 151b. The exemplary first capacitor array 151a has a first plurality of individual fixed capacitors, each of which has a first capacitance value. The second capacitor array 151b has a second plurality of individual fixed capacitors, each of which has a second capacitance value. The first capacitance value differs from the second capacitance value so that the EVC 151 can provide coarse and fine control of the capacitance generated by the EVC 151. The first and second capacitor arrays are connected in parallel between a signal input 113 and a signal output 130.

[0044] The first and second capacitance values ​​can be any values ​​sufficient to provide the desired overall capacitance value for the EVC 151. In one embodiment, the second capacitance value is half (1 / 2) or less of the first capacitance value. In another embodiment, the second capacitance value is one-third (1 / 3) or less of the first capacitance value. In yet another embodiment, the second capacitance value is one-quarter (1 / 4) or less of the first capacitance value.

[0045] The electronic circuit 150 further includes a control circuit 145, which may have features similar to the control circuit 45 described above. The control circuit 145 is operably connected to a first capacitor array 151a and a second capacitor array 151b by a command input 129, the command input 129 being operably connected to the first capacitor array 151a and the second capacitor array 151b. In an exemplary embodiment, the command input 129 has a direct electrical connection to the capacitor arrays 151a and 151b, but in other embodiments, this connection may be indirect. The connection of the control circuit 145 to the capacitor arrays 151a and 151b will be described in more detail below.

[0046] The control circuit 145 is configured to change the variable capacitance of the EVC 151 by controlling the on and off states of (a) each individual fixed capacitor of the first plurality of individual fixed capacitors and (b) each individual fixed capacitor of the second plurality of individual fixed capacitors. As described above, the control circuit 145 may have similar features to those described for the control circuit 45 in the preceding figure. For example, the control circuit 145 may receive inputs from capacitor arrays 151a and 151b to change the capacitance of the EVC 151, perform calculations to determine the changes to capacitor arrays 151a and 151b, and deliver commands to capacitor arrays 151a and 151b. The EVC 151 in Figure 4 may include a plurality of electronic switches. Each electronic switch may be configured to activate and deactivate one or more individual capacitors.

[0047] Similar to the control circuit 45 in the preceding figure, the control circuit 145 can also be connected to a driver circuit 139 and an RF choke and filter circuit 137. The control circuit 145, the driver circuit 139, and the RF choke and filter circuit 137 can have capabilities similar to those discussed with respect to the preceding figure. In an exemplary embodiment, the driver circuit 139 is operably coupled between the control circuit 145 and a first capacitor array 151a and a second capacitor array 151b. The driver circuit 139 is configured to change its variable capacitance based on a control signal received from the control circuit 145. The RF filter 137 is operably coupled between the driver circuit 139 and the first capacitor array 151a and the second capacitor array 151b. In response to a control signal transmitted by the control unit 145, the driver circuit 139 and the RF filter 137 are configured to transmit a command signal to the command input 129. The command signal is configured to change the variable capacitance by instructing at least one of the electronic switches to activate or deactivate (a) at least one of the first plurality of separate capacitors, or (b) at least one of the second plurality of separate capacitors.

[0048] In an exemplary embodiment, the driver circuit 139 is configured to switch the high-voltage source on or off in less than 15 microseconds, and the high-voltage source controls the respective electronic switches of the first and second capacitor arrays for the purpose of changing the variable capacitance. However, the EVC 151 can be switched by any means or speed considered in this application.

[0049] The control circuit 145 can be configured to calculate the coarse capacitance and fine capacitance values ​​provided by the respective capacitor arrays 151a and 151b. In an exemplary embodiment, the control circuit 145 is configured to calculate the coarse capacitance value provided by controlling the on and off states of the first capacitor array 151a. Furthermore, the control circuit is configured to calculate the fine capacitance value provided by controlling the on and off states of the second capacitor array 151b. In other embodiments, the capacitor arrays 151a and 151b may provide alternative levels of capacitance. In other embodiments, the EVC may utilize additional capacitor arrays.

[0050] The EVC 151 in Figure 4 can be used in a variety of systems requiring varying capacitance. For example, the EVC 151 can be used as a series EVC and / or shunt EVC in an L-matched network, or as one or both of a shunt EVC in a pi-matched network. The difference between capacitance values ​​is often desirable to allow both a sufficiently fine resolution of the overall capacitance of the circuit and a wide range of capacitance values ​​that enables better impedance matching at the input of the RF-matched network, and the EVC 151 makes this possible.

[0051] Switching the input and output of individual capacitors to change the EVC capacitance. As described above, an EVC is a type of variable capacitor that can use multiple switches (each used to create an open circuit or a short circuit) along with individual series capacitors to change the capacitance of the variable capacitor. The switches can be mechanical (such as relays) or solid-state (such as PIN diodes, transistors, or other switching devices). The following is a consideration of methods for setting up an EVC or other variable capacitor to provide a changing capacitance.

[0052] In what is sometimes called a “cumulative setup” of an EVC or other variable capacitor, the approach of linearly increasing the capacitor value from a minimum starting point (where all switches are open) is to progressively increase the number of micro-tuned capacitors that are switched to input to the circuit. When the maximum number of micro-tuned capacitors are switched to input to the circuit, the coarse-tuned capacitors are switched to input and the micro-tuned capacitors are switched to output. The process restarts by increasing the number of micro-tuned capacitors that are switched to input to the circuit until all micro-tuned and coarse-tuned capacitors are switched to input, at which point another coarse-tuned capacitor is switched to input and a micro-tuned capacitor is switched to output. This process can continue until all coarse-tuned and micro-tuned capacitors are switched to input.

[0053] In this embodiment, all micro-tuned capacitors have the same or substantially similar values, and all coarse-tuned capacitors have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuned capacitor is approximately equal to the combined capacitance value of all micro-tuned capacitors and any additional micro-tuned capacitors in the circuit, thus allowing for a linear increase in capacitance. However, the embodiments are not limited in this way. Micro-tuned capacitors (and coarse-tuned capacitors) do not need to have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuned capacitor does not need to be equal to the combined capacitance value of all micro-tuned capacitors and any additional micro-tuned capacitors. In one embodiment, the coarse capacitance value and the fine capacitance value have a substantially similar ratio of 10:1. In another embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0054] An example of the aforementioned embodiment in an ideal setting is when the fine-tuned capacitor is equal to 1pF and the coarse-tuned capacitor is equal to 10pF. In this ideal setting, when all switches are open, the capacitance is equal to 0pF. When the first switch is closed, there is 1pF in the circuit. When the second switch is closed, there is 2pF in the circuit, and this continues until the nine fine-tuned switches are closed, giving 9pF. Next, the first 10pF capacitor is switched to the input to the circuit, opening the nine fine-tuned switches and giving a total capacitance of 10pF. Next, the fine-tuned capacitors are switched to the input to the circuit from 11pF to 19pF. Next, another coarse-tuned capacitor can be switched to the input to the circuit, and all fine-tuned capacitors can be switched to the output from the circuit, giving 20pF. This process can be repeated until the desired capacitance is reached.

[0055] This can also be taken one step further. Using the previous embodiment, which has nine 1pF capacitors and nine 10pF capacitors, the variable capacitor circuit can have an even larger value of 100pF to switch the input and output of the circuit. This would allow the previous capacitor array to rise up to 99pF, and then the 100pF capacitor can be used for the next increment. This can be repeated further using larger increments and can also be used in conjunction with any counting system. According to the cumulative setup, increasing the total capacitance of the variable capacitor is achieved by switching more fine-tuned capacitors or fine-tuned capacitors to the input than are already switched to the input, without switching the coarse-tuned capacitors that are already switched to the input to the output. Furthermore, when the total variable capacitance increases and the control circuit does not switch more coarse-tuned capacitors to the input than are already switched to the input, the control circuit switches more fine-tuned capacitors to the input than are already switched to the input, without switching the fine-tuned capacitors that are already switched to the input to the output. U.S. Patents 10,431,428 and 11,195,698 relating to cumulative setups are incorporated herein by reference in their entirety. It should be noted that the claimed invention is not limited to the use of cumulative setups. For example, U.S. Patents 10,679,824 and 10,692,699 (both incorporated herein by reference in their entirety) consider alternative setups such as “partial binaries.”

[0056] Figure 5 is a schematic diagram of a variable capacitance system 155 for switching the input and output of individual fixed capacitors of an electronically variable capacitor. If this figure uses reference numerals similar to those in Figure 4, it should be understood that the relevant components may have features similar to those considered in Figure 4. The variable capacitance system 155 comprises a variable capacitor 151 for providing a changing capacitance. The variable capacitor 151 has an input 113 and an output 130. The variable capacitor 151 includes a plurality of individual fixed capacitors 153 operably connected in parallel. The plurality of capacitors 153 include a first (fine-tuned) capacitor 151a and a second (coarse-tuned) capacitor 151B. Furthermore, the variable capacitor 151 includes a plurality of switches 161. One of the switches 161 is operably connected in series to each of the plurality of capacitors, switching the input and output of each capacitor, thereby enabling the variable capacitor 151 to provide a changing total capacitance. The variable capacitor 151 has a variable total capacitance that increases when the individual capacitor 153 is switched to input, and decreases when the individual capacitor 153 is switched to output.

[0057] Switch 161 can be coupled to a switch driver circuit 139 to drive the switch on and off. The variable capacitance system 155 may further include a control unit 145 operably coupled to a variable capacitor 151. Specifically, the control unit 145 can be operably coupled to the driver circuit 139 to instruct the driver circuit 139 to switch one or more of the switches 161, thereby turning one or more of the capacitors 153 on or off. In one embodiment, the control unit 145 may form part of a control unit that controls the variable capacitor (such as a control unit that instructs the variable capacitor of a matching network to change its capacitance to achieve impedance matching). The driver circuit 139 and the control unit 145 may have features similar to those described above with reference to Figure 4, and therefore may also utilize the RF choke and filter as described above.

[0058] Electronically variable capacitor switching circuit Figure 6 shows one embodiment of the switching circuit 140A for the EVC 151 of the matched network according to one embodiment. In the exemplary embodiment, the EVC 151 is the EVC 151 of Figure 5, but the EVC of the present invention is not so limited as it may have any of the other features discussed herein (including a different number of individual fixed capacitors 153 and individual fixed capacitors with values ​​different from those discussed with respect to Figure 5). Furthermore, the EVC can form part of any type of matched network, including the various types of matched networks discussed herein. An exemplary matched network is connected between an RF source and a plasma chamber, for example, as shown in the preceding figures.

[0059] An exemplary EVC comprises a plurality of individual fixed capacitors 153A, 153B connected to a first terminal 113. Each individual capacitor 153A, 153B has a corresponding switch 161A, 161B configured to switch the individual capacitor to input (or "on") and to switch the individual capacitor to output (or "off") in order to change the total capacitance of the EVC 151. In the exemplary embodiment, switch 161A is in series with the individual capacitor 153A, but the present invention is not limited thereto. Furthermore, in the exemplary embodiment, switch 161A is a PIN diode, but the present invention is not limited thereto and may be another type of switch, such as a NIP diode. In yet another embodiment, the switch may be a MOSFET, a JFET, or another type of switch. Furthermore, in the exemplary embodiment, the PIN diodes have a common anode configuration such that the anode of each PIN diode 161A, 161B is connected to ground 40, which may be any common node. However, the present invention is not limited thereto, as in other embodiments the EVC may use a common cathode configuration such that the cathode of each PIN diode is connected to ground 40 (and the components of the driver circuit are changed accordingly). Furthermore, it should be noted that two or more switches may be used in series to increase the rated voltage and / or two or more switches may be used in parallel to increase the rated current of the channel.

[0060] Each PIN diode switch 161A, 161B has its own switching circuits 140A, 140B, which are connected to a control circuit 145. Switching circuit 140B is shown as including a switch 161B, a filter 141B (this filter may be similar to the filter circuits 37, 41 discussed above), and a driver circuit 139B. Filter 141B may be, for example, an LC circuit similar to filter circuit 9 in U.S. Patent No. 10,340,879, or a filter circuit next to output 207 in Figure 6A of U.S. Patent No. 9,844,127. Each of these patents is incorporated herein by reference in whole.

[0061] The exemplary switching circuit 140A has the same components as the switching circuit 140B, but the driver circuit 139A is shown in more detail. The driver circuit 139A may be integrated with the PIN diode 161A (or other type of switch), or with the individual fixed capacitors of the EVC of the matching network. Those skilled in the art will recognize that certain components of the driver circuit 139A can be replaced with other components that perform the same essential function, while allowing for greater variability of other circuit parameters (e.g., voltage range, current range, etc.).

[0062] The exemplary driver circuit 139A has two inputs 105A-1 and 105A-2 for receiving control signals from the control circuit to control the voltage at a common output 107A connected to and driving the PIN diode 161A. The voltage at the common output 107A switches the PIN diode 161A between an on and off state, and therefore switches the individual capacitor 153A to which the PIN diode 161A is connected input / on and output / off. In this exemplary embodiment, the state of the individual capacitor follows the state of the corresponding PIN diode, so that when the PIN diode is on, the individual capacitor is also input / on, and similarly, when the PIN diode 161A is off, the individual capacitor is also output / off. Thus, the description herein of the state of the PIN diode 161A essentially describes the simultaneous state of the corresponding individual capacitor 153A of the EVC 151.

[0063] In one preferred embodiment, each of the first power switch 111A and the second power switch 113A is a MOSFET having a body diode, but in other embodiments, either of the power switches may be a different type of switch, including any other type of semiconductor switch. The present invention may utilize a variety of switching circuit configurations. For example, the present invention may utilize either of the switching circuits disclosed in U.S. Patent Application No. 9,844,127 (such as the switching circuits shown in Figures 3, 6A, and 6B) or either of the switching circuits disclosed in U.S. Patent Application No. 10,340,879 (such as the switching circuit shown in Figure 18). As described above, each of these patents is incorporated herein by reference in its entirety.

[0064] In an exemplary embodiment, a high-voltage power supply 115A is connected to a first power switch 111A and provides a high-voltage input that is switchably connected to a common output 107A. A low-voltage power supply 117A is connected to a second power switch 113A and similarly provides a low-voltage input that is switchably connected to a common output 107A. In the configuration of the shown driver circuit 139A, the low-voltage power supply 117A may supply a low-voltage input of about -3.3V. Such a low voltage having negative polarity is sufficient to provide a forward bias for switching the PIN diode 161A. For other configurations of the driver circuit 139A, higher or lower voltage inputs may be used, and the low-voltage inputs may have positive polarity depending on the configuration and type of the electronic switch being controlled.

[0065] In the exemplary switching circuit 140A, the first power switch 111A and the second power switch 113A are configured to asynchronously connect a high-voltage power supply 115A and a low-voltage power supply 117A to a common output 107A for the purpose of switching a PIN diode 161A between an on and off state, thereby switching the input and output of the corresponding individual fixed capacitor 153A. The high-voltage power supply 115A provides a reverse bias DC voltage for the PIN diode switch 161A. This reverse-biases the PIN diode 161A, thus preventing current from flowing, and therefore switches its corresponding individual capacitor 153A to output, and may therefore also be called a “blocking voltage”. As used herein, the term “blocking voltage” refers to any voltage used to switch the input and output of the corresponding individual capacitor. It should be further noted that the switching circuit may be any circuit for switching the input and output of an individual capacitor, such as the capacitor shown in U.S. Patent No. 9,844,127 (which is incorporated herein by reference in its entirety), although the switching circuit is not limited to that shown in Figure 6.

[0066] In an exemplary embodiment, the control circuit provides separate control signals to separate inputs 105A-1 and 105A-2 of the driver circuit 139A. In this embodiment, the separate inputs 105A-1 and 105A-2 are connected to first and second power switches 111A and 113A, respectively. The control signals to the separate inputs may have opposite polarity. In a preferred embodiment, the first power switch 161A and the second power switch 113A are MOSFETs, and the separate control signals go to separate drivers to power the MOSFETs. In an alternative embodiment, the control circuit 145 provides a common input signal. The common input signal may asynchronously control the on and off states of the first power switch 111A and the second power switch 113A, so that when the first power switch 111A is ON, the second power switch 113A is OFF, and similarly when the first power switch is OFF, the second power switch 113A is ON. In this way, a common input signal asynchronously connects the high-voltage and low-voltage inputs to the common output for the purpose of controlling the first power switch 111A and the second power switch 113A to switch the PIN diode 161A between the on and off states. However, the present invention is not limited to such asynchronous control.

[0067] Inputs 105A-1 and 105A-2 may be configured to receive any type of appropriate control signal for the selected switch type for the first power switch 111A and the second power switch 113A, which may be, for example, a +15V control signal. In one preferred embodiment, the driver circuit has separate drivers for driving the first power switch 111A and the second power switch 112A, respectively. In another embodiment, the first power switch 111A and the second power switch 113A are selected to be able to receive a common input signal.

[0068] In an exemplary embodiment, power supply 118 is connected to the input of low-voltage power supply 117A. In a preferred embodiment, power supply 118 provides 24VDC. However, the present invention is not limited in this way, as other power supplies may be used.

[0069] In an exemplary embodiment, when the second power switch 113A is ON, current 163A flows between the PIN diode 161A and the low-voltage power supply 117A. Simultaneously, current flows from power supply 118 to the input of low-voltage power supply 117A and to ground 40. A sensor may be positioned at a node of the switching circuit 140A to measure a parameter associated with the current 163A flowing between the low-voltage power supply 117A and the PIN diode switch 161A. In an exemplary embodiment, sensor 164A is positioned at the input of low-voltage power supply 117A to measure the current 167A flowing from power supply 118 to the input, which is associated with current 163A. In other embodiments, the sensor may be positioned at other locations in the switching circuit 140A, such as at node 165A (output of the low-voltage power supply) or node 166A (anode of PIN diode 161A), or in the path of filter 141A between the driver circuit and the switch (e.g., driver output 107A or output of filter 141A). In an exemplary embodiment, the parameter is the value of the current flowing through the node, but in other embodiments, the measured parameter may be any parameter (including voltage) associated with the current flowing through the switch(s). In yet another embodiment, the parameter is any parameter associated with the driver circuit.

[0070] The harmonized networks discussed herein may incorporate bias circuits, such as the bias circuit discussed in PCT / US22 / 23395 filed April 5, 2022, and it should be noted that the entire circuit is incorporated herein by reference. For example, the bias inductor of the bias circuit may be used to switch a fixed individual capacitor of the EVC in series, and this EVC is not grounded.

[0071] Determining the capacitance value to achieve matching Figure 7 is a flowchart of process 500A for impedance matching according to one embodiment. The matching network may include components similar to those discussed above. In one embodiment, the matching network of Figure 3 is used. In the first step of the illustrated process 500A in Figure 7, the input impedance at RF input 13 is determined (step 501A). The input impedance is based on RF input parameters detected by RF input sensor 21 at RF input 13. RF input sensor 21 can be any sensor configured to detect RF input parameters at RF input 13. Input parameters can be any measurable parameters at RF input 13, including voltage, current, or phase at RF input 13. In an exemplary embodiment, RF input sensor 21 detects voltage, current, and phase at RF input 13 of the matching network 11. Based on the RF input parameters detected by RF input sensor 21, control circuit 45 determines the input impedance.

[0072] Next, the control circuit 45 determines the plasma impedance presented by the plasma chamber 19 (step 502A). In one embodiment, the determination of the plasma impedance is based on the input impedance (determined in step 501A), the capacitance of the series EVC 31, and the capacitance of the shunt EVC 33. In another embodiment, the determination of the plasma impedance can be performed using an output sensor 49 operably coupled to the RF output, which is configured to detect RF output parameters. The RF output parameters can be any measurable parameters at the RF output 17, including voltage, current, or phase at the RF output 17. The RF output sensor 49 may also detect output parameters at the RF output 17 of the matched network 11. Based on the RF output parameters detected by the RF output sensor 21, the control circuit 45 may determine the plasma impedance. In yet another embodiment, the determination of the plasma impedance can be based on both RF output parameters and RF input parameters.

[0073] Once the variable impedance of the plasma chamber 19 is known, the control circuit 45 can determine changes to be made to one or both of the variable capacitances of the series EVC and shunt EVCs 31, 33 in order to achieve impedance matching. Specifically, the control circuit 45 determines a first capacitance value for the series variable capacitance and a second capacitance value for the shunt variable capacitance (step 503A). These values ​​represent new capacitance values ​​for the series EVC 31 and shunt EVC 33 to enable impedance matching, or at least substantial impedance matching. In an exemplary embodiment, the determination of the first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0074] Once the first and second capacitance values ​​are determined, the control circuit 45 generates a control signal to change at least one of the series variable capacitance and shunt variable capacitance to the first and second capacitance values, respectively (step 504A). This takes approximately t = -5 μs. The control signal instructs the switching circuit to change one or both of the series EVC 31 and shunt EVC 33 variable capacitances.

[0075] In an exemplary embodiment, while the EVC is changed, the RF source continues to supply RF signals to the RF input to the matched network. It is not necessary to stop supplying RF signals before changing the EVC. The determination of the new capacitance value and the change in EVC can be performed continuously (and repeatedly) while RF signals continue to be supplied to the matched network.

[0076] The changes in EVCs 31 and 33 take a total of approximately 9–11 microseconds, compared to approximately 1–2 seconds in an RF matching network using VVCs. Once the switch to the different variable capacitances is complete, there is a delay as the additional individual capacitors making up the EVCs couple and charge the circuit. This part of the matching tuning process takes approximately 55 microseconds. Finally, the RF power profile 403 shows a decrease from a peak-to-peak value of approximately 380 mV to a peak-to-peak value of approximately 100 mV just before t=56 microseconds. This decrease in the RF power profile 403 represents a decrease in reflected power 407, which occurs over a period of approximately 10 microseconds, at which point the matching tuning process is considered complete.

[0077] Changes in the series variable capacitance and the shunt variable capacitance can include transmitting a control signal to the series driver circuit 39 and the shunt driver circuit 43 to control the series variable capacitance and the shunt variable capacitance, respectively, where the series driver circuit 39 is operably coupled to the series EVC 31 and the shunt driver circuit 43 is operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to their desired capacitance values, the input impedance may match the fixed RF source impedance (e.g., 50 ohms), thus providing impedance matching. If sufficient impedance matching does not occur due to variations in the plasma impedance, the 500A process may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0078] The input impedance can be represented as follows using an RF matching network 11 (such as that shown in FIG. 3).

[0079]

Number

[0081] This determined plasma impedance (Z P ) and known desired

number

number

number

[0082]

number

[0083] Newly calculated

number

number

[0084] An exemplary method for calculating desired first and second capacitance values ​​and reaching those values ​​in a single step is significantly faster than stepping the two EVCs to either zero out the error signal or minimize the reflected power / reflection coefficient. In semiconductor plasma processing where a faster tuning scheme is desirable, this approach provides a significant improvement in the tuning speed of the matching network. It should be noted that the method for determining new EVC capacitance values ​​discussed herein is merely illustrative. In other embodiments, other parameters and / or methods may be used to determine new EVC capacitance values. For example, the parameters on which the new capacitance values ​​are based may be any parameters related to the plasma chamber.

[0085] Determining capacitance values ​​using a parameter matrix Figure 8 provides an alternative process 500 for impedance matching using a parameter matrix. In the exemplary process, the control circuit 45 (see Figure 3 for matching network components) is configured and / or programmed to perform each of the steps. As one of two initial steps, RF parameters are measured at RF input 13 by RF input sensor 21, and the input impedance at RF input 13 is calculated using the measured RF parameters (step 501). For this exemplary process 500, forward voltage and forward current are measured at RF input 13. In certain other embodiments, RF parameters may be measured at RF output 17 by RF output sensor 49, but such embodiments may require calculations different from those described below. In yet another embodiment, RF parameters may be measured at both RF input 13 and RF output 17.

[0086] An impedance matching circuit connected between the RF source 15 and the plasma chamber 19 may be characterized by one of several types of parameter matrices known to those skilled in the art, including a two-port parameter matrix. The S-parameter matrix and the Z-parameter matrix are two examples of such parameter matrices. Other examples include, but are not limited to, the Y-parameter matrix, G-parameter matrix, H-parameter matrix, T-parameter matrix, and ABCD-parameter matrix. Those skilled in the art will also recognize that these various parameter matrices can be mathematically converted to one another for electrical circuits such as matching networks. A second initial step of the exemplary process 500 is to look up the parameter matrix for the existing configuration of the impedance matching circuit in a parameter lookup table (step 502). The existing configuration of the impedance matching circuit is defined by the existing operating parameters of the impedance matching circuit, in particular the existing array configuration for both the series EVC 31 and the shunt EVC 33. To achieve impedance matching, the existing configuration of the impedance matching circuit is changed to a new configuration of the impedance matching circuit as part of the exemplary process 500.

[0087] The parameter lookup table includes multiple parameter matrices, each parameter matrix associated with a specific configuration of the serial EVC 31 and shunt EVC 33. The parameter lookup table may include one or more of the parameter matrices of the types described above. In exemplary process 500, the parameter lookup table includes at least several S-parameter matrices. In certain embodiments, the parameter lookup table may include at least several Z-parameter matrices. In embodiments in which the parameter lookup table includes multiple types of parameter matrices, different types of parameter matrices are associated within the parameter lookup table in such a way that the need for mathematical transformations between different types of parameter matrices is eliminated. For example, a T-parameter matrix may be included as part of the parameter lookup table, each T-parameter matrix associated with a corresponding S-parameter matrix resulting from a transformation between two matrices.

[0088] The input impedance calculation (step 501) and parameter matrix lookup (step 502) may be performed in any order. After the input impedance is calculated (step 501) and the parameter matrix for the existing configuration of the impedance matching circuit is identified in the parameter lookup table (step 502), the plasma or load impedance may be calculated using the calculated input impedance and the parameter matrix for the existing configuration (step 503). Next, from the calculated plasma impedance, matching configurations of the series EVC 31 and shunt EVC 33 that will achieve impedance matching, or at least substantial impedance matching, between the RF source 15 and the plasma chamber 19 are retrieved in the array configuration lookup table (step 504). These matching configurations from the array configuration lookup table are array configurations that result in new capacitance values ​​for the series EVC 31 and shunt EVC 33, and impedance matching is achieved with the new array configuration and the associated new capacitance values. The array configuration lookup table is a table of array configurations for series EVCs 31 and shunt EVCs 33, and when used in combination, it includes each possible array configuration for series EVCs 31 and shunt EVCs 33. As an alternative to using the array configuration lookup table, the actual capacitance values ​​of EVCs 31 and 33 may be calculated during the process, but such real-time calculations of capacitance values ​​are inherently more time-consuming than searching for a matched configuration in the array configuration lookup table. After the matched configurations for series EVCs 31 and shunt EVCs 33 are identified in the array configuration lookup table, one or both of the series and shunt array configurations are changed to the identified matched configurations for series EVCs 31 and shunt EVCs 33, respectively (step 505).

[0089] The change between the series array configuration and the shunt array configuration (step 505) may include the control circuit 45 transmitting control signals to the series driver circuit 39 and the shunt driver circuit 43 to control the series array configuration and the shunt array configuration, respectively, the series driver circuit 39 being operably coupled to the series EVC 31 and the shunt driver circuit 43 being operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to a matched configuration, the input impedance may be matched to a fixed RF source impedance (e.g., 50 ohms), thus resulting in impedance matching. If sufficient impedance matching does not occur due to fluctuations in plasma impedance, the process 500 may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0090] The lookup tables used in the process described above are compiled before the RF matched network is used in conjunction with the plasma chamber 19. In creating the lookup tables, the RF matched network 11 is tested before use in the plasma chamber to determine at least one parameter matrix of each type and the load impedance associated with each array configuration of the series EVC 31 and shunt EVC 33. The parameter matrices resulting from the testing are compiled into a parameter lookup table so that at least one parameter matrix of each type is associated with the respective array configurations of the EVCs 31 and 33. Similarly, the load impedances are compiled into an array configuration lookup table so that each parameter matrix is ​​associated with the respective array configurations of the EVCs 31 and 33. The compiled lookup tables may also take into account other factors related to the operation of the RF matched network, such as the fixed RF source impedance (e.g., 50 ohms), the power output of the RF source, and the operating frequency of the RF source. Thus, each lookup table may have tens of thousands or more entries to consider all possible configurations of the EVCs 31 and 33. The number of possible configurations is primarily determined by the number of individual fixed capacitors that make up each of the EVCs 31 and 33. When compiling the lookup tables, possible safety limits, such as the maximum allowable voltage and current at critical locations in the matched network, may be considered, which may serve to exclude one or more entries in the lookup tables for specific configurations of the EVCs 31 and 33.

[0091] As is well known in this art, an S-parameter matrix is ​​composed of components called scattering parameters, or S-parameters for short. The S-parameter matrix of an impedance matching circuit consists of four S-parameters, namely S 11 S 12 S 21 S 22It has four such parameters, each representing the ratio of the voltages at RF input 13 and RF output 17. All four S-parameters of the impedance matching circuit are determined and / or calculated in advance so that the entire S-parameter matrix is ​​known. The parameters of other types of parameter matrices may similarly be determined and / or calculated in advance and incorporated into the parameter matrix. For example, the Z-parameter matrix of an impedance matching circuit has four Z-parameters, namely Z 11 , Z 12 , Z 21 , Z 22 It has.

[0092] By compiling parameter lookup tables in this manner, the total time cost of any particular calculation occurs during the testing phase of the RF matching network and not during the actual use of the RF matching network 11 with the plasma chamber 19. Furthermore, since retrieving values ​​in a lookup table can take less time than calculating those same values ​​in real time, using a lookup table can help reduce the overall time required to achieve impedance matching. In plasma deposition or etching processes that potentially involve hundreds or thousands of impedance matching adjustments throughout the entire process, this time saving can directly translate to cost savings in the overall manufacturing process.

[0093] From the start of the matching tuning process, which begins with the control circuit determining the variable impedance of the plasma chamber and the matching configuration of the series and shunts, to the end of the matching tuning process, when the RF power reflected toward the RF source decreases, the entire matching tuning process of an RF impedance matching network using an EVC has an elapsed time of approximately 110 μs, or approximately 150 μs or less. This short elapsed time for a single iteration of the matching tuning process represents a significant increase compared to a VVC matching network. Furthermore, due to this short elapsed time for a single iteration of the matching tuning process, an RF impedance matching network using an EVC may perform the matching tuning process iteratively, repeating the two determination steps to generate another control signal for further changes in the array configuration of one or both of the electronically variable capacitors. By iteratively repeating the matching tuning process, it is expected that better impedance matching can be achieved within approximately 2 to 4 iterations of the matching tuning process. Furthermore, depending on the time required for each iteration of the matching tuning process, it is expected that 3 to 4 iterations can be performed in 500 μs or less. Considering the 1-2 second matching time for a single iteration of the matching and tuning process for RF impedance matching networks using VVCs, the ability to perform multiple iterations in a short amount of time represents a significant advantage of RF impedance matching networks using EVCs.

[0094] Those skilled in the art will recognize that several factors can contribute to the sub-millisecond duration of the impedance matching process in an RF impedance matching network using an EVC. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the driver circuit used. Other factors not listed may also contribute to the overall duration of the impedance matching process. Therefore, the total time required for the matching and tuning process for an RF impedance matching network with an EVC is expected to be approximately 500 microseconds or less, from the start of the process (i.e., measurement by the control circuit and calculation of the adjustments necessary to create impedance matching) to the end of the process (the point at which the efficiency of the RF power coupled into the plasma chamber increases due to impedance matching and reduction of reflected power). Even a matching and tuning process of around 500 microseconds still represents a significant improvement over RF impedance matching networks using a VVC.

[0095] Table 1 presents data comparing the operating parameters of one example EVC and one example VVC. As can be seen, EVC offers several advantages in addition to enabling high-speed switching for RF impedance matching networks. [Table 1]

[0096] As can be seen, in addition to the high-speed switching capability enabled by EVC, EVC also offers advantages in terms of reliability, current operation, and size. Further advantages of RF impedance matching networks that use the switching circuit itself for EVC and / or EVC include: The disclosed RF impedance matching network contains no moving parts, thus reducing the possibility of mechanical failure to that of other complete electrical circuits that could be used as part of a semiconductor manufacturing process. For example, a typical EVC may be formed from a highly durable ceramic substrate with copper metallization to form individual capacitors. The removal of moving parts also increases resistance to failure due to thermal fluctuations during use. EVCs are more compact in size compared to VVCs, and as a result, the reduction in weight and volume can save valuable space within the manufacturing facility. • EVC design offers an increased ability to customize RF matching networks for specific design needs of particular applications. EVCs may consist of custom capacitance ranges, one example being nonlinear capacitance ranges. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. As another example, custom capacitance ranges can provide greater resolution in specific areas of impedance matching. Custom capacitance ranges can also enable the generation of higher ignition voltages to facilitate plasma collisions. A short matching and tuning process (approximately 500 μs or less) allows the RF impedance matching network to withstand plasma changes within the manufacturing process, thereby increasing plasma stability and providing more controlled power to the manufacturing process. In RF impedance matching networks, using digitally controlled EVCs instead of mechanical devices provides more opportunities to fine-tune the control algorithms through programming. • EVC exhibits superior low-frequency (kHz) performance compared to VCC.

[0097] Balance the RF voltage across the series-connected PIN diodes. As described above, PIN diodes may be used as solid-state switches in RF matching networks, such as the matching networks shown in Figures 1-3. (The following discussion will focus on PIN diodes, but those skilled in the art will understand that this discussion can also be applied to NIP diodes.) As described above, the EVC may be equipped with fixed capacitors, each of which has a switching circuit for switching the input and output of the fixed capacitor. For example, the EVC may utilize the switching circuit 140A shown in Figure 6. In this switching circuit 140A, the switch is a single PIN diode 161A.

[0098] PIN diodes are effective RF switches because they have very low leakage current and capacitance when off. These characteristics allow PIN diodes to appear like an open circuit when off. Some commercially available PIN diodes have a maximum blocking voltage of several thousand volts. This maximum blocking voltage is commonly called the reverse breakdown voltage. Above this voltage, the device will fail in an avalanche. This breakdown voltage limits the useful power range of the PIN diode. PIN diodes also have a maximum current rating when on. This finite current rating also limits the maximum useful power range of the diode. Multiple diodes may be arranged in series and parallel to create a high-power RF switch using PIN diodes. Figure 9 provides an example of such a PIN diode array. Adding PIN diodes in series increases the maximum blocking voltage of the diode-based switch 261A, and connecting PIN diodes in parallel increases the overall current-carrying capacity of switch 261A. Adding PIN diodes in this way increases the overall voltage and current carrying capacity of the switch, while it is even more desirable that diodes D1-D9 equally share the RF potential, effectively and efficiently preventing any one device from experiencing avalanche.

[0099] An exemplary PIN diode switch is turned on using a forward bias current. In high-power applications, this current may be approximately 0.5A. This forward bias current puts the PIN diode into a low-resistance conduction state. In the off or blocked state, the exemplary PIN diode receives a reverse voltage from cathode to anode that is greater than the circuit's peak RF potential. This ensures that the PIN diode remains in a reverse-biased state and does not conduct forward. When multiple PIN diodes are connected in series, it is desirable that the reverse blocking voltage is equally shared among each PIN diode. If the RF potential across one of the diodes exceeds the DC blocking voltage across that diode, it will enter conduction mode.

[0100] Balance resistors can be used to balance the voltage across each PIN diode (see, for example, balance resistor 169A(R1-R3) in Figure 9). In exemplary embodiments, the resistors are significantly lower than the leakage resistance across the PIN diodes, but the resistance is not too low, or it would dissipate excess power. In certain embodiments, the balance resistors are the same value (e.g., 10 MΩ), but the present invention is not so limited.

[0101] In high-power applications, PIN diodes often require cooling, and heat sinks are used to dissipate heat. Figure 10 shows one potential arrangement for heat dissipation. Specifically, Figure 10 shows a PIN diode 251 mounted on (and potentially manufactured on) a thermally conductive but electrically non-conductive substrate 252. The substrate may have copper traces for establishing electrical connections. The substrate may, but is not limited to, ceramic. The substrate is preferably an electrical insulator and a good thermal conductor. This allows for electrical isolation of the PIN diode from the package or heat sink, while the thermal impedance from the junction to the case remains low. The substrate 252 is positioned on a heat sink 253. The substrate may be clamped to the heat sink, and thermal grease is applied between them. The heat sink is typically grounded and made of a metallic conductive material, but the present invention is not so limited. As will be discussed in more detail below, parasitic capacitance 254 consequently arises between the PIN diode 251 and conductive heat 253.

[0102] The balance resistor 169A in Figure 9 may balance the DC blocking voltage, but it may not be able to properly balance the RF voltage. At higher frequencies, the capacitance reactance of the PIN diode junction capacitance may be less than the value of the DC balance resistor. At this point, the junction capacitance may become the main cause of balancing the RF voltage across the series-connected PIN diodes. Furthermore, when multiple PIN diodes are connected in series, the junction capacitance and the capacitance from the die to ground create a voltage divider. This voltage divider affects the voltage division across the PIN diodes. As a result, this unequal voltage distribution limits the useful range of the series-connected PIN diodes. Figure 9 shows these parasitic capacitances 171. Cp1-4 are the capacitances from the die to the heatsink, and Cj1-3 are the capacitances from cathode to anode of the off-state PIN diode.

[0103] In ideal conditions, the blocking voltage is evenly divided among the PIN diodes. For example, if three diodes are used and the DC blocking voltage is 3kV, the blocking voltage will be evenly divided so that there is 1kV between each diode. The RF potential will also be evenly divided.

[0104] Figure 11 is a graph of the voltage across the diodes in the diode-based switch of Figure 9, based on a simulation. The model used a 3kV, 17A PIN diode. This diode has a junction capacitance of 2.2pF and a leakage current of 10uA at 3kV. A 13MHz frequency source was used with an amplitude of 2500V. A DC blocking voltage of 3kV was used.

[0105] Waveforms 201-203 in Figure 11 show how the voltage across each PIN diode switch is affected by parasitic capacitance from the die to ground. Waveform 201 shows the voltage across the first diode D1. This diode D1 has the maximum RF voltage across it. Waveform 202 shows the voltage across the second diode D2. This diode D2 has the second maximum potential. Waveform 203 shows the voltage across the third diode D3. This diode D3 has the minimum RF voltage across it. The voltage across D1 exceeds a blocking voltage of 1kV. As a result, D1 conducts forward for a portion of the sinusoidal wave. [Heat sink float]

[0106] One way to eliminate parasitic capacitance to ground is to remove ground by making the heatsink levitate. In this case, the heatsink acts as ground. In this case, the additional parasitic capacitance Cp5 lies between the levitating heatsink and the circuit ground. This option is shown in Figure 9 as parasitic capacitance Cp5.

[0107] Figure 12 is a graph of the voltage across the diodes in the diode-based switch of Figure 9, using a floating heatsink. In this simulation, a very small capacitance of 0.1 pF was used to model the capacitance from the heatsink to ground, and a very high resistance of 1000 MΩ was used to model the resistance from the heatsink to ground.

[0108] Figure 12 shows that the voltages across the PIN diodes are not equal. Waveform 204 is the voltage across D1, waveform 205 is the voltage across D2, and waveform 206 is the voltage across D3. The voltages are not equal because the heatsink acts like a floating ground plane. The parasitic capacitances from the PIN diodes to the floating ground are coupled together. Since these capacitances are not equal across each diode, the voltages are unbalanced. One possible solution to this problem is to use a separate floating heatsink for each PIN diode die. This would eliminate the common coupling path between the parasitic capacitances. However, this approach may not be practical from a mechanical mounting standpoint because the heatsinks can be large.

[0109] [Unbalanced resistors] As shown in Figure 11, the voltages across the PIN diodes are not equal, and the diode with the highest voltage potential is forward conductive. This occurs because the DC blocking voltage is not greater than the RF potential across this diode. One solution to this problem is to use unequal values ​​for the balance resistors. In one embodiment, referring again to Figure 9, R1 is 15 MΩ, R2 is 10 MΩ, and R3 is 5 MΩ. Figure 13 shows the simulation results. Waveform 207 is the voltage across diode D1, waveform 208 is the voltage across diode D2, and waveform 209 is the voltage across diode D3. Figure 13 shows the simulation results. The DC blocking voltage across each diode is proportional to the unequal RF potentials. The RF waveform is centered on the DC offset. Now all three diodes remain off and do not conduct in the forward direction. However, if the RF potential across one of the diodes is greater than the diode's reverse voltage rating, the diode will still avalanche, which can destroy the device. In this approach, the total voltage rated potential of the series-connected diodes cannot be obtained unless the voltage across each diode is equally divided.

[0110] [Balanced Capacitor] Since the unequal voltage distribution is the result of a series of equal voltage divisions created by parasitic capacitance, one solution is to restore the balance of the voltages across each diode using a lumped or integrated printed balancing capacitor. In one embodiment, the printed capacitor is formed on a substrate with copper traces and utilizes the dielectric constant of the substrate material, but the present invention is not limited thereto.

[0111] Figure 14 shows a diode-based switch 162B utilizing a balanced capacitor 170B (Cb1, Cb2) according to one embodiment. As shown, the balanced capacitors Cb1 and Cb2 are added across the first and second diodes 173 and 174 of each string 168B, respectively, to change the voltage division between them during the off state. Although not shown, it is also possible to add a balanced capacitor across the last diode 175 of each string 168B. In the exemplary embodiment, the cathode-to-anode parasitic capacitance would be used in place of the capacitor on the last diode 175 (D3, D6, D9). Furthermore, in this embodiment, the balance resistor 169B is of equal value because the balanced capacitor 170B causes the RF potential to be equal across each diode, but the present invention is not limited in this way. In other embodiments, the balance resistor may be omitted.

[0112] In Figure 14, switch 162B is shown having a string 168B of series-connected diodes. Three strings 168B are shown, but in other embodiments, any number of strings may be present. Each of the series-connected diodes is a PIN diode, but alternatively, the diodes can be NIP diodes. For each string 168B, at least one of the diodes has a balanced capacitor 170B in parallel with the diode. In this example, the first diode 173 of each string is in parallel with the balanced capacitor Cb1, and the second capacitor 174 of each string is in parallel with the balanced capacitor Cb2. The third diode 175 has a parallel balanced capacitor, but in other embodiments, these diodes 175 may have balanced capacitors.

[0113] In this exemplary embodiment, the diodes of string 168B are arranged in an array such that the first diode D1 of the first string 176 is in parallel with the first diodes D4 and D7 of the other strings 177 and 178, respectively, and the second diode D2 of the first string 176 is connected in parallel with the second diodes D5 and D6 of the other strings, respectively. Furthermore, each first diode 173 of string 168B shares a common first balance capacitor Cb1, and each second diode 174 of string 168B shares a common second balance capacitor Cb2. In addition, in this embodiment, each first diode 173 of string 168B shares a common first balance resistor R1 connected in parallel with the first diode 173, and each second diode 174 of string 168B shares a common second balance resistor R2 connected in parallel with the second diode 174.

[0114] The values ​​of the balanced capacitors may be different or the same. These values ​​may be selected by various methods and may depend on the specific switches used, the values ​​of the diodes, the expected parasitic capacitance values, the values ​​of the resistors, etc. Methods may be used to calculate the capacitance values, while trial and error may be used instead to determine the capacitance values ​​that are most effective in allowing the voltage to be divided evenly (or nearly evenly) across each diode.

[0115] Figure 15 shows an alternative configuration for utilizing a balanced capacitor within a diode-based switch 162C. This configuration is identical to Figure 14, except that the diodes in a given row of the array (e.g., the first diode 173C (D1, D4, D7)) are not connected in parallel with each other. In this case, instead of having a balanced capacitor (e.g., Cb1) in parallel with each row (e.g., the first diode 173C), there are separate balanced capacitors in parallel with each diode in the first and second diode rows 173C, 174C. In this embodiment, the last row of diodes 175C does not have a balanced capacitor. In other embodiments, the diodes in the last row may also have their own balanced capacitors. In other words, diode D1 has a balanced capacitor Cb11, diode D2 has a balanced capacitor Cb21, diode D4 has a balanced capacitor Cb12, diode D5 has a balanced capacitor Cb22, diode D7 has a balanced capacitor Cb1n, and diode D2 has a balanced capacitor Cb2n. Although the balance resistor is omitted in this figure, it may be included as in Figure 14.

[0116] Figure 16 below is a schematic simulation of a diode-based switch 162D utilizing an array of balanced capacitors and resistors similar to that in Figure 14. For diodes D1, D2, and D3, the simulation used 3kV 17A PIN diodes with a junction capacitance of 2.2pF and a leakage current of 10uA at 3kV. A 13MHz frequency source V1 (connected to ground 40) was used with an amplitude of 2500V. A DC blocking voltage of 3kV was used. Note that the simulation schematic in Figure 16 is simplified. The voltage source V1 may also include a DC offset voltage (e.g., 3kV). The DC offset voltage may be used to simulate the blocking voltage typically supplied to the cathode of the PIN diode through a choke. This choke may also be used to alternatively supply a forward bias voltage (e.g., -5V) when the switch is ON.

[0117] A single first string 168D of PIN diodes D1, D2, and D3 is used, which has corresponding balance resistors 169D (Rb1, Rb2, Rb3) to evenly distribute the 3kV blocking voltage. In this simulation, each of the balance resistors 169D has a resistance of 10MΩ. The first two diodes D1 and D2 have corresponding balance capacitors 170D. Balance capacitor Cb1 has a capacitance of 3pF, and balance capacitor Cb2 has a capacitance of 1pF. Parasitic capacitances 171 are also represented, Cp1, Cp2, and Cp3 respectively. A bias inductor Lbias (1m) was used as an RF choke. This has a high impedance at the operating frequency, which provides a DC return path for the DC blocking voltage and forward bias voltage. In addition, a DC blocking capacitor C1 was used to block the DC blocking voltage, but to allow RF to pass through. Resistor Rl (10MΩ) is the RF load.

[0118] Figure 17 is a graph of the voltage across the diodes in the diode-based switch of Figure 15, utilizing a balanced capacitor, according to one embodiment. As can be observed, the RF potentials are balanced, and the voltage across each diode is represented by waveform 210.

[0119] As described above, the diode-based switches discussed herein may be incorporated into EVCs used in RF matching networks. Such matching networks for impedance matching may be used in semiconductor processing tools. Such matching networks may also be used in impedance matching methods and / or in methods for manufacturing semiconductors that involve impedance matching.

[0120] [Non-conductive heat sink] As mentioned above with respect to Figure 10, the use of an electrically conductive metal heatsink can lead to parasitic capacitance 254, which causes an imbalance in the RF potential across the diodes in a diode-based switch. The above solution uses a balanced capacitor to address this problem and balance the RF potential.

[0121] Another approach to maintaining RF potential balance between diodes is to use a non-conductive heatsink, as shown in Figure 18. In this approach, the heatsink 255 is fabricated from a material that is thermally conductive but electrically insulating. The diode 251 of a diode-based switch is positioned directly on the non-conductive heatsink, in contrast to the diode 251 being positioned on a non-conductive substrate that is positioned on a conductive heatsink. In certain embodiments, the heatsink contains or is fabricated from ceramic materials such as beryllium oxide (BeO), aluminum nitride (AlN), or alumina ceramic (Al2O3). These materials are effective thermal conductors and also effective electrical insulators. There are also numerous composite materials that can be used instead of ceramics. The heatsink may be air-cooled or water-cooled.

[0122] When the conductive properties of the heatsink are removed, the schematic circuit is similar to that in Figure 9, but without the parasitic capacitance 171. Therefore, the RF potential is evenly balanced between diodes 251 and 168A.

[0123] As described above with respect to Figure 10, when the PIN diode array is manufactured on a non-conductive substrate, the substrate may have copper traces on it to establish electrical connections. Components may be soldered to the substrate. If the substrate is mounted on a conductive heatsink, it may be clamped to the heatsink, and thermal grease may be applied between them. However, the grease adds extra thermal impedance to the assembly and raises the temperature of the components mounted on the assembly. To make the non-conductive heatsink and the circuit ceramic substrate a single homogeneous part, the substrate clamp and thermal grease may be removed by removing the conductive heatsink. According to this embodiment, the circuit can be manufactured directly on top of the ceramic heatsink.

[0124] In addition to eliminating (or reducing) voltage imbalances between the diodes of the switch, it should be noted that the non-conductive heatsink in Figure 18 may offer another advantage. In L-type matching (such as that shown in Figure 2), parasitic capacitance from the series output capacitor (see, for example, series capacitor 31 in Figure 2) to ground can be problematic because this capacitance can limit the matching network range. As discussed herein, parasitic capacitance may occur when the switching circuit is placed on a ceramic substrate that is sequentially clamped to a grounded conductive heatsink. This is particularly evident at higher frequencies where the reactance of this parasitic capacitance is low. By mounting the capacitor array on a ceramic heatsink, the parasitic capacitance may be eliminated, thus increasing the tuning range. Alternatively, the conductive heatsink can be floated.

[0125] It should be noted that while the embodiments of the matched networks discussed herein have used L or pi configurations, the matched network covered by the claims may consist of other matched network configurations, such as a "T" configuration. Unless otherwise stated, the variable capacitors, switching circuits, and methods discussed herein may be used in any configuration suitable for an RF impedance matched network.

[0126] It should be noted that the embodiments discussed herein may use one or more variable capacitors in a matching network to achieve impedance matching, while also using any variable reactance elements. The variable reactance elements may include one or more individual reactance elements, which are capacitors, inductors, or similar reactive devices.

[0127] This application incorporates, by reference, the entirety of U.S. Patent No. 10,460,912, U.S. Patent Publication No. US2021 / 0327684, U.S. Patent Publication No. US2021 / 0327684, and U.S. Patent No. 10,984,985, all owned by the same owner.

[0128] While the present invention has been described in relation to specific embodiments, including current preferred methods of implementation, those skilled in the art will understand that there are numerous variations and modifications of the systems and techniques described above. Naturally, other embodiments may be utilized and structural and functional modifications may be made without departing from the scope of the invention. Therefore, the spirit and scope of the invention should be interpreted broadly as set forth in the appended claims. [Explanation of Symbols]

[0129] 11. Integrity Network 13 RF input 15 RF source 17 RF output 19 Plasma Chamber 21 sensors 23 First electrode 25 Second electrode 27 Base material 31 Series Capacitors 33 Shunt Capacitor 35 Series Inductors 37 RF choke and filter circuit 39 Driver Circuit 41 RF choke and filter circuit 43 Driver Circuit 45 Control circuits 47 Power supply 49 Sensors 85A Semiconductor Processing System 86 Semiconductor Processing Tools 105A input 107A Common Output 111A First power switch 113 input 113A Second power switch 115 High-voltage power supply 117 Low-voltage power supply 129 Command Input 130 Output 137 RF Choke and Filter Circuit 139 Driver Circuit 140A, B switching circuit 141A, B filters 145 Control circuits 150 circuits 151 EVC 151a First capacitor array 151b Second capacitor array 153A, B Fixed Capacitor 153 Capacitors 155 Variable Capacitance System 161 switches 162B, C, D switch 163A current 164A Sensor 165A node Node 166A 167A current 168A, B, D strings 169A, B, D Balance Resistors 170B,D Balanced Capacitor 171 Parasitic capacitance 173 First diode 174 Second Capacitor 175 Third Diode 176 First String 177 Strings 178 strings 201-210 waveform 251 diodes 252 Base material 253 Heatsink 254 Parasitic capacitance 255 Heatsink 261 switches 407 Reflected power

Claims

1. A radio frequency (RF) impedance matching circuit, An RF input configured to be operably connected to an RF source that provides an RF signal, An RF output configured to be operably connected to the plasma chamber, At least one electronically variable capacitor (EVC), wherein each of the at least one EVC comprises a fixed capacitor, and each of the fixed capacitors has a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, A control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC in order to enable impedance matching, Equipped with, Each switching circuit for each fixed capacitor of each EVC, A switch operably connected to the fixed capacitor to cause switching of the input and output of the fixed capacitor, wherein the switch comprises at least one string of series-connected diodes, and each of the series-connected diodes is a PIN diode or a NIP diode, For each of the at least one string, at least one of the diodes in the string has a balanced capacitor in parallel with the diode. Radio frequency (RF) impedance matching circuit.

2. The impedance matching circuit according to claim 1, wherein the value of each balance capacitor is based on the expected value of one or more parasitic capacitances in the switching circuit when the balance capacitors are not present.

3. The impedance matching circuit according to claim 1, wherein the at least one string of series-connected diodes includes at least two strings of series-connected diodes connected in parallel with each other.

4. The diodes of at least two strings are arranged in an array such that the first diode of the first string is in parallel with the first diode of each of the other strings, and the second diode of the first string is connected in parallel with the second diode of each of the other strings. The impedance matching circuit according to claim 3, wherein each of the first diodes in at least two strings shares a common first balanced capacitor, and each of the second diodes in the strings shares a common second balanced capacitor.

5. The impedance matching circuit according to claim 4, wherein each of the first diodes in the string shares a common first balance resistor connected in parallel with the first diode, and each of the second diodes in the string shares a common second balance resistor connected in parallel with the second diode.

6. The impedance matching circuit according to claim 5, wherein the first and second balance resistors have equal resistance values.

7. The impedance matching circuit according to claim 4, wherein the first balancing capacitor has a capacitance value different from the capacitance value of the second balancing capacitor.

8. The impedance matching circuit according to claim 1, wherein each of the series-connected diodes is positioned on a substrate that conducts heat but does not conduct electricity, and the substrate is positioned on a heat sink that conducts electricity.

9. The impedance matching circuit according to claim 8, wherein the substrate includes a ceramic material.

10. A method for matching impedances, Connecting the radio frequency (RF) input of the matching circuit to an RF source that provides an RF signal, The RF output of the matching circuit is connected to the plasma chamber, wherein the matching circuit is At least one electronically variable capacitor (EVC), wherein each of the at least one EVC comprises a fixed capacitor, and each of the fixed capacitors has a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, A control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC in order to enable impedance matching, Equipped with, Each switching circuit for each fixed capacitor of each EVC, A switch operably connected to the fixed capacitor to cause switching of the input and output of the fixed capacitor, wherein the switch comprises at least one string of series-connected diodes, and each of the series-connected diodes is a PIN diode or a NIP diode, For each of the at least one string, at least one of the diodes in the string has a balanced capacitor in parallel with the diode. Connecting and The impedance is matched by at least one of the switching circuits of the at least one EVC, and the input and output of the corresponding fixed capacitor are switched to change the total capacitance of the EVC. Methods that include...

11. The method according to claim 10, wherein the value of each balance capacitor is based on the expected value of one or more parasitic capacitances in the switching circuit when the balance capacitor is not present.

12. The method according to claim 10, wherein at least one string of series-connected diodes includes at least two strings of series-connected diodes connected in parallel with each other.

13. The diodes of at least two strings are arranged in an array such that the first diode of the first string is in parallel with each of the first diodes of the other strings, and the second diode of the first string is connected in parallel with each of the second diodes of the other strings. The method according to claim 12, wherein each of the first diodes of at least two strings shares a common first balanced capacitor, and each of the second diodes of the strings shares a common second balanced capacitor.

14. Each of the first diodes in the string shares a common first balance resistor connected in parallel with the first diode, and each of the second diodes in the string shares a common second balance resistor connected in parallel with the second diode. The method according to claim 13, wherein the first and second balance resistors have equal resistance values.

15. It is a semiconductor processing tool, A plasma chamber configured to deposit a material onto a substrate or to etch a material from the substrate, The plasma chamber comprises an impedance matching circuit operably connected to it, wherein the matching circuit An RF input configured to be operably connected to an RF source that provides an RF signal, An RF output configured to be operably connected to the plasma chamber, At least one electronically variable capacitor (EVC), wherein each of the at least one EVC comprises a fixed capacitor, and each of the fixed capacitors has a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, A control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC in order to enable impedance matching, Equipped with, Each switching circuit for each fixed capacitor of each EVC, A switch operably connected to the fixed capacitor to cause switching of the input and output of the fixed capacitor, wherein the switch comprises at least one string of series-connected diodes, and each of the series-connected diodes is a PIN diode or a NIP diode, For each of the at least one string, at least one of the diodes in the string has a balanced capacitor in parallel with the diode. Semiconductor processing tools.

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