Semiconductor equipment

Abstract

This semiconductor device comprises: a first semiconductor element that switches between a conduction state and a cutoff state according to a first driving signal; a first control element that generates the first driving signal on the basis of a first input signal; a second semiconductor element that switches between a conduction state and a cutoff state according to a second driving signal; and a second control element that generates the second driving signal on the basis of a second input signal. The first control element receives the second input signal and determines whether the second semiconductor element is in the conduction state on the basis of the second input signal. When the second semiconductor element is in the conduction state, the first control element delays the switching of the first semiconductor element from the cutoff state to the conduction state.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] As one of various semiconductor devices, there is what is called an IPM (Intelligent Power Module). Such a semiconductor device includes a plurality of semiconductor elements, a plurality of control elements, and a lead frame (see Patent Document 1). Each of the plurality of semiconductor elements is a power semiconductor element that performs power control. The plurality of semiconductor elements includes a high-voltage-side semiconductor element and a low-voltage-side semiconductor element. The high-voltage-side semiconductor element and the low-voltage-side semiconductor element are connected in series to form upper and lower arms. The plurality of control elements control the driving of each of the plurality of semiconductor elements. The plurality of control elements includes a HVIC (High-Voltage IC) that controls the high-voltage-side semiconductor element and a LVIC (Low-Voltage IC) that controls the low-voltage-side semiconductor element. The lead frame supports the plurality of semiconductor elements and the plurality of control elements and forms conduction paths for them.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When each semiconductor element (the high-voltage-side semiconductor element and the low-voltage-side semiconductor element) of the upper and lower arms turns on simultaneously, a power short circuit (arm short circuit) occurs and a large current flows through each semiconductor element. The occurrence of such an arm short circuit is a factor that destroys each semiconductor element.

[0005] In view of the above circumstances, an object of this disclosure is to provide a semiconductor device capable of suppressing an arm short circuit caused by simultaneous on of the upper and lower arms. [Means for solving the problem]

[0006] The semiconductor device provided by this disclosure includes: a first semiconductor element that receives a first drive signal and switches between a conduction state and a disconnection state in response to the first drive signal; a first control element that receives a first input signal and generates the first drive signal based on the first input signal and outputs it to the first semiconductor element; a second semiconductor element that receives a second drive signal and switches between a conduction state and a disconnection state in response to the second drive signal; and a second control element that receives a second input signal and generates the second drive signal based on the second input signal and outputs it to the second semiconductor element. The first control element further receives the second input signal and determines, based on the second input signal, that the second semiconductor element is in a conduction state, and delays the switching of the first semiconductor element from the disconnection state to the conduction state. [Effects of the Invention]

[0007] According to the above configuration, arm short circuits caused by the simultaneous activation of the upper and lower arms can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a semiconductor device according to the first embodiment. [Figure 2] In the perspective view of Figure 1, the sealing member is indicated by dashed lines (two-dot lines). [Figure 3] This is a plan view showing a semiconductor device according to the first embodiment. [Figure 4] In the plan view of Figure 3, the sealing member is indicated by dashed lines (two-dot lines). [Figure 5] This is a magnified view of a portion of Figure 4. [Figure 6] This is a front view showing a semiconductor device according to the first embodiment. [Figure 7] This is a side view (right side view) of a semiconductor device according to the first embodiment. [Figure 8]It is a cross-sectional view taken along line VIII-VIII of FIG. 4. [Figure 9] It is a partial enlarged view enlarging a part of FIG. 8. [Figure 10] It is a partial enlarged view enlarging a part of FIG. 8. [Figure 11] It is a cross-sectional view taken along line XI-XI of FIG. 4. [Figure 12] It is a partial enlarged view enlarging a part of FIG. 11. [Figure 13] It is a diagram showing a circuit configuration example of a semiconductor device according to the first embodiment. [Figure 14] It is a timing chart showing an operation example of a semiconductor device according to the first embodiment. [Figure 15] It is a timing chart showing an operation example of a conventional semiconductor device. [Figure 16] It is a plan view showing a semiconductor device according to the second embodiment. [Figure 17] It is a diagram in which a sealing member is shown by an imaginary line (two-dot chain line) in the plan view of FIG. 16. [Figure 18] It is a partial enlarged view enlarging a part of FIG. 17. [Figure 19] It is a partial enlarged view enlarging a part of FIG. 17. [Figure 20] It is a partial enlarged view enlarging a part of FIG. 17. [Figure 21] It is a cross-sectional view taken along line XXI-XXI of FIG. 17. [Figure 22] It is a cross-sectional view taken along line XXII-XXII of FIG. 17. [Figure 23] It is a timing chart showing an operation example of a semiconductor device according to a modification. [Figure 24] It is a timing chart showing an operation example of a semiconductor device according to a modification. [Figure 25] It is a plan view showing a semiconductor device according to a modification, in which a sealing member is shown by an imaginary line (two-dot chain line). [Figure 26] It is a diagram showing a circuit configuration example of the semiconductor device shown in FIG. 25. [Figure 27]It is a timing chart showing an operation example of the semiconductor device shown in FIG. 25.

Embodiments for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, for the same and similar components, the same reference numerals will be given and duplicate explanations will be omitted.

[0010] FIGS. 1 to 13 show a semiconductor device A1 according to the first embodiment. As shown in these figures, the semiconductor device A1 includes a plurality of semiconductor elements 11 and 12, a plurality of protection elements 13, two control elements 2A and 2B, a plurality of electronic components 29, a plurality of leads 3A to 3G and 3Z, a plurality of leads 4A to 4P, a support substrate 51, a plurality of connection members 6, and a sealing member 7. The plurality of connection members 6 includes a plurality of wires 6A to 6K. The use of the semiconductor device A1 is not particularly limited, but it is configured as an IPM used for, for example, drive control of an inverter motor.

[0011] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a view showing the sealing member 7 in an imaginary line (two-dot chain line) in the perspective view of FIG. 1. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a view showing the sealing member 7 in an imaginary line (two-dot chain line) in the plan view of FIG. 3. FIG. 5 is a partially enlarged view of a part of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a side view (right side view) showing the semiconductor device A1. FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. 4. FIG. 9 is a partially enlarged view of a part of FIG. 8. FIG. 10 is a partially enlarged view of a part of FIG. 8. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 4. FIG. 12 is a partially enlarged view of a part of FIG. 11. FIG. 13 is a view showing a circuit configuration example of the semiconductor device A1.

[0012] In the following description, three directions orthogonal to each other, namely the x direction, the y direction, and the z direction, will be appropriately referred to. The z direction corresponds to, for example, the thickness direction of the semiconductor device A1.

[0013] Each of the semiconductor elements 11 and 12 is a functional element that enables the semiconductor device A1 to function as an IPM (Integrated Power Processor). Each semiconductor element 11 and 12 is a power semiconductor element that inputs and outputs, for example, the three-phase alternating current that is controlled in the IPM. Each semiconductor element 11 and 12 is, for example, an IGBT (Insulated-Gate Bipolar Transistor), a bipolar transistor, a MOSFET (Metal-Oxide-Semiconductor Field-effect Transistor), and a HEMT (High Electron Mobility Transistor). Each of the semiconductor elements 11 and 12 is composed of a semiconductor material. The semiconductor material may be, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride). In the example shown in Figures 1 to 12, the semiconductor device A1 comprises three semiconductor elements 11 and three semiconductor elements 12, but the number of semiconductor elements 11 and 12 is not limited to this. In the following, when distinguishing between the three semiconductor elements 11, they will be referred to as semiconductor elements 11A, 11B, and 11C. Similarly, when distinguishing between the multiple semiconductor elements 12, they will be referred to as semiconductor elements 12A, 12B, and 12C. Each semiconductor element 11 is an example of a "first semiconductor element," and each semiconductor element 12 is an example of a "second semiconductor element."

[0014] Each of the multiple semiconductor elements 11 has a main surface 11a and a back surface 11b, as shown in Figures 9 and 12. The main surface 11a and the back surface 11b are spaced apart in the z direction. The main surface 11a faces the z2 direction, and the back surface 11b faces the z1 direction. The main surface 11a and the back surface 11b are both flat (or substantially flat). In each semiconductor element 11, the back surface 11b faces the lead 3A.

[0015] Each of the multiple semiconductor elements 11 includes a first electrode 111, a second electrode 112, and a third electrode 113, as shown in Figures 4, 9, and 12. As shown in Figure 12, the first electrode 111 is provided on the back surface 11b of the element, and the second electrode 112 and the third electrode 113 are provided on the main surface 11a of the element. In the example where each semiconductor element 11 is a MOSFET or HEMT, the first electrode 111 is the drain electrode, the second electrode 112 is the source electrode, and the third electrode 113 is the gate electrode. Each semiconductor element 11 performs a switching operation in response to a drive signal (first drive signal) input to the third electrode 113. The switching operation in each semiconductor element 11 is the operation of switching between a conductive state and a disconnected state between the first electrode 111 and the second electrode 112.

[0016] Each of the multiple semiconductor elements 11 is bonded to the lead 3A via a conductive bonding material 191, as shown in Figures 8, 9, 11, and 12. The conductive bonding material 191 is, for example, solder, metal paste, or sintered metal.

[0017] Each of the multiple semiconductor elements 12 has a main surface 12a and a back surface 12b, as shown in Figure 10. The main surface 12a and the back surface 12b are spaced apart in the z direction. The main surface 12a faces the z2 direction, and the back surface 12b faces the z1 direction. The main surface 12a and the back surface 12b are both flat (or approximately flat). In each semiconductor element 12, the back surface 12b faces one of the leads 3B, 3C, or 3D, according to a configuration that will be described in detail later.

[0018] Each of the multiple semiconductor elements 12 includes a fourth electrode 121, a fifth electrode 122, and a sixth electrode 123, as shown in Figures 4 and 10. The fourth electrode 121 is provided on the back surface 12b of the element, and the fifth electrode 122 and sixth electrode 123 are provided on the main surface 12a of the element. In the example where each semiconductor element 12 is a MOSFET, the fourth electrode 121 is the drain electrode, the fifth electrode 122 is the source electrode, and the sixth electrode 123 is the gate electrode. Each semiconductor element 12 performs a switching operation in response to a drive signal (second drive signal) input to the sixth electrode 123. The switching operation in each semiconductor element 12 is the operation of switching between a conduction state and a disconnection state between the fourth electrode 121 and the fifth electrode 122.

[0019] Each of the multiple semiconductor elements 12 is bonded to one of the multiple leads 3B, 3C, or 3D via a conductive bonding material 192, as shown in Figures 8 and 10. The conductive bonding material 192 is, for example, solder, metal paste, or sintered metal.

[0020] Each of the multiple protection elements 13 is, for example, a freewheeling diode. As shown in Figure 4, one protection element 13 is provided for each of the multiple semiconductor elements 11 and 12. As can be seen from Figures 4, 11, and 12, each of the multiple protection elements 13 is bonded to the same leads 3A to 3D as each pair of semiconductor elements 11 and 12 via a conductive bonding material 193. The conductive bonding material 193 is, for example, solder, metal paste, or sintered metal. In configurations different from semiconductor device A1, it is not necessary to have multiple protection elements 13.

[0021] Each protective element 13 includes a first electrode 131 and a second electrode 132, as shown in Figure 11. The first electrode 131 is formed on the upper surface (the surface facing the z2 direction) of each protective element 13, and the second electrode 132 is formed on the lower surface (the surface facing the z1 direction) of each protective element 13. In the example where each protective element 13 is a diode, the first electrode 131 is the anode electrode and the second electrode 132 is the cathode electrode.

[0022] Each protection element 13 is connected in antiparallel to each semiconductor element 11 and 12. Antiparallel means that the forward current in each semiconductor element 11 and 12 and the forward current in each protection element 13 are connected in opposite directions. Specifically, as can be seen from Figure 11, the first electrode 131 of each protection element 13 is connected to the second electrode 112 of each semiconductor element 11 or the fifth electrode 122 of each semiconductor element 12, and the second electrode 132 of each protection element 13 is connected to the first electrode 111 of each semiconductor element 11 or the fourth electrode 121 of each semiconductor element 12. As a result, when a reverse voltage is applied to each semiconductor element 11 and 12, a forward current flows through each protection element 13, reducing the reverse voltage applied to each semiconductor element 11 and 12.

[0023] The two control elements 2A and 2B are control system semiconductor elements that control the operation of multiple semiconductor elements 11 and 12, and are, for example, driver ICs. Control element 2A controls the switching operation of each semiconductor element 11 by inputting a first drive signal (for example, gate voltage) to the third electrode 113 (gate electrode) of each semiconductor element 11. Control element 2A generates a first drive signal that causes each semiconductor element 11 to operate as an upper arm. Control element 2B controls the switching operation of each semiconductor element 12 by inputting a second drive signal (for example, gate voltage) to the sixth electrode 123 (gate electrode) of each semiconductor element 12. Control element 2B generates a second drive signal that causes each semiconductor element 12 to operate as a lower arm. Control element 2A is an example of a "first control element", and control element 2B is an example of a "second control element".

[0024] The two control elements 2A and 2B are joined to leads 4H and 4O via a bonding material 25, as shown in Figure 10. In semiconductor device A1, since no electrodes are formed on the underside (the surface facing the z1 direction) of each control element 2A and 2B, the bonding material 25 can be either conductive or insulating. If electrodes are formed on the underside of each control element 2A and 2B, a conductive material (such as solder, metal base material, or sintered metal) is used for the bonding material 25.

[0025] The multiple electronic components 29 are elements that assist the functions of the two control elements 2A and 2B, and are, for example, diodes. In the examples shown in Figures 2 and 4, there are three electronic components 29, but the number of electronic components 29 is not limited to this. When distinguishing between the three electronic components 29, they are referred to as electronic components 29U, 29V, and 29W. Each of the multiple electronic components 29 is bonded to leads 4A, 4B, and 4C, respectively, as shown in Figure 4. Each of the multiple electronic components 29 is bonded by a conductive bonding material 291, as shown in Figure 10. The conductive bonding material 291 is, for example, solder, metal paste, or sintered metal.

[0026] The semiconductor device A1 includes at least lead 4E (leads 4F, 4G) as the first lead, lead 4I (4J, 4K) as the second lead, lead 4H, 4O as the third lead, lead 3A as the fourth lead, lead 3B (3C, 3D) as the fifth lead, and lead 3E (3F, 3G) as the sixth lead. In this embodiment, it includes multiple leads 3A-3G, 3Z and multiple leads 4A-4P. As shown in Figures 2-4, the multiple leads 3A-3G, 3Z and the multiple leads 4A-4P support multiple semiconductor elements 11, 12, multiple protection elements 13, two control elements 2A, 2B, and multiple electronic components 29, and constitute conductive paths to these. Of the multiple leads 3A-3G, 3Z and the multiple leads 4A-4P, lead 4H and lead 4O are formed integrally, while the others are spaced apart from each other. The auxiliary line L1 shown in Figures 4 and 5 indicates the boundary between lead 4H and lead 4O, that is, the part where they are connected as a single unit. Alternatively, lead 4H and lead 4O may be considered as a single lead. In contrast to this example, lead 4H and lead 4O may be spaced apart from each other.

[0027] Multiple leads 3A-3G,3Z and multiple leads 4A-4P may be formed from different conductive materials or from a single conductive material. Multiple leads 3A-3G,3Z and multiple leads 4A-4P may be made of, for example, Cu or a Cu alloy. The constituent material of each of the multiple leads 3A-3G,3Z and multiple leads 4A-4P may be Ni or a Ni alloy, or a 42 alloy, etc. The constituent materials of each of the multiple leads 3A-3G,3Z and multiple leads 4A-4P may be the same or different.

[0028] When semiconductor device A1 is configured as an IPM, the motor drive current flows through multiple leads 3A to 3G, and the control current flows through multiple leads 4A to 4P. Therefore, a higher voltage is applied to multiple leads 3A to 3G than to multiple leads 4A to 4P, and a larger current flows through them. As shown in Figure 4, in this embodiment, the multiple leads 3A to 3G and 3Z on the high-voltage side and the leads 4A to 4P on the low-voltage side are arranged on opposite sides in the y-direction.

[0029] The lead 3A is configured to support each semiconductor element 11, as will be described in detail later, and is electrically connected to the first electrode 111 of each semiconductor element 11. As shown in Figure 4 and other figures, the lead 3A includes a mounting portion 31A, a terminal portion 32A, a pad portion 33A, and a connecting portion 34A.

[0030] The mounting portion 31A is covered by a sealing member 7. As shown in Figures 4, 11, and 12, a plurality of semiconductor elements 11 and a plurality of protective elements 13 are mounted on the mounting portion 31A. The mounting portion 31A is electrically connected to the first electrode 111 of each semiconductor element 11 via a conductive bonding material 191, and is electrically connected to the second electrode 132 of each protective element 13 via a conductive bonding material 193. In other words, the first electrode 111 and the second electrode 132 are electrically connected to each other via the mounting portion 31A. As shown in Figures 8, 9, 11, and 12, the mounting portion 31A is bonded to the support substrate 51 via a bonding material 39. The bonding material 39 may be conductive or insulating. Preferably, the bonding material 39 has excellent thermal conductivity.

[0031] As shown in Figure 4, the terminal portion 32A is the part of the lead 3A that protrudes from the sealing member 7. In the y-direction, the terminal portion 32A protrudes from the mounting portion 31A on the opposite side from the leads 4A to 4P. The terminal portion 32A is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32A is bent upward in the z-direction to form an L-shape.

[0032] The pad portion 33A and the connecting portion 34A are covered by the sealing member 7. As shown in Figure 4, the pad portion 33A and the connecting portion 34A are interposed between the mounting portion 31A and the terminal portion 32A. The pad portion 33A is located on the z2 side relative to the mounting portion 31A and is connected to the terminal portion 32A. As shown in Figure 11, the connecting portion 34A is connected to both the mounting portion 31A and the pad portion 33A and is inclined with respect to the y direction.

[0033] As shown in Figures 3 and 4, leads 3B, 3C, and 3D are positioned in the x1 direction relative to lead 3A. Leads 3B, 3C, and 3D are aligned in the x direction. The shapes of leads 3B, 3C, and 3D are not particularly limited, and in the illustrated example, leads 3B, 3C, and 3D are the same shape (or nearly the same shape) and the same size (or nearly the same size).

[0034] Lead 3B is on which the semiconductor element 12A is mounted. Lead 3B is electrically connected to the second electrode 112 of semiconductor element 11A and the fourth electrode 121 of semiconductor element 12A by a configuration that will be described in detail later. As shown in Figure 4, lead 3B includes a mounting portion 31B, a terminal portion 32B, a pad portion 33B, and a connecting portion 34B.

[0035] The mounting section 31B is covered by the sealing member 7. As shown in Figure 4, a semiconductor element 12A and a protective element 13 are mounted on the mounting section 31B. The mounting section 31B is electrically connected to the fourth electrode 121 of the semiconductor element 12A via the conductive bonding material 192, and is also electrically connected to the second electrode 132 of the protective element 13 via the conductive bonding material 193. In other words, the fourth electrode 121 and the second electrode 132 are electrically connected to each other via the mounting section 31B.

[0036] As shown in Figure 4, the terminal portion 32B is the part of the lead 3B that protrudes from the sealing member 7. In the y-direction, the terminal portion 32B protrudes from the mounting portion 31B on the opposite side from the leads 4A to 4P. The terminal portion 32B is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32B is bent upward in the z-direction to form an L-shape.

[0037] The pad portion 33B and the connecting portion 34B are covered by the sealing member 7. As shown in Figure 4, the pad portion 33B and the connecting portion 34B are interposed between the mounting portion 31B and the terminal portion 32B. The pad portion 33B is located above the mounting portion 31B in the z direction (z2 direction), similar to the pad portion 33A. The pad portion 33B is connected to the terminal portion 32B. The wire 6A is joined to the pad portion 33B. The connecting portion 34B is connected to the mounting portion 31B and the pad portion 33B, and is inclined with respect to the y direction, similar to the connecting portion 34A.

[0038] Lead 3C is on which the semiconductor element 12B is mounted. Lead 3C is electrically connected to the second electrode 112 of semiconductor element 11B and the fourth electrode 121 of semiconductor element 12B, as will be described in detail later. As shown in Figure 4, lead 3C includes a mounting portion 31C, a terminal portion 32C, a pad portion 33C, and a connecting portion 34C.

[0039] The mounting section 31C is covered by the sealing member 7. As shown in Figure 4, a semiconductor element 12B and a protective element 13 are mounted on the mounting section 31C. The mounting section 31C is electrically connected to the fourth electrode 121 of the semiconductor element 12B via the conductive bonding material 192, and is also electrically connected to the second electrode 132 of the protective element 13 via the conductive bonding material 193. In other words, the fourth electrode 121 and the second electrode 132 are electrically connected to each other via the mounting section 31C.

[0040] As shown in Figure 4, the terminal portion 32C is the part of the lead 3C that protrudes from the sealing member 7. In the y-direction, the terminal portion 32C protrudes from the mounting portion 31C on the opposite side from the leads 4A to 4P. The terminal portion 32C is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32C is bent upward in the z-direction to form an L-shape.

[0041] The pad portion 33C and the connecting portion 34C are covered by the sealing member 7. As shown in Figure 4, the pad portion 33C and the connecting portion 34C are interposed between the mounting portion 31C and the terminal portion 32C. The pad portion 33C is located above the mounting portion 31C in the z direction (z2 direction), similar to the pad portions 33A and 33B. The pad portion 33C is connected to the terminal portion 32C. The wire 6B is joined to the pad portion 33C. The connecting portion 34C is connected to the mounting portion 31C and the pad portion 33C, and is inclined with respect to the y direction, similar to the connecting portions 34A and 34B.

[0042] Lead 3D is on which semiconductor element 12C is mounted. Lead 3D is electrically connected to the second electrode 112 of semiconductor element 11C and the fourth electrode 121 of semiconductor element 12C by a configuration that will be described in detail later. As shown in Figure 4, lead 3D includes a mounting portion 31D, a terminal portion 32D, a pad portion 33D, and a connecting portion 34D.

[0043] The mounting portion 31D is covered by the sealing member 7. As shown in Figure 4, a semiconductor element 12C and a protective element 13 are mounted on the mounting portion 31D. The mounting portion 31D is electrically connected to the fourth electrode 121 of the semiconductor element 12C via the conductive bonding material 192, and is also electrically connected to the second electrode 132 of the protective element 13 via the conductive bonding material 193. In other words, the fourth electrode 121 and the second electrode 132 are electrically connected to each other via the mounting portion 31D.

[0044] As shown in Figure 4, the terminal portion 32D is the part of the lead 3D that protrudes from the sealing member 7. In the y-direction, the terminal portion 32D protrudes from the mounting portion 31D on the opposite side from the leads 4A to 4P. The terminal portion 32D is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32D is bent upward in the z-direction to form an L-shape.

[0045] The pad portion 33D and the connecting portion 34D are covered by the sealing member 7. As shown in Figure 4, the pad portion 33D and the connecting portion 34D are interposed between the mounting portion 31D and the terminal portion 32D. The pad portion 33D is located above the mounting portion 31D in the z direction (z2 direction), similar to the pad portions 33A, 33B, and 33C. The pad portion 33D is connected to the terminal portion 32D. A wire 6C is joined to the pad portion 33D. The connecting portion 34D is connected to the mounting portion 31D and the pad portion 33D, and is inclined with respect to the y direction, similar to the connecting portions 34A, 34B, and 34C.

[0046] As shown in Figures 3 and 4, leads 3E, 3F, and 3G are positioned on the x1 side relative to lead 3D. Leads 3E, 3F, and 3G are aligned in the x direction. Leads 3B, 3C, and 3D do not have any of the multiple semiconductor elements 11, 12 or the multiple protection elements 13 mounted on them, respectively.

[0047] Lead 3E is electrically connected to the fifth electrode 122 of semiconductor element 12A by a configuration that will be described in detail later. Lead 3E includes a terminal portion 32E and a pad portion 33E, as shown in Figure 4 and other figures. The terminal portion 32E and the pad portion 33E are connected.

[0048] The terminal portion 32E is the part of the lead 3E that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 32E protrudes in the y-direction away from the pad portion 33E and on the opposite side from the leads 4A to 4P. The terminal portion 32E is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32E is bent upward in the z-direction to form an L-shape.

[0049] The pad portion 33E is covered by the sealing member 7 and, in the illustrated example, is rectangular in plan view. As shown in Figure 4, the pad portion 33E does not overlap the support substrate 51 in plan view. The pad portion 33E, like the pad portions 33A to 33D, is located above each mounting portion 31A to 31D in the z direction (z2 direction). As shown in Figure 4, a wire 6D is joined to the pad portion 33E, and it is electrically connected to the fifth electrode 122 of the semiconductor element 12A via the wire 6D.

[0050] Lead 3F is electrically connected to the fifth electrode 122 of semiconductor element 12B by a configuration that will be described in detail later. As shown in Figure 4 and other figures, lead 3F includes a terminal portion 32F and a pad portion 33F. The terminal portion 32F and the pad portion 33F are connected.

[0051] The terminal portion 32F is the part of the lead 3F that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 32F protrudes in the y-direction away from the pad portion 33F and on the opposite side from the leads 4A to 4P. The terminal portion 32F is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32F is bent upward in the z-direction to form an L-shape.

[0052] The pad portion 33F is covered by the sealing member 7 and, in the illustrated example, is rectangular in plan view. As shown in Figure 4, the pad portion 33F does not overlap the support substrate 51 in plan view. The pad portion 33F, like the pad portions 33A to 33E, is located above each mounting portion 31A to 31D in the z direction (z2 direction). As shown in Figure 4, a wire 6E is joined to the pad portion 33F, and it is electrically connected to the fifth electrode 122 of the semiconductor element 12B via the wire 6E.

[0053] Lead 3G is electrically connected to the fifth electrode 122 of semiconductor element 12C by a configuration that will be described in detail later. As shown in Figure 4 and other figures, lead 3G includes a terminal portion 32G and a pad portion 33G. The terminal portion 32G and the pad portion 33G are connected.

[0054] The terminal portion 32G is the part of the lead 3G that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 32G protrudes in the y-direction away from the pad portion 33G and on the opposite side from the leads 4A to 4P. The terminal portion 32G is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 32G is bent upward in the z-direction to form an L-shape.

[0055] The pad portion 33G is covered by the sealing member 7. As shown in Figure 4, the pad portion 33G does not overlap the support substrate 51 in a plan view. The pad portion 33G, like the pad portions 33A to 33F, is located above each mounting portion 31A to 31D in the z direction (z2 direction). As shown in Figure 4, a wire 6F is joined to the pad portion 33G, and it is electrically connected to the fifth electrode 122 of the semiconductor element 12C via the wire 6F.

[0056] Lead 3Z is positioned in the x2 direction relative to lead 3A. Lead 3Z does not conduct to any of the multiple semiconductor elements 11, 12, multiple protection elements 13, or the two control elements 2A, 2B. As shown in Figure 4, lead 3Z includes a terminal portion 32Z and a pad portion 33Z. The terminal portion 32Z and the pad portion 33Z are connected.

[0057] The terminal portion 32Z is ​​the part of the lead 3Z that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 32Z protrudes in the y-direction on the opposite side from the leads 4A to 4P relative to the pad portion 33Z. In the illustrated example, the terminal portion 32Z is ​​bent upward in the z-direction to form an L-shape.

[0058] The pad portion 33Z is covered by the sealing member 7. As shown in Figures 3 and 4, the pad portion 33Z does not overlap the support substrate 51 in a plan view. The pad portion 33Z, like the pad portions 33A to 33G, is located above each mounting portion 31A to 31D in the z direction (z2 direction).

[0059] As shown in Figures 3 and 4, leads 4A, 4B, and 4C are positioned in the x2 direction relative to lead 4D. The following description will focus on lead 4A, but leads 4B and 4C also contain similar components. In this case, replacing "A" in each component of lead 4A with "B" or "C" results in the components of leads 4B and 4C.

[0060] As shown in Figure 4, lead 4A includes a terminal portion 42A and a pad portion 43B. As mentioned above, although details are omitted, as shown in Figure 4, lead 4B includes a terminal portion 42B and a pad portion 43B, and lead 4C includes a terminal portion 42C and a pad portion 43C.

[0061] The terminal portion 42A is the part of the lead 4A that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 42A protrudes in the y-direction away from the pad portion 43A and the leads 3A-3G and 3Z. The terminal portion 42A is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 42A is bent upward in the z-direction to form an L-shape.

[0062] The pad portion 43A is covered by the sealing member 7. As shown in Figure 4, each electronic component 29 and each wire 6I are bonded to the pad portion 43A. Electronic component 29U is bonded to pad portion 43A, electronic component 29V is bonded to pad portion 43B, and electronic component 29W is bonded to pad portion 43C. The shape of the pad portion 43A is not limited to the illustrated example.

[0063] As shown in Figures 3 and 4, multiple leads 4D to 4G are arranged in the x1 direction relative to lead 4C. The following will focus on lead 4D, but leads 4E, 4F, and 4G also contain similar components. In this case, the components of leads 4E, 4F, and 4G are obtained by changing the "D" in each component of lead 4D to "E," "F," or "G."

[0064] As shown in Figure 4, lead 4D includes a terminal portion 42D, a pad portion 43D, and a connecting portion 44D. As described above, although details are omitted, as shown in Figure 4, lead 4E includes a terminal portion 42E, a pad portion 43E, and a connecting portion 44E, lead 4F includes a terminal portion 42F, a pad portion 43F, and a connecting portion 44F, and lead 4G includes a terminal portion 42G, a pad portion 43G, and a connecting portion 44G. Terminal portion 42E (42F, 42G) is an example of a "first terminal portion".

[0065] The terminal portion 42D is the part of the lead 4D that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 42D protrudes in the y-direction away from the pad portion 43D and on the opposite side from the leads 3A-3G and 3Z. The terminal portion 42D is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 42D is bent upward in the z-direction to form an L-shape.

[0066] The pad portion 43D is covered by the sealing member 7. As shown in Figure 4, each wire 6I is joined to the pad portion 43D, and electrical conductivity is provided to the second electrode 22 of the control element 2A via each wire 6I. Also, as shown in Figure 5, in addition to the wire 6I, wire 6K is also joined to the pad portions 43E, 43F, and 43G. In this embodiment, each pad portion 43E, 43F, and 43G is an example of a "first conductive portion".

[0067] The connecting portion 44D is covered by the sealing member 7. As shown in Figure 4, the connecting portion 44D is connected to the terminal portion 42D and the pad portion 43D, and is interposed between them.

[0068] Lead 4H is equipped with a control element 2A. As shown in Figure 4 and other figures, lead 4H includes a mounting portion 41H, a terminal portion 42H, a pad portion 43H, multiple connecting portions 44H, and a protruding portion 45H.

[0069] The mounting portion 41H is covered by the sealing member 7. A control element 2A is mounted on the mounting portion 41H, as shown in Figures 4 and 11. As described above, the control element 2A is fixed to the mounting portion 41H by the bonding material 25. As shown in Figure 11, the mounting portion 41H is spaced apart from the support substrate 51 in the z direction.

[0070] The terminal portion 42H is the part of the lead 4H that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 42H protrudes in the y-direction on the opposite side from the leads 3A-3G and 3Z from the mounting portion 41H. The terminal portion 42H is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 42H is bent in the z-direction to form an L-shape.

[0071] The pad portion 43H is covered by the sealing member 7. The pad portion 43H is adjacent to the mounting portion 41H. As shown in Figure 4, a wire 6I is joined to the pad portion 43H.

[0072] Each of the multiple connecting portions 44H is covered by a sealing member 7. Some of the multiple connecting portions 44H are interposed between the terminal portion 42H and the pad portion 43H and connect to them, and others are interposed between the mounting portion 41H and the protruding portion 45H and connect to them.

[0073] As shown in Figure 4, the protruding portion 45H extends in the y2 direction from the connecting portion 44H connected to the mounting portion 41H and protrudes from the sealing member 7.

[0074] The lead 4O is on which the control element 2B is mounted. As shown in Figure 4 and other figures, the lead 4O includes a mounting portion 41O, a terminal portion 42O, a pad portion 43O, and a connecting portion 44O.

[0075] The mounting portion 41O is covered by the sealing member 7. A control element 2B is mounted on the mounting portion 41O, as shown in Figure 4. As described above, the control element 2B is fixed to the mounting portion 41O by the bonding material 25. The mounting portion 41O, like the mounting portion 41H, is spaced apart from the support substrate 51 in the z direction (see Figure 11).

[0076] The terminal portion 42O is the part of the lead 4O that protrudes from the sealing member 7. As shown in Figure 4, the terminal portion 42O protrudes in the y-direction on the opposite side from the leads 3A-3G and 3Z from the mounting portion 41O. The terminal portion 42O is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 42O is bent in the z-direction to form an L-shape.

[0077] The pad portion 43O is covered by the sealing member 7. The pad portion 43O is adjacent to the mounting portion 41O. As shown in Figure 4, a wire 6I is joined to the pad portion 43O.

[0078] Each connecting portion 44O is covered by a sealing member 7. The connecting portion 44O is interposed between the terminal portion 42O and the pad portion 43O and connects to them.

[0079] As shown in Figures 3 and 4, multiple leads 4I-4N and 4P are arranged in the x1 direction relative to lead 4H. In the following, lead 4I will be described in detail, but leads 4J, 4K, 4L, 4M, 4N, and 4P also contain similar constituent parts. In this case, the constituent parts of leads 4J, 4K, 4L, 4M, 4N, and 4P are obtained by changing the "I" in each constituent part of lead 4I to "J", "K", "L", "M", "N", or "P".

[0080] As shown in Figures 4 and 5, lead 4I includes a terminal portion 42I, a pad portion 43I, and a connecting portion 44I. As described above, although details are omitted, as shown in Figures 4 and 5, lead 4J includes a terminal portion 42J, a pad portion 43J, and a connecting portion 44J; lead 4K includes a terminal portion 42K, a pad portion 43K, and a connecting portion 44K; lead 4L includes a terminal portion 42L, a pad portion 43L, and a connecting portion 44L; lead 4M includes a terminal portion 42M, a pad portion 43M, and a connecting portion 44M; lead 4N ​​includes a terminal portion 42N, a pad portion 43N, and a connecting portion 44N; and lead 4P includes a terminal portion 42P, a pad portion 43P, and a connecting portion 44P. Terminal portion 42I (42J, 42K) is an example of a "second terminal portion".

[0081] The terminal portion 42I is the part of the lead 4I that protrudes from the sealing member 7. As shown in Figures 4 and 5, the terminal portion 42I protrudes in the y direction on the opposite side from the pad portion 43I to the leads 3A-3G and 3Z. The terminal portion 42I is used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the terminal portion 42I is bent in the z direction to form an L shape. The terminal portions 42I-42N of the multiple leads 4I-4N are each positioned in the x direction between the terminal portion 42H of lead 4H and the terminal portion 42O of lead 4O, and the terminal portion 42P of lead 4P is located in the x1 direction relative to the terminal portion 42O.

[0082] The pad portion 43I is covered by the sealing member 7. As shown in Figures 4 and 5, each wire 6I is joined to the pad portion 43I, and electrical conductivity is provided to the second electrode 22 of the control element 2B via each wire 6I. However, in the example shown in Figures 4 and 5, the pad portion 43P does not have a wire 6I joined to it. Also, as shown in Figure 5, in addition to the wire 6I, the pad portions 43I, 43J, and 43K also have a wire 6J joined to them. In this embodiment, each pad portion 43I, 43J, and 43K is an example of a "second conductive portion".

[0083] The connecting portion 44I is covered by the sealing member 7. As shown in Figure 4, the connecting portion 44I is connected to the terminal portion 42I and the pad portion 43I, and is interposed between them.

[0084] In the illustrated example, multiple terminals 42A to 42C are arranged in the x-direction with a first pitch width d1 (see Figure 4). Similarly, multiple terminals 42D to 42P are arranged in the x-direction with a second pitch width d2 (see Figure 4). The first pitch width d1 is greater than the second pitch width d2. The distance between terminals 42C and 42D along the x-direction is the first pitch width d1.

[0085] The support substrate 51 supports a plurality of leads 3A to 3D and is provided to transfer heat from each of the plurality of semiconductor elements 11, 12 and the plurality of protective elements 13 to the outside of the semiconductor device A1, for example. The support substrate 51 is plate-shaped and rectangular in plan view. The support substrate 51 is made of an insulating material, and as the insulating material, ceramics such as alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and zirconia-containing alumina are used. Although a ceramic structure for the support substrate 51 is preferred from the viewpoint of strength, heat transfer coefficient and insulating properties, it is not limited to this and various materials (for example, epoxy resin and silicon) can be used. Furthermore, it is preferable that the support substrate 51 be made of a material with a higher thermal conductivity than the sealing member 7.

[0086] As shown in Figures 4 and 8 to 12, the support substrate 51 has a first surface 511, a second surface 512, a third surface 513, a fourth surface 514, a fifth surface 515, and a sixth surface 516. As shown in Figures 8 to 12, the first surface 511 and the second surface 512 are spaced apart in the z direction. The first surface 511 faces in the z2 direction, and the second surface 512 faces in the z1 direction. As shown in Figure 8, the mounting portions 31A, 31B, 31C, and 31D are joined to the first surface 511 via a bonding material 39. The second surface 512 is exposed from the sealing member 7, as shown in Figures 8 to 12. The third surface 513, the fourth surface 514, the fifth surface 515, and the sixth surface 516 are located between the first surface 511 and the second surface 512 in the z direction and are connected to them. As shown in Figures 4 and 8, the third surface 513 and the fourth surface 514 are separated in the x-direction. The third surface 513 faces in the x1 direction, and the fourth surface 514 faces in the x2 direction. As shown in Figures 4 and 11, the fifth surface 515 and the sixth surface 516 are separated in the y-direction. The fifth surface 515 faces in the y1 direction, and the sixth surface 516 faces in the y2 direction. In the illustrated example, the first surface 511, the second surface 512, the third surface 513, the fourth surface 514, the fifth surface 515, and the sixth surface 516 are all flat.

[0087] Multiple connecting members 6 provide electrical conductivity to two points that are spaced apart from each other. As can be seen from Figures 2, 4, and 5, the multiple connecting members 6 include multiple wires 6A to 6K. Each wire 6A to 6K (each connecting member 6) is a bonding wire. Note that instead of each wire 6A to 6K, a plate-shaped conductive lead material may be used as each connecting member 6.

[0088] As shown in Figure 4, wire 6A is connected to the second electrode 112 of semiconductor element 11A and to the pad portion 33B of lead 3B. In addition, wire 6A is connected to the first electrode 131 of protective element 13 (the rightmost protective element 13 in Figure 4) between the portions connected to these two. As a result, in Figure 4, the second electrode 112 of semiconductor element 11A is electrically connected to lead 3B via wire 6A, and also to the first electrode 131 of the rightmost protective element 13 in Figure 4. Since lead 3B is electrically connected to the fourth electrode 121 of semiconductor element 12A, the fourth electrode 121 of semiconductor element 12A and the second electrode 112 of semiconductor element 11A are electrically connected via lead 3B and wire 6A.

[0089] As shown in Figure 4, wire 6B is joined to the second electrode 112 of semiconductor element 11B and to the pad portion 33C of lead 3C. In addition, wire 6B is joined to the first electrode 131 of protective element 13 (the second protective element 13 from the right in Figure 4) between the portions joined to these two. As a result, the second electrode 112 of semiconductor element 11B is electrically connected to lead 3C via wire 6B, and also to the first electrode 131 of protective element 13 (the second protective element 13 from the right in Figure 4). Since lead 3C is electrically connected to the fourth electrode 121 of semiconductor element 12B, the fourth electrode 121 of semiconductor element 12B and the second electrode 112 of semiconductor element 11B are electrically connected via lead 3C and wire 6B.

[0090] As shown in Figure 4, wire 6C is joined to the second electrode 112 of semiconductor element 11C and to the pad portion 33D of lead 3D. Furthermore, between these joined portions, wire 6C is joined to the first electrode 131 of protective element 13 (the third protective element 13 from the right in Figure 4). As a result, the second electrode 112 of semiconductor element 11C conducts to lead 3D via wire 6C, and also conducts to the first electrode 131 of protective element 13 (the third protective element 13 from the right in Figure 4). Since lead 3D conducts to the fourth electrode 121 of semiconductor element 12C, the fourth electrode 121 of semiconductor element 12C and the second electrode 112 of semiconductor element 11C conduct via lead 3D and wire 6C.

[0091] As shown in Figure 4, wire 6D is joined to the fifth electrode 122 of semiconductor element 12A and to the pad portion 33E of lead 3E. In addition, wire 6D is joined to the first electrode 131 of protective element 13 mounted on lead 3B between the portions joined to these two points. As a result, the fifth electrode 122 of semiconductor element 12A is electrically connected to lead 3E via wire 6D, and also to the first electrode 131 of protective element 13 mounted on lead 3B.

[0092] As shown in Figure 4, wire 6E is joined to the fifth electrode 122 of semiconductor element 12B and to the pad portion 33F of lead 3F. In addition, wire 6E is joined to the first electrode 131 of protective element 13 mounted on lead 3C between the portions joined to these two points. As a result, the fifth electrode 122 of semiconductor element 12B is electrically connected to lead 3F via wire 6E, and also to the first electrode 131 of protective element 13 mounted on lead 3C.

[0093] As shown in Figure 4, wire 6F is joined to the fifth electrode 122 of semiconductor element 12C and to the pad portion 33G of lead 3G. In addition, wire 6F is joined to the first electrode 131 of protective element 13 mounted on lead 3D between the portions joined to these two. As a result, the fifth electrode 122 of semiconductor element 12C is electrically connected to lead 3G via wire 6F, and also to the first electrode 131 of protective element 13 mounted on lead 3D.

[0094] As shown in Figure 4, the multiple wires 6G are connected to the second electrode 112 and third electrode 113 of each semiconductor element 11 and to the first electrode 21 of the control element 2A. Therefore, each wire 6G either makes the second electrode 112 and the first electrode 21 conductive, or makes the third electrode 113 and the first electrode 21 conductive. The first drive signal flows through the wire 6A connected to the third electrode 113 of each semiconductor element 11 and the first electrode 21 of the control element 2A.

[0095] As shown in Figure 4, the multiple wires 6H are connected to the sixth electrode 123 of each semiconductor element 12 and the first electrode 21 of the control element 2B. Therefore, each wire 6H makes the sixth electrode 123 and the first electrode 21 conductive. The second drive signal flows through each wire 6H.

[0096] As shown in Figure 4, the multiple wires 6I are connected to the second electrodes 22 of each control element 2A, 2B and to the pad portions 43A to 43P of either one of the multiple electronic components 29 or one of the multiple leads 4A to 4P. Thus, each wire 6I makes electrical contact between each control element 2A, 2B and each lead 4A to 4P.

[0097] As shown in Figures 4 and 5, multiple wires 6J are connected to the second electrode 22 of the control element 2B and to the respective pad portions 43E, 43F, and 43G of the leads 4E, 4F, and 4G. Thus, each wire 6J provides electrical conductivity between the control element 2B and each lead 4E, 4F, and 4G. Each wire 6J is an example of a "first connecting member".

[0098] As shown in Figures 4 and 5, the multiple wires 6K are connected to the second electrode 22 of the control element 2A and to the respective pad portions 43I, 43J, and 43K of the leads 4I, 4J, and 4K. Thus, each wire 6K makes electrical contact between the control element 2A and each lead 4I, 4J, and 4K. Each wire 6K is an example of a "second connecting member".

[0099] In the multiple connecting members 6, each wire 6A to 6F has a larger diameter than each wire 6G to 6K. This is because, when the semiconductor device A1 is configured as an IPM, a higher voltage is applied to the multiple leads 3A to 3G, and a larger current flows through them than to the multiple leads 4A to 4F. Each wire 6A to 6F is made of, for example, Al or an Al alloy. The constituent material of each wire 6A to 6F may be Au or an Au alloy or Cu or a Cu alloy, instead of Al or an Al alloy. Each wire 6G to 6K is made of, for example, Au or an Au alloy. The constituent material of each wire 6G to 6K may be Al or an Al alloy or Cu or a Cu alloy, instead of Au or an Au alloy.

[0100] As shown in Figures 1, 3, 4, and 6 to 12, the sealing member 7 covers a plurality of semiconductor elements 11, 12, a plurality of protection elements 13, two control elements 2A, 2B, a plurality of electronic components 29, a portion of each of the plurality of leads 3A to 3G, 3Z, a portion of each of the plurality of leads 4A to 4P, a portion of the support substrate 51, and a plurality of connecting members 6. The sealing member 7 is, for example, a black epoxy resin. The sealing member 7 has a resin main surface 71, a resin back surface 72, and a plurality of resin side surfaces 73 to 76.

[0101] As shown in Figures 6-8 and Figure 10, the resin main surface 71 and the resin back surface 72 are spaced apart in the z direction. The resin main surface 71 faces the z2 direction, and the resin back surface 72 faces the z1 direction. The resin main surface 71 and the resin back surface 72 are both flat (or nearly flat). Multiple resin side surfaces 73-76 are each located between the resin main surface 71 and the resin back surface 72 in the z direction and are connected to them. As shown in Figures 3, 4 and 8, the resin side surfaces 73 and 74 are spaced apart in the x direction. The resin side surface 73 faces the x1 direction, and the resin side surface 74 faces the x2 direction. As shown in Figures 3, 4 and 11, the resin side surfaces 75 and 76 are spaced apart in the y direction. The resin side surface 75 faces the y1 direction, and the resin side surface 76 faces the y2 direction. As shown in Figures 3 and 4, etc., a recess 731 is formed in the resin side surface 73, which is recessed in the x direction. The resin side surface 74 has recesses 741 that are recessed in the x-direction. The recesses 731 and 741 are used, for example, to fix semiconductor device A1 when mounting it. The resin side surface 76 has a plurality of recesses 761 that are recessed in the y-direction.

[0102] In semiconductor device A1, a first DC voltage applied to terminals 32A (lead 3A) and 32E (lead 3E) is converted to a first AC voltage by the switching operations of semiconductor elements 11A and 12A. The frequency of the first AC voltage depends on the switching frequencies of semiconductor elements 11A and 12A. This first AC voltage is then output from terminal 32B (lead 3B). Furthermore, a second DC voltage applied to terminals 32A (lead 3A) and 32F (lead 3F) is converted to a second AC voltage by the switching operations of semiconductor elements 11B and 12B. The frequency of the second AC voltage depends on the switching frequencies of semiconductor elements 11B and 12B. This second AC voltage is then output from terminal 32C (lead 3C). Furthermore, the third DC voltage applied to terminals 32A (lead 3A) and 32G (lead 3G) is converted into a third AC voltage by the switching operations of semiconductor elements 11C and 12C. The frequency of the third AC voltage depends on the switching frequencies of semiconductor elements 11C and 12C. This third AC voltage is then output from terminal 32D (lead 3D).

[0103] Next, the circuit configuration of semiconductor device A1 will be explained with reference to Figure 13. In Figure 13, each semiconductor element 11 and 12 is a MOSFET.

[0104] As shown in Figure 13, the semiconductor device A1 has a configuration in which three switching arms 10U, 10V, and 10W are connected in parallel to each other. Switching arm 10U has semiconductor elements 11A and 12A, switching arm 10V has semiconductor elements 11B and 12B, and switching arm 10W has semiconductor elements 11C and 12C.

[0105] The drains (first electrode 111) of each semiconductor element 11A to 11C are connected to each other and connected to the P terminal (lead 3A). The source (second electrode 112) of semiconductor element 11A is connected to the drain (fourth electrode 121) of semiconductor element 12A, the source (second electrode 112) of semiconductor element 11B is connected to the drain (fourth electrode 121) of semiconductor element 12B, and the source (second electrode 112) of semiconductor element 11C is connected to the drain (fourth electrode 121) of semiconductor element 12C. Node N1 between the source of semiconductor element 11A and the drain of semiconductor element 12A is connected to the U terminal (lead 3B). Node N2 between the source of semiconductor element 11B and the drain of semiconductor element 12B is connected to the V terminal (lead 3C). Node N3 between the source of semiconductor element 11C and the drain of semiconductor element 12C is connected to the W terminal (lead 3D). The source (fifth electrode 122) of semiconductor element 12A is connected to the NU terminal (lead 3E), the source (fifth electrode 122) of semiconductor element 12B is connected to the NV terminal (lead 3F), and the source (fifth electrode 122) of semiconductor element 12C is connected to the NW terminal (lead 3G).

[0106] The voltage levels applied to the U terminal (lead 3B), V terminal (lead 3C), and W terminal (lead 3D) are, for example, approximately 0V to 650V. On the other hand, the voltage levels applied to the NU terminal (lead 3E), NV terminal (lead 3F), and NW terminal (lead 3G) are, for example, approximately 0V, which is lower than the voltage levels applied to the terminals (lead 3B), V terminal (lead 3C), and W terminal (lead 3D). Semiconductor elements 11A to 11C constitute the high-potential side transistors of the three-phase inverter circuit, and semiconductor elements 12A to 12C constitute the low-potential side transistors of the three-phase inverter circuit.

[0107] The gates (third electrodes 113) of semiconductor elements 11A to 11C are connected to control element 2A, and the sources (second electrodes 112) of semiconductor elements 11A to 11C are each connected to control element 2A. The gates (sixth electrodes 123) of semiconductor elements 12A to 12C are each connected to control element 2B.

[0108] The HINU terminal (lead 4E), HINV terminal (lead 4F), and HINW terminal (lead 4G) are connected to an external gate control circuit (not shown), and the first input signal is input from the gate control circuit. The LINU terminal (lead 4I), LINV terminal (lead 4J), and LINW terminal (lead 4K) are connected to the same gate control circuit, and the second input signal is input from the gate control circuit.

[0109] Control element 2A is electrically connected to the VBU terminal (lead 4A), VBV terminal (lead 4B), VBW terminal (lead 4C), first VCC terminal (lead 4D), HINU terminal (lead 4E), HINV terminal (lead 4F), HINW terminal (lead 4G), and first GND terminal (lead 4H). Control element 2A is also electrically connected to the HINU terminal (lead 4E), HINV terminal (lead 4F), and HINW terminal (lead 4G). The first VCC terminal is the terminal that supplies the power supply voltage VCC to control element 2A. Control element 2A receives first input signals from the HINU terminal, HINV terminal and HINW terminal, and second input signals from the LINU terminal, LINV terminal and LINW terminal. Based on the input first and second input signals, control element 2A generates first drive signals (e.g., gate voltages) to drive each semiconductor element 11A to 11C. The generated first drive signal is then input to the gates (third electrodes 113) of each semiconductor element 11A to 11C. The first GND terminal (lead 4H) and the second GND terminal (lead 4O) are connected inside the semiconductor device A1 and are at the same potential.

[0110] Control element 2B is electrically connected to the LINU terminal (lead 4I), LINV terminal (lead 4J), LINW terminal (lead 4K), second VCC terminal (lead 4L), FO terminal (lead 4M), CIN terminal (lead 4N), and second GND terminal (lead 4O). Control element 2B is also electrically connected to the HINV terminal (lead 4F), HINW terminal (lead 4G), and first GND terminal (lead 4H). The second VCC terminal supplies the power supply voltage VCC to control element 2B. Control element 2B receives second input signals from the LINU, LINV, and LINW terminals, and first input signals from the HINU, HINV, and HINW terminals. Based on the input first and second input signals, control element 2B generates a second drive signal (e.g., gate voltage) to drive each semiconductor element 12A to 12C. Then, the generated second drive signal is input to the gate (sixth electrode 123) of each semiconductor element 12A to 12C.

[0111] The first voltage of the electrical signal applied to the HINU terminal (lead 4E), HINV terminal (lead 4F), and HINW terminal (lead 4G) is lower than the second voltage (power supply voltage VCC) applied from the first VCC terminal (lead 4D) to drive the control element 2A. Also, the first voltage of the electrical signal applied to the LINU terminal (lead 4I), LINV terminal (lead 4J), and LINW terminal (lead 4K) is lower than the second voltage (power supply voltage VCC) applied from the second VCC terminal (lead 4L) to drive the control element 2B.

[0112] Next, an example of the operation of semiconductor device A1 will be explained with reference to Figures 14 and 15.

[0113] Figure 14 is a timing chart showing an example of the operation of semiconductor device A1. The example of the operation of semiconductor device A1 shown in Figure 14 shows, for example, the operation of semiconductor elements 11A and 12A in switching arm 10U (see Figure 13), but the other switching arms 10V and 10W are similar examples of operation. However, the waveforms of the three switching arms 10U, 10V, and 10W are each shifted in phase by, for example, 120°. Figure 14(a) shows the waveform of the first input signal IN_H, which is the waveform at the input terminal of control element 2A. Figure 14(b) shows the waveform of the second input signal IN_L, which is the waveform at the input terminal of control element 2B. Figure 14(c) shows the waveform of the first drive signal G_H, which is the waveform at the output terminal of control element 2A. Figure 14(d) shows the waveform of the second drive signal G_L, which is the waveform at the output terminal of control element 2B. Figure 14(e) shows the driving state of semiconductor element 11, where the solid line shows the waveform of the current (drain current) ID11 of semiconductor element 11, and the dashed line shows the waveform of the voltage (drain-source voltage) VDS11 of semiconductor element 11. Figure 14(f) shows the driving state of semiconductor element 12, where the solid line shows the waveform of the current (drain current) ID12 of semiconductor element 12, and the dashed line shows the waveform of the voltage (drain-source voltage) VDS12 of semiconductor element 12. For ease of understanding, the waveforms shown in Figure 14 represent the ideal case of change, but in reality, some oscillation, phase shift, amplitude shift, etc. may occur.

[0114] As shown in Figures 14(a) and (b), the first input signal IN_H and the second input signal IN_L are rectangular pulse waves that alternate between high and low levels. In this embodiment, the first input signal IN_H has a high level for the on-level indicating the conduction state of the semiconductor element 11 and a low level for the off-level indicating the cutoff state of the semiconductor element 11. Alternatively, the on-level could be set to a low level and the off-level to a high level. In the example shown in Figure 14, the duty cycles of the first input signal IN_H and the second input signal IN_L are 50%, but these can be changed as appropriate. As shown in Figures 14(a) and (b), the second input signal IN_L is the inverted signal of the first input signal IN_H. That is, while the first input signal IN_H is at a high level, the second input signal IN_L is at a low level, and conversely, while the first input signal IN_H is at a low level, the second input signal IN_L is at a high level.

[0115] As shown in Figure 14(c), the first drive signal G_H alternately switches between an ON signal that turns the semiconductor element 11 into a conductive state and an OFF signal that turns the semiconductor element 11 into a blocked state. The first drive signal G_H is generated by the control element 2A and output to the semiconductor element 11. In the example shown in Figure 14, when the first input signal IN_H switches from a high level to a low level (times t1, t7), the first drive signal G_H switches from an ON signal to an OFF signal simultaneously (or approximately simultaneously) with the switching of the first input signal IN_H. On the other hand, when the first input signal IN_H switches from a low level to a high level (times t4, t10), the first drive signal G_H switches from an OFF signal to an ON signal after at least the first period Td_H has elapsed. The first period Td_H will be described later.

[0116] As shown in Figure 14(d), the second drive signal G_L alternately switches between an ON signal that turns the semiconductor element 12 into a conductive state and an OFF signal that turns the semiconductor element 12 into a blocked state. The second drive signal G_L is generated by the control element 2B and output to the semiconductor element 12. In the example shown in Figure 14, when the second input signal IN_L switches from a high level to a low level (times t4, t10), the second drive signal G_L switches from an ON signal to an OFF signal simultaneously (or approximately simultaneously) with the switching of the second input signal IN_L. On the other hand, when the second input signal IN_L switches from a low level to a high level (times t1, t7), the second drive signal G_L switches from an OFF signal to an ON signal after at least the second period Td_L has elapsed. The second period Td_L will be described later.

[0117] As shown in Figure 14(e), the semiconductor element 11 switches from a conductive state to a blocked state (times t2, t8) after the first drive signal G_H switches from an ON signal to an OFF signal (times t1, t7) and after the OFF transition time Toff_H has elapsed. Also, the semiconductor element 11 switches from a blocked state to a conductive state (times t6, t12) after the first drive signal G_H switches from an OFF signal to an ON signal (times t5, t11) and after the ON transition time Ton_H has elapsed. The OFF transition time Toff_H and the ON transition time Ton_H vary appropriately depending on, for example, the wiring distance from the control element 2A to the semiconductor element 11 and the switching speed of the semiconductor element 11. The switching speed is the speed from when the first drive signal is input to the third electrode 113 (gate electrode) of the semiconductor element 11 until it actually switches. In the example shown in Figure 14(e), the semiconductor element 11 switches between a conduction state and a disconnection state when the current ID11 and voltage VDS11 of the semiconductor element 11 intersect. However, the conditions for determining the switching between the conduction state and the disconnection state of the semiconductor element 11 are not limited to this. For example, the conditions for determining the switching may be the timing when the current ID11 becomes 0 (zero), or the timing when the current ID11 becomes less than or equal to a threshold (or a predetermined ratio of the maximum value of current ID11 to ID11max). Alternatively, the conditions may be the timing when the voltage VDS11 reaches its maximum value VDS11max, or the timing when the voltage VDS11 becomes greater than or equal to a threshold (or a predetermined ratio of the maximum value of voltage VDS11 to VDS11max).

[0118] As shown in Figure 14(f), the semiconductor element 12 switches from a conductive state to a blocked state (times t5, t11) after the second drive signal G_L switches from an ON signal to an OFF signal (times t4, t10) and the OFF transition time Toff_L has elapsed. Also, the semiconductor element 12 switches from a blocked state to a conductive state (times t3, t9) after the second drive signal G_L switches from an OFF signal to an ON signal (times t2, t8) and the ON transition time Ton_L has elapsed. The OFF transition time Toff_L and the ON transition time Ton_L vary appropriately depending on, for example, the wiring distance from the control element 2B to the semiconductor element 12 and the switching speed of the semiconductor element 12. The switching speed is the speed from when the second drive signal is input to the sixth electrode 123 (gate electrode) of the semiconductor element 12 until it actually switches. In the example shown in Figure 14(f), the semiconductor element 12 switches between a conduction state and a disconnection state when the current ID12 and voltage VDS12 of the semiconductor element 12 intersect. However, the conditions for determining the switching between the conduction state and the disconnection state of the semiconductor element 12 are not limited to this. For example, the conditions for determining the switching may be the timing when the current ID12 becomes 0 (zero), or the timing when the current ID12 becomes less than or equal to a threshold (or a predetermined ratio of the maximum value of current ID12 to ID12max). Alternatively, the conditions may be the timing when the voltage VDS12 reaches its maximum value VDS12max, or the timing when the voltage VDS12 becomes greater than or equal to a threshold (or a predetermined ratio of the maximum value of voltage VDS12 to VDS12max).

[0119] In semiconductor device A1, the control element 2A receives both a first input signal IN_H and a second input signal IN_L. Based on the second input signal IN_L, the control element 2A estimates the driving state of semiconductor element 12. If it determines that semiconductor element 12 is in a conductive state, it delays the switching of semiconductor element 11 from the disconnected state to the conductive state.

[0120] For example, even if the second input signal IN_L switches from a high level to a low level at times t4 and t10, the control element 2A determines that the semiconductor element 12 is in a conductive state until a predetermined first period Td_H has elapsed. The first period Td_H is set based on the off-state transition time Toff_L when the semiconductor element 12 switches to a cutoff state, and in the example shown in Figure 14, the first period Td_H is the same as (or approximately the same as) the off-state transition time Toff_L. The off-state transition time Toff_L is an example of the "first transition time". During the first period Td_H (from time t4 to time t5 and from time t10 to time t11), that is, while the control element 2A determines that the semiconductor element 12 is in a conductive state, even if the first input signal IN_H switches from a low level to a high level, the control element 2A does not switch the first drive signal G_H from an off signal to an on signal (i.e., delays the switching of the first drive signal). As a result, the first drive signal G_H generated by the control element 2A does not switch from an off signal to an on signal during the period when the semiconductor element 12 is determined to be in a conductive state (first period Td_H). In other words, the control element 2A generates the first drive signal G_H in such a way that the semiconductor element 11 does not become conductive during the period when the semiconductor element 12 is in a conductive state.

[0121] Subsequently, at times t5 and t11, and after the first period Td_H has elapsed, as shown in Figure 14(f), the semiconductor element 12 switches from a conductive state to a disconnected state. The control element 2A determines that the semiconductor element 12 is not conductive and switches the first drive signal G_H from an off signal to an on signal. In the example shown in Figure 14, the first input signal IN_H switches from a low level to a high level at the same time that the second input signal IN_L switches from a high level to a low level. Therefore, the timing at which the first drive signal G_H switches from an off signal to an on signal (times t5 and t11) is delayed by the duration of the first period Td_H from the timing at which the first input signal IN_H switches from a low level to a high level (times t4 and t10). Unlike the example shown in Figure 14, if the switching of the first input signal IN_H from a low level to a high level occurs after the first period Td_H has elapsed, rather than during the first period Td_H, then the control element 2A should switch the first drive signal G_H from an off signal to an on signal at the same time as the switching of the first input signal IN_H. In other words, the timing of switching the first drive signal G_H from an off signal to an on signal should be simultaneous (or nearly simultaneous) with the timing of the switching of the first input signal IN_H from a low level to a high level.

[0122] When the first drive signal G_H switches from an off signal to an on signal (times t5, t11), as shown in Figure 14(e), after the on-state transition time Ton_H has elapsed, the semiconductor element 11 switches from an off state to a conductive state (times t6, t12). Through this operation, semiconductor device A1 switches semiconductor element 11 from an off state to a conductive state after semiconductor element 12 has switched from a conductive state to an off state.

[0123] In semiconductor device A1, the control element 2B receives both a first input signal IN_H and a second input signal IN_L. Based on the first input signal IN_H, the control element 2B estimates the driving state of semiconductor element 11. If it determines that semiconductor element 11 is in a conductive state, it delays the switching of semiconductor element 12 from the disconnected state to the conductive state.

[0124] For example, even if the first input signal IN_H switches from a high level to a low level at times t1 and t7, the control element 2B determines that the semiconductor element 11 is in a conductive state until a predetermined second period Td_L has elapsed. The second period Td_L is set based on the off-state transition time Toff_H when the semiconductor element 11 switches to a cutoff state, and in the example shown in Figure 14, the second period Td_L is the same as (or approximately the same as) the off-state transition time Toff_H. The off-state transition time Toff_H is an example of a "second transition time". During the second period Td_L (from time t1 to time t2 and from time t7 to time t8), that is, while the control element 2B determines that the semiconductor element 11 is in a conductive state, even if the second input signal IN_L switches from a low level to a high level, the control element 2B does not switch the second drive signal G_L from an off signal to an on signal. As a result, the second drive signal G_L generated by the control element 2B does not switch from an off signal to an on signal during the period when the semiconductor element 11 is judged to be in a conductive state (second period Td_L). In other words, the control element 2B generates the second drive signal G_L in such a way that the semiconductor element 12 does not become conductive during the period when the semiconductor element 11 is in a conductive state.

[0125] Subsequently, at times t2 and t8, and after the second period Td_L has elapsed, as shown in Figure 14(e), the semiconductor element 11 switches from a conductive state to a disconnected state. The control element 2B determines that the semiconductor element 11 is not conductive and switches the second drive signal G_L from an off signal to an on signal. In the example shown in Figure 14, the second input signal IN_L switches from a low level to a high level at the same time that the first input signal IN_H switches from a high level to a low level. Therefore, the timing at which the second drive signal G_L switches from an off signal to an on signal (times t2 and t8) is delayed by the second period Td_L from the timing at which the second input signal IN_L switches from a low level to a high level (times t1 and t7). Unlike the example shown in Figure 14, if the switching of the second input signal IN_L from a low level to a high level occurs after the second period Td_L has elapsed, rather than during the second period Td_L, then the control element 2B should switch the second drive signal G_L from an off signal to an on signal at the same time as the switching of the second input signal IN_L. In other words, the timing of switching the second drive signal G_L from an off signal to an on signal should be simultaneous (or nearly simultaneous) with the timing of the switching of the second input signal IN_L from a low level to a high level.

[0126] When the second drive signal G_L switches from an off signal to an on signal (times t2, t8), as shown in Figure 14(f), after the on-state transition time Ton_L has elapsed, the semiconductor element 12 switches from an off state to a conductive state (times t3, t9). Through this operation, semiconductor device A1 switches semiconductor element 12 from an off state to a conductive state after semiconductor element 11 has switched from a conductive state to an off state.

[0127] Next, an example of the operation of a semiconductor device A0 (for example, the semiconductor device described in Patent Document 1), which is different from semiconductor device A1, will be explained with reference to Figure 15. Figure 15 is a timing chart showing an example of the operation of semiconductor device A0. In semiconductor device A0, the second input signal is not input to control element 2A, and the first input signal is not input to control element 2B. Figures 15(a) to (f) show waveforms corresponding to Figures 14(a) to (f), respectively. Note that the times t0 to t12 in Figure 14 and the times t0 to t12 in Figure 15 are not correlated.

[0128] In semiconductor device A0, control element 2A does not receive the second input signal IN_L and therefore cannot determine the conduction state of semiconductor element 12. As a result, as shown in Figures 15(a) and (c), the generated first drive signal G_H has the same shape (or nearly the same shape) as the first input signal IN_H. Similarly, control element 2B does not receive the first input signal IN_H and therefore cannot determine the conduction state of semiconductor element 11. As a result, as shown in Figures 15(b) and (d), the generated second drive signal G_L has the same shape as the second input signal IN_L. When the first drive signal G_H switches from an ON signal to an OFF signal (times t1, t7), semiconductor element 11 switches from a conduction state to a disconnected state after the off-state transition time Toff_H has elapsed (times t3, t9). Furthermore, when the first drive signal G_H switches from an off signal to an on signal (times t4, t10), after the on-state transition time Ton_H has elapsed, it switches from an off state to a conduction state (times t5, t11). On the other hand, when the second drive signal G_L switches from an off signal to an on signal (times t1, t7), the semiconductor element 12 switches from an off state to a conduction state after the on-state transition time Ton_L has elapsed (times t2, t8). Also, when the second drive signal G_L switches from an on signal to an off signal (times t4, t10), after the off-state transition time Toff_L has elapsed, it switches from a conduction state to an off state (times t6, t12). As a result, in semiconductor device A0, as can be seen from Figures 15(e) and (f), there are periods between time t2(t8) and time t3(t9), and between time t5(t11) and time t6(t12), during which semiconductor element 11 and semiconductor element 12 are simultaneously in a conductive state (see the dotted areas in Figure 15). Therefore, in semiconductor device A1, by inputting not only the first input signal but also the second input signal to control element 2A, and inputting not only the second input signal but also the first input signal to control element 2B, it can be seen that the period during which semiconductor element 11 and semiconductor element 12 are simultaneously in a conductive state can be suppressed, as shown in Figure 14.

[0129] The effects and benefits of semiconductor device A1 are as follows:

[0130] In semiconductor device A1, when control element 2A receives the second input signal IN_L and determines that semiconductor element 12 is in a conductive state based on the second input signal IN_L, it delays the switching of semiconductor element 11 from the off state to the conductive state. With this configuration, if semiconductor element 12 is determined to be in a conductive state, the switching of semiconductor element 11 from the off state to the conductive state is suppressed. Therefore, when semiconductor element 11 switches from the off state to the conductive state, it is suppressed that semiconductor element 11 and semiconductor element 12 become conductive simultaneously. In other words, in semiconductor device A1, when semiconductor element 11 switches from the off state to the conductive state, arm short circuits caused by the simultaneous turning on of the upper and lower arms can be suppressed.

[0131] In semiconductor device A1, the control element 2A does not switch the semiconductor element 12 to a conductive state until the first period Td_H has elapsed after the second input signal IN_L switches from an on level to an off level. In this embodiment, the on level corresponds to a high level, and the off level corresponds to a low level. The first period Td_H is set based on the off-state transition time Toff_L until the semiconductor element 12 switches to a blocked state. In semiconductor device A1, even if the second input signal IN_L switches from an on level to an off level, the semiconductor element 12 will not enter a blocked state until the off-state transition time Toff_L has elapsed. Therefore, the control element 2A is made to determine that the semiconductor element 12 is in a conductive state until the first period Td_H, which is set based on the off-state transition time Toff_L, has elapsed. As a result, semiconductor device A1 does not switch semiconductor element 11 to a conductive state during the first period Td_H, thereby delaying the switch of semiconductor element 11 from the disconnected state to the conductive state during the period in which semiconductor element 12 is determined to be in a conductive state.

[0132] In semiconductor device A1, when control element 2B receives a first input signal IN_H and determines, based on the first input signal IN_H, that semiconductor element 11 is in a conductive state, it delays the switching of semiconductor element 12 from the off state to the conductive state. With this configuration, if semiconductor element 11 is determined to be in a conductive state, the switching of semiconductor element 12 from the off state to the conductive state is suppressed. Therefore, when semiconductor element 12 switches from the off state to the conductive state, it is suppressed that semiconductor element 11 and semiconductor element 12 become conductive simultaneously. In other words, in semiconductor device A1, when semiconductor element 12 switches from the off state to the conductive state, it is possible to suppress arm short circuits caused by the simultaneous turning on of the upper and lower arms.

[0133] In semiconductor device A1, the control element 2B does not switch the semiconductor element 12 to a conductive state until the second period Td_L has elapsed after the first input signal IN_H switches from an on-level to an off-level. In this embodiment, the on-level corresponds to a high level, and the off-level corresponds to a low level. The second period Td_L is set based on the off-time transition time Toff_H until the semiconductor element 11 switches to a blocked state. In semiconductor device A1, even if the first input signal IN_H switches from an on-level to an off-level, the semiconductor element 11 does not enter a blocked state until the off-time transition time Toff_H has elapsed. Therefore, the control element 2B is made to determine that the semiconductor element 11 is in a conductive state until the second period Td_L, which is set based on the off-time transition time Toff_H, has elapsed. As a result, semiconductor device A1 does not switch semiconductor element 12 to a conductive state during the second period Td_L, thereby delaying the switch of semiconductor element 12 from the disconnected state to the conductive state during the period in which semiconductor element 11 is judged to be in a conductive state.

[0134] In semiconductor device A1, control element 2A is conductive to both lead 4E (4F, 4G) and lead 4I (4J, 4K). The first input signal IN_H is input to lead 4E (4F, 4G), and the second input signal IN_L is input to lead 4I (4J, 4K). Control element 2A and lead 4I (4J, 4K) are conductive, for example, by a connecting member 6 (wire 6J). With this configuration, the first input signal IN_H and the second input signal IN_L can be input to control element 2A. Control element 2B is conductive to both lead 4E (4F, 4G) and lead 4I (4J, 4K). Control element 2B and lead 4E (4F, 4G) are conductive, for example, by a connecting member 6 (wire 6K). With this configuration, the first input signal IN_H and the second input signal IN_L can be input to the control element 2B.

[0135] In semiconductor device A1, the second input signal IN_L is an inverted signal obtained by inverting the first input signal IN_H. In other words, in semiconductor device A1, by suppressing the simultaneous conduction of semiconductor elements 11 and 12 connected in series without pre-setting a dead time period between the first input signal IN_H and the second input signal IN_L input from an external gate control circuit, arm short circuits caused by simultaneous activation of the upper and lower arms can be suppressed.

[0136] In the first embodiment, an example was shown in which one end of each wire 6J is joined to the control element 2A and the other end is joined to the pad portions 43I, 43J, and 43K, respectively. However, the other end may be joined to the connecting portions 44I, 44J, and 44K instead of the pad portions 43I, 43J, and 43K, or it may be joined directly to the control element 2B. Depending on the shape of the leads 4I, 4J, and 4K, the length of each wire 6J can be shortened by connecting the other end to a position closer to the control element 2A. Similarly, in the first embodiment, an example was shown in which one end of each wire 6K is joined to the control element 2B and the other end is joined to the pad portions 43E, 43F, and 43G, respectively. However, the other end may be joined to the connecting portions 44E, 44F, and 44G instead of the pad portions 43E, 43F, and 43G, or it may be joined directly to the control element 2A. Depending on the shape of leads 4E, 4F, and 4G, the closer the other end is connected to the control element 2A, the shorter the length of each wire 6K can be.

[0137] Figures 16 to 22 show a semiconductor device A2 according to a second embodiment. As shown in these figures, the semiconductor device A2 comprises a plurality of semiconductor elements 11, 12, two control elements 2A, 2B, a plurality of electronic components 29, a plurality of leads 3A to 3G, 3Z, a plurality of leads 4A to 4P, a support substrate 51, a wiring pattern 52, a plurality of connecting members 6, and a sealing member 7. In the example shown in Figures 16 to 22, the semiconductor device A2 does not have a plurality of protective elements 13, but it may have a plurality of protective elements 13, similar to the semiconductor device A1.

[0138] Figure 16 is a plan view showing semiconductor device A2. Figure 17 is a diagram showing the sealing member 7 in the plan view of Figure 16, indicated by dashed lines. Figure 18 is a magnified portion of Figure 17. Figure 19 is a magnified portion of Figure 17. Figure 20 is a magnified portion of Figure 17. Figure 21 is a cross-sectional view along line XXI-XXI in Figure 17. Figure 22 is a cross-sectional view along line XXII-XXII in Figure 17.

[0139] The wiring pattern 52 is formed on the first surface 511 of the support substrate 51. The wiring pattern 52 is made of a conductive material. The wiring pattern 52 is covered by a sealing member 7. The wiring pattern 52 includes at least a first wiring section 52E (52F, 52G), a second wiring section 52I (52J, 52K), and a third wiring section 52H, 52O. In this embodiment, it includes a plurality of wiring sections 52A to 52P and a plurality of joint sections 53A to 53D.

[0140] Multiple wiring sections 52A to 52P are each formed on a support substrate 51. In this embodiment, each wiring section 52A to 52P is formed on the first surface 511 of the support substrate 51. Each wiring section 52A to 52P is made of a conductive material. The conductive material constituting each wiring section 52A to 52P is not particularly limited, but examples include materials containing Ag, Cu, Au, etc. In the following description, the case in which each wiring section 52A to 52P contains Ag will be described as an example. Note that each wiring section 52A to 52P may contain Cu instead of Ag, or Au instead of Ag or Cu. Alternatively, each wiring section 52A to 52P may contain Ag-Pt or Ag-Pd. Furthermore, the method for forming each wiring section 52A to 52P is not limited, and for example, they may be formed by printing a paste containing these metals and then firing it.

[0141] Of the multiple wiring sections 52A to 52P, wiring section 52H and wiring section 52O are formed integrally, while the others are spaced apart. The auxiliary line L2 shown in Figures 17 and 19 indicates the boundary between wiring section 52H and wiring section 52O, that is, the part where they are connected integrally. In contrast to this example, wiring section 52H and wiring section 52O may be spaced apart from each other.

[0142] As shown in Figure 17, wiring sections 52A, 52B, and 52C are arranged in the x2 direction relative to wiring section 52D.

[0143] As shown in Figure 18, the wiring section 52A includes two pad sections 521A and 522A and a connecting section 523A. A wire 6I connected to the control element 2A and an electronic component 29U are joined to pad section 521A, and a lead 4A is joined to pad section 522A. Pad section 522A is located on the opposite side of pad section 521A from leads 3A-3G and 3Z in the y-direction. In the example shown in Figure 18, each pad section 521A and 522A is rectangular in plan view. The connecting section 523A connects pad section 521A and pad section 522A.

[0144] As shown in Figure 18, the wiring section 52B includes two pad sections 521B and 522B and a connecting section 523B. The wire 6I connected to the control element 2A and the electronic component 29V are joined to pad section 521B, and the lead 4B is joined to pad section 522B. In the y-direction, pad section 522B is located on the opposite side of pad section 521B from leads 3A-3G and 3Z. In the example shown in Figure 18, each pad section 521B and 522B is rectangular in plan view. The connecting section 523B connects pad section 521B and pad section 522B.

[0145] The wiring section 52C includes two pad sections 521C, 522C and a connecting section 523C, as shown in Figures 18, 19, and 22. A wire 6I connected to the control element 2A and an electronic component 29W are joined to pad section 521C, and a lead 4C is joined to pad section 522C. Pad section 522C is located on the opposite side of pad section 521C from leads 3A-3G and 3Z in the y-direction. In the example shown in Figure 18, each pad section 521C and 522C is rectangular in plan view. The connecting section 523C connects pad section 521C and pad section 522C.

[0146] As shown in Figures 17 and 19, the wiring section 52D is positioned in the x1 direction relative to the wiring section 52C. As shown in Figure 19, the wiring section 52D includes two pad sections 521D and 522D and a connecting section 523D. A wire 6I connected to the control element 2A is joined to pad section 521D, and a lead 4D is joined to pad section 522D. In the y direction, pad section 522D is located on the opposite side of pad section 521D from leads 3A-3G and 3Z. In the example shown in Figure 19, each pad section 521D and 522D is rectangular in plan view. The connecting section 523D connects pad section 521D and pad section 522D.

[0147] As shown in Figures 17 and 19, wiring sections 52E, 52F, and 52G are arranged in the x1 direction relative to wiring section 52D. The wiring section 52E will be described in detail below, but wiring sections 52F and 52G also include similar components. In this case, replacing the "E" in each component of wiring section 52E with "F" or "G" results in the components of wiring section 52F and wiring section 52G.

[0148] As shown in Figure 19, the wiring section 52E includes two pad sections 521E, 522E and a connecting section 523E. As mentioned above, although details are omitted, as shown in Figure 19, the wiring section 52F includes two pad sections 521F, 522F and a connecting section 523F, and the wiring section 52G includes two pad sections 521G, 522G and a connecting section 523G.

[0149] The pad portion 521E is joined to wire 6I, which is connected to control element 2A, and wire 6K, which is connected to control element 2B. The pad portion 522E is joined to lead 4E. The pad portion 522F is joined to lead 4F, and the pad portion 522G is joined to lead 4G. In the y-direction, the pad portion 522E is located on the opposite side of the pad portion 521E from leads 3A-3G and 3Z. In the example shown in Figure 18, each pad portion 521E and 522E is rectangular in plan view. The connecting portion 523E connects the pad portion 521E and the pad portion 522E.

[0150] The wiring section 52H is on which the control element 2A is mounted. As shown in Figures 18 and 19, the wiring section 52H includes two pad sections 521H and 522H, a connecting section 523H, and a mounting section 524H.

[0151] A wire 6I connected to the control element 2A is joined to pad portion 521H, and a lead 4H is joined to pad portion 522H. Pad portion 522H is located on the opposite side of pad portion 521H from leads 3A-3G and 3Z in the y-direction. In the example shown in Figure 19, each pad portion 521H and 522H is rectangular in plan view. Pad portion 521H is connected to mounting portion 524H. Connecting portion 523H connects pad portion 521H and pad portion 522H. The control element 2A is mounted on mounting portion 524H. The control element 2A is fixed to mounting portion 524H by bonding material 25.

[0152] The wiring section 52O is on which the control element 2B is mounted. As shown in Figures 19 and 20, the wiring section 52O includes two pad sections 521O and 522O, a connecting section 523O, and a mounting section 524O.

[0153] A wire 6I connected to the control element 2B is joined to pad portion 521O, and a lead 4O is joined to pad portion 522O. Pad portion 522O is located on the opposite side of pad portion 521O from leads 3A to 3G in the y-direction. In the example shown in Figure 20, each pad portion 521O and 522O is rectangular in plan view. Pad portion 521O is connected to mounting portion 524O. Connecting portion 523O connects pad portion 521O and pad portion 522O. The control element 2B is mounted on mounting portion 524O. The control element 2B is fixed to mounting portion 524O by bonding material 25.

[0154] As shown in Figures 17 and 19, wiring sections 52I, 52J, and 52K are arranged in the x1 direction relative to wiring section 52H. The wiring section 52I will be described in detail below, but wiring sections 52J and 52K also include similar components. In this case, replacing the "I" in each component of wiring section 52I with "J" or "K" results in the components of wiring sections 52J and 52K.

[0155] As shown in Figure 19, the wiring section 52I includes two pad sections 521I and 522I and a connecting section 523I. As mentioned above, although details are omitted, as shown in Figure 19, the wiring section 52J includes two pad sections 521J and 522J and a connecting section 523J, and the wiring section 52K includes two pad sections 521K and 522K and a connecting section 523K.

[0156] The pad portion 521I is joined to wire 6I, which is connected to the control element 2B, and to wire 6J, which is also connected to the control element 2B. The pad portion 522I is joined to lead 4I. Lead 4J is joined to pad portion 522J, and lead 4K is joined to pad portion 522K. In the y-direction, pad portion 522I is located on the opposite side from leads 3A-3G and 3Z to pad portion 521I. In the example shown in Figure 19, each pad portion 521I and 522I is rectangular in plan view. The connecting portion 523I connects pad portion 521I and pad portion 522I.

[0157] As shown in Figures 17 and 20, the multiple wiring sections 52L to 52N and 52P are arranged in the x1 direction relative to wiring section 52K. The wiring section 52L will be described in detail below, but the wiring sections 52M, 52N, and 52P also contain similar components. In this case, the components of wiring sections 52M, 52N, and 52P are obtained by changing the "L" in each component of wiring section 52L to "M", "N", or "P".

[0158] As shown in Figure 20, the wiring section 52L includes two pad sections 521L, 522L and a connecting section 523L. As described above, although details are omitted, as shown in Figure 20, the wiring section 52M includes two pad sections 521M, 522M and a connecting section 523M, the wiring section 52N includes two pad sections 521N, 522N and a connecting section 523N, and the wiring section 52P includes two pad sections 521P, 522P and a connecting section 523P.

[0159] A wire 6I connected to the control element 2B is joined to the pad portion 521L. However, in the example shown in Figure 20, the wire 6I is not joined to the pad portion 521P. A lead 4L is joined to the pad portion 522L. Furthermore, a lead 4M is joined to the pad portion 522M, a lead 4N ​​is joined to the pad portion 522N, and a lead 4P is joined to the pad portion 522P. In the y-direction, the pad portion 522L is located on the opposite side from the leads 3A-3G and 3Z relative to the pad portion 521L. In the example shown in Figure 20, each pad portion 521L and 522L is rectangular in plan view. The connecting portion 523L connects the pad portion 521L and the pad portion 522L.

[0160] As shown in Figures 17 to 20, each pad portion 522A to 522P is arranged along the periphery of the support substrate 51 in a plan view.

[0161] Multiple joints 53A to 53D are each formed on the support substrate 51. As shown in Figures 21 and 22, each joint 53A to 53D, like each wiring section 52A to 52P, is formed on the first surface 511 of the support substrate 51. As can be seen from Figures 17 and 21, joint 53A is located below the mounting section 31A of lead 3A, joint 53B is located below the mounting section 31B of lead 3B, joint 53C is located below the mounting section 31C of lead 3C, and joint 53D is located below the mounting section 31D of lead 3D. The constituent material of each joint 53A to 53D is not particularly limited and is made of a material capable of joining the support substrate 51 and each lead 3A to 3D. Each joint 53A to 53D is made of, for example, a conductive material. The conductive material constituting each joint 53A to 53D is not particularly limited, but examples include those containing Ag, Cu, Au, etc. Each joint 53A to 53D contains the same conductive material as that which constitutes each wiring section 52A to 52P. Each joint 53A to 53D may contain copper instead of silver, or gold instead of silver or copper. Alternatively, each wiring section 52 to 52P may contain Ag-Pt or Ag-Pd. Furthermore, the method for forming each joint 53A to 53D is not limited; for example, they may be formed by printing a paste containing these metals and then firing it, similar to the wiring sections 52 to 52P.

[0162] In semiconductor device A2, multiple leads 4A to 4P are each connected to the wiring pattern 52. Furthermore, semiconductor device A2 has an additional lead 4Z compared to semiconductor device A1.

[0163] As shown in Figure 17, multiple leads 4A to 4P are arranged in the x1 direction relative to lead 4Z. The following will describe lead 4A in detail, but the other leads 4B to 4P also contain similar components. In this case, the components of each lead 4B to 4P are obtained by changing "A" to "B" to "P" in each component of lead 4A.

[0164] As shown in Figure 17, the lead 4A includes a terminal portion 42A, a connecting portion 44A, and a joint portion 46A. The terminal portion 42A of semiconductor device A2 is configured similarly to the terminal portion 42A of semiconductor device A1. The joint portion 46A is joined to the pad portion 522A of the wiring portion 52A. Similarly, the joint portions 46B (46C~46P) are joined to the pad portions 522B (522C~522P) of the wiring portion 52B (52C~52P). The joint portions 46A (46B~46P) are joined to the pad portions 522A (522B~522P) via a conductive bonding material 49. The conductive bonding material 49 is, for example, solder, metal paste, sintered metal, etc. (see Figure 22). In the example shown in Figure 18, a through hole 461A is formed in the joint portion 46A, but this through hole 461A does not have to be formed. The through hole 461A penetrates the joint portion 46A in the z direction (see Figure 22). Similarly, as shown in Figures 18 to 20, the joint portion 46B (46C to 46P) has a through hole 461B (461C to 461P), but this through hole 461B (461C to 461P) is not required. The connecting portion 44A connects the terminal portion 42A and the joint portion 46A.

[0165] Lead 4Z is positioned in the x2 direction relative to lead 4A. Lead 4Z does not conduct to any of the semiconductor elements 11, 12 or the two control elements 2A, 2B. Lead 4Z includes a pad portion 43Z and a protrusion portion 45Z, as shown in Figure 17. The pad portion 43Z and the protrusion portion 45Z are connected.

[0166] The pad portion 43Z is covered by the sealing member 7. As shown in Figure 17, the pad portion 43Z does not overlap the support substrate 51 in a plan view.

[0167] As shown in Figures 16 and 17, the protruding portion 45Z extends from the pad portion 43Z in the y2 direction and protrudes from the sealing member 7.

[0168] The circuit configuration and operation example of semiconductor device A2 are the same as those of semiconductor device A1 (see Figure 13) and operation example (see Figure 14). However, since semiconductor device A2 does not have multiple protection elements 13, its circuit configuration is the same as that of semiconductor device A1 shown in Figure 13, but with the multiple protection elements 13 removed.

[0169] The semiconductor device A2 can achieve the same effect as the semiconductor device A1. Therefore, like the semiconductor device A1, the semiconductor device A2 can suppress arm short circuits caused by the simultaneous activation of the upper and lower arms.

[0170] The semiconductor device A2 comprises a support substrate 51 and a wiring pattern 52 formed on a first surface 511. The wiring pattern 52 includes a plurality of wiring sections 52A to 52P, which transmit control signals (e.g., a first input signal, a second input signal, a first drive signal, and a second drive signal) for controlling control elements 2A and 2B, and constitute a transmission path for said control signals. The plurality of wiring sections 52A to 52P are formed, for example, by printing a paste containing Ag and then firing it. With this configuration, it is possible to make the transmission path thinner and denser compared to, for example, a case where the transmission path for the control signals is made of a metal lead frame. Therefore, the semiconductor device A2 can be highly integrated.

[0171] In the second embodiment, an example was shown in which one end of each wire 6J is joined to the control element 2A and the other end is joined to the pad portions 521I, 521J, and 521K, respectively. However, the other end may be joined to the connecting portions 523I, 523J, and 523K instead of the pad portions 521I, 521J, and 521K, or it may be joined directly to the control element 2B. Depending on the shape of the wiring portions 52I, 52J, and 52K, the length of each wire 6J can be shortened by connecting the other end to a position closer to the control element 2A. Similarly, in the second embodiment, an example was shown in which one end of each wire 6K is joined to the control element 2B and the other end is joined to the pad portions 521E, 521F, and 521G, respectively. However, the other end may be joined to the connecting portions 523E, 523F, and 523G instead of the pad portions 521E, 521F, and 521G, or it may be joined directly to the control element 2A. Depending on the shape of the wiring sections 52E, 52F, and 52G, the closer the other end is connected to the control element 2A, the shorter the length of each wire 6K can be.

[0172] In the first and second embodiments, an example was shown in which the first period Td_H was the same length as (or approximately the same length as) the off-state transition time Toff_L until the semiconductor element 12 switched to the off-state. However, the first period Td_H may be shorter or longer than the off-state transition time Toff_L. Similarly, an example was shown in which the second period Td_L was the same length as (or approximately the same length as) the off-state transition time Toff_H until the semiconductor element 11 switched to the off-state. However, the second period Td_L may be shorter or longer than the off-state transition time Toff_H. Below, a semiconductor device according to this modified example will be described with reference to Figures 23 and 24.

[0173] Figure 23 is a timing chart showing an example of the operation of a semiconductor device when the first period Td_H is shorter than the off-time transition time Toff_L, and the second period Td_L is shorter than the off-time transition time Toff_H. In the modified example shown in Figure 23, the first period Td_H is shortened to take into account the on-time transition time Ton_H when the semiconductor element 11 switches from the disconnected state to the conductive state. However, if the sum of the first period Td_H and the on-time transition time Ton_H is shorter than the off-time transition time Toff_L, there is a risk that a period will occur when the semiconductor element 11 and the semiconductor element 12 are simultaneously in a conductive state when the semiconductor element 11 is switched from the disconnected state to the conductive state. Therefore, it is necessary to set the first period Td_H such that the sum of the first period Td_H and the on-time transition time Ton_H is greater than the off-time transition time Toff_L. Furthermore, the second period Td_L is shortened to account for the ON transition time Ton_L when the semiconductor element 12 switches from the disconnected state to the conductive state. However, if the sum of the second period Td_L and the ON transition time Ton_L is shorter than the OFF transition time Toff_H, there is a risk that a period will occur when the semiconductor element 11 and semiconductor element 12 are simultaneously in a conductive state when the semiconductor element 12 is switched from the disconnected state to the conductive state. Therefore, it is necessary to set the second period Td_L such that the sum of the second period Td_L and the ON transition time Ton_L is greater than the OFF transition time Toff_H.

[0174] Figure 24 is a timing chart showing an example of the operation of a semiconductor device when the first period Td_H is longer than the off-state transition time Toff_L, and the second period Td_L is also longer than the off-state transition time Toff_H. In the modified example shown in Figure 24, since the first period Td_H is longer than the off-state transition time Toff_L, the first drive signal G_H switches from an off signal to an on signal (times t5', t11') after the semiconductor element 12 switches from a conductive state to a disconnected state. Therefore, when switching the semiconductor element 11 from a conductive state to a disconnected state, the possibility of semiconductor element 11 and semiconductor element 12 being conductive at the same time can be reduced. However, as can be seen from Figure 24(e), the period during which the semiconductor element 11 is conductive becomes shorter, which may reduce the output voltage (AC voltage). Therefore, it is necessary to set the first period Td_H so that the delay time from when the first input signal IN_H switches from a low level (off level) to a high level (on level) until the semiconductor element 11 switches from the disconnected state to the conductive state does not become too long. Also, in the modified example shown in Figure 24, since the second period Td_L is longer than the off-state transition time Toff_H, the second drive signal G_L switches from an off signal to an on signal (times t2', t8') after the semiconductor element 11 switches from the conductive state to the disconnected state. Thus, when switching the semiconductor element 12 from the conductive state to the disconnected state, the possibility that semiconductor elements 11 and 12 will be in a conductive state simultaneously can be reduced. However, as can be seen from Figure 24(f), the period during which the semiconductor element 12 is in a conductive state becomes shorter, which may reduce the output voltage (AC voltage). Therefore, it is necessary to set the second period Td_L so that the delay time from when the second input signal IN_L switches from a low level (off level) to a high level (on level) until the semiconductor element 12 switches from the cutoff state to the conduction state does not become too long.

[0175] In the first and second embodiments, examples were shown in which each of the two control elements 2A and 2B receives both the first input signal and the second input signal. However, it is sufficient if either one of the two control elements 2A or 2B receives both the first input signal and the second input signal. Below, a semiconductor device according to this modified example will be described with reference to Figures 25 to 27.

[0176] Figure 25 is a plan view showing the semiconductor device according to this modified example, with the sealing member 7 indicated by dashed lines. Figure 26 shows an example of the circuit configuration of the semiconductor device shown in Figure 25. Figure 27 is a timing chart showing an example of the operation of the semiconductor device shown in Figure 25. As shown in Figure 25, the semiconductor device according to this modified example differs from semiconductor device A1 in that it does not have multiple wires 6K. In the examples shown in Figures 25 to 27, the first input signal and the second input signal are input to the control element 2A, so when switching the semiconductor element 11 from a closed state to a conductive state, arm short circuits caused by the simultaneous turning on of the upper and lower arms can be suppressed. However, as shown in Figure 26, the first input signal and the second input signal are input to the control element 2A, but the first input signal is not input to the control element 2B. Therefore, the control element 2B cannot determine whether the semiconductor element 11 is in a conductive state based on the first input signal, and generates the second drive signal G_L according to the input second input signal IN_L. As a result, in the semiconductor device according to this modification, compared to semiconductor device A1, there is a risk that when semiconductor element 12 switches from an off state to a conductive state, semiconductor element 11 and semiconductor element 12 may simultaneously become conductive. Therefore, as shown in Figure 27, it is advisable to provide a dead time period (from time t1 to time t2, and from time t7 to time t8) in which both the first input signal IN_H and the second input signal IN_L are at a low level (off level). In the example shown in Figure 27, the dead time period is provided by reducing the duty cycle of the second input signal IN_L, but the duty cycle of the first input signal IN_H may also be reduced, or the duty cycles of both the first input signal IN_H and the second input signal IN_L may be reduced.

[0177] In the examples shown in Figures 25 to 27, the semiconductor device A1 is shown without wire 6K, but the semiconductor device A2 may also be configured without wire 6K. Also, in the examples shown in Figures 25 to 27, the wire 6K is shown without wire 6K, but the configuration may also be configured without wire 6J instead of wire 6K. In this case, the control element 2A is not input with the second input signal, only the first input signal is input, and the control element 2B is input with both the first and second input signals. In the modified example in which both the first and second input signals are input to either control element 2A or control element 2B, considering that control element 2A operates at a higher potential than control element 2B, the control signal in control element 2A (such as the first drive signal) fluctuates more than the control signal in control element 2B (such as the second drive signal). Therefore, by inputting both the first and second input signals to control element 2A and delaying the switching of semiconductor element 11 to the conductive state, it becomes possible to switch semiconductor elements 11 and 12 with relatively higher safety. On the other hand, by inputting the first input signal and the second input signal to the control element 2B and delaying the switching of the semiconductor element 12 to a conductive state, it becomes possible to switch the semiconductor elements 11 and 12, which are relatively easier to control. The reason that the control element 2A operates at a higher potential than the control element 2B is that the second drive signal generated by the control element 2B uses the potential of the power GND terminal (NU terminal (lead 3E), NV terminal (lead 3F), and NW terminal (lead 3G)) as the reference potential, while the first drive signal generated by the control element 2A uses the potential of the output terminal (U terminal (lead 3B), V terminal (lead 3C), and W terminal (lead 3D)) as the reference potential.

[0178] In the first and second embodiments, an IPM that inputs and outputs three-phase AC current, such as an inverter motor, was shown as an example, but the invention is not limited thereto. The technical concept of this disclosure can be appropriately applied to a device comprising a pair of semiconductor elements 11 and 12 connected in series, and two control elements 2A and 2B. For example, the semiconductor device according to this disclosure is applicable to a single-phase inverter circuit that inputs and outputs single-phase AC current.

[0179] The semiconductor devices relating to this disclosure are not limited to the embodiments described above. The specific configuration of each part of the semiconductor device relating to this disclosure can be modified in various ways. This disclosure includes the embodiments described in the following appendix. Note 1. A first semiconductor element that receives a first drive signal and switches between a conductive state and a disconnected state in accordance with the first drive signal, A first control element that receives a first input signal, generates a first drive signal based on the first input signal, and outputs it to the first semiconductor element, A second semiconductor element that receives a second drive signal and switches between a conductive state and a disconnected state in accordance with the second drive signal, A second control element that receives a second input signal, generates the second drive signal based on the second input signal, and outputs it to the second semiconductor element, It is equipped with, A semiconductor device wherein the first control element, upon receiving the second input signal and determining that the second semiconductor element is in a conductive state based on the second input signal, delays the switching of the first semiconductor element from a blocked state to a conductive state. Note 2. The second input signal is a rectangular pulse wave having an on-level and an off-level, The first control element does not switch the first semiconductor element to a conductive state until the first period has elapsed after the second input signal has switched from an on level to an off level. The semiconductor device according to Appendix 1, wherein the first period is set based on a first transition time from when the second drive signal is output from the second control element to the second semiconductor element in order to switch the second semiconductor element from a conduction state to a disconnection state, until the second semiconductor element switches from a conduction state to a disconnection state. Note 3. The aforementioned first period is equal to or greater than the aforementioned first transition time, The semiconductor device described in Appendix 2, wherein the first semiconductor element is switched from a blocked state to a conductive state based on the first drive signal after the first period has elapsed. Note 4. A first lead including a first terminal for inputting the first input signal, A second lead including a second terminal for inputting the second input signal, Furthermore, The first lead is electrically connected to the first control element and the second control element. The semiconductor device according to any one of the appendices 1 to 3, wherein the second lead is electrically connected to the second control element. Note 5. The system further comprises a first connecting member connected to the first control element, The first connecting member is a semiconductor device as described in Appendix 4, which is electrically connected to the second lead. Note 6. The semiconductor device according to Appendix 5, wherein the second control element further delays the switching of the second semiconductor element from the disconnected state to the conductive state when the first input signal is input and the first semiconductor element is determined to be in a conductive state based on the first input signal. Note 7. The first input signal is a rectangular pulse wave having an on-level and an off-level, The second control element does not switch the second semiconductor element to a conductive state until the second period has elapsed after the first input signal has switched from an on level to an off level. The semiconductor device according to Appendix 6, wherein the second period is set based on a second transition time from when the first drive signal is output from the first control element to the first semiconductor element in order to switch the first semiconductor element from a conduction state to a disconnection state, until the first semiconductor element switches from a conduction state to a disconnection state. Note 8. The second period is equal to or greater than the second transition time. The semiconductor device according to Appendix 7, wherein the second control element generates the second drive signal to switch the second semiconductor element from a blocked state to a conductive state after the second period has elapsed. Note 9. The semiconductor device according to either Appendix 7 or Appendix 8, wherein the second input signal is an inverted signal obtained by inverting the first input signal. Note 10. The system further comprises a second connecting member connected to the second control element, The second connecting member is a semiconductor device according to any one of the appendices 6 to 9, which is electrically connected to the first lead. Note 11. A substrate having a first surface, The first surface further comprises a wiring pattern made of a conductive material formed on the first surface, The wiring pattern includes a first wiring section that is conductive to the first lead and a second wiring section that is conductive to the second lead. The first connecting member is connected to the second wiring section, The semiconductor device described in Appendix 10, wherein the second connecting member is connected to the first wiring section. Note 12. The semiconductor device according to Appendix 11, wherein the wiring pattern includes a third wiring portion to which at least one of the first control element and the second control element is joined. Note 13. The first lead includes a first conductive portion electrically connected to the first terminal portion. The second lead includes a second conductive portion that is electrically connected to the second terminal portion. The first connecting member is connected to the second conductive part, The semiconductor device described in Appendix 10, wherein the second connecting member is connected to the first conductive part. Note 14. The semiconductor device according to Appendix 13, further comprising a third lead to which at least one of the first control element and the second control element is joined. Note 15. The first semiconductor element has a first electrode, a second electrode, and a third electrode, and when the first drive signal is input to the third electrode, the conduction state and the disconnection state between the first electrode and the second electrode are switched. The semiconductor device according to any one of the appendices 1 to 14, wherein the second semiconductor element has a fourth electrode, a fifth electrode, and a sixth electrode, and when the second drive signal is input to the sixth electrode, the conduction state and the disconnection state between the fourth electrode and the fifth electrode are switched. Note 16. The first semiconductor element is mounted on a fourth lead that conducts to the first electrode, The second semiconductor element is mounted on a fifth lead that conducts to the fourth electrode and the second electrode, A sixth lead that is electrically connected to the fifth electrode, The semiconductor device described in Appendix 15, further comprising the features described therein. Note 17. A DC voltage is applied between the fourth lead and the sixth lead. The switching between the conductive and disconnected states of the first semiconductor element, and the switching between the conductive and disconnected states of the second semiconductor element, converts the DC voltage into an AC voltage. The semiconductor device described in Appendix 16, to which the AC voltage is applied to the fifth lead. [Explanation of symbols]

[0180] A1, A2: Semiconductor equipment 10U, 10V, 10W: Switching Arm 11, 11A, 11B, 11C: Semiconductor devices 11a: Main surface of the element 11b: Back surface of the element 111: 1st electrode 112: 2nd electrode 113: Third electrode 12, 12A, 12B, 12C: Semiconductor element 12a: Main surface of the element 12b: Back surface of the element 121: 4th electrode 122: 5th electrode 123: Sixth electrode 13: Protective element 131: 1st electrode 132: 2nd electrode 191,192,193: Conductive bonding material 2A, 2B: Control elements 21: First electrode 22: Second electrode 25: Bonding material 29, 29U, 29V, 29W: Electronic components 291: Conductive bonding material 3A~3G,3Z: Lead 31A~31D: Mounting part 32A~32G,32Z: Terminal part 33A~33G,33Z: Pad section 34A~34D: Connecting section 39: Jointing material 4A~4P, 4Z: Lead 41H, 41O: Mounting part 42A~42P: Terminal part 43A~43P, 43Z: Pad section 44A~44P: Connecting section 45H, 45Z: Protrusion 46A~46P: Joint 461A~461P: Through hole 49: Conductive bonding material 51: Support substrate 511: First surface 512: 2nd side 513: 3rd side 514:Side 4 515:Side 5 516: Side 6 52: Wiring pattern 52A~52P: Wiring section 521A~521P: Pad section 522A~522P: Pad section 523A~523P: Connecting section 524H, 524O: Mounting part 53A~53D: Joint part 6: Connecting components 6A~6K: Wire 7: Sealing member 71: Resin main surface 72: Back of the resin 73~76: Side of the resin 731,741,761: recessed

Claims

1. A first semiconductor element that receives a first drive signal and switches between a conductive state and a disconnected state in accordance with the first drive signal, A first control element that receives a first input signal, generates a first drive signal based on the first input signal, and outputs it to the first semiconductor element, A second semiconductor element that receives a second drive signal and switches between a conductive state and a disconnected state in accordance with the second drive signal, A second control element that receives a second input signal, generates the second drive signal based on the second input signal, and outputs it to the second semiconductor element, It is equipped with, When the first control element receives the second input signal and determines, based on the second input signal, that the second semiconductor element is in a conductive state, it delays the switching of the first semiconductor element from the disconnected state to the conductive state. A first lead including a first terminal for inputting the first input signal, A second lead including a second terminal for inputting the second input signal, Furthermore, The first lead is electrically connected to the first control element and the second control element. The second lead is electrically connected to the second control element. The system further comprises a first connecting member connected to the first control element, The first connecting member is electrically connected to the second lead, When the second control element receives the first input signal and determines, based on the first input signal, that the first semiconductor element is in a conductive state, it delays the switching of the second semiconductor element from the disconnected state to the conductive state. The system further comprises a second connecting member connected to the second control element, The second connecting member is a semiconductor device that is electrically connected to the first lead.

2. The second input signal is a rectangular pulse wave having an on-level and an off-level, The first control element does not switch the first semiconductor element to a conductive state until the first period has elapsed after the second input signal has switched from an on level to an off level. The semiconductor device according to claim 1, wherein the first period is set based on a first transition time from when the second drive signal is output from the second control element to the second semiconductor element in order to switch the second semiconductor element from a conductive state to a disconnected state, until the second semiconductor element switches from a conductive state to a disconnected state.

3. The first period is equal to or greater than the first transition time, The semiconductor device according to claim 2, wherein the first control element generates a first drive signal that switches the first semiconductor element from a blocked state to a conductive state after the first period has elapsed.

4. The first input signal is a rectangular pulse wave having an on-level and an off-level, The second control element does not switch the second semiconductor element to a conductive state until the second period has elapsed after the first input signal has switched from an on level to an off level. The semiconductor device according to any one of claims 1 to 3, wherein the second period is set based on a second transition time from when the first drive signal is output from the first control element to the first semiconductor element in order to switch the first semiconductor element from a conduction state to a disconnection state, until the first semiconductor element switches from a conduction state to a disconnection state.

5. The second period is equal to or greater than the second transition time. The semiconductor device according to claim 4, wherein the second control element generates a second drive signal that switches the second semiconductor element from a blocked state to a conductive state after the second period has elapsed.

6. The semiconductor device according to claim 4 or claim 5, wherein the second input signal is an inverted signal obtained by inverting the first input signal.

7. A substrate having a first surface, The first surface further comprises a wiring pattern made of a conductive material formed on the first surface, The wiring pattern includes a first wiring section that is electrically connected to the first lead and a second wiring section that is electrically connected to the second lead. The first connecting member is connected to the second wiring section, The semiconductor device according to any one of claims 1 to 6, wherein the second connecting member is connected to the first wiring portion.

8. The semiconductor device according to claim 7, wherein the wiring pattern includes a third wiring portion to which at least one of the first control element and the second control element is joined.

9. The first lead includes a first conductive portion electrically connected to the first terminal portion. The second lead includes a second conductive portion that is electrically connected to the second terminal portion. The first connecting member is connected to the second conductive part, The semiconductor device according to any one of claims 1 to 7, wherein the second connecting member is connected to the first conductive portion.

10. The semiconductor device according to claim 9, further comprising a third lead to which at least one of the first control element and the second control element is joined.

11. The first semiconductor element has a first electrode, a second electrode, and a third electrode, and when the first drive signal is input to the third electrode, the conduction state and the disconnection state between the first electrode and the second electrode are switched. The semiconductor device according to any one of claims 1 to 10, wherein the second semiconductor element has a fourth electrode, a fifth electrode, and a sixth electrode, and when the second drive signal is input to the sixth electrode, the conduction state and the disconnection state between the fourth electrode and the fifth electrode are switched.

12. The first semiconductor element is mounted on a fourth lead that conducts to the first electrode, The second semiconductor element is mounted on a fifth lead that is electrically connected to the fourth electrode and the second electrode, A sixth lead that is electrically connected to the fifth electrode, The semiconductor device according to claim 11, further comprising:

13. A DC voltage is applied between the fourth lead and the sixth lead. The switching between the conductive and disconnected states of the first semiconductor element, and the switching between the conductive and disconnected states of the second semiconductor element, converts the DC voltage into an AC voltage. The semiconductor device according to claim 12, wherein the AC voltage is applied to the fifth lead.

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