Semiconductor chamber component with multilayer coating

Abstract

An exemplary semiconductor processing chamber may include a chamber body. The chamber may include a showerhead. The chamber may include a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled to the platen along a second surface of the platen opposite the first surface of the platen. The shaft may extend at least partially through the chamber body. The coating may extend conformally around the first surface of the platen. The coating may include a first layer of silicon proximate the first surface of the platen and may include a second layer of material overlying the first layer of silicon.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefits and priority of U.S. Nonprovisional Application No. 17 / 693,037, filed on 11 March 2022, entitled “SEMICONDUCTOR CHAMBER COMPONENTS WITH MULTI-LAYER COATING,” the entirety of which is incorporated herein by reference for all purposes.

[0002] This technology relates to semiconductor systems, semiconductor processes, and semiconductor equipment. More specifically, this technology relates to a system including a coating on a chamber component, or a system for forming a coating on a chamber component. [Background technology]

[0003] Integrated circuits are made possible by the process of creating layers of material with complex patterns on a substrate surface. Creating patterned material on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring patterns in photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on a surface. Often, it is desirable to have an etching process that etches one material more quickly than another, for example, to facilitate a pattern transfer process. Such an etching process is said to be selective for the first material. As a result of the diversity of materials, circuits, and processes, etching processes have been developed to be selective for a variety of materials.

[0004] Etching processes can be called wet or dry, depending on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes can have difficulty penetrating some constrained trenches and can sometimes deform the remaining material. Wet processes can also damage chamber components. For example, HF etching solutions can chemically attack chamber components made of metals such as aluminum alloys. Dry etching, performed in a localized plasma formed within the substrate processing area, can penetrate more constrained trenches and results in less deformation of fragile remaining structures. However, localized plasma can damage the substrate due to arc generation when the localized plasma discharges. Localized plasma and plasma emissions can also damage chamber components.

[0005] Therefore, there is a need for improved systems and methods that can be used to create high-quality devices and structures. This technology addresses these and other needs. [Overview of the project]

[0006] An exemplary semiconductor processing chamber may include a chamber body. The chamber may include a showerhead. The chamber may include a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled to the platen along a second surface of the platen opposite to the first surface of the platen. The shaft may extend at least partially through the chamber body. A coating may conformally extend around the first surface of the platen. The coating may include a first layer of silicon adjacent to the first surface of the platen, a second layer of material on top of the first layer of silicon, or vice versa.

[0007] In some embodiments, the second layer of the coating is or may contain a silicon-containing material. The second layer of the coating is or may contain silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride. The platen may define a plurality of protrusions extending from the first surface of the platen. The coating may extend around each of the plurality of protrusions. The coating may be characterized by having a thickness of about 1 μm or more on all coated surfaces. The coating over the first surface of the substrate support may be characterized by a thickness variation of about 10% or less. The corner feature of the platen extending from the first surface may be characterized by having a coating thickness of at least 10% thicker than the coating thickness along the first surface of the platen. The shaft of the substrate support may be coupled to a hub outside the semiconductor processing chamber, and the coating may extend along the shaft to the hub. The platen may be aluminum nitride or may contain aluminum nitride. The showerhead may include a first plate and a second plate joined together to define a volume between the first and second plates. The outer surfaces of the first and second plates of the showerhead may be coated with a material similar to that of the substrate support.

[0008] Some embodiments of this technology may encompass a semiconductor processing method. The method may include sending a plasma emission of a halogen-containing precursor into a processing area of ​​a semiconductor processing chamber. The semiconductor processing chamber may include a chamber body, a showerhead, and a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled to the platen along a second surface of the platen opposite to the first surface of the platen. The shaft may extend at least partially through the chamber body. A coating may conformally extend around the first surface of the platen. The coating may include a first layer of silicon adjacent to the first surface of the platen and a second layer of silicon-containing material on top of the first layer of silicon.

[0009] In some embodiments, the method may include coating a substrate support in a coating chamber separate from the semiconductor processing chamber. The method may include placing the substrate support in the semiconductor processing chamber. The method may include processing at least 10 substrates in the semiconductor processing chamber or cleaning the processing area of ​​the semiconductor processing chamber at least 10 times with a halogen-containing precursor before removing the substrate support. The second layer of coating may be or include silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride. The coating may be characterized by having a thickness of about 1 μm or more on all coated surfaces. The second layer of coating may have a density of about 10 atoms / cm². 2 The following may be characterized by the incorporation of aluminum trace metals. Corner features of the platen extending from the first surface may be characterized by a coating thickness that is at least 10% thicker than the coating thickness along the first surface of the platen.

[0010] Some embodiments of this technology may encompass a semiconductor processing chamber. The chamber may include a chamber body, a showerhead, and a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled to the platen along a second surface of the platen opposite to the first surface of the platen. The shaft may extend at least partially through the chamber body. The coating may extend around the first surface of the platen, the second surface of the platen, and the shaft. The coating may conformally extend around the first surface of the platen. The coating may include a first layer of silicon adjacent to the first surface of the platen and a second layer of silicon-containing material on top of the first layer of silicon. The coating may be characterized by having a thickness of about 5 μm or more on all coated surfaces. In some embodiments, the second layer of the coating includes silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

[0011] Such technologies can offer many advantages over conventional systems and techniques. For example, embodiments of this technology can provide a substrate support that can be protected from several corrosion processes. Furthermore, protective coatings formed on the substrate support and / or other components can be maintained across hundreds or thousands of wafers, thereby improving throughput. Many of these embodiments and other embodiments, as well as their advantages and features, will be described in more detail below, along with the accompanying figures.

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a top view of an exemplary processing system according to several embodiments of this technology. [Figure 2A]This is a schematic cross-sectional view of an exemplary processing chamber according to an embodiment of this technology. [Figure 2B] This is a detailed view of a portion of the processing chamber shown in Figure 2A, according to an embodiment of this technology. [Figure 3] This is a bottom view of an exemplary shower head according to an embodiment of this technology. [Figure 4] This is a schematic partial cross-sectional view of an exemplary semiconductor processing chamber according to several embodiments of this technology. [Figure 5] This is a schematic partial cross-sectional view of an exemplary substrate support assembly according to several embodiments of the present technology. [Figure 6] This figure shows an exemplary operation in a method according to several embodiments of this technology. [Modes for carrying out the invention]

[0014] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and do not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0015] In the attached diagram, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by a letter following the reference label that distinguishes them from similar components. If only a first reference label is used in the specification, its description is applicable to any of the similar components having the same first reference label, regardless of the letter.

[0016] Semiconductor processing may involve several operations to create complex patterns of material on a substrate. These operations may include several forming and removal processes that utilize corrosive or erosive materials, including plasma-enhanced materials formed remotely or at the substrate level. For example, a halogen-containing gas may be introduced into the processing area, where the material's gases or plasma emissions come into contact with the substrate placed within the area. While etching solutions may preferentially etch the substrate material, chemical etching solutions may also come into contact with other components in the chamber. Etching solutions may chemically attack components, and depending on the process performed, one or more components may be exposed to plasma emissions, which can erode the material. Chemical and physical damage to chamber components caused by etching solutions can lead to wear over time, potentially resulting in higher replacement costs and longer chamber downtime. Similarly, deposition processes may use plasma-enhanced processes to form or deposit material on the substrate, which may also be deposited on chamber components. This process may require a cleaning operation after the substrate is removed from the chamber. The cleaning process may involve using one or more halogen-containing precursors or plasma emissions of these precursors to remove material deposited on the surface within the processing chamber. While cleaning may target deposited material, the surfaces of many exposed chamber components may also be attacked. For example, when a substrate is removed from the processing chamber, the central region of the substrate support will be exposed without residual material. The cleaning process may initiate pitting corrosion or other removal of the substrate support, which may reduce the flatness and integrity of the chuck.

[0017] Conventional techniques have struggled to limit both corrosion and erosion to chamber components, and there is a tendency to regularly replace components due to damage caused by one or both of these mechanisms. Some processes may include a seasoning process prior to semiconductor substrate processing, but this seasoning process can cause further problems. For example, the seasoning process may cover a portion of the substrate support, but will not completely cover the backside or the stem, and the backside or the stem can still be exposed to process materials and cleaning materials. Further, the seasoning process typically deposits coatings of 100 nanometers or less. This can lead to the need to replace the seasoning for each substrate being processed, which can increase queue times and reduce the possibility of uniform or complete coverage.

[0018] The present technology overcomes these problems by coating chamber components prior to substrate processing. For example, components can be completely coated on the surfaces that are exposed within the semiconductor processing chamber. Further, the coating can be characterized by an increasing thickness, which can improve complete coverage and allow the component to be used during the processing of several wafers before the coating is reapplied. Coating the chamber components can partially address corrosion and / or erosion of the coated components, but depending on the coating, further problems can arise. For example, certain oxide coatings can increase the integrity of the component against corrosive materials being sent into the chamber, but the oxide may allow the intrusion of aluminum from the underlying component material and leaching that can penetrate the oxide coating and potentially be present as trace substances on the substrate being processed. However, the present technology can overcome this problem by creating a multi-layer coating that can have an intermediate layer between the underlying component and the overlying protective layer. The intermediate layer can include aluminum or other materials that can limit trace diffusion, which can further protect the chamber component during processing while improving the processing results.

[0019] The remaining disclosure will identify the specific etching processes that utilize the disclosed technology as prescribed, but it will be readily understood that the systems and methods are equally applicable to other deposition chambers and cleaning chambers, as well as the processes that may be performed within the chambers described. Thus, the technology should not be considered limited to use only with these specific etching processes or chambers. Before describing additional variations and adaptations to this system according to embodiments of the technology in this disclosure, one possible system and chamber that may include a pedestal according to embodiments of the technology will be described.

[0020] FIG. 1 shows a top view of one embodiment of a processing system 100 for deposition, etching, baking, and curing chambers according to an embodiment. In the figure, a pair of front-opening unified pods 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a - 108f located within tandem sections 109a - 109c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to and from the substrate processing chambers 108a - 108f. Each substrate processing chamber 108a - 108f may be equipped to perform several substrate processing operations, including the formation of a laminate of semiconductor materials described herein, in addition to other substrate processes, including plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing, ashing, etc.

[0021] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films or other films on a substrate. In one configuration, two pairs of processing chambers, e.g., 108c-108d and 108e-108f, may be used to deposit dielectric material on a substrate, and a third pair of processing chambers, e.g., 108a-108b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-108f, may be configured to deposit a laminate of alternating dielectric films on a substrate. Any one or more of the processes described may, in different embodiments, be performed in a chamber separated from the indicated manufacturing system. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are intended by system 100.

[0022] Figure 2A shows a cross-sectional view of an exemplary process chamber system 200 having a plasma generation region partitioned within the processing chamber. During etching of films such as titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, a process gas may be flowed into the first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may be optionally included in the system to process the first gas, which then moves through the gas inlet assembly 205. The inlet assembly 205 may include two or more separate gas supply channels, and if a second channel is included, the second channel (not shown) may bypass the RPS 201.

[0023] A cooling plate 203, a faceplate 217, an ion suppressor 223, a shower head 225, and a pedestal 265 or substrate support on which a substrate 255 is placed are shown, each of which may be included according to the embodiment. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, and the heat exchange channels may operate to heat and / or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265 may include aluminum, ceramic, or a combination thereof, and may also be resistance-heated using embedded resistance heater elements to achieve relatively high temperatures, such as from about 100°C or below to about 1100°C or above.

[0024] The faceplate 217 may be pyramidal, conical, or another similar structure with a narrow top widening to a broad base. The faceplate 217 may also be flat, as shown, and may include multiple through-channels used to distribute the processing gas. For more uniform delivery to the first plasma region 215, depending on the use of the RPS 201, the plasma-generating gas and / or plasma-excited species may pass through multiple holes in the faceplate 217, as shown in Figure 2B.

[0025] An exemplary configuration may include having a gas inlet assembly 205 that opens into a gas supply region 258 partitioned from the first plasma region 215 by the faceplate 217, so that a gas / seed flows into the first plasma region 215 through a hole in the faceplate 217. Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 to the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The faceplate 217, i.e., the conductive upper part of the chamber, and the showerhead 225 are shown together with an insulating ring 220 positioned between them, which allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or ion suppressor 223. The insulating ring 220 may be located between the faceplate 217 and the showerhead 225 and / or ion suppressor 223, thereby allowing a capacitively coupled plasma (CCP) to form in the first plasma region. In addition, to influence the fluid flow entering the region through the gas inlet assembly 205, a baffle (not shown) may be positioned within the first plasma region 215 or otherwise coupled to the gas inlet assembly 205.

[0026] The ion suppressor 223 may comprise a plate or other shape dimensions defining multiple openings throughout the structure, the openings configured to suppress the movement of charged ions departing from the first plasma region 215, while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into the activated gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may comprise a porous plate with various opening configurations. These uncharged species may include highly reactive species transported through the openings along with a less reactive carrier gas. As described above, the movement of ion species through the holes can be reduced, and in some cases completely suppressed. By controlling the amount of ion species passing through the ion suppressor 223, control over the mixed gas in contact with the underlying wafer substrate can be advantageously improved, and consequently, control over the deposition and / or etching properties of the mixed gas can be improved. For example, adjusting the ion concentration of the mixed gas can significantly alter its etching selectivity, such as the SiNx:SiOx etching ratio, Si:SiOx etching ratio, etc. In alternative embodiments where deposition is performed, the balance between conformal deposition and flow deposition of the dielectric material can also be shifted.

[0027] Multiple openings within the ion suppressor 223 may be configured to control the passage of the activated gas, i.e., ionic species, radical species, and / or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, i.e., the diameter relative to the length of the holes, and / or the shape dimensions of the holes may be controlled to reduce the flow of charged ionic species in the activated gas passing through the ion suppressor 223. The holes within the ion suppressor 223 may include tapered portions facing the plasma excitation region 215 and cylindrical portions facing the showerhead 225. The cylindrical portions may have a shape and dimensions that control the flow of ionic species passing through the showerhead 225. As an additional means for controlling the flow of ionic species through the suppressor, an adjustable electrical bias may be applied to the ion suppressor 223.

[0028] The ion suppressor 223 may function to reduce or remove the amount of charged ions moving from the plasma generation region to the substrate. Uncharged neutral and radical species may further pass through the ion suppressor opening to react with the substrate. Note that in embodiments, complete removal of charged ions in the reaction region around the substrate may not be achieved. In certain cases, ion species are intended to reach the substrate to perform etching and / or deposition processes. In such cases, the ion suppressor may help control the concentration of ion species in the reaction region to a level that supports the process.

[0029] By combining the showerhead 225 with the ion suppressor 223, it is possible to avoid the plasma present in the first plasma region 215 directly exciting the gas in the substrate processing region 233, while simultaneously allowing excited species to move from the chamber plasma region 215 into the substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from coming into contact with the substrate 255 being etched. This is advantageous in that it can protect various complex structures and films patterned on the substrate that could be damaged, displaced, or distorted if they were directly contacted by the generated plasma. Furthermore, if it is permissible for the plasma to come into contact with the substrate or approach the substrate level, the etching rate of oxide species may increase. Therefore, if the exposed area of ​​the material is an oxide, this material can be further protected by keeping the plasma away from the substrate.

[0030] The processing system may further include a power supply 240 electrically coupled to the processing chamber for powering the faceplate 217, ion suppressor 223, showerhead 225, and / or pedestal 265 to generate plasma in the first plasma region 215 or processing region 233. The power supply may be configured to deliver a tunable amount of power to the chamber depending on the process being performed. Such a configuration may allow for the use of a tunable plasma in the process being performed. Unlike remote plasma units, which are often presented with on or off functions, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This may allow for the development of specific plasma properties, such as when precursors are dissociated in a particular way to enhance the etching profile created by these precursors.

[0031] The plasma can be ignited in either the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. For example, the plasma may be present in the chamber plasma region 215 to create a radical precursor from the inflow of a fluorine-containing precursor or other precursor. To ignite the plasma in the chamber plasma region 215 during deposition, a typically high-frequency (RF) band AC voltage may be applied between the conductive upper part of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or the ion suppressor 223. The RF power supply may generate a high RF frequency of 13.56 MHz, but may generate other frequencies alone or in combination with the 13.56 MHz frequency.

[0032] Figure 2B shows a detailed diagram 253 of features that affect the distribution of the processing gas through the faceplate 217. As shown in Figures 2A and 2B, the faceplate 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258 into which the processing gas can be supplied from the gas inlet 205. The gas can fill the gas supply region 258 and flow through openings 259 in the faceplate 217 to the first plasma region 215. The processing gas can flow into the processing region 233, but the openings 259 may be configured to direct the flow substantially in one direction so that backflow into the gas supply region 258 after crossing the faceplate 217 is partially or completely prevented.

[0033] A gas distribution assembly, such as the showerhead 225 used in the processing chamber section 200, may be referred to as a dual-channel showerhead, which is described in more detail in the embodiment shown in Figure 3. A dual-channel showerhead can provide an etching process that allows for the separation of the etching solution outside the processing area 233, resulting in limited interaction between the chamber components and each other before being delivered into the processing area.

[0034] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be joined to each other so as to define a volume 218 between them. The joining of the plates may provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the volume 218 through the lower plate 216 only through the second fluid channel 221, and the first fluid channel 219 may be fluidically isolated from the volume 218 between the plates and the second fluid channel 221. The volume 218 may be fluidly accessible through the sides of the showerhead 225.

[0035] Figure 3 is a bottom view of a showerhead 325 used in a processing chamber according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in Figure 2A. The through-holes 365, which represent the appearance of the first fluid channel 219, may have multiple shapes and configurations to control and influence the flow of the precursor through the showerhead 225. The small holes 375, which represent the appearance of the second fluid channel 221, may be distributed substantially uniformly on the surface of the showerhead even between the through-holes 365, and may help provide a more uniform mixing of the precursor as it exits the showerhead compared to other configurations.

[0036] Figure 4 shows a schematic partial cross-sectional view of an exemplary semiconductor processing chamber 400 according to several embodiments of the present technology. Figure 4 may include one or more components described above with respect to Figure 2A and may illustrate further details of the chamber. The chamber 400 may be used to perform semiconductor processing operations, including etching or removal and deposition operations or cleaning operations. For example, the processing chamber 400 may be a chamber for a plasma etcher or plasma etching reactor, a plasma cleaner, a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, or any other type of semiconductor processing chamber. The chamber 400 may show a partial view of the processing area of ​​a semiconductor processing system and may not include all components understood to be incorporated in some embodiments of the chamber 400, such as the additional lid stack components described above.

[0037] As mentioned, Figure 4 may illustrate a portion of the processing chamber 400. The chamber 400 may include a shower head 405 and a substrate support 410. The shower head 405 and the substrate support 410, together with the chamber sidewall 415, can define a substrate processing area 420, within which plasma may be generated in several processes. The processing area 420 may illustrate a location where a substrate may be housed for semiconductor processing. The substrate support assembly may include a platen 425, which may include one or more components embedded or positioned within the body, including electrodes, heaters, fluid channels, or other components. Components incorporated within the upper pack may not be exposed to the processing material in some embodiments and may be entirely contained within the platen 425. The platen 425 may define a substrate support surface 427 that can face the shower head 405, which may be characterized by a thickness and length or diameter depending on the specific shape dimensions of the platen. In some embodiments, the platen may be elliptical and characterized by one or more radial dimensions from a central axis passing through the body. The upper pack may have any shape and dimensions, and if radial dimensions are mentioned, it should be understood that these radial dimensions may define any length from the center position of the platen.

[0038] The platen 425 may be coupled to a stem or shaft 430, which may support the platen and include channels for supplying and receiving electrical and / or fluid lines that may be coupled to internal components of the platen 425. The platen 425 may include an electrostatic chuck, a vacuum chuck, or other type of chucking system, and associated channels or components that act as a non-chucking substrate support surface. The shaft 430 may be coupled to the platen on a second surface of the platen opposite the substrate support surface. The platen 425 may include an electrode 435, which may be a DC electrode, embedded within the platen in close proximity to the substrate support surface. The electrode 435 may be electrically coupled to a power supply 440. The power supply 440 may be configured to supply energy or voltage to the conductive chuck electrode 435. This may act to form a precursor plasma within the processing area 420 of the semiconductor processing chamber 400, although other plasma operations may also continue. For example, electrode 435 may also be a chucking mesh acting as an electrical ground for a capacitive plasma system including an RF source 407 electrically coupled to a showerhead 405. For example, electrode 435 may act as a ground path for RF power from the RF source 407 and at the same time as an electrical bias to the substrate to provide electrostatic clamping of the substrate to the substrate support surface. Power supply 440 may include filters, power supplies, and many other electrical components configured to provide chucking voltages. Electrode 435 may also be a heating element that can be incorporated into the platen as an additional electrode or as a replacement for an electrode.

[0039] In some embodiments, the platen 425 may also define a recessed region 445 within the substrate support surface, which may provide a recessed pocket in which a substrate can be placed. The recessed region 445 may be formed in the internal region of the upper pack and may be configured to accommodate a substrate for processing. The recessed region 445 may surround the central region of the platen, as illustrated, and may be sized to accommodate various substrate sizes. The substrate may be seated within the recessed region and accommodated by an external region 447 that may surround the substrate. In some embodiments, the height of the external region 447 may be such that the substrate is recessed to the same height as the surface height of the substrate support surface in the external region 447, or to a lower height. The recessed surface may control the edge effect during processing, which may, in some embodiments, improve uniformity across the entire substrate. In some embodiments, an edge ring may be positioned around the upper pack and may at least partially define a recess in which a substrate can be seated. In some embodiments, the surface of the platen may be substantially planar, and the edge ring may completely define a recess in which a substrate can be seated. Furthermore, the platen may be characterized by an edge profile, which will be further described below, or any other shape dimensions or features that may be created around the substrate support.

[0040] In some embodiments, the platen 425 and / or shaft 430 may be an insulating or dielectric material, while in some embodiments, the platen 425 and / or shaft 430 may be a metal such as aluminum or other conductive material. For example, oxides, nitrides, carbides, and other materials may be used to form the components. Exemplary materials may include ceramics, including aluminum oxide, aluminum nitride, silicon carbide, tungsten carbide, and oxides, nitrides, carbides, borides, or titanates of any other metal or transition metal, as well as combinations of these materials with other insulating or dielectric materials. Different grades of ceramic materials may be used to provide composites configured to operate within a specific temperature range, and therefore, in some embodiments, different ceramic grades of similar materials may be used for the top pack and stem. In some embodiments, dopants may be incorporated to adjust the electrical properties. Exemplary dopant materials may include yttrium, magnesium, silicon, iron, calcium, chromium, sodium, nickel, copper, zinc, or any number of other elements known to be incorporated into ceramic or dielectric materials.

[0041] The heater may be capable of adjusting the temperature of the entire platen 425, as well as the substrate on the substrate support surface 427. The heater may have an operating temperature range for heating the platen and / or substrate to about 100°C or higher, and the heater may be configured to heat to about 125°C or higher, about 150°C or higher, about 175°C or higher, about 200°C or higher, about 250°C or higher, about 300°C or higher, about 350°C or higher, about 400°C or higher, about 450°C or higher, about 500°C or higher, about 550°C or higher, about 600°C or higher, about 650°C or higher, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, about 950°C or higher, about 1000°C or higher, or higher. The heater may also be configured to operate within any range that falls within any two of these listed values, or within a smaller range that falls within either of these ranges.

[0042] As described above, the technology can perform processing within a chamber incorporating coated chamber components. While the substrate support is described frequently in the remaining disclosure, in some embodiments, any component including the chamber wall or any lid stack component may be similarly coated with any of the coating materials described below. For example, a showerhead which may include two plates joined together may be coated individually as each plate before joining, or after joining, some or all of the outer surfaces of the showerhead may be coated as described below.

[0043] The substrate support 410 may include a coating 450 that can extend around all exposed surfaces of the substrate support 410, including the first and second surfaces of the platen and the shaft. The coating may be formed individually or conformally with respect to each component. For example, the coating 450 may be applied after coupling with the platen and stem, or applied to each component before coupling. The shaft 430 may extend at least partially through the chamber body, as illustrated, and in some embodiments, the entire length of the shaft, including the length through the chamber, may be coated. The shaft 430 may be coupled to a hub 455 that may be located outside the processing chamber, as illustrated. The coating 450 may extend along the shaft body to the hub. A ring connector 457 may extend around the shaft and connect the shaft to the hub, and in some embodiments, the coating may extend within a portion of the connector. As mentioned above and further described below, in some embodiments, the coating 450 may consist of multiple layers.

[0044] Figure 5 shows a schematic partial cross-sectional view of an exemplary substrate support assembly 500 according to several embodiments of the present art, which may show further details of the previously illustrated coated platen 425. Although the coating is not shown, the coating may conformally extend around all the aforementioned surfaces, including the protrusions and edge features described herein, and according to several embodiments of the present art, may include any number of coating layers. The substrate support assembly 500 may include any of the aforementioned materials or components, which may illustrate further details of the aforementioned substrate support assembly. As illustrated, the platen 505 may define a substrate support surface 506. In some embodiments, the surface may be flat, but in some embodiments, it may include features and be defined by the platen. These features may be configured to support a semiconductor substrate. The substrate support surface may define a region 508 within the substrate support surface in which the substrate can be held, such as a recessed pocket as described above. The recessed pocket may be formed by an outer division, but in some embodiments, any number of other edge features extending from the first surface of the substrate support may be formed. For example, a concave ledge 510 may also be formed on the substrate support surface. The concave ledge may extend radially outward from the radial outer edge of the concave pocket to the outer edge of the platen.

[0045] Furthermore, the substrate support surface may define a number of protrusions 525 extending from the substrate support surface within the support surface in region 508. The exposed surface over the entire protrusion 525 may define contact positions where the substrate can come into contact with the substrate support surface. For example, the technology may form protrusions characterized by having a diameter or width of about 1 mm, about 2 mm, or larger, and in some embodiments, this may include a combination of protrusions characterized by a diameter of about 1 mm or more and protrusions characterized by a diameter of about 2 mm or more. In embodiments of the technology, the protrusions may be characterized by any number of shape dimensions and profiles. In an exemplary substrate support assembly, the substrate support surface in the recessed pocket may define about 250 or more protrusions, and further may define about 500 or more protrusions, about 750 or more protrusions, about 1000 or more protrusions, about 1250 or more protrusions, about 1500 or more protrusions, about 1750 or more protrusions, about 2000 or more protrusions, or more protrusions. The protrusions can be defined by any number of arrangements or patterns, including uniform patterns and overall distributions across the entire surface.

[0046] The coating 450 can be formed on all areas of the substrate support. Unlike the seasoning process, the coating 450 can be formed evenly around the substrate support, such as along the back of the platen and along the entire length of the shaft. The coating is or may contain a silicon-containing coating, and may be silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride, and any combination of these materials, or may contain them. The coating can be formed to a thickness of about 1 μm or more over the entire surface of the pedestal, and further to a thickness of about 2 μm or more, about 5 μm or more, about 10 μm or more, about 15 μm or more, about 20 μm or more, about 25 μm or more, about 30 μm or more, or thicker. This makes it possible to create coatings that are orders of magnitude thicker than any seasoning, and also to create coatings that cover all surfaces of the component. Furthermore, the coating can be maintained at a thickness of approximately 50 μm or less, approximately 45 μm or less, approximately 40 μm or less, approximately 35 μm or less, or thinner, thereby ensuring that in some embodiments, the coating can be formed around the entire surface of the protrusions but does not completely fill the features.

[0047] As described above, in some embodiments of this technology, the coating may be a multilayer coating that can offer advantages over any single-layer coating. To create any number of composite coatings, any layer of the coating may be one of the materials described above, or contain one of the materials described above. In a non-limiting example, in some embodiments, a first layer of the coating adjacent to the part surface, including being adjacent to or in contact with the part surface, may be a silicon layer. The silicon layer may be amorphous silicon, but crystalline silicon may also be used. A second layer of silicon-containing material, such as one of the materials described above, may be present on the amorphous silicon. In a non-limiting example, silicon oxide may be formed on the silicon layer. Silicon oxide may be a crystalline material, but in some embodiments, silicon oxide may also be amorphous silicon oxide.

[0048] Silicon oxide can be formed by oxidizing a portion of the formed silicon layer, and in some embodiments, this can constitute a silicon oxide layer. However, oxidation operations at high temperatures are more likely to produce crystalline silicon oxide, or may produce only crystalline silicon oxide. Crystalline silicon oxide may provide less protection compared to amorphous silicon oxide, and therefore, in some embodiments, silicon oxide may be subsequently deposited on top of amorphous silicon, thereby ensuring two consecutive amorphous layers of the material. In some embodiments of the art, any number of additional layers may be formed on top of any of these layers, and any of the other materials mentioned may be used together with or in place of these materials.

[0049] As described above, the components on which a layer may be formed may be, or may contain, any number of other ceramic materials, including aluminum containing aluminum nitride, or several constituent elements such as yttrium, sodium, nickel, and potassium, among other elements commonly incorporated. High-temperature processing can increase the diffusion of trace substances, and silicon oxide can diffuse aluminum or other substances into the layer, which may exist as particles on the substrate being processed. Amorphous silicon, due to its higher material density, can act as a barrier to elemental diffusion much more readily than silicon oxide, limiting or further reducing the presence of these elements on the substrate being processed. Silicon can be readily etched or corroded by etchant gases or radical species, and therefore, having a corrosive layer of material on top can prevent the removal of silicon during the etching process. Thus, multilayer coatings can improve elemental diffusion from the underlying component material and can also provide better corrosion and / or erosion protection than conventional materials.

[0050] Depending on the component material on which the coating is formed, silicon may have lower adhesion than other materials, which can reduce the effectiveness of the coating or cause delamination. Therefore, in some embodiments, an additional adhesive layer may be formed between the amorphous silicon layer and the component itself. For example, in some embodiments, to create a multilayer coating, an additional silicon oxide layer may be formed as an adhesive layer between the component and the amorphous silicon layer, along with an amorphous silicon oxide layer formed on top of the amorphous silicon layer. The adhesive layer may be amorphous silicon oxide in some embodiments, but crystalline silicon oxide may also be used. By incorporating an adhesive layer, the coating can be well maintained on the substrate component and withstand tensile tests while exhibiting an adhesive strength of about 500 psi or more. Incorporating an adhesive layer can result in adhesive strengths of about 750 psi or more, about 1000 psi or more, about 1250 psi or more, about 1500 psi or more, about 1750 psi or more, about 2000 psi or more, or higher. Since the multilayer coating produced by this technology can be used in high-temperature environments, the risk of coating delamination is much greater than in other environments. Therefore, by having higher adhesive strength, the coating can be reliably maintained through numerous processing operations.

[0051] A multilayer coating comprising any individual layers may be characterized by having any of the thicknesses described above, but in some embodiments, the overall thickness of the coating may be limited to a few micrometers or less to ensure that protrusions or other substrate or component features are not clogged or filled by the coating. Furthermore, in some embodiments, the layers may be characterized by having different thicknesses from one another based on the function of the layer in the coating, thereby maximizing the degree of corrosion or erosion resistance of the layers while minimizing the height of the constituent layers. For example, in the case of an exemplary multilayer coating comprising or consisting of a silicon oxide adhesive layer, an amorphous silicon barrier layer, and an amorphous silicon oxide outer protective layer, the layers may or may not be characterized by having similar thicknesses.

[0052] As an example of coating thickness, the adhesive layer may be formed to a thickness that adequately coats the component and provides an adhesive surface to the silicon layer above it, and the adhesive layer may be formed to a thickness of about 100 nm or less, and further to a thickness of about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, or thinner. The amorphous silicon barrier layer may be formed to a thickness greater than the adhesive layer to ensure sufficient barrier properties against the diffusion of aluminum or other trace elements, but its thickness may be limited to allow the majority of the layer thickness to be used for corrosion protection. Therefore, the amorphous silicon barrier layer can be formed to a thickness of approximately 50 nm or more, approximately 75 nm or more, approximately 100 nm or more, approximately 125 nm or more, approximately 150 nm or more, approximately 175 nm or more, approximately 200 nm or more, approximately 225 nm or more, approximately 250 nm or more, approximately 275 nm or more, approximately 300 nm or more, approximately 325 nm or more, approximately 350 nm or more, approximately 375 nm or more, approximately 400 nm or more, or thicker than that, but the barrier properties may be sufficient with a thickness of approximately 500 nm or less, and furthermore, may be sufficient with a thickness of approximately 450 nm or less, approximately 400 nm or less, approximately 350 nm or less, approximately 300 nm or less, or less.

[0053] An outer layer, such as amorphous silicon dioxide, or any of the other materials mentioned above, may constitute the majority of the coating thickness. To provide sufficient protective properties, the second coating layer, or the outermost layer of a multilayer coating, may be characterized by a thickness of approximately 500 nm or more, and further, by a thickness of approximately 550 nm or more, approximately 600 nm or more, approximately 650 nm or more, approximately 700 nm or more, approximately 750 nm or more, approximately 800 nm or more, approximately 850 nm or more, approximately 900 nm or more, approximately 950 nm or more, approximately 1.0 μm or more, or thicker. The outermost layer may also constitute approximately 60% or more of the total thickness of the multilayer coating, and further, it may constitute approximately 70% or more, approximately 75% or more, approximately 80% or more, approximately 82% or more, approximately 84% or more, approximately 86% or more, approximately 88% or more, approximately 90% or more, approximately 91% or more, approximately 92% or more, approximately 93% or more, approximately 94% or more, approximately 95% or more, approximately 96% or more, approximately 97% or more, approximately 98% or more, or more of the total thickness of the coating. This allows for sufficient barrier and adhesive properties while maximizing the ability to protect the underlying components from etching or other process conditions.

[0054] The coating or constituent layer may be created by any number of methods, including plasma chemical vapor deposition, which can form a consistent coating around the feature. For example, in some embodiments, the thickness of the coating or any individual layer over the entire substrate support surface may be kept substantially constant, characterized by surface variation of about 10% or less between any two positions on the substrate support surface, and further characterized by surface variation of about 9% or less, about 8% or less, about 7% or less, about 6% or less, about 5% or less, about 4% or less, about 3% or less, about 2% or less, about 1% or less, or less.

[0055] Based on the coating process, some surfaces may be characterized by greater coverage. For example, a concave ledge 510, or any other corner feature including a ledge defining a concave internal pocket as described above, may be characterized by a coating and / or coating layer thickness that is at least 10% thicker than the coating thickness along the first surface of the platen, and furthermore, the coating thickness may be about 15% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, or thicker than the coating thickness along the first surface of the platen. Unlike substrate surfaces or back surfaces that can be covered or are directly outside the flow path or plasma area, these features such as corner features can be exposed during plasma operation, so the additional coverage can enhance the protection of these areas during processing, which may allow for a longer time before recoating can be performed on the chamber component.

[0056] Figure 6 shows exemplary operation of method 600, which can be performed in any chamber containing a chamber component having the aforementioned coating, according to several embodiments of the Art. In optional operation 605, the coating may be applied in a coating chamber, which may be separate from a semiconductor processing chamber in which a substrate may be processed using the chamber component. Each layer of a multilayer coating may be formed in the same chamber or, according to several embodiments of the Art, in multiple chambers. The coating may be applied to all surfaces of the component and may contain any of the materials described above. The coating or component may feature any of the aforementioned features or characteristics. For example, a silicon-containing material may be coated on the entire surface of the platen and shaft of a substrate support, or on the outer surface of a bonded substrate support, or on other chamber components. In optional operation 610, the chamber component may be placed in a semiconductor processing chamber, which may extend the component partially or entirely within the chamber. For example, the aforementioned substrate support may extend at least partially out of the chamber, including portions that may contain the previously applied coating.

[0057] In operation 615, semiconductor processing can be performed on the component. For example, using the coated component described above, any number of substrates can be processed in the chamber or any number of cleaning operations can be performed in the processing chamber. For example, more than about 5 substrates can be processed or more than about 5 cleaning operations can be performed. The coating can be affected by each process, but the coating can enable the processing of more than about 10 substrates or the performance of more than about 10 cleaning operations, and further enable more than about 50, more than about 100, more than about 500, more than about 1,000, more than about 5,000, or more processing. The processing can include any number of different etching processes or other semiconductor manufacturing processes that expose the coated component to any number of etching chemicals. For example, the component can be exposed to an etching solution in either radical or non-excited form and can be exposed to one or more of BCl3, Cl2, HF, NF3, F2, PCl5, HI, C2F6, CF4, or any other halogen-containing material, such as one or more halogen-containing gases or radicals including fluorine-containing materials or chlorine-containing materials.

[0058] Furthermore, the multilayer coating can limit aluminum or other trace metal contamination on the substrate or within the outer layer or the second layer of the multilayer coating. For example, the uptake of aluminum from the second layer or the outermost layer of the coating or from components beneath the substrate being processed can be 2 less than about 1E12 atoms / cm 2 and further, less than about 1.8E11 atoms / cm 2 less than about 1.6E11 atoms / cm 2 less than about 1.4E11 atoms / cm 2 less than about 1.2E11 atoms / cm 2 less than about 1.0E11 atoms / cm 2 less than about 1.8E10 atoms / cm 2 less than about 1.6E10 atoms / cm 2 less than about 1.4E10 atoms / cm 2Below, about 1.0E10atoms / cm 2 It may be maintained at or below the following levels. By limiting downtime for seasoning or component replacement, coated components according to embodiments of this technology can improve throughput and protect components and substrates compared to conventional technologies.

[0059] In the above description, many details have been provided for illustrative purposes in order to provide an understanding of the various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be carried out without some of these details or with further details.

[0060] While several embodiments have been disclosed, those skilled in the art will understand that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the Art.

[0061] Where a range of values ​​is provided, unless otherwise specified in the context, each value interposing between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest fraction of the lower limit. Any narrower range between any listed value or unlisted interposing value within a listed range and any other listed value or interposing value within that listed range is included. The upper and lower limits of these smaller ranges may be included or excluded from the range alone, and ranges that include one or both limit values, ranges that do not include either limit value, or ranges that include both limit values ​​are each included in this technique, subject to any limit values ​​explicitly excluded in the listed range. If a listed range includes one or both limit values, the range excluding one or both of those limit values ​​is also included.

[0062] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless otherwise specified in the context. Thus, for example, a reference to "an electrode" includes multiple such electrodes, and a reference to "the protrusion" includes one or more protrusions and equivalents well known to those skilled in the art.

[0063] Furthermore, the terms “comprise,” “comprising,” “contain,” “containing,” “include,” and “including,” as used herein and in the following claims, are intended to specify the presence of the described feature, integer, component, or action, but do not preclude the presence or addition of one or more other features, integers, components, actions, functions, or groups.

Claims

1. A semiconductor processing chamber, Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, A semiconductor processing chamber wherein the coating extends over the entire surface of the substrate support exposed within the semiconductor processing chamber and to the portion of the shaft extending outside the semiconductor processing chamber, and the coating conformally extends around the first surface of the platen, and the coating comprises a first layer of silicon on the first surface of the platen and a second layer of material on the first layer of silicon.

2. The semiconductor processing chamber according to claim 1, wherein the second layer of the coating comprises a silicon-containing material.

3. The semiconductor processing chamber according to claim 2, wherein the second layer of the coating comprises silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

4. The semiconductor processing chamber according to claim 1, wherein the platen defines a plurality of protrusions extending from the first surface of the platen.

5. The semiconductor processing chamber according to claim 4, wherein the coating extends around each of the multiple protrusions.

6. The semiconductor processing chamber according to claim 1, characterized in that the coating has a thickness of 1 μm or more on all coated surfaces.

7. The semiconductor processing chamber according to claim 6, characterized in that the coating extending over the first surface of the substrate support has a thickness variation of 10% or less.

8. A semiconductor processing chamber, Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, The coating extends over the entire surface of the substrate support exposed within the semiconductor processing chamber, and the coating conformally extends around the first surface of the platen, wherein the coating comprises a first layer of silicon on the first surface of the platen and a second layer of material on the first layer of silicon. The corner feature of the platen extending from the first surface is characterized in that the thickness of the coating is at least 10% thicker than the thickness of the coating along the first surface of the platen. Semiconductor processing chamber.

9. The semiconductor processing chamber according to claim 1, wherein the shaft of the substrate support is coupled to a hub on the outside of the semiconductor processing chamber, and the coating extends along the shaft to the hub.

10. The semiconductor processing chamber according to claim 1, wherein the platen contains aluminum nitride.

11. A semiconductor processing chamber, Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, The coating extends over the entire surface of the substrate support exposed within the semiconductor processing chamber, and the coating conformally extends around the first surface of the platen, wherein the coating comprises a first layer of silicon on the first surface of the platen and a second layer of material on the first layer of silicon. The shower head comprises a first plate and a second plate joined together so as to define a volume between the first plate and the second plate, and the outer surfaces of the first plate and the second plate of the shower head are coated with a material similar to that of the substrate support. Semiconductor processing chamber.

12. A semiconductor processing method comprising sending a halogen-containing precursor plasma emission into a processing area of ​​a semiconductor processing chamber, wherein the semiconductor processing chamber is Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, A semiconductor processing method comprising: a coating extending over the entire surface of the substrate support exposed within the semiconductor processing chamber and over the portion of the shaft extending outside the semiconductor processing chamber, and a coating conformally extending around the first surface of the platen, wherein the coating comprises a first layer of silicon on the first surface of the platen and a second layer of silicon-containing material on the first layer of silicon.

13. Coating the substrate support in a coating chamber separate from the semiconductor processing chamber, The substrate support is placed inside the semiconductor processing chamber. The semiconductor processing method according to claim 12, further comprising:

14. The semiconductor processing method according to claim 12, further comprising processing at least 10 substrates in the semiconductor processing chamber before removing the substrate support, or cleaning the processing area of ​​the semiconductor processing chamber at least 10 times with a halogen-containing precursor.

15. The semiconductor processing method according to claim 12, wherein the second layer of the coating comprises silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

16. The semiconductor processing method according to claim 12, characterized in that the coating has a thickness of 1 μm or more on all coated surfaces.

17. The second layer of the coating has a density of 1E10 atoms / cm². ２ The semiconductor processing method according to claim 16, characterized by containing the following trace amounts of aluminum metal.

18. A semiconductor processing method comprising sending a halogen-containing precursor plasma emission into a processing area of ​​a semiconductor processing chamber, wherein the semiconductor processing chamber is Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, The coating extends over the entire surface of the substrate support exposed within the semiconductor processing chamber, and the coating conformally extends around the first surface of the platen, wherein the coating comprises a first layer of silicon on the first surface of the platen and a second layer of silicon-containing material on the first layer of silicon. The corner feature of the platen extending from the first surface is characterized in that the thickness of the coating is at least 10% thicker than the thickness of the coating along the first surface of the platen. Semiconductor processing method.

19. A semiconductor processing chamber, Chamber body and Shower head and A substrate support, A platen characterized by a first surface facing the shower head, and A shaft connected to the platen along the second surface of the platen, opposite to the first surface of the platen. A substrate support comprising Equipped with, The shaft extends at least partially through the chamber body, A semiconductor processing chamber characterized in that the coating extends over the entire surface of the substrate support exposed within the semiconductor processing chamber and to the portion of the shaft extending outside the semiconductor processing chamber, the coating conformally extends around the first surface of the platen, the coating comprises a first layer of silicon on the first surface of the platen and a second layer of silicon-containing material on the first layer of silicon, and the thickness of the coating on all coated surfaces is 5 μm or more.

20. The semiconductor processing chamber according to claim 19, wherein the second layer of the coating comprises silicon carbide, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

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