Microchip for driving resonant circuits

Abstract

A microchip (300) for driving a resonant circuit, the resonant circuit being an LC tank, an antenna or a piezo transducer, the microchip (300) being a single unit including multiple interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog to digital converter (ADC) subsystem (318), and a digital to analog converter (DAC) subsystem (327).

Description

Technical Field

[0001] The present invention relates to a microchip for driving a resonant circuit. More particularly, the present invention relates to a microchip for driving a resonant circuit in the form of an LC tank, an antenna or a piezoelectric transducer.

Background Art

[0002] Therapeutic aerosol delivery is a mainstay in the treatment of asthma, chronic obstructive pulmonary disease (COPD) and cystic fibrosis. Therapeutic aerosols also have uses for the treatment of influenza, osteoporosis and the delivery of vaccines.

[0003] Lung delivery of therapeutic agents for the treatment of non-respiratory systemic diseases is attractive because of high pulmonary vascularity, thin blood-alveolar barrier, large surface area, avoidance of gastric enzymes and first-pass liver metabolism. It is also attractive for improved patient comfort and adherence. The pulmonary system can be utilized to deliver antibodies, proteins, analgesics and nucleic acids. Treatment of central nervous system disorders such as tobacco dependence can be significantly enhanced through the efficient delivery of nicotine to the systemic circulation through the lungs.

[0004] The effectiveness of therapeutic aerosols is related to the amount of drug deposited beyond the oropharyngeal region. The region where deposition occurs is a function of the inhaled particle size.

[0005] Devices currently used for the administration of inhaled drugs are classified into three categories: nebulizers, metered-dose inhalers, and dry powder inhalers. Nebulizers are typically classified into two types: jet and ultrasonic, but both types have weaknesses and present problems in conventional devices.

[0006] Jet nebulizers are based on Bernoulli's principle and produce relatively large droplets, which generally deposit in the oral and pharyngeal region and are therefore not particularly effective. Ultrasonic nebulizers use piezoelectric crystals that vibrate at frequencies in the range of 1 MHz to 1.7 MHz, transferring vibrational energy to a liquid and converting it into an aerosol. Ultrasonic nebulizers are not effective when viscous suspensions or solutions are used and tend to heat the medication, thus destroying molecules and negating the benefits of inhalation.

[0007] Other applications require a resonant circuit that is efficiently driven in an optimal manner at or near its resonant frequency. For example, a device incorporating a resonant circuit in the form of an antenna typically needs to drive the antenna with a precise AC drive signal to enable the antenna to function optimally. Furthermore, a device incorporating a resonant circuit in the form of an ultrasonic piezo transducer must generate an AC drive signal to optimally drive the ultrasonic transducer.

[0008] Therefore, in the art, there is a need for microchips for driving resonant circuits such as LC tanks, antennas, or piezo transducers that attempt to address at least some of the problems described herein. [Overview of the Initiative]

[0009] The present invention provides a microchip as described in claim 1 or claim 13 and an apparatus as described in claim 16. The present invention also provides preferred embodiments as described in the dependent claims.

[0010] The various examples of this disclosure described below offer several advantages and benefits over conventional microchips. These advantages and benefits are described below.

[0011] The example microchips and devices of this disclosure enable more efficient operation than conventional microchips and devices, and therefore the example microchips and devices of this disclosure have environmental benefits due to reduced power requirements. [Brief explanation of the drawing]

[0012] To make the disclosure more easily understandable, preferred embodiments of the disclosure are described herein merely as examples with reference to the accompanying drawings. [Figure 1] This is a schematic diagram of the integrated circuit configuration of the disclosed information. [Figure 2] This is a schematic diagram of the integrated circuit of the present disclosure. [Figure 3] This is a schematic diagram of the pulse width modulation generator disclosed herein. [Figure 4] This is a timing diagram of an example of the disclosure. [Figure 5] This is a timing diagram of an example of the disclosure. [Figure 6] This table shows an example of port functionality in this disclosure. [Figure 7] This is a schematic diagram of the integrated circuit of the present disclosure. [Figure 8] This is a circuit diagram of an example of an H-bridge in this disclosure. [Figure 9] This is a circuit diagram of an example of a current sensing configuration in this disclosure. [Figure 10] This is a circuit diagram of an example of an H-bridge in this disclosure. [Figure 11] Figure 8 is a graph showing the voltages during the operation phases of the H-bridge. [Figure 12] Figure 8 is a graph showing the voltages during the operation phases of the H-bridge. [Figure 13] This graph shows the voltage and current at the terminals of the ultrasonic transducer while it is driven by the H-bridge shown in Figure 8. [Figure 14] This is a schematic diagram showing the connections between integrated circuits in this disclosure. [Figure 15] This is a schematic diagram of the integrated circuit of the present disclosure. [Figure 16]It is a diagram showing steps of an authentication method of an example of the present disclosure.

Mode for Carrying Out the Invention

[0013] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that in accordance with standard practice in the art, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. For the sake of simplifying the present disclosure, specific examples of components, concentrations, uses, and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, the attachment of the first feature and the second feature in the following description may include an embodiment in which the first feature and the second feature are attached in direct contact, and an embodiment in which additional features may be arranged between the first feature and the second feature so that the first feature and the second feature do not have to be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself define the relationship between the various embodiments and / or configurations being discussed.

[0015] The following disclosure describes representative examples. Each example may be considered an embodiment, and any reference to "example" may be changed to "embodiment" in the present disclosure.

[0016] Referring now to FIG. 1 of the accompanying drawings, driver device 202 includes a microchip, herein referred to as a power management integrated circuit or PMIC 300. PMIC 300 is a microchip for driving a resonant circuit. The resonant circuit is an LC tank, an antenna, or a piezoelectric transducer. In this example, the resonant circuit is ultrasonic transducer 215 provided within resonant circuit device 201. In this example, resonant circuit device 201 is a separate device releasably coupled to driver device 202. In other examples, elements of resonant circuit device 201 are incorporated into the same device as driver device 202.

[0017] In the present disclosure, the terms chip, microchip, and integrated circuit are interchangeable. A microchip or integrated circuit is a single unit that includes multiple interconnected embedded components and subsystems. A microchip is, for example, at least partially semiconductor such as silicon and is manufactured using semiconductor manufacturing techniques.

[0018] The present disclosure describes an exemplary resonant circuit device 201 that includes ultrasonic transducer 215 of a mist inhaler device. When ultrasonic transducer 215 is activated by driver device 202, ultrasonic transducer 215 atomizes a liquid to produce a mist for inhalation by a user.

[0019] However, it should be understood that elements of the driver device are used differently in other applications that include a resonant circuit. In these other examples, ultrasonic transducer 215 is replaced with another resonant circuit such as an LC tank or an antenna.

[0020] In one example, the resonant circuit device 201 comprises a resonant circuit in the form of a piezoelectric ultrasonic transducer that generates ultrasonic waves used for wireless power transmission. In this example, the ultrasonic transducer is driven by a driver device 202 to generate ultrasonic waves that can be focused and sent to a receiver transducer. The receiver transducer converts the ultrasonic waves back into electrical energy and stores that energy in an energy storage device such as a battery, or uses that electrical energy to power the device. In this way, the device can be remotely charged or powered via power transmitted wirelessly through ultrasonic waves, without the device needing to be connected to an electrical outlet.

[0021] As described below, the driver device 202 is configured to modulate the frequency and duty cycle of an AC power signal that drives an ultrasonic transducer with high precision and efficiency. In the case of a power transmission system, this allows the driver device 202 to encode information for wireless transmission by modulating ultrasound that carries encoded information. For example, the driver device 202 is configured for use in a wireless power transmission system such as, but is not limited to, the type described in U.S. Patent No. 9001622, entitled “receiver communications for wireless power transfer,” which is incorporated herein by reference in its entirety.

[0022] In another example, the driver device 202 drives a resonant circuit in the form of an ultrasonic transducer to deliver ultrasound at precise frequency and high intensity to treat a tumor. The high-intensity focused ultrasound from the ultrasonic transducer is used as a non-invasive targeted therapy to raise the temperature within the tumor to over 65°C, killing tumor cells without damaging surrounding tissue.

[0023] In further applications, the driver device 202 is used to drive a resonant circuit in the form of an antenna to precisely control the frequency and power of the waves transmitted by the antenna. In this example, the antenna can be used for any purpose. In one example, the driver device 202 drives the antenna to transmit waves at a precise frequency for the purpose of searching for minerals or materials such as gold in the earth.

[0024] The driver device 202 comprises a second microchip electrically connected to the PMIC 300, which is referred to herein as a bridge integrated circuit or bridge IC 301. The bridge IC 301 is a microchip for driving resonant circuits such as LC tanks, antennas, or piezo transducers. The bridge IC 301 is a single unit comprising multiple interconnected embedded components and subsystems.

[0025] In this example, the PMIC 300 and the bridge IC 301 are mounted on the same PCB as the driver device 202. In this example, the physical dimensions of the PMIC 300 are 1-3 mm in width and 1-3 mm in length, and the physical dimensions of the bridge IC 301 are 1-3 mm in width and 1-3 mm in length.

[0026] In this example, the resonant circuit device 201 comprises an optional programmable or one-time programmable integrated circuit or OTP IC 242. When the resonant circuit device 201 is coupled to the driver device 202, the OTP IC is electrically connected to the PMIC 300 to receive power from the PMIC 300 so that the PMIC 300 can manage the voltage supplied to the OTP IC 242. The OTP IC 242 is also connected to a communication bus 302 within the driver device 202. In this example, the communication bus 302 is an I2C bus, but in other examples, the communication bus 302 is another type of digital serial communication bus.

[0027] OTP IC 242 provides the security features described below. However, it should be understood that OTP IC 242 is omitted in the examples of this disclosure where such security features are not required.

[0028] The ultrasonic transducer 215 within the resonant circuit device 201 is electrically connected to the bridge IC 301, and the ultrasonic transducer 215 can be driven by the AC drive signal generated by the bridge IC 301 when device 200 is in use.

[0029] The driver device 202 comprises a processor in the form of a microcontroller 303 that is electrically coupled to the communication bus 302. In this example, the microcontroller 303 is a Bluetooth® Low Energy (BLE) microcontroller, but in other examples, the microcontroller 303 is a general-purpose processor. The microcontroller 303 receives power from a low-dropout regulator (LDO) 304 driven by a battery 250. The LDO 304 supplies a stable, regulated voltage to the microcontroller 303, enabling the controller 303 to operate consistently even when the voltage of the battery 250 fluctuates.

[0030] The driver device 202 includes a voltage regulator in the form of a DC-DC boost converter 305 powered by the battery 250. The boost converter 305 raises the voltage of the battery 250 to a programmable voltage VBOOST. The programmable voltage VBOOST is set by the boost converter 305 in response to a voltage control signal VCTL from the PMIC 300. As will be described in more detail below, the boost converter 305 outputs the voltage VBOOST to the bridge IC 301. In other examples, the voltage regulator is a buck converter or another type of voltage regulator that outputs a selectable voltage.

[0031] The voltage control signal VCTL is generated in this example by a digital-to-analog converter (DAC) implemented within the PMIC 300. Since the DAC is integrated into the PMIC 300, it is not visible in Figure 1. The DAC and the technical benefits of integrating it into the PMIC 300 are explained in detail below.

[0032] In this example, the PMIC 300 is connected to a power connector in the form of a USB connector 306 so that the PMIC 300 can receive the charging voltage VCHRG when the Universal Serial Bus (USB) connector 306 is plugged into a USB charger.

[0033] In this example, the driver device 202 includes a first pressure sensor 307, which is a static pressure sensor in this example. The driver device 202 also includes a second pressure sensor 308, which is a dynamic pressure sensor in this example. However, in other examples, the driver device 202 may include only one of the two pressure sensors 307, 308, or the pressure sensors 307, 308 may be omitted entirely. In this example relating to a mist generator device, the pressure sensors 307, 308 sense changes in pressure within an aerosol chamber (not shown) to sense when the user is drawing mist from the aerosol chamber.

[0034] In this example, the driver device 202 includes multiple LEDs 308 controlled by the PMIC 300. In other examples, the LEDs 308 are omitted.

[0035] The microcontroller 303 functions as a master device on the communication bus 302, the PMIC 300 is the first slave device, the OTP IC 242 is the second slave device, the second pressure sensor 308 is the third slave device, and the first pressure sensor 307 is the fourth slave device. The communication bus 302 allows the microcontroller 303 to control the following functions within the driver device 202. 1. All functions of the PMIC are highly configurable by the microcontroller 303. 2. The current flowing through the resonant circuit (ultrasonic transducer 215) is sensed by a high-bandwidth sensing and rectifying circuit at a high common-mode voltage (high-side of the bridge). The sensed current is converted to a voltage proportional to the rms current and supplied as a buffer voltage at the current sensing output pin 309 of the bridge IC 301. This voltage is supplied to the PMIC 300 for sampling and made available as a digital representation via I2C requests. Sensing the current flowing through the ultrasonic transducer 215 forms part of the resonant frequency tracking function. As described herein, the device's ability to enable this function within the bridge IC 301 provides significant technical advantages. 3. The DAC (not shown in Figure 1) integrated within the PMIC 300 allows the DC-DC boost converter voltage VBOOST to be programmed to be between 10V and 20V. 4. The microcontroller 303 enables the device 202's charger subsystem to manage the charging of the battery, which in this example is a single-cell battery. 5. A light-emitting diode (LED) driver module (not shown) is powered by the PMIC 300 to digitally drive and dim the LED 308 in either linear mode or gamma correction mode. 6. The microcontroller 303 can read pressure #1 and pressure #2 sensor values ​​from pressure sensors 307 and 308.

[0036] Referring here to Figure 2 of the attached drawings, the PMIC 300 in this example is an integrated chip or integrated circuit comprising an integrated subsystem and a plurality of pins that supply electrical inputs and outputs to the PMIC 300. References to integrated circuits or chips in this disclosure are interchangeable, and either term encompasses semiconductor devices, which may be made of silicon, for example.

[0037] The PMIC 300 includes an analog core 310 which comprises analog components including a reference block (BG) 311, an LDO 312, a current sensor 313, a temperature sensor 314, and an oscillator 315.

[0038] As will be described in more detail below, oscillator 315 is coupled to a delay-locked loop (DLL) that outputs pulse-width modulation (PWM) phases A and B. Oscillator 315 and the DLL generate a two-phase center-matched PWM output that drives the H-bridge in bridge IC 301.

[0039] The DLL comprises multiple end-to-end delay lines, the total delay of which is equal to the period of the main clock signal clk_m. In this example, the DLL is implemented in a digital processor subsystem, referred to herein as the digital core 316, of a PMIC 300 that receives a clock signal from oscillator 315 and a regulated power supply voltage from LDO 312. The DLL is implemented in the digital core 316 with a large number (e.g., millions) of end-to-end delay gates.

[0040] Implementing oscillators 315 and DLL within the same integrated circuit as the PMIC 300 to generate a two-phase center-matched PWM signal is unique because there are currently no signal generator components in the integrated circuit market that include this implementation.

[0041] As described herein, PWM is part of the functionality that allows the driver device 202 to accurately track the resonant frequency of the ultrasonic transducer 215 in order to maintain efficient transmission from electrical energy to kinetic energy in order to optimize mist generation. The same functionality allows for other examples with different resonant circuits by efficiently driving the resonant circuit at high power and high frequency.

[0042] In this example, the PMIC 300 includes a charger circuit 317 that controls the charging of the battery 250 using power from, for example, a USB power source. The charger circuit 317 is omitted in other examples that do not require a battery.

[0043] The PMIC 300 includes an integrated power switch VSYS that configures the PMIC 300 to supply power to the analog core 310 from the battery 250, or from an external power supply if the battery 250 is charged.

[0044] The PMIC 300 includes an embedded analog-to-digital converter (ADC) subsystem 318. Since there are no other integrated circuits on the integrated circuit market that feature an oscillator and ADC implemented as subblocks within the integrated circuit, implementing the ADC 318 together with the oscillator 315 within the same integrated circuit is unique in itself. In conventional devices, the ADC is typically supplied as a separate component from the oscillator, and the separate ADC and oscillator are mounted on the same PCB. The problem with this conventional configuration is that the two separate components, the ADC and oscillator, unnecessarily occupy space on the PCB. A further problem is that conventional ADCs and oscillators are usually connected to each other by a serial data communication bus, such as an I2C bus, which has a limited communication speed of only up to 400 kHz. In contrast to conventional devices, the PMIC 300 features an ADC 318 and an oscillator 315 integrated within the same integrated circuit, eliminating any delay in communication between the ADC 318 and the oscillator 315. This means that the ADC 318 and the oscillator 315 can communicate with each other at high speeds, such as the oscillator 315's speed (e.g., 3MHz to 5MHz).

[0045] In this example of the PMIC 300, the oscillator 315 operates at 5 MHz and generates a 5 MHz clock signal, SYS CLOCK. However, in other examples, the oscillator 315 generates a clock signal at much higher frequencies, up to 105 MHz. All integrated circuits described herein are configured to operate at the higher frequencies of the oscillator 315.

[0046] The ADC 318 has multiple feedback input terminals or analog inputs 319, each with multiple GPIO inputs (IF_GPIO1 to 3). At least one of the feedback input terminals or analog inputs 319 receives a feedback signal from the H-bridge circuit in the bridge IC 301, which indicates parameters of the operation of the H-bridge circuit or AC drive signal when the H-bridge circuit is driving a resonant circuit, such as an ultrasonic transducer 215, with the AC drive signal. As described below, the GPIO inputs are used to receive current-sensing signals from the bridge IC 301, which indicate the root-mean-square (rms) current reported by the bridge IC 301. In this example, one of the GPIO inputs is a feedback input terminal that receives a feedback signal from the H-bridge in the bridge IC 301.

[0047] The ADC subsystem 318 samples the analog signals received by the multiple ADC input terminals 319 at a sampling frequency proportional to the frequency of the main clock signal. The ADC subsystem 318 then uses the sampled analog signals to generate ADC digital signals.

[0048] In this example, the ADC 318 integrated into the PMIC 300 samples not only the RMS current flowing through the H-bridge 334 and ultrasonic transducer 215, but also the voltages available in the system (e.g., VBAT, VCHRG, VBOOST), the temperature of the PMIC 300, the temperature of the battery 250, and GPIO inputs (IF_GPIO 1-3) to allow for future expansion.

[0049] The digital core 316 receives the ADC-generated digital signal from the ADC subsystem, processes the ADC digital signal, and generates a driver control signal. The digital core 316 communicates the driver control signal to the PWM signal generator subsystem (DLL 332) to control the PWM signal generator subsystem.

[0050] Rectifier circuits available on the market today have very limited bandwidth (typically less than 1 MHz). Since the oscillator 315 of the PMIC 300 operates at up to 5 MHz or even up to 105 MHz, a high-bandwidth rectifier circuit is implemented within the PMIC 300. Sensing the RMS current in the H-bridge of the bridge IC 301, as described below, forms part of a feedback loop that enables the driver device 202 to drive the ultrasonic transducer 215 with high precision. The feedback loop is a game-changer in the industry for driving ultrasonic transducers, as it accommodates any process variations (variations in resonant frequency) in piezo transducer manufacturing and compensates for temperature effects of the resonant frequency. This is achieved in part by the realization of the present invention, which integrates the ADC 318, oscillator 315, and DLL within the same integrated circuit of the PMIC 300. This integration allows these subsystems to communicate with each other at high speed (e.g., at clock frequencies up to 5 MHz or 105 MHz). Reducing the latency between these subsystems is a game-changer in the ultrasonic industry, particularly in the field of mist generator devices.

[0051] The ADC 318 includes a battery voltage monitoring input VBAT and a charger input voltage monitoring input VCHG, as well as voltage monitoring inputs VMON and VRTH, and a temperature monitoring input TEMP.

[0052] The temperature monitoring input TEMP receives a temperature signal from a temperature sensor 314 embedded within the PMIC 300. This allows the PMIC 300 to accurately sense the actual temperature within the PMIC 300, and as a result, the PMIC 300 can detect any malfunctions within the PMIC 300, as well as malfunctions of other components on the printed circuit board that affect the temperature of the PMIC 300. The PMIC 300 can then control the bridge IC 301 to prevent excitation of the ultrasonic transducer 215 in the event of a malfunction, in order to maintain the safety of the resonant circuit device 201.

[0053] The additional temperature sensor input VRTH receives a temperature sensing signal from an external temperature sensor in the driver device 202, which monitors the battery temperature. The PMIC 300 can then react to reduce the risk of damage caused by excessively high battery temperatures by stopping the battery from charging in the event of a high battery temperature, or otherwise shutting down the driver device 202.

[0054] In this example, the PMIC 300 includes an LED driver 320 that receives a digital drive signal from the digital core 316 and supplies LED drive output signals to six LEDs 321-326, which are configured to be coupled to the output pins of the PMIC 300. Thus, the LED driver 320 can drive and dim the LEDs 321-326 on up to six independent channels.

[0055] The PMIC 300 includes a first digital-to-analog converter (DAC) 327 that converts the digital signals within the PMIC 300 into analog voltage control signals output from the PMIC 300 via the output pin VDAC0. The first DAC 327 converts the digital control signals generated by the digital core 316 into analog voltage control signals, which are output via the output pin VDAC0 and control voltage regulator circuits such as the boost converter 305. Thus, the voltage control signals control the voltage regulator circuits to generate a predetermined voltage for modulation by an H-bridge circuit in order to drive the resonant circuit (ultrasonic transducer 215) in response to a feedback signal indicating the operation of the resonant circuit (ultrasonic transducer 215).

[0056] In this example, the PMIC 300 includes a second DAC 328 that converts the digital signals within the PMIC 300 into analog signals output from the PMIC 300 via a second analog output pin VDAC1.

[0057] Embedding DAC 327 or DAC 327,328 on the same microchip as other subsystems of PMIC 300 allows DAC 327,328 to communicate with the digital core 316 and other components within PMIC 300 at high speed with no or minimal communication delay. DAC 327,328 provides analog outputs to control external feedback loops. For example, the first DAC 327 supplies the control signal VCTL to the boost converter 305 to control its operation. In other examples, DAC 327,328 are configured to supply drive signals to a DC-DC buck converter instead of, or in addition to, the boost converter 305. Integrating two independent DAC channels into the PMIC 300 allows the PMIC 300 to manipulate the feedback loop of any regulator used in the driver device 202, enabling the driver device 202 to adjust the ultrasonic processing power of the ultrasonic transducer 215 or to set analog thresholds for the absolute maximum current and temperature settings of the ultrasonic transducer 215.

[0058] The PMIC 300 features a serial communication interface, which in this example is an I2C interface that incorporates an external I2C address configured via a pin.

[0059] The PMIC 300 also features various functional blocks, including a Digital Machine Module (FSM) for implementing the functionality of the microchip. These blocks are described in more detail below.

[0060] Referring here to Figure 3 of the attached drawings, the pulse-width modulation (PWM) signal generator subsystem 329 is embedded within the PMIC 300. The PWM generator system 329 comprises an oscillator 315, a frequency divider 330, a multiplexer 331, and a delay-locked loop (DLL) 332. As described below, the PWM generator system 329 is a two-phase center-matched PWM generator.

[0061] The frequency divider 330, the multiplexer 331, and the DLL 332 are implemented in the digital logic components (e.g., transistors, logic gates, etc.) within the digital core 316.

[0062] In the examples of this disclosure, the frequency ranges covered by the oscillator 315 and the PWM generator system 329, respectively, are 50 kHz to 5 MHz or up to 105 MHz. The frequency accuracy of the PWM generator system 329 is ±1%, and the temperature spread is ±1%. There are no ICs on the current IC market that have an embedded oscillator and a two-phase center-matched PWM generator capable of providing a frequency range from 50 kHz to 5 MHz or 105 MHz.

[0063] Oscillator 315 generates a main clock signal (clk_m) having a frequency from 50kHz to 5MHz or 105MHz. The main clock clk_m is input to a frequency divider 330, which divides the frequency of the main clock clk_m by one or more predetermined divisors. In this example, the frequency divider 330 divides the frequency of the main clock clk_m by 2, 4, 8, and 16, and supplies the divided frequency clocks as an output to a multiplexer 331. The multiplexer 331 multiplexes the divided frequency clocks and supplies the divided frequency outputs to a DLL 332. This signal passed to the DLL 332 is a frequency reference signal that controls the DLL 332 to output a signal at the desired frequency. In other examples, the frequency divider 330 and multiplexer 331 are omitted.

[0064] Oscillator 315 also generates two phases, a first phase clock signal Phase 1 and a second phase clock signal Phase 2. The phases of the first phase clock signal and the second phase clock signal are center-matched. As shown in Figure 4, The first phase clock signal, Phase1, is high for a variable time of the positive half-period of clk_m and low for the negative half-period of clk_m. The second phase clock signal, phase 2, is high for a variable time of the negative half-period of clk_m and low for the positive half-period of clk_m.

[0065] Next, Phase 1 and Phase 2 are sent to DLL 332, which uses the first phase clock signal Phase 1 and the second phase clock signal Phase 2 to generate a double-frequency clock signal. The double-frequency clock signal is twice the frequency of the main clock signal clk_m. In this example, an "OR" gate in DLL 332 generates a double-frequency clock signal using the first phase clock signal Phase 1 and the second phase clock signal Phase 2. This double-frequency clock, or the divided frequency coming from the frequency divider 330, is selected based on the chosen target frequency and then used as the reference for DLL 332.

[0066] In DLL 332, the signal hereafter referred to as "clock" represents the doubled main clock clk_m, and the signal hereafter referred to as "clock_del" is a duplicate of the clock delayed by one period of frequency. Both clock and clock_del pass through the phase frequency detector. Then, node Vc is charged or discharged by the charge pump based on the phase error polarity. The control voltage is supplied directly to control the delay of all single delay units within DLL 332 until the total delay of DLL 332 is exactly one period.

[0067] The DLL 332 controls the rising edges of the first phase clock signal Phase 1 and the second phase clock signal Phase 2 to synchronize with the rising edges of the double-frequency clock signal. The DLL 332 adjusts the frequency and duty cycle of the first phase clock signal Phase 1 and the second phase clock signal Phase 2 in response to their respective frequency reference and duty cycle control signals to generate the first phase output signal PHASE A and the second phase output signal PHASE B, which drive the H-bridge or inverter to generate the AC drive signal for driving the ultrasonic transducer.

[0068] The PMIC 300 includes a first phase output signal terminal PHASE_A that outputs a first phase output signal PHASE A to the H-bridge circuit, and a second phase output signal terminal PHASE_B that outputs a second phase output signal PHASE B to the H-bridge circuit.

[0069] In this example, DLL 332 adjusts the duty cycles of the first phase clock signal Phase1 and the second phase clock signal Phase2 in response to the duty cycle control signal by changing the delay of each delay line within DLL 332 in response to the duty cycle control signal.

[0070] The clock is used at twice its frequency to ensure better accuracy. As shown in Figure 5, if the frequency of the main clock clk_m is used for illustrative purposes (not used in the examples of this disclosure), PHASE A is synchronized with the rising edge R of the clock, and PHASE B is synchronized with the falling edge F of the clock. Since the delay line of DLL 332 controls the rising edge R, for the falling edge F, the PWM generator system 329 must rely on the perfect alignment of the delay unit of DLL 332, which may be imperfect. However, to eliminate this error, the PWM generator system 329 uses a double-frequency clock such that both PHASE A and PHASE B are synchronized with the rising edge R of the double-frequency clock.

[0071] To execute duty cycles from 20% to 50% with a step size of 2%, the delay line of DLL 332 has 25 delay units, with the output of each delay unit representing the nth phase. Finally, the phase of the output of the last delay unit corresponds to the input clock. Assuming all delays are approximately the same, a particular duty cycle can be obtained using the output of a particular delay unit with simple logic in the digital core 316.

[0072] Since DLL 332 can lock for two or more delay periods instead of just one, potentially putting DLL 332 into a non-converging zone, handling the startup of DLL 332 is crucial. To circumvent this problem, a startup circuit is implemented within the PWM generator system 329 that allows DLL 332 to start from known deterministic conditions. The startup circuit further enables DLL 332 to start with minimal delay.

[0073] In the example of this disclosure, the frequency range covered by the PWM generator system 329 is extended so that the delay unit in the DLL 332 can provide delays from 4 ns (for an oscillator frequency of 5 MHz) to 400 ns (for an oscillator frequency of 50 kHz). To accommodate these different delays, a capacitor Cb is included in the PWM generator system 329, and the capacitor value is selected to provide the required delay.

[0074] PHASE A and PHASE B are output from DLL 332 and passed to bridge IC 301 via digital I / O, so that PHASE A and PHASE B can be used to control the operation of bridge IC 301.

[0075] Next, the battery charging function of the driver device 202 will be described in more detail. The battery charging subsystem includes a charger circuit 317 embedded in the PMIC 300 and controlled by a digital charge controller hosted in the PMIC 300. The charger circuit 317 is controlled by a microcontroller 303 via a communication bus 302. The battery charging subsystem can charge a single-cell lithium polymer (LiPo) or lithium-ion (Li-ion) battery.

[0076] In this example, the battery charging subsystem can charge one or more batteries from a 5V power supply (e.g., a USB power supply) with a maximum charging current of 1A. To adapt the battery charging parameters, one or more of the following parameters can be programmed via the communication bus 302 (I2C interface). The charging voltage can be set in 100mV increments between 3.9V and 4.3V. The charging current can be set in 50mA increments between 150mA and 1000mA. • The pre-charge current is 1 / 10 of the charging current. • Pre-charge and fast-charge timeouts can be set to 20 minutes and 340 minutes respectively, between 5 minutes and 85 minutes. • Optionally, an external negative temperature coefficient (NTC) thermistor can be used to monitor the battery temperature.

[0077] In some examples, the battery charging subsystem reports one or more of the following events by generating an interrupt in the host microcontroller 303: • Battery detected • The battery is charging. • The battery is fully charged. • Battery is not present • Charging timeout reached • The charging supply is below the insufficient voltage limit.

[0078] The main advantage of having the charger circuit 317 embedded in the PMIC 300 is that all enumerated programming options and event indicators are implemented within the PMIC 300, ensuring the safe operation of the battery charging subsystem. Furthermore, significant savings in manufacturing costs and PCB space can be achieved compared to conventional resonant circuit devices such as mist inhaler devices, which have separate components of the charging system mounted separately on the PCB. The charger circuit 317 also allows for highly versatile settings of charging current and voltage, different fault timeouts, and numerous event flags for detailed state analysis.

[0079] Next, the analog-to-digital converter (ADC) 318 will be described in more detail. The inventors had to overcome significant technical challenges in integrating the ADC 318 within the PMIC 300 with the high-speed oscillator 315. Furthermore, integrating the ADC 318 within the PMIC 300 goes against conventional methods in the art, which rely on using one of the many discrete ADC devices available on the IC market.

[0080] In this example, the ADC 318 samples at least one parameter within the ultrasonic transducer driver chip (PMIC 300) at a sampling rate equal to the frequency of the main clock signal clk_m. In this example, the ADC 318 is a 10-bit analog-to-digital converter that can unload digital sampling from the microprocessor 303 to conserve resources on the microprocessor 303. Integrating the ADC 318 within the PMIC 300 also avoids the need to use an I2C bus, which would otherwise slow down the ADC's sampling capability (conventional devices typically rely on an I2C bus to communicate data between a dedicated discrete ADC and a microcontroller at a limited clock speed of typically up to 400 kHz).

[0081] In the example of this disclosure, one or more of the following parameters may be sequentially sampled by the ADC 318. i. An RMS current signal received by the ultrasonic transducer driver chip (PMIC 300) from an external inverter circuit driving the ultrasonic transducer. In this example, this parameter is the root mean square (rms) current reported by the bridge IC 301. Sensing the RMS current is important for implementing the feedback loop used to drive the ultrasonic transducer 215. Since the ADC 318 does not rely on this information transmitted via the I2C bus, the ADC 318 can sense the RMS current directly from the bridge IC 301 via a signal with minimal or no delay. This provides significant speed and accuracy benefits compared to conventional devices constrained by the relatively low speed of the I2C bus. ii. The voltage of the battery connected to the PMIC 300. iii. Voltage of the charger connected to the PMIC 300. iv. Temperature signals, such as a temperature signal indicating the PMIC 300 chip temperature. As mentioned above, this temperature can be measured very accurately because the temperature sensor 314 is embedded in the same IC as the oscillator 315. For example, when the temperature of the PMIC 300 rises, the current, frequency, and PWM are adjusted by the PMIC 300 to control the transducer oscillation, and the transducer oscillation controls the temperature. v. Two external pins. vi. External NTC temperature sensor for monitoring battery pack temperature.

[0082] In some examples, the ADC 318 sequentially samples one or more of the aforementioned sources, for example, in a round-robin manner. The ADC 318 samples the sources at a high speed, such as the speed of the oscillator 315, which may be up to 5 MHz or up to 105 MHz.

[0083] In some examples, device 202 is configured so that the device user or manufacturer can specify how many samples should be taken from each source for averaging. For example, the user can configure the system to take 512 samples from the RMS current input, 64 samples from the battery voltage, 64 samples from the charger input voltage, 32 samples from the external pins, and 8 samples from the NTC pins. Furthermore, the user can also specify whether one of the above sources should be skipped.

[0084] In some examples, for each source, the user can specify two digital thresholds that divide the entire range into multiple zones, such as three zones. The user can then configure the system to release an interrupt when the sampled value changes zones, for example, from zone 2 to zone 3.

[0085] Conventional ICs available on the market today cannot perform the above-mentioned features of the PMIC 300. Such flexibility and granular sampling are crucial when driving resonant circuits or components, such as ultrasonic transducers.

[0086] In this example, the PMIC 300 features 8-bit general-purpose digital input / output ports (GPIO). Each port can be configured as a digital input and a digital output. Some of the ports have analog input capabilities, as shown in the table in Figure 6.

[0087] The GPIO7-GPIO5 ports of the PMIC 300 can be used to set the addresses of devices on the I2C communication bus 302. Eight identical devices can then be used on the same I2C bus. This is a unique feature in the IC industry, as it allows eight identical devices to be used on the same I2C bus without conflicting addresses. This is implemented by each device reading the state of GPIO7-GPIO5 during the first 100μs after the PMIC 300 is powered on and storing that portion of the address internally in the PMIC 300. After the PMIC 300 is powered on, the GPIOs can be used for any other purpose.

[0088] As described above, the PMIC 300 includes a 6-channel LED driver 320. In this example, the LED driver 320 features a 5V-tolerant N-channel metal-oxide-semiconductor (NMOS) current source. The LED driver 320 is configured to set the LED current to four discrete levels: 5mA, 10mA, 15mA, and 20mA. The LED driver 320 is configured to dim each LED channel with a 12-bit PWM signal, with or without gamma correction. The LED driver 320 is configured to vary the PWM frequency from 300Hz to 1.5kHz. This feature is unique in the field of resonant circuit devices, such as ultrasonic mist inhaler devices, because the functionality is embedded as a subsystem of the PMIC 300.

[0089] In this example, the PMIC 300 includes two independent 6-bit digital-to-analog converters (DACs) 327 and 328, which are integrated into the PMIC 300. The purpose of DACs 327 and 328 is to output analog voltages to manipulate the feedback path of an external regulator (e.g., DC-DC boost converter 305, buck converter, or LDO). Furthermore, in some examples, DACs 327 and 328 may also be used to dynamically adjust the overcurrent shutdown level of the bridge IC 301, as described below.

[0090] The output voltage of each DAC 327, 328 is programmable between 0V and 1.5V, or between 0V and V_battery(Vbat). In this example, the DAC output voltage is controlled via I2C commands. Having two DACs integrated into the PMIC 300 is unique and enables dynamic monitoring and control of current. If either DAC 327 or 328 were an external chip, the speed would be subject to the same speed limitations as those imposed by the I2C protocol. The active power monitoring configuration of device 202 operates with optimal efficiency when all these embedded features are within the PMIC. If they are external components, the active power monitoring configuration is inefficient overall.

[0091] Referring here to Figure 7 of the attached drawings, the bridge IC 301 is a microchip with an embedded power switching circuit 333. In this example, the power switching circuit 333 is an H-bridge 334, shown in Figure 8 and described in detail below. However, it should be understood that in other examples, the bridge IC 301 may incorporate an alternative power switching circuit for the H-bridge 334, provided that the power switching circuit performs an equivalent function of generating an AC drive signal for driving the ultrasonic transducer 215.

[0092] The bridge IC 301 includes a first phase terminal PHASE A that receives a first phase output signal PHASE A from the PWM signal generator subsystem of the PMIC 300. The bridge IC 301 also includes a second phase terminal PHASE B that receives a second phase output signal PHASE B from the PWM signal generator subsystem of the PMIC 300.

[0093] The bridge IC 301 includes a current sensing circuit 335 that directly senses the current in the H-bridge 334 and supplies an RMS current output signal via the RMS_CURR pin of the bridge IC 301. The current sensing circuit 335 is configured for overcurrent monitoring and detects when the current flowing through the H-bridge 334 exceeds a predetermined threshold. Integrating the power switching circuit 333, which includes the H-bridge 334, and the current sensing circuit 335, all within the same embedded circuit of the bridge IC 301 is a unique combination in the IC market. Currently, other integrated circuits in the IC market do not have an H-bridge with an embedded circuit for sensing the RMS current flowing through the H-bridge.

[0094] The bridge IC 301 includes a temperature sensor 336 that includes over-temperature monitoring. The temperature sensor 336 is configured to shut down the bridge IC 336 or disable at least a portion of the bridge IC 301 if it detects that the bridge IC 301 is operating at a temperature above a predetermined threshold. Thus, the temperature sensor 336 provides an integrated safety feature that prevents damage to the bridge IC 301 or other components in the driver device 202 if the bridge IC 301 operates at an excessively high temperature.

[0095] The bridge IC 301 includes a digital state machine 337 integrally connected to the power switching circuit 333. The digital state machine 337 receives PHASE A and PHASE B signals from the PMIC 300 and an ENABLE signal from, for example, the microcontroller 303. The digital state machine 337 generates timing signals based on the first phase output signal PHASE A and the second phase output signal PHASE B.

[0096] The digital state machine 337 outputs timing signals corresponding to the A-phase signal and B-phase signal, as well as the BRIDGE PR signal and BRIDGE EN signal, to the power switching circuit 333 in order to control the power switching circuit 333. Therefore, the digital state machine 337 outputs timing signals to switches T1 to T4 of the H-bridge circuit 334, controlling switches T1 to T4 to sequentially turn them on and off so that the H-bridge circuit outputs AC drive signals to drive resonant circuits such as the ultrasonic transducer 215.

[0097] As will be explained in more detail below, the switching sequence includes a free-floating period in which the first switch T1 and the second switch T1 are turned off and the third switch T3 and the fourth switch T4 are turned on in order to dissipate the energy accumulated by the resonant circuit (ultrasonic transducer 215).

[0098] The bridge IC 301 includes a test controller 338 that allows the bridge IC 301 to be tested to determine whether the embedded components within the bridge IC 301 are functioning correctly. The test controller 338 is coupled to the TEST_DATA pin, the TEST_CLK pin, and the TEST_LOAD pin, so that the bridge IC 301 can be connected to an external control device that sends data to and sends data out of the bridge IC 301 to test the operation of the bridge IC 301. The bridge IC 301 also includes a TEST BUS that allows the digital communication bus within the bridge IC 301 to be tested via the TST_PAD pin.

[0099] The bridge IC 301 includes a power-on reset circuit (POR) 339 that controls the startup operation of the bridge IC 301. The POR 339 ensures that the bridge IC 301 starts up properly only when the supply voltage is within a predetermined range. If the supply voltage is outside the predetermined range, for example, if the supply voltage is too high, the POR 339 delays the startup of the bridge IC 301 until the supply voltage is within the predetermined range.

[0100] The bridge IC 301 includes a reference block (BG) 340 that provides a precise reference voltage for use by other subsystems of the bridge IC 301.

[0101] The bridge IC 301 includes a current reference 341 that supplies precise current to other subsystems within the bridge IC 301, such as the power switching circuit 333 and / or the current sensor 335.

[0102] The temperature sensor 336 continuously monitors the silicon temperature of the bridge IC 301. If the temperature exceeds a predetermined temperature threshold, the power switching circuit 333 is automatically switched off. Furthermore, it can report the overtemperature to an external host to notify the external host that an overtemperature event has occurred.

[0103] In this example, the digital state machine (FSM) 337 generates timing signals for the power switching circuit 333, which are timing signals for controlling the H-bridge 334.

[0104] The bridge IC 301 includes comparators 342 and 343 that compare signals from various subsystems of the bridge IC 301 with voltage and current references 340 and 341 and supply reference output signals via the pins of the bridge IC 301.

[0105] Referring again to Figure 8 of the attached drawings, the H-bridge 334 in this example has four switches in the form of NMOS field-effect transistor (FET) switches on both sides of the H-bridge 334. The H-bridge 334 has four switches or transistors T1-T4 connected in an H-bridge configuration, and each transistor T1-T4 is driven by its respective logic inputs A-D. Transistors T1-T4 are configured to be driven by a bootstrap voltage generated internally by two external capacitors Cb connected as shown in Figure 8.

[0106] The H-bridge 334 has various power inputs and outputs connected to each pin of the bridge IC 301. The H-bridge 334 receives a programmable voltage VBOOST output from the boost converter 305 via a first power supply terminal labeled VBOOST in Figure 8. The H-bridge 334 has a second power supply terminal labeled VSS_P in Figure 8.

[0107] The H-bridge 334 has outputs OUTP and OUTN, which are configured to be connected to the respective terminals of the ultrasonic transducer 215 so that the AC drive signals output from the H-bridge 334 can drive the ultrasonic transducer 215.

[0108] The switching of the four switches or transistors T1-T4 is controlled by switching signals from the digital state machine 337 via logic inputs A-D. Figure 8 shows the four transistors T1-T4, but it should be understood that in other examples, the H-bridge 334 incorporates more transistors or other switching components to implement the functions of an H-bridge.

[0109] In this example, the H-bridge 334 operates with switching power of 22W to 50W to supply an AC drive signal with sufficient power to optimally drive the ultrasonic transducer 215 at or near its resonant frequency. The voltage switched by the H-bridge 334 in this example is ±15V. In other examples, the voltage is ±20V.

[0110] In this example, the H-bridge 334 switches at frequencies of 3 MHz to 5 MHz or up to 105 MHz. This is a high switching speed compared to conventional integrated circuit H-bridges available on the IC market. For example, conventional integrated circuit H-bridges available on the IC market today are configured to operate at a maximum frequency of only 2 MHz. Apart from the bridge IC 301 described herein, conventional integrated circuit H-bridges available on the IC market cannot operate at frequencies up to 5 MHz, let alone 105 MHz, with power supplies of 22 V to 50 V.

[0111] Referring here to Figure 9 of the attached drawings, the current sensor 335 comprises positive and negative current-sensing resistors RshuntP and RshuntN connected in series with the respective high-side and low-side of the H-bridge 334, as shown in Figure 8. The current-sensing resistors RshuntP and RshuntN are low-value resistors, which in this example are 0.1Ω. The current sensor 335 comprises a first voltage sensor in the form of a first operational amplifier 344 that measures the voltage drop across the first current-sensing resistor RshuntP, and a second voltage sensor in the form of a second operational amplifier 345 that measures the voltage drop across the second current-sensing resistor RshuntN. In this example, the gain of each operational amplifier 344 and 345 is 2V / V. The output of each operational amplifier 344 and 345 is 1mA / V in this example. The current sensor 335 comprises a pull-down resistor Rcs, which in this example is 2kΩ. The outputs of operational amplifiers 344 and 345 pass through a low-pass filter 346 to remove transients in the signal CSout, and then produce an output CSout. The output Vout of the low-pass filter 346 is the output signal of the current sensor 335.

[0112] Therefore, the current sensor 335 measures the AC current flowing through the H-bridge 334 and the ultrasonic transducer 215, respectively. The current sensor 335 converts the AC current into an equivalent RMS output voltage (Vout) relative to ground. The current sensor 335 has high bandwidth capability because the H-bridge 334 can operate at frequencies up to 5 MHz, or up to 105 MHz in some examples. The output Vout of the current sensor 335 reports a positive voltage equal to the measured AC RMS current flowing through the ultrasonic transducer 215. In this example, the output voltage Vout of the current sensor 335 is fed back to the control circuit in the bridge IC 301, allowing the bridge IC 301 to shut down the H-bridge 334 if the current flowing through the H-bridge 334 and therefore through the transducer 215 exceeds a predetermined threshold. In addition, overcurrent threshold events are reported to the first comparator 342 within the bridge IC 301 so that the bridge IC 301 can report overcurrent events via the OVC_TRIGG pin of the bridge IC 301.

[0113] Next, referring to Figure 10 in the attached drawings, the control of the H-bridge 334 will be explained, also referring to the equivalent piezo model of the ultrasonic transducer 215.

[0114] As shown by V_out in Figure 10, the switching sequence of transistors T1-T4 via inputs A-D to generate a positive voltage across the outputs OUTP and OUTN of the H-bridge 334 (note the direction of the arrows) is as follows: 1. Positive output voltage applied to ultrasonic transducer 215: A-ON, B-OFF, C-OFF, D-ON. 2. Transition from positive output voltage to 0: A-OFF, B-OFF, C-OFF, D-ON. During this transition, if there is a switching error or delay in A, C is first switched off to minimize or avoid power loss by minimizing or avoiding the current flowing through A and C. 3.0 Output Voltage: A-OFF, B-OFF, C-ON, D-ON. During this 0 output voltage phase, the OUTP and OUTN terminals of the H-bridge 334 are grounded by the C and D switches, which remain ON. This dissipates the energy stored by the capacitor in the equivalent circuit of the ultrasonic transducer and minimizes voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer. 4.0 transition to negative output voltage: A-OFF, B-OFF, C-ON, D-OFF. 5. Negative output voltage applied to ultrasonic transducer 215: A-OFF, B-ON, C-ON, D-OFF.

[0115] At high frequencies up to 5 MHz or 105 MHz, the duration of each part of the switching sequence is very short, on the order of nanoseconds or picoseconds. For example, at a switching frequency of 6 MHz, each part of the switching sequence occurs in approximately 80 ns.

[0116] A graph showing the output voltages OUTP and OUTN of the H-bridge 334 due to the switching sequence described above is shown in Figure 11 of the attached drawings. The 0 output voltage portion of the switching sequence is included to correspond to the energy stored by the ultrasonic transducer 215 (for example, the energy stored by the capacitor in the equivalent circuit of the ultrasonic transducer). As described above, this minimizes voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer, and therefore minimizes unnecessary power dissipation and heating in the ultrasonic transducer.

[0117] Minimizing or eliminating voltage overshoot also reduces the risk of damage to transistors within the bridge IC 301 by preventing them from receiving voltages exceeding their rated voltages. Furthermore, minimizing or eliminating voltage overshoot allows the bridge IC 301 to accurately drive the ultrasonic transducer in a manner that minimizes disruption to the current-sensing feedback loop described herein. As a result, the bridge IC 301 can drive the ultrasonic transducer at high power levels of 22W to 50W or 70W at high frequencies up to 5MHz or 105MHz.

[0118] The bridge IC 301 in this example is configured to be controlled by the PMIC 300 to operate in two different modes, referred to herein as forced mode and natural frequency mode. These two operating modes are novel to existing bridge ICs. In particular, natural frequency mode is a major innovation that provides substantial benefits in accuracy and efficiency for driving ultrasonic transducers compared to conventional devices.

[0119] Forced Frequency Mode (FFM) In forced frequency mode, the H-bridge 334 is controlled by the sequence described above, but at a user-selectable frequency. As a result, the H-bridge transistors T1-T4 are forcibly controlled regardless of the natural resonant frequency of the ultrasonic transducer 215, switching the output voltage across the ultrasonic transducer 215. Thus, forced frequency mode allows the H-bridge 334 to drive the ultrasonic transducer 215, which has a resonant frequency f1, at a different frequency f2.

[0120] Driving an ultrasonic transducer at a frequency different from its resonant frequency may be appropriate to adapt its operation to different applications. For example, it may be appropriate to drive an ultrasonic transducer at a frequency slightly outside its resonant frequency (for mechanical reasons to prevent mechanical damage to the transducer). Alternatively, it may be appropriate to drive an ultrasonic transducer at a lower frequency, but ultrasonic transducers have different natural resonant frequencies due to their size.

[0121] The driver device 202 controls the bridge IC 301 to drive the ultrasonic transducer 215 in forced frequency mode, in response to the configuration of the driver device 202 for a particular application or for a particular ultrasonic transducer. For example, the driver device 202 may be configured to operate in forced frequency mode when the resonant circuit device 201 is used in a particular application, such as generating a mist from a liquid of a certain viscosity containing a drug for delivery to a user.

[0122] Natural frequency mode (NFM) The following natural frequency operating modes represent a significant development and offer advantages in improved accuracy and efficiency compared to conventional ultrasonic drivers available on the IC market today.

[0123] The natural frequency operating mode follows the same switching sequence as described above, but the timing of the 0 output portion of the sequence is adjusted to minimize or avoid problems that may arise due to current spikes in forced frequency mode operation. These current spikes occur when the voltage across the ultrasonic transducer 215 is switched to its opposite voltage polarity. An ultrasonic transducer containing a piezoelectric crystal has an electrical equivalent circuit that incorporates a parallel-connected capacitor (see, for example, the piezoelectric model in Figure 10). When the voltage across the ultrasonic transducer is hard-switched from a positive voltage to a negative voltage, a large current may flow as the energy stored in the capacitor dissipates due to the high dV / dt.

[0124] The natural frequency mode avoids hard switching the voltage across the ultrasonic transducer 215 from a positive voltage to a negative voltage (and vice versa). Instead, before applying a reverse voltage, the ultrasonic transducer 215 (piezocrystal) is left free-floating with a 0 voltage applied across its terminals for a free-floating period. The PMIC 300 sets the drive frequency of the bridge IC 301 so that the bridge 334 sets the free-floating period, and the current flow in the ultrasonic transducer 215 (due to the energy stored in the piezocrystal) reverses the voltage across the terminals of the ultrasonic transducer 215 during the free-floating period.

[0125] As a result, when the H-bridge 334 applies a negative voltage to the terminals of the ultrasonic transducer 215, the ultrasonic transducer 215 (capacitor in the equivalent circuit) is already reverse-charged and does not have a high dV / dt, so no current spike occurs.

[0126] However, it should be understood that when the ultrasonic transducer 215 is first activated, it takes time for the charge within the ultrasonic transducer 215 (piezocrystal) to accumulate. Therefore, the ideal situation in which the energy within the ultrasonic transducer 215 reverses the voltage during the free-floating period only occurs after the oscillation within the ultrasonic transducer 215 has accumulated charge. To address this, when the bridge IC 301 first activates the ultrasonic transducer 215, the PMIC 300 controls the power delivered to the ultrasonic transducer 215 through the H-bridge 334 to a first value, which is a low value (e.g., 5V). Then, the PMIC 300 controls the power delivered to the ultrasonic transducer 215 through the H-bridge 334 to accumulate the energy stored within the ultrasonic transducer 215, increasing it to a second value (e.g., 15V) that is higher than the first value over a period of time. Current spikes still occur during this ramp of oscillation until the current within the ultrasonic transducer 215 has fully developed. However, by using a low first voltage during startup, these current spikes are kept low enough to minimize their impact on the operation of the ultrasonic transducer 215.

[0127] To implement the natural frequency mode, the driver device 202 precisely controls the frequency of the oscillator 315 and the duty cycle (ratio of on-time to free-floating time) of the AC drive signal output from the H-bridge 334. In this example, the driver device 202 runs three control loops to adjust the oscillator frequency and duty cycle so that voltage inversion at the terminals of the ultrasonic transducer 215 is as accurate as possible and current spikes are minimized or avoided as much as possible. Precise control of the oscillator and duty cycle using control loops represents a significant advance in the field of IC ultrasonic drivers.

[0128] During the natural frequency operation mode, the current sensor 335 senses the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free-floating period. When the current sensor 335 senses that the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free-floating period is 0, the digital state machine 337 adjusts the timing signal to switch either the first switch T1 or the second switch T2 to the ON position.

[0129] Figure 12 of the attached drawing shows the oscillator voltage waveform 347 (V(osc)), the switching waveform 348 resulting from the on and off of the left high switch T1 of the H bridge 334, and the switching waveform 349 resulting from the on and off of the right high switch T2 of the H bridge 334. During the intervening free-floating period 350, both high switches T1 and T2 of the H bridge 334 are turned off (free-floating phase). The duration of the free-floating period 350 is controlled by the magnitude of the free-floating control voltage 351 (Vphioff).

[0130] Figure 13 of the attached drawings shows the voltage waveform 352 at the first terminal of the ultrasonic transducer 215 (the voltage waveform is inverted at the second terminal of the ultrasonic transducer 215) and the piezoelectric current 353 flowing through the ultrasonic transducer 215. The piezoelectric current 353 represents a (nearly) ideal sinusoidal waveform (which is never possible with forced frequency modes or any bridge on the IC market).

[0131] Before the sine wave of the piezoelectric current 353 reaches zero, the left-side high switch T1 of the H-bridge 334 is turned off (where switch T1 is turned off when the piezoelectric current 353 is approximately 6A). The remaining piezoelectric current 353 flowing through the ultrasonic transducer 215 (the capacitor of the piezoelectric equivalent circuit), due to the energy stored in the ultrasonic transducer 215, is the cause of the voltage reversal during the free-floating period 350. The piezoelectric current 353 decays to zero during the free-floating period 350 and then decays into the negative current flow domain. The terminal voltage in the ultrasonic transducer 215 drops to less than 2V from the supply voltage (19V in this case), and this decline stops when the piezoelectric current 353 reaches zero. This is the perfect time to turn on the low-side switch T3 of the H-bridge 334 to minimize or avoid current spikes.

[0132] Compared to the forced frequency modes described above, natural frequency modes have at least three advantages. 1. Current spikes associated with hard switching of package capacitors are significantly reduced or completely avoided. 2. Power loss due to hard switching is almost completely eliminated. 3. The frequency is tuned by a control loop and kept close to the resonance of the piezoelectric crystal (i.e., the natural resonant frequency of the piezoelectric crystal).

[0133] In the case of frequency adjustment via a control loop (advantage 3 above), the PMIC 300 starts by controlling the bridge IC 301 to drive the ultrasonic transducer 215 at a frequency above the resonance of the piezoelectric crystal. The PMIC 300 then controls the bridge IC 301 so that the frequency of the AC drive signal is attenuated / reduced during startup. As soon as the frequency approaches the resonance frequency of the piezoelectric crystal, the piezoelectric current rapidly generates / increases. When the piezoelectric current becomes high enough to cause the desired voltage inversion, the frequency attenuation / reduction is stopped by the PMIC 300. The control loop of the PMIC 300 then takes over the adjustment of the frequency and duty cycle of the AC drive signal.

[0134] In forced frequency mode, the power delivered to the ultrasonic transducer 215 is controlled through the duty cycle and / or frequency shift, and / or by varying the supply voltage. However, in this example, in natural frequency mode, the power delivered to the ultrasonic transducer 215 is controlled solely by the supply voltage.

[0135] In this example, during the driver device's setup phase, the bridge IC 301 is configured to measure the time length it takes for the current flowing through the ultrasonic transducer 215 (resonant circuit) to drop to zero when the first switch T1 and the second switch T2 are turned off and the third switch T3 and the fourth switch T4 are turned on. The bridge IC 301 then sets the free-floating period to be equal to the measured time length.

[0136] Referring here to Figure 14 of the attached drawings, the PMIC 300 and bridge IC 301 in this example are designed to work together as a companion chipset. The PMIC 300 and bridge IC 301 are electrically connected to each other in order to communicate with one another. In this example, there is an interconnection between the PMIC 300 and bridge IC 301 that enables the following two categories of communication: 1. Control signals 2. Feedback signal

[0137] The connection between the PHASE_A and PHASE_B pins of the PMIC 300 and the bridge IC 301 carries the PWM modulation control signal that drives the H-bridge 334. The connection between the EN_BR pin of the PMIC 300 and the bridge IC 301 carries the EN_BR control signal that triggers the start of the H-bridge 334. The timing between the PHASE_A, PHASE_B, and EN_BR control signals is critical and is handled by the digital bridge control of the PMIC 300.

[0138] The connections between the CS, OC, and OT pins of the PMIC 300 and the bridge IC 301 carry the CS (current sensing), OC (overcurrent), and OT (overtemperature) feedback signals back from the bridge IC 301 to the PMIC 300. Most notably, the CS (current sensing) feedback signal contains a voltage equal to the rms current flowing through the ultrasonic transducer 215, as measured by the current sensor 335 of the bridge IC 301.

[0139] The OC (overcurrent) and OT (overtemperature) feedback signals are digital signals indicating that either an overcurrent or overvoltage event has been detected by the bridge IC 301. In this example, the overcurrent and overtemperature thresholds are set by external resistors. Alternatively, the thresholds can also be set dynamically in response to a signal passed from one of the two DAC channels VDAC0, VDAC1 from the PMIC 300 to the OC_REF pin of the bridge IC 301.

[0140] In this example, the design of the PMIC 300 and bridge IC 301 allows the pins of these two integrated circuits to be directly connected to each other (e.g., via copper tracks on the PCB), thereby minimizing or eliminating delay in signal communication between the PMIC 300 and bridge IC 301. This offers a significant speed advantage over conventional bridges in the IC market, which are typically signal-controlled via digital communication buses. For example, a standard I2C bus is clocked at only 400 kHz, which is too slow to communicate sampled data at higher clock speeds of up to 5 MHz in the examples of this disclosure.

[0141] While examples of the disclosure have been described above with respect to microchip hardware, it should be understood that other examples of the disclosure include methods for operating each microchip component and subsystem to perform the functions described herein. For example, a method for operating the PMIC 300 and bridge IC 301 in either forced frequency mode or natural frequency mode.

[0142] Referring here to Figure 15 of the attached drawings, the optional OTP IC 242 comprises a power-on reset circuit (POR) 354, a bandgap reference (BG) 355, a capless low-dropout regulator (LDO) 356, a communication (e.g., I2C) interface 357, a one-time programmable memory bank (electronic fuse) 358, an oscillator 359, and a general-purpose input / output interface 360. The OTP IC 242 also comprises a digital core 361 including a cryptographic authentication device. In this example, the cryptographic authentication device uses an elliptic curve digital signature algorithm (ECDSA) within the OTP IC 242 to encrypt / decrypt data stored within the OTP IC, as well as data transmitted to and from the OTP IC 242.

[0143] The POR 354 ensures that the OTP IC 242 starts up properly only when the supply voltage is within a specified range. If the supply voltage is outside the specified range, the POR 354 resets the OTP IC 242 and waits until the supply voltage returns to the specified range.

[0144] BG 355 supplies accurate reference voltage and current to LDO 356 and oscillator 359. LDO 356 supplies power to digital core 361, communication interface 357, and electronic fuse memory bank 358.

[0145] The OTP IC 242 is configured to operate in at least the following modes: • Fuse Programming (Fusing): During e-fuse programming (programming of one-time programmable memory), a high current is required to blow the relevant fuses in the electronic fuse memory bank 358. In this mode, a higher bias current is supplied to maintain the gain and bandwidth of the adjustment loop. • Fuse reading. In this mode, an intermediate level of current is required to maintain electronic fuse readings in the electronic fuse memory bank 358. This mode is performed during startup of the OTP IC 242 to transfer the fuse contents to the shadow register. In this mode, the gain and bandwidth of the adjustment loop are set to lower values ​​than in fusing mode. • Normal operation: In this mode, the LDO 356 is driven under very low bias current conditions to operate the OTP IC 242 at low power, so that the OTP IC 242 consumes as little power as possible.

[0146] Oscillator 359 supplies the necessary clock to the digital core / engine 361 during testing (SCAN test), fusing, and normal operation. Oscillator 359 is trimmed to meet the strict timing requirements during fusing mode.

[0147] In this example, the communication interface 357 conforms to the FM+ specification of the I2C standard, but also conforms to both low-speed and high-speed modes. The OTP IC 242 uses the communication interface 357 to communicate with the driver device 202 (host) for data and key exchange.

[0148] The digital core 361 implements the control and communication functions of the OTP IC 242. The cryptographic authentication device of the digital core 361 enables the OTP IC 242 to authenticate itself with the driver device 202 (for example, for a specific application) (for example, using ECDSA encrypted messages) to ensure that the OTP IC 242 is genuine and authorized to connect to the driver device 202 (or another product).

[0149] Referring to Figure 16 of the attached diagram, the OTP IC 242 performs the following PKI procedure to authenticate the OTP IC 242 for use with the host (e.g., driver device 202). 1. Verification of the signer's public key: The host requests the manufacturing public key and certificate. The host verifies the certificate with the authenticated public key. 2. Device public key verification: If verification is successful, the host will request the device public key and certificate. The host will verify the certificate with the manufacturer's public key. 3. Challenge-Response: If verification is successful, the host creates a random number challenge and sends it to the device. The final product signs the random number challenge with the device's private key. 4. The signature is sent back to the host for verification using the device's public key.

[0150] If all steps of the authentication procedure are completed successfully, the chain of trust is verified back to the trust root, and the OTP IC 242 is successfully authenticated for use with the host. However, if any step of the authentication procedure fails, the OTP IC 242 will not be authenticated for use with the host, and the use of devices incorporating the OTP IC 242 will be restricted or prevented.

[0151] The above outlines some examples or embodiments so that those skilled in the art may better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the various examples or embodiments presented herein. Those skilled in the art should also understand that such equivalent configurations may be made in various ways, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

[0152] While the subject matter has been described in language specific to structural features or methodological actions, it should be understood that the subject matter of the attached claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms that implement at least some of the claims.

[0153] Various operations of examples or embodiments are provided herein. The order in which some or all operations are described should not be construed as implying that these operations are necessarily dependent on that order. Alternative orderings will be understood to be of interest to this description. Furthermore, it will be understood that not all operations are necessarily present in every embodiment provided herein. Also, it will be understood that not all operations are necessary in some examples or embodiments.

[0154] Furthermore, “exemplary” is used herein to mean useful as an example, case, illustration, etc., and is not necessarily advantageous. Where used in this application, “or” is intended to mean inclusive “or” and not exclusive “or”. Furthermore, “a” and “an” as used in this application and the attached claims are generally interpreted to mean “one or more” unless otherwise specified or unless it is clear from the context that they refer to a singular form. Also, at least one of A and B, etc., generally means A or B, or both A and B. Furthermore, wherever “includes,” “having,” “has,” “with,” or variations thereof are used, such terms are intended to be inclusive, as is the term “comprising.” Also, unless otherwise specified, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects, and such terms are used solely as identifiers, names, etc., for features, elements, items, etc. For example, the first element and the second element generally correspond to element A and element B, or two different or two identical elements or the same element.

[0155] Furthermore, while this disclosure has been shown and described in relation to one or more implementations, equivalent modifications and alterations will be conceivable to those skilled in the art based on reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and alterations and is limited only by the following claims. In particular, with respect to the various functions performed by the features described above (e.g., elements, resources, etc.), the terminology used to describe such features is intended to correspond to any feature that is not structurally equivalent to the disclosed structure but performs a particular function of the described feature (e.g., functionally equivalent), unless otherwise indicated. In addition, while certain features of this disclosure may be disclosed in relation to only one of several implementations, such features may be combined with one or more other features of other implementations so as to be desired and advantageous for any given or particular application.

[0156] Examples or embodiments of the subject matter and functional operations described herein may be implemented in digital electronic circuits, or in computer software, firmware, or hardware, or in a combination of one or more thereof, including the structures disclosed herein and their structural equivalents.

[0157] Some examples or embodiments are implemented using one or more modules of computer program instructions encoded on a computer-readable medium for execution by a data processing device or for controlling the operation of a data processing device. The computer-readable medium can be a manufactured product such as a hard drive or embedded system in a computer system. The computer-readable medium may be acquired separately and later encoded together with one or more modules of computer program instructions, for example, by delivery of one or more modules of computer program instructions over a wired or wireless network. The computer-readable medium may be a machine-readable storage device, a machine-readable storage board, a memory device, or a combination of one or more of these.

[0158] The terms “computing device” and “data processing device” encompass all devices, machines, and equipment for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, a device may include code that creates an execution environment for the computer program in question, such as processor firmware, protocol stacks, database management systems, operating systems, runtime environments, or code comprising one or more of these. Furthermore, a device may employ various different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0159] The processes and logical flows described herein may be executed by one or more programmable processors that run on input data and execute one or more computer programs to perform a function by generating an output.

[0160] Processors suitable for executing computer programs include, for example, both general-purpose and dedicated microprocessors, as well as any one or more processors in any type of digital computer. Generally, a processor receives instructions and data from read-only memory or random-access memory or both. Essential elements of a computer are a processor that executes instructions and one or more memory devices for storing instructions and instructions and data. Generally, a computer also includes one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or is operablely coupled to them to receive data from them, transfer data to them, or both. However, a computer is not required to have such devices. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices.

[0161] As used herein and in the claims, the terms “comprises” and “comprising,” and their variations, mean that a particular feature, step, or integer is included. These terms should not be construed as excluding the presence of other features, steps, or components.

[0162] The present invention may also be more widely available individually or collectively in any or all combinations of two or more such parts, elements, steps, examples, and / or features mentioned or indicated herein. In particular, one or more features in any of the embodiments described herein may be combined with one or more features from any other embodiments described herein.

[0163] Protection may be sought for any feature disclosed in any one or more public documents referenced herein in conjunction with this disclosure.

[0164] While certain exemplary embodiments of the present invention have been described, the appended claims are not intended to be limited to these embodiments only. The claims should be construed literally, intentionally, and / or to encompass equivalents.

[0165] Typical features Representative features are described in the following clauses, which may be described independently or in any combination with one or more features disclosed in the text and / or drawings of this specification. 1. A microchip for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna, or a piezo transducer, and the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the subsystem being: It is an oscillator, Main clock signal and, A first phase clock signal that is initially high during the positive half-cycle of the main clock signal and low during the negative half-cycle of the main clock signal, An oscillator configured to generate a second phase clock signal which is high twice during the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-matched. A pulse-width modulation (PWM) signal generator subsystem, A delay-locked loop is configured to use a first phase clock signal and a second phase clock signal to generate a double-frequency clock signal which has twice the frequency of the main clock signal, to control the rising edges of the first phase clock signal and the second phase clock signal to synchronize with the rising edge of the double-frequency clock signal, to generate a first phase output signal and a second phase output signal, by adjusting the frequency and duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal, and the first phase output signal and the second phase output signal are configured to drive an H-bridge circuit to generate an AC drive signal for driving a resonant circuit. A first phase output signal terminal configured to output a first phase output signal to an H-bridge circuit, A second phase output signal terminal configured to output a second phase output signal to an H-bridge circuit, A PWM signal generator subsystem comprising a feedback input terminal configured to receive a feedback signal from an H-bridge circuit, Analog-to-digital converter (ADC) subsystem, A plurality of ADC input terminals configured to receive multiple analog signals, each of which is connected to a feedback input terminal, wherein one of the plurality of ADC input terminals is connected to a feedback input terminal so that the ADC subsystem receives a feedback signal from an H-bridge circuit, the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the main clock signal, and the ADC subsystem is configured to generate an ADC digital signal using the sampled analog signal. An ADC subsystem comprising: a digital processor subsystem configured to receive an ADC digital signal from an ADC subsystem, process the ADC digital signal, and generate a driver control signal, and further configured to communicate the driver control signal to a PWM signal generator subsystem to control the PWM signal generator subsystem; A digital-to-analog converter (DAC) subsystem, A digital-to-analog converter (DAC) configured to control a voltage regulator circuit configured to convert a digital control signal generated by a digital processor subsystem into an analog voltage control signal, thereby generating a voltage for modulation by an H-bridge circuit, A microchip comprising a DAC subsystem, the DAC subsystem having a DAC output terminal configured to output an analog voltage control signal for controlling a voltage regulator circuit to generate a predetermined voltage for modulation by an H-bridge circuit to drive a resonant circuit in response to a feedback signal indicating the operation of the resonant circuit. 2. The microchip described in Clause 1, wherein the oscillator is configured to generate a main clock signal at a frequency of 50 kHz to 105 MHz. 3. The microchip The microchip according to Clause 1 or 2, further comprising a frequency divider connected to the oscillator to receive a main clock signal from the oscillator, and configured to divide the main clock signal by a predetermined divisor and output a frequency reference signal to a delay-locked loop. 4. A delay-locked loop comprises multiple delay lines connected end to end, the total delay of the delay lines being equal to the period of the main clock signal, as described in any one of clauses 1 to 3 of the microchip. 5. The microchip described in Clause 4, wherein the delay-locked loop is configured to adjust the duty cycles of the first phase clock signal and the second phase clock signal in response to a driver control signal by varying the delay of each delay line within the delay-locked loop. 6. A microchip according to any one of Clauses 1 to 5, wherein the feedback input terminal is configured to receive a feedback signal indicating the parameters of operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal. 7. A microchip according to any one of Clauses 1 to 6, wherein the feedback input terminal is configured to receive a feedback signal from an H-bridge circuit in the form of a voltage indicating the rms current of the AC drive signal driving the resonant circuit. 8. The microchip according to any one of Clauses 1 to 7, wherein the ADC subsystem comprises a plurality of further ADC input terminals configured to receive a feedback signal indicating at least one of the voltages of a battery connected to the microchip or a battery charger connected to the microchip. 9. Microchips A microchip according to any one of Clauses 1 to 8, further comprising a temperature sensor embedded in a microchip, the temperature sensor configured to generate a temperature signal indicating the temperature of the microchip, the temperature signal being received by a further ADC input terminal of an ADC subsystem, and the temperature signal being sampled by an ADC. 10. The microchip described in any one of clauses 1 to 9, wherein the ADC subsystem is configured to sequentially sample signals received at multiple ADC input terminals, and each signal is sampled by the ADC subsystem a predetermined number of times. 11. Microchips, The microchip described in any one of the clauses 1 to 10 further comprises a battery charging subsystem configured to control the charging of an external battery connected to the microchip. 12. The DAC subsystem is The microchip according to any one of the clauses 1 to 11, further comprising a further digital-to-analog converter (DAC) configured to convert further digital control signals generated by a digital processor subsystem into further analog voltage control signals for controlling a voltage regulator circuit. 13. A microchip for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna, or a piezo transducer, and the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the subsystem being The first power terminal and The second power terminal and An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, The first switch and the third switch are connected in series between the first power terminal and the second power terminal. The first output terminal is electrically connected between the first switch and the third switch. The second and fourth switches are connected in series between the first power terminal and the second power terminal. The second output terminal is electrically connected to an H-bridge circuit between the second switch and the fourth switch, A first phase terminal configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator, A second phase terminal configured to receive a second phase output signal from a PWM signal generator, A digital state machine configured to generate timing signals based on a first phase output signal and a second phase output signal, output the timing signals to switches of an H-bridge circuit, and sequentially control the switches on and off so that the H-bridge circuit outputs AC drive signals to drive a resonant circuit, wherein the sequence includes a free-floating period in which the first and second switches are turned off and the third and fourth switches are turned on to dissipate the energy stored by the resonant circuit. It is a current sensor, A first current-sensing resistor is connected in series between the first switch and the first power terminal, A first voltage sensor is configured to measure the voltage drop across a first current-sensing resistor and to supply a first voltage output indicating the current flowing through the first current-sensing resistor. A second current-sensing resistor is connected in series between the second switch and the first power terminal, A second voltage sensor is configured to measure the voltage drop across a second current sensor resistor and to supply a second voltage output indicating the current flowing through the second current sensing resistor. A current sensor is provided, which incorporates a current sensor output terminal configured to supply an RMS output voltage to ground equal to a first voltage output and a second voltage output, The RMS output voltage of the microchip represents the RMS current flowing through the first or second switch and the current flowing through the resonant circuit connected between the first and second output terminals. 14. The microchip described in Clause 13, wherein the H-bridge circuit is configured to output 22W to 50W of power to a resonant circuit connected to a first output terminal and a second output terminal. 15. Microchips are The microchip according to Clause 13 or 14, further comprising a temperature sensor embedded in the microchip, the temperature sensor being configured to measure the temperature of the microchip and to disable at least a portion of the microchip if the temperature sensor detects that the microchip is above a predetermined threshold. 16. A device for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna, or a piezo transducer, and the device is A first microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the subsystem being The first power terminal and The second power terminal and An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, The first switch and the third switch are connected in series between the first power terminal and the second power terminal. The first output terminal is electrically connected between the first switch and the third switch. The second and fourth switches are connected in series between the first power terminal and the second power terminal. The second output terminal is electrically connected to an H-bridge circuit between the second switch and the fourth switch, A first phase terminal configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator subsystem, A second phase terminal configured to receive a second phase output signal from a PWM signal generator, A digital state machine configured to generate timing signals based on a first phase output signal and a second phase output signal, output the timing signals to switches of an H-bridge circuit, and sequentially control the switches on and off so that the H-bridge circuit outputs an AC drive signal to a resonant circuit to drive the resonant circuit and generate and transmit ultrasonic waves, wherein the sequence includes a free-floating period in which the first and second switches are turned off and the third and fourth switches are turned on to dissipate the energy accumulated by the resonant circuit. It is a current sensor, A first current-sensing resistor is connected in series between the first switch and the first power terminal, A first voltage sensor is configured to measure the voltage drop across a first current-sensing resistor and to supply a first voltage output indicating the current flowing through the first current-sensing resistor. A second current-sensing resistor is connected in series between the second switch and the first power terminal, A second voltage sensor is configured to measure the voltage drop across a second current sensor resistor and to supply a second voltage output indicating the current flowing through the second current sensing resistor. A current sensor output terminal that supplies an RMS output voltage to ground equal to the first voltage output and the second voltage output, The RMS output voltage is indicated by the current sensor output terminal, which shows the RMS current flowing through the first or second switch and the current flowing through the resonant circuit connected between the first output terminal and the second output terminal. A second microchip connected to a first microchip and controlling an H-bridge circuit to generate an AC drive signal, wherein the second microchip is a single unit comprising a plurality of interconnected embedded components and subsystems. It is an oscillator, Main clock signal and, A first phase clock signal that is initially high during the positive half-cycle of the main clock signal and low during the negative half-cycle of the main clock signal, An oscillator configured to generate a second phase clock signal which is high twice during the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-matched. A pulse width modulation (PWM) signal generator subsystem, A delay-locked loop configured to generate a double-frequency clock signal, which is twice the frequency of a main clock signal, using a first phase clock signal and a second phase clock signal, wherein the delay-locked loop is configured to control the rising edges of the first phase clock signal and the second phase clock signal to synchronize with the rising edges of the double-frequency clock signal, and the delay-locked loop is configured to generate a first phase output signal and a second phase output signal by adjusting the frequency and duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal, wherein the first phase output signal and the second phase output signal are configured to drive an H-bridge circuit to generate an AC drive signal for driving a resonant circuit, A first phase output signal terminal configured to output a first phase output signal to an H-bridge circuit, A second phase output signal terminal configured to output a second phase output signal to an H-bridge circuit, A PWM signal generator subsystem comprises a feedback input terminal configured to receive a feedback signal from an H-bridge circuit, wherein the feedback signal indicates parameters of the operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving a resonant circuit with an AC drive signal. Analog-to-digital converter (ADC) subsystem, A plurality of ADC input terminals configured to receive multiple analog signals, each of which is connected to a feedback input terminal, wherein one of the plurality of ADC input terminals is connected to a feedback input terminal so that the ADC subsystem receives a feedback signal from an H-bridge circuit, the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the main clock signal, and the ADC subsystem is configured to generate an ADC digital signal using the sampled analog signal. An ADC subsystem comprising: a digital processor subsystem configured to receive an ADC digital signal from an ADC subsystem, process the ADC digital signal, and generate a driver control signal, and further configured to communicate the driver control signal to a PWM signal generator subsystem to control the PWM signal generator subsystem; A digital-to-analog converter (DAC) subsystem, A digital-to-analog converter (DAC) configured to control a voltage regulator circuit configured to convert a digital control signal generated by a digital processor subsystem into an analog voltage control signal, thereby generating a voltage for modulation by an H-bridge circuit, A device comprising a first microchip, comprising a DAC subsystem, which includes a DAC output terminal configured to output an analog voltage control signal for controlling a voltage regulator circuit to generate a predetermined voltage for modulation by an H-bridge circuit to drive a resonant circuit in response to a feedback signal indicating the operation of the resonant circuit. 17. The device is The apparatus according to Clause 16, comprising a boost converter circuit configured to increase the voltage of a power supply to a boost voltage in response to an analog voltage output signal from a DAC output terminal, the boost converter circuit further comprising a boost converter circuit configured to supply the boost voltage at a first power supply terminal such that the boost voltage is modulated by switching of a switch of an H-bridge circuit. 18. The apparatus according to Clause 16 or 17, wherein a current sensor is configured to sense the current flowing through a resonant circuit during a free-floating period, and a digital state machine is configured to adapt a timing signal to switch either a first switch or a second switch to the ON position when the current sensor senses that the current flowing through the resonant circuit during a free-floating period is zero. 19. During the setup phase of the device's operation, the second microchip, When the first and second switches are turned off and the third and fourth switches are turned on, the time length until the current flowing through the resonant circuit becomes zero is measured. The apparatus described in any one of clauses 16 to 18, which is configured to set the length of the free-floating period to be equal to the measured length of time.

Claims

1. A microchip for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna, or a piezo transducer, and the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems. It is an oscillator, Main clock signal and, A first phase clock signal that is initially high during the positive half-cycle of the main clock signal and low during the negative half-cycle of the main clock signal, An oscillator configured to generate a second phase clock signal which is high twice during the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-matched. A pulse-width modulation (PWM) signal generator subsystem, A delay-locked loop is configured to use the first phase clock signal and the second phase clock signal to generate a double-frequency clock signal having twice the frequency of the main clock signal, to control the rising edges of the first phase clock signal and the second phase clock signal to synchronize with the rising edge of the double-frequency clock signal, and to adjust the frequency and duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal in order to generate a first phase output signal and a second phase output signal, wherein the first phase output signal and the second phase output signal are configured to drive an H-bridge circuit to generate an AC drive signal for driving the resonant circuit, A first phase output signal terminal configured to output the first phase output signal to the H-bridge circuit, A second phase output signal terminal configured to output the second phase output signal to the H-bridge circuit, A feedback input terminal configured to receive a feedback signal based on a current sensing signal from the H-bridge circuit, wherein the feedback signal represents a parameter of the operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit, and the feedback input terminal comprises: The PWM signal generator subsystem includes a PWM signal generator subsystem that minimizes the voltage overshoot of the voltage applied to the resonant circuit, Analog-to-digital converter (ADC) subsystem, A plurality of ADC input terminals configured to receive a plurality of analog signals, wherein one of the plurality of ADC input terminals is connected to the feedback input terminal so that the ADC subsystem receives the feedback signal from the H-bridge circuit, the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the main clock signal, and the ADC subsystem is configured to use the sampled analog signals to generate an ADC digital signal that generates the driver control signal, ADC subsystem comprising: a digital processor subsystem configured to receive the ADC digital signal from the ADC subsystem, process the ADC digital signal to generate the driver control signal, and communicate the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; A digital-to-analog converter (DAC) subsystem, A digital-to-analog converter (DAC) is configured to control a voltage regulator circuit that, in response to the feedback signal, converts a digital control signal generated by the digital processor subsystem into an analog voltage control signal to generate a voltage for modulation by the H-bridge circuit, and controls the absolute maximum current of the resonant circuit. A DAC subsystem comprising: a DAC output terminal configured to output an analog voltage control signal for controlling the voltage regulator circuit to generate a predetermined voltage for modulation by the H-bridge circuit in order to drive the resonant circuit in response to a feedback signal indicating the operation of the resonant circuit; A microchip equipped with this feature.

2. The microchip according to claim 1, wherein the oscillator is configured to generate the main clock signal at a frequency of 50 kHz to 105 MHz.

3. The aforementioned microchip The microchip according to claim 1 or 2, further comprising a frequency divider connected to the oscillator for receiving the main clock signal from the oscillator, and configured to divide the main clock signal by a predetermined divisor and output a frequency reference signal to the delay-locked loop.

4. The microchip according to any one of claims 1 to 3, wherein the delay-locked loop comprises a plurality of delay lines connected from end to end, and the total delay of the delay lines is equal to the period of the main clock signal.

5. The microchip according to claim 4, wherein the delay-locked loop is configured to adjust the duty cycles of the first phase clock signal and the second phase clock signal in response to the driver control signal by changing the delay of each delay line within the delay-locked loop.

6. The microchip according to any one of claims 1 to 5, wherein the feedback input terminal is configured to receive a feedback signal indicating the parameters of the operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal.

7. The microchip according to any one of claims 1 to 6, wherein the feedback input terminal is configured to receive a feedback signal from the H-bridge circuit in the form of a voltage indicating the rms current of the AC drive signal driving the resonant circuit.

8. The microchip according to any one of claims 1 to 7, wherein the ADC subsystem comprises a plurality of further ADC input terminals configured to receive a feedback signal indicating at least one of the voltage of a battery connected to the microchip or the voltage of a battery charger connected to the microchip.

9. The aforementioned microchip The microchip according to any one of claims 1 to 8, further comprising a temperature sensor embedded in the microchip, the temperature sensor being configured to generate a temperature signal indicating the temperature of the microchip, the temperature signal being received by a further ADC input terminal of the ADC subsystem, and the temperature signal being sampled by the ADC subsystem.

10. The microchip according to any one of claims 1 to 9, wherein the ADC subsystem is configured to sequentially sample signals received at the plurality of ADC input terminals, and each signal is sampled by the ADC subsystem a predetermined number of times.

11. The aforementioned microchip The microchip according to any one of claims 1 to 10, further comprising a battery charging subsystem configured to control the charging of an external battery connected to the microchip.

12. The DAC subsystem, The microchip according to any one of claims 1 to 11, further comprising a further digital-to-analog converter (DAC) configured to convert further digital control signals generated by the digital processor subsystem into further analog voltage control signals for controlling the voltage regulator circuit.

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