Packaging substrate and method for manufacturing the same

Abstract

To provide: a glass substrate that reduces undulation that may occur when various types of elements are mounted; a packaging substrate where a large number of elements are mounted on the glass substrate; and a manufacturing method of the packaging substrate.SOLUTION: In a semiconductor device, a packaging substrate 20 includes a core layer 22, which includes: a glass substrate 21 including a first surface 213 and a second surface 214 facing each other; and a plurality of cavity portions 28 that open toward the first surface or the second surface and have different depths. Accordingly, a packaging substrate can reduce undulation that may occur when active elements such as a transistor, or power transfer elements such as a multilayer ceramic capacitor (MLCC), that are various types of cavity elements including passive elements are mounted.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This embodiment relates to a packaging substrate and a method for manufacturing a packaging substrate, and more specifically, to a packaging substrate including a glass substrate and a manufacturing method therefor.

Background Art

[0002] In fabricating electronic components, the process of implementing a circuit on a semiconductor wafer is referred to as the front-end process (FE), and the process of assembling the wafer into a state where it can be used in an actual product is referred to as the back-end process (BE). This back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nanoscale line widths, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively speaking, there is no technology that can perfectly package this. Therefore, the electrical performance of a semiconductor may sometimes be determined by packaging technology and the electrical connections thereby, rather than the performance of the semiconductor technology itself.

[0004] Ceramics or resins are applied as materials for packaging substrates. Recently, research has been underway to apply silicon or glass to high-end packaging substrates. In particular, a packaging substrate having a cavity structure has been developed by applying a glass substrate.

[0005] On the other hand, within the packaging process, redistribution layer (RDL) refers to a general term for techniques that change the position of electrical terminals (e.g., Al Pads) already formed using wafer-level packaging (WLP) process technology to any desired position. Such RDL is used as a method to overcome design limitations in semiconductor manufacturing plants through packaging, that is, it is utilized in the stacking of semiconductor chips.

[0006] Relevant prior art includes U.S. Patent Publication US2023 / 0162992A1 and Korean Patent Publication No. 10-2014-0082305. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The objective of this embodiment is to provide a packaging substrate that mitigates undulation that occurs when mounting various types of elements in a glass substrate and a packaging substrate on which a large number of elements are mounted, and a manufacturing method for the same.

[0008] Furthermore, the purpose of this embodiment is to provide a packaging substrate with cavities of various depths arranged to accommodate the design of elements with various heights, as well as a method for manufacturing the same.

[0009] Furthermore, the purpose of this embodiment is to enable the formation of a flat insulating layer on a glass substrate and a flat upper layer on top of the insulating layer. [Means for solving the problem]

[0010] To achieve the above objective, a packaging substrate according to one embodiment includes a core layer, the core layer includes a glass substrate including a first surface and a second surface facing each other; and at least two or more cavity portions having openings that open in the direction of the first surface or the direction of the second surface, respectively.

[0011] The two or more cavity portions have different depths from each other.

[0012] The packaging substrate may include: a cavity element comprising two or more individual elements arranged in the cavity and having different heights from each other; and an insulating layer embedded inside the cavity and positioned on the surface of the glass substrate where the opening is formed.

[0013] The cavity portion may include: a first cavity portion that is recessed and opens in the direction of the first surface and has a first depth; and a second cavity portion that is recessed and opens in the direction of the first surface or the second surface and has a second depth. The second depth is greater than the first depth.

[0014] In this case, the cavity element may include a first cavity element arranged in the first cavity portion and a second cavity element arranged in the second cavity portion.

[0015] One or more connecting electrodes may be placed on the first cavity element, and one or more connecting electrodes may be placed on the second cavity element.

[0016] In another example, the cavity includes: a first cavity recessed and opening in the direction of the first surface and having a first depth; a second cavity recessed and opening in the direction of the first surface or the second surface and having a second depth; and a third cavity having a third depth that penetrates the first surface and the second surface. The second depth may be greater than the first depth.

[0017] A first cavity element may be arranged in the first cavity portion, a second cavity element may be arranged in the second cavity portion, and a third cavity element may be arranged in the third cavity portion.

[0018] One or more connecting electrodes may be arranged on the first cavity element. One or more connecting electrodes may be arranged on the second cavity element. One or more connecting electrodes may be arranged on the third cavity element in the direction of the first plane or the direction of the second plane.

[0019] One or more connecting electrodes may be further arranged on the third cavity element between them in the direction of the second plane.

[0020] One or more connecting electrodes may be arranged on the third cavity element in both the first and second plane directions.

[0021] To achieve the above objective, a method for manufacturing a packaging substrate according to one embodiment may include: a defect formation step of providing a glass substrate including a first surface and a second surface facing each other, and forming a plurality of defects on the first surface or the second surface to different degrees; and a cavity formation step of etching the glass substrate to form at least two or more cavity portions having different depths.

[0022] The method for manufacturing the packaging substrate may further include an array step and an insulating layer formation step after the cavity formation step.

[0023] The aforementioned arrangement step is the step of arranging cavity elements in the cavity portion.

[0024] The insulating layer formation step is to form an insulating layer on the surface where the opening of the cavity portion is formed.

[0025] The cavity elements arranged in the cavity portion may have different heights from each other.

[0026] The cavity portion includes a first cavity portion and a second cavity portion. The first cavity portion is recessed and open in the direction of the first surface, and has a first depth. The second cavity portion is recessed and open in the direction of the first surface or the second surface, and has a second depth deeper than the first depth.

[0027] The cavity element includes a first cavity element and a second cavity element. The first cavity element is arranged in the first cavity portion, and the second cavity element is arranged in the second cavity portion.

[0028] The method for manufacturing the packaging substrate can further include a connection electrode formation step.

[0029] The connection electrode formation step can be a step of forming one or more connection electrodes connected to the first cavity element and one or more connection electrodes connected to the second cavity element.

[0030] According to another example, the cavity portion can include a first cavity portion, a second cavity portion, and a third cavity portion.

[0031] The first cavity portion is recessed and open in the direction of the first surface, and has a first depth.

[0032] The second cavity portion is recessed and open in the direction of the first surface or the second surface, and has a second depth deeper than the first depth.

[0033] The third cavity portion penetrates through the first surface and the second surface, and has a third depth.

[0034] The cavity element can include a first cavity element, a second cavity element, and a third cavity element.

[0035] The first cavity element can be arranged in the first cavity portion.

[0036] The second cavity element may be arranged in the second cavity portion.

[0037] The third cavity element may be arranged in the third cavity portion.

[0038] The method for manufacturing the packaging substrate may further include a step of forming connecting electrodes.

[0039] The connection electrode formation step may be the step of forming one or more connection electrodes connected to the first cavity element; one or more connection electrodes connected to the second cavity element; and one or more connection electrodes connected to the third cavity element.

[0040] The aforementioned connection electrode formation step allows for the formation of further connection electrodes on two or more surfaces of the third cavity element. [Effects of the Invention]

[0041] The packaging substrate and its manufacturing method, as demonstrated in this example, can mitigate undulation that may occur when mounting various types of components.

[0042] One concrete example is the ability to provide a packaging substrate with a core layer that has an overall flat surface, even while mounting elements of various heights within a glass substrate.

[0043] In practical applications, the structural features of the cavity sections, which have varying heights, allow for a substantially flat surface on the core layer. This can be utilized to provide a packaging substrate in which a substantially flat insulating layer and / or upper layer is formed on the packaging substrate. [Brief explanation of the drawing]

[0044] The above and other subjects, features and advantages of this disclosure will become further apparent to those of an ordinary person in the art by describing in detail exemplary embodiments with reference to the accompanying drawings. [Figure 1] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in a real-world example. [Figure 2] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate related to other concrete examples. [Figure 3] (a) and (b) are conceptual diagrams illustrating a portion of a packaging substrate related to an actual example in cross-section. [Figure 4] This flowchart shows a cross-sectional view of the process of generating the core distribution layer, which is part of the manufacturing process of a packaging substrate related to a concrete example. [Figure 5] This flowchart shows a cross-sectional view of the process of generating the insulating layer in the manufacturing process of a packaging substrate, as illustrated in the example. [Figure 6] Figures (a) to (c) are diagrams illustrating a portion of a packaging substrate related to an actual example in cross-section. [Figure 7] Figures (a) to (c) are diagrams illustrating a cross-sectional view of a part of a packaging substrate relating to another concrete example. [Figure 8] This flowchart shows a cross-sectional view of the manufacturing process of a packaging substrate in a concrete example, where S1 is the defect formation step, S2 is the cavity formation step, S3 is the array step, S4 is the insulating layer formation step, and S5 is the connection electrode formation step. [Best Mode for Carrying Out the Invention]

[0045] The embodiments are described below in detail with reference to the accompanying drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the embodiments belong. However, the embodiments can be realized in a variety of different forms and are not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0046] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0047] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0048] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0049] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0050] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0051] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0052] In the process of developing a semiconductor device that is more integrated, thinner, and capable of high performance, the inventors recognized that not only the element itself but also the packaging is a crucial factor in improving performance. While researching this, they discovered that, unlike conventional methods that applied two or more core layers as a packaging substrate on a motherboard, such as interposers and organic substrates, applying a single layer of glass core and a cavity structure could make the packaging substrate even thinner and contribute to improving the electrical characteristics of the semiconductor device.

[0053] Components performing various functions can be mounted in a cavity structure on a glass substrate, which can further reduce the overall thickness of the packaging substrate. Components mounted in a cavity structure have various sizes and thicknesses (heights) depending on their type. Therefore, when applied to the same cavity structure, differences in component height can cause undulation, i.e., defects in the form of waves or undulations. Such undulation can affect the thinning and weight of the packaging substrate and may also weaken its electrical characteristics.

[0054] As a result of further research, we confirmed that undulation can be improved by adjusting the degree of etching while considering the height (thickness) or size of the element when forming a cavity structure for mounting the element on a glass substrate, and thus completed the invention.

[0055] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in an example; Figure 2 shows a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in another example; and Figures 3(a) and 3(b) are conceptual diagrams illustrating a cross-sectional portion of a packaging substrate in an example, respectively.

[0056] To achieve the above objective, the semiconductor device 100 according to the embodiment includes a semiconductor element section 30 on which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20 and transmitting external electrical signals to the semiconductor elements 32, 34, and 36.

[0057] A packaging substrate 20 according to one example includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be positioned.

[0058] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connecting electrodes or the like. Specifically, the semiconductor element portion 30 may be, for example, a computing element such as a CPU or GPU (first element: 32, second element: 34), a memory element such as a memory chip (third element: 36), etc., but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0059] The motherboard 10 may be a printed circuit board, a printed wiring board, or the like.

[0060] The packaging substrate 20 may further include a lower layer (not shown) selectively located below the core layer.

[0061] The core layer 22 may include: a glass substrate 21 having a first area 221 having a first thickness 211, and a second area 222 adjacent to the first area 221 and having a second thickness 212 which is thinner than the first thickness; a number of core vias 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23, which electrically connects a first surface 213 of the glass substrate 21 and a second surface 214 facing the first surface via the core vias 23. That is, the core layer 22 may include a glass substrate 21 having a first surface 213 and a second surface 214 facing each other, core vias 23, a cavity 28, or all of these.

[0062] The second region 222 of the core layer 22 can function as a cavity structure.

[0063] Within the same area, the glass substrate 21 has a first surface 213 and a second surface 214 that face each other, and since these two surfaces are generally parallel to each other, the glass substrate 21 has a constant thickness throughout.

[0064] The internal space 281 is formed by the difference in thickness between the first area 221 and the second area 222, and serves to accommodate part or all of the cavity element 40.

[0065] The glass substrate 21 may include core vias 23 that penetrate the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first region 221 and the second region 222 and may be formed with an intended pitch and pattern.

[0066] Conventionally, packaging substrates for semiconductor devices have been applied in a form where silicon substrates and organic substrates are stacked. In the case of silicon substrates, due to their semiconductor properties, there is a risk of parasitic elements occurring when applied to high-speed circuits, which is a disadvantage as it results in relatively large power losses. In the case of organic substrates, a large area is required to form even more complex distribution patterns, which does not fit with the trend towards manufacturing ultra-miniaturized electronic devices. In order to form complex distribution patterns within a given size, it is practically necessary to miniaturize the pattern, but due to the properties of materials such as polymers used in organic substrates, there are practical limitations to the miniaturization of the pattern.

[0067] In this concrete example, a glass substrate 21 is used as a support for the core layer 22 to solve these problems. Furthermore, by applying core vias 23 formed through the glass substrate 21 together with the glass substrate 21, the length of the electrical current is further shortened, resulting in a more compact packaging substrate 20 with faster response and lower loss characteristics.

[0068] The glass substrate 21 is preferably a glass substrate used for semiconductors, and may, but is not limited to, a borosilicate glass substrate or an alkali-free glass substrate.

[0069] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined area of ​​the glass substrate 21, specifically by etching a plate-shaped glass by physical and / or chemical methods.

[0070] Specifically, the formation of the core via 23 may involve a method such as forming defects (scratches) on the surface of the glass substrate using a laser, followed by chemical etching, or laser etching, but is not limited to these methods.

[0071] The number of core vias 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024 based on the unit area (1 cm × 1 cm) of the glass substrate 21. When these pitch conditions are met, the formation of electrically conductive layers and the performance of the packaging substrate can be improved.

[0072] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate via through vias, and a core insulating layer 223 surrounding the core distribution pattern 241. The core layer 22, having an electrically conductive layer formed inside it via core vias, acts as an electrical passage across the glass substrate 21, and by connecting the upper and lower parts of the glass substrate over a relatively short distance, it can have faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0073] The shape of the cavity portion 28 may be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, etc., and there are no limitations on its shape.

[0074] The shape of the cavity element 40 may be generally cylindrical, rectangular, or polygonal.

[0075] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0076] On the other hand, the cavity portion according to other embodiments may be implemented in a form that penetrates the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by the same process as the core via 23 formation process, and the area and shape that penetrate the glass substrate 21 may differ from those of the core via 23.

[0077] In such an embodiment, an insulating layer may be generated after the cavity elements 40 are arranged in the cavity. That is, the insulating layer may also be generated in the cavity through the process by which the core insulating layer 223 described above is generated.

[0078] The core distribution pattern 241 may be formed to be electrically connectable to the cavity element 40.

[0079] The cavity element 40 may include an active element such as a transistor, or a power transfer element such as a multilayer ceramic capacitor (MLCC), i.e., a passive element.

[0080] When a transistor or similar element is used as the cavity element 40, which plays a role in converting electrical signals between the motherboard and the semiconductor element to an appropriate level, the transistor or similar element is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0081] Furthermore, power transfer elements such as multilayer ceramic capacitors (MLCCs) play a crucial role in the performance of semiconductor devices. These passive power transfer elements are typically applied in quantities of at least 200 to a semiconductor device, and their performance is influenced by the characteristics of the electrical conductive layer surrounding the element in terms of power transfer. In one example, non-circular core vias can be applied where a low-resistance electrical conductive layer is required, such as in these power transfer elements.

[0082] On the other hand, the cavity element 40 may be fitted with passive elements such as capacitors individually inserted, or a group of elements containing a number of passive elements may be formed so that the electrodes are exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate can be further streamlined and it is even more advantageous to ensure that the insulating layer is positioned sufficiently and with high reliability in the complex spaces between elements.

[0083] The glass substrate 21 plays an intermediate or mediating role in connecting the semiconductor element section 30 and the motherboard 10 to its upper and lower parts, respectively, and the core via 23 acts as a passage for transmitting these electrical signals, thereby ensuring smooth signal transmission.

[0084] The upper layer 26 is located on the first surface 213.

[0085] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the uppermost surface of the upper layer 26 may be protected by a cover layer 60 having openings formed therein that allow the connection electrodes of the semiconductor element to make direct contact.

[0086] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface and an upper distribution pattern 251 embedded in the upper insulating layer 253, which is an electrically conductive layer having a predetermined pattern and to which the core distribution layer 24 and at least a portion thereof are electrically connected.

[0087] The upper insulating layer 253 can be any material that is applied as an insulating layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler may be used, but it is not limited to this.

[0088] The insulating layer may be formed by forming a coating layer and curing it, or by laminating an in-cured or semi-cured insulating film onto the core layer 22 and curing it. In this case, if a vacuum lamination method or the like is applied, the insulating material can be embedded into the space inside the core via 23, enabling efficient process execution.

[0089] In one embodiment, even when multiple insulating layers are laminated and applied, it may be difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case their boundary is not substantially distinguished. Alternatively, in other embodiments, the boundary between the insulating layers can be created by setting different pressures and temperatures for curing the multilayer insulating layers.

[0090] The upper distribution pattern 251 refers to an electrically conductive layer located within the upper insulating layer 253 in a predetermined configuration, and may be formed, for example, by a build-up layer method. Specifically, by forming an insulating layer, removing unnecessary portions of the insulating layer, forming an electrically conductive layer by a method such as copper plating, selectively removing unnecessary portions of the electrically conductive layer, forming another insulating layer on this electrically conductive layer, removing unnecessary portions again, and then forming another electrically conductive layer by a method such as plating, an upper distribution pattern 251 can be formed in which electrically conductive layers are formed vertically or horizontally in the desired pattern.

[0091] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, it is formed to include a fine pattern in at least a part of it so that electrical signals can be transmitted smoothly with the semiconductor element portion 30 and the intended complex pattern can be adequately accommodated. In this case, the fine pattern may have a width and spacing of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm, respectively (the description of the fine pattern is the same hereafter).

[0092] At least a portion of the upper connection layer 27 is electrically connected to the upper distribution pattern 251, and the upper connection layer 27 includes; an upper connection pattern 272 located on the upper insulating layer 253; and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion of the upper connection pattern 272 may be embedded while being exposed on the upper insulating layer 253. For example, if the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating, and if the upper connection pattern is embedded while being exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or electrically conductive layer may be removed by methods such as surface polishing or surface etching.

[0093] At least a portion of the top connection pattern 272 may include a fine pattern, similar to the top distribution pattern 251 described above. A top connection pattern 272 including such a fine pattern allows even more elements to be electrically connected in a smaller area, making the connection of electrical signals between elements or to the outside smoother and enabling more integrated packaging.

[0094] The upper connection electrode 271 may be directly connected to the semiconductor element portion 30 via a terminal or the like, or it may be connected via an element connection portion 51 such as a solder ball.

[0095] The cavity portion 28 is located above and / or below the second area 222. The cavity portion 28 includes an internal space 281 in which a cavity distribution layer 282 and a cavity element 40, which are electrically connected to the core distribution pattern 241, are located.

[0096] Specifically, the thickness of the glass substrate 21 in the second region 222 is even thinner than the thickness of the glass substrate 21 in the first region 221, allowing the cavity element 40 to be located in the internal space 281 formed by the difference in thickness. Furthermore, the core vias 23 and core distribution layer 24 formed on the glass substrate 21 serve as electrical connection structures connecting the cavity element 40 to external elements.

[0097] Furthermore, a cavity portion may be formed in the glass substrate 21 that penetrates the first surface 213 and the second surface 214 of the glass substrate 21, and cavity elements 40 may be arranged in the cavity portion.

[0098] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 via terminals or the like, or it may be electrically connected via board connection parts 52 such as solder balls. Alternatively, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located below the core layer 22.

[0099] For example, the packaging substrate 20 located between the semiconductor element section 30 and the motherboard 10 may not have any substantially additional substrates applied other than the glass substrate 21.

[0100] Conventionally, when connecting elements and motherboards, an interposer and an organic substrate were stacked together between them. This multi-layered configuration was applied for at least two reasons: firstly, there were scaling issues when directly bonding the fine patterns of the elements to the motherboard; and secondly, the difference in thermal expansion coefficients could cause damage to the wiring during the bonding process or the operation of the semiconductor device. In this example, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element was applied, and a fine pattern with a scale sufficient for mounting the element was formed on the first surface and the upper layer of the glass substrate, thereby solving these problems.

[0101] The following describes a method for manufacturing a packaging substrate according to an embodiment of the present invention.

[0102] Figures 4 and 5 are flowcharts illustrating the manufacturing process of a packaging substrate in a cross-sectional view, based on an actual example.

[0103] First, a glass substrate 21a having a flat first surface and a flat second surface is prepared as shown in Figure 4(a), and defects (scratches) 21b are formed on the glass surface at predetermined positions for the formation of core vias. The glass substrate may be a glass substrate used for electronic devices, and may, for example, an alkali-free glass substrate, but is not limited to this. Commercial products manufactured by companies such as Corning, Schott, and AGC may be used. Methods such as mechanical etching and laser irradiation may be used to form the defects (scratches).

[0104] As shown in Figure 4(b), the glass substrate 21a on which the defect (scratch) 21b is formed undergoes an etching step to form core vias 23 through a physical or chemical etching process. During the etching process, vias are formed in the defective area of ​​the glass substrate, and at the same time, the surface of the glass substrate 21a may also be etched. To prevent such etching of the glass surface, a masking film or the like can be applied. However, considering the hassle of applying and removing the masking film, it is possible to etch the defective glass substrate itself. In such a case, the thickness of the glass substrate with core vias may be slightly thinner than the thickness of the original glass substrate.

[0105] Subsequently, as shown in Figures 4(c) and 4(d), the core layer manufacturing step can be carried out by forming an electrically conductive layer 21d on the glass substrate. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited to this.

[0106] Because the surface of glass (including the surface of the glass substrate and the surface of the core via) and the surface of copper metal have different properties, their adhesion is generally poor. In practical applications, the adhesion between the glass surface and the metal can be improved using two methods: a dry method and a wet method.

[0107] The dry method is a method that applies sputtering, that is, a method that forms a seed layer 21c on the glass surface and the inner diameter surface of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper, etc. In such cases, the adhesion between the glass and the metal can be improved by an anchoring effect caused by the interaction between the surface morphology of the glass and the metal particles.

[0108] The wet method is a method of priming, in which a primer layer 21c is formed by pretreatment with a compound having a functional group such as an amine. Depending on the desired degree of adhesion, pretreatment with a silane coupling agent can be performed, followed by priming with a compound or particles having an amine functional group. As mentioned above, the support substrate in the embodiment needs to be high-performance enough to form a fine pattern, and this must be maintained even after priming. Therefore, when such a primer contains nanoparticles, it is preferable to use nanoparticles having an average diameter of 150 nm or less, and for example, it is preferable to use nanoparticles for particles having an amine group. The primer layer may, as an example, be formed by applying an adhesion improver manufactured by MEC's ​​CZ series or the like.

[0109] The seed layer / primer layer 21c can selectively form a metal layer with or without removing portions where the formation of an electrical conductive layer is unnecessary. Furthermore, the seed layer / primer layer 21c can be treated in a state where the formation of an electrical conductive layer is necessary or unnecessary, either by activating or deactivating it with metal plating, before proceeding to subsequent steps. For example, the activation or deactivation treatment may include light irradiation treatment such as a laser of a certain wavelength, or chemical treatment. For the formation of the metal layer, copper plating methods used in the manufacture of semiconductor devices may be used, but are not limited to these.

[0110] As shown in Figure 4(e), if a portion of the core distribution layer is unnecessary, it may be removed, or the etching layer 21e of the core distribution layer may be formed by partially removing or deactivating the seed layer and then performing metal plating to form an electrically conductive layer in a predetermined pattern.

[0111] Figure 5 illustrates the manufacturing steps for forming the insulating layer and the upper distribution pattern using an example.

[0112] As shown in Figure 5(a), the core via can undergo an insulating layer formation step in which the void space is filled with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. At this time, the insulating layer to be applied may be one manufactured in the form of a film, for example, by laminating an insulating layer in the form of a film under reduced pressure. By performing lamination under reduced pressure in this way, the insulating layer is sufficiently embedded into the void space inside the core via, thereby forming a core insulating layer without void formation.

[0113] Figures 5(b) to (e) illustrate the upper layer manufacturing steps.

[0114] The upper layer manufacturing step involves forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating with a resin composition that forms the insulating layer 23a, or by laminating an insulating film, and the method of laminating an insulating film is preferred for simplicity. The lamination of the insulating film can be carried out by a process of laminating and curing the insulating film, and in this case, if a reduced-pressure lamination method is applied, the insulating resin can be sufficiently embedded even in layers where an electrically conductive layer has not been formed inside the core vias. The upper insulating layer also comes into direct contact with the glass substrate at least in part, and therefore, one with sufficient adhesion is used. Specifically, it is preferable that the glass substrate and the upper insulating layer have characteristics that satisfy an adhesion test value of 4B or higher according to ASTM D3359.

[0115] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching away unnecessary parts to form an etched layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with the insulating layer in between, the pattern can be formed by forming blind vias 23b in the insulating layer and then performing a plating process. Blind vias can be formed using dry etching methods such as laser etching or plasma etching, or wet etching methods using a masking layer and etching solution.

[0116] Subsequently, although not shown in the diagram, an upper connecting layer and a cover layer may be formed.

[0117] The top connection pattern and top connection electrodes can also be formed by a process similar to that of the top distribution layer. Specifically, the top connection pattern and top connection electrodes may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, then forming an electrically conductive layer thereon, and then forming an etching layer of the electrically conductive layer. Alternatively, a method may be applied in which only the electrically conductive layer is selectively formed without applying the etching method. The cover layer may be formed so that an opening (not shown) is formed at a position corresponding to the top connection electrodes, exposing the top connection electrodes and allowing direct connection to the element connection part or the terminals of the element.

[0118] Once the upper layer is generated, the process of forming the lower connecting layer and cover layer to generate the lower layer can be carried out. The lower distribution layer and / or lower connecting layer, and selectively a cover layer (not shown) can be formed in a manner similar to the upper connecting layer and cover layer formation steps described above.

[0119] In concrete examples, when a large number of elements are mounted on the glass substrate 21, cavity portions 29a and 29b of different heights can be generated by taking into consideration the design of the elements (i.e., the position in which the elements are arranged, and the area or height of the elements).

[0120] Figures 6(a) to 6(c) are diagrams illustrating a cross-sectional view of a portion of a packaging substrate related to an actual implementation example.

[0121] As shown in Figure 6(a), one embodiment may include the formation of a first cavity 29a having a first depth h1 and a second cavity 29b having a second depth h2 in the glass substrate 21. Both the first cavity 29a and the second cavity 29b may be recessed by opening in the direction of the first surface 213.

[0122] The second depth h2 may be deeper than the first depth h1. A cavity element section having a height corresponding to the depth of the first cavity section 29a may be placed in the first cavity section 29a, and a cavity element section having a height corresponding to the depth of the second cavity section 29b may be placed in the second cavity section 29b. In this case, the height corresponding to A means a height that is substantially the same as or smaller than the height of A, but does not mean to exclude heights greater than the height of A at a level that can be covered by an upper layer or the like (the same applies hereinafter). The cavity element section may consist of one or more cavity elements 40a, 40b arranged in a row. The cavity element section may consist of individual cavity elements arranged and molded together. Alternatively, the cavity element section may consist of one or more cavity elements molded together with insulating material or the like.

[0123] Although the cavity element portion of the first cavity portion 29a and the cavity element portion of the second cavity portion 29b have different heights, the upper insulating layer 61 formed on the first cavity portion 29a and the second cavity portion 29b can be formed flat with substantially no waviness.

[0124] Furthermore, although the heights of the first cavity element 40a and the second cavity element 40b are different, the upper insulating layer 61 formed on the first cavity element 40a and the second cavity element 40b can be formed substantially flat without waviness.

[0125] The insulating layer can be formed by a method of low-pressure lamination of a semiconductor insulating film, such as Ajinomoto's ABF (Ajinomoto Build-up Film), but is not limited to this method.

[0126] Due to the characteristics of insulating materials manufactured in a specific form (e.g., film), the deep and wide spaces in which the insulating material is placed during the formation of the insulating layer can cause unevenness on the surface of the insulating layer. In particular, in cavity structures where the embedding of insulating material and the formation of the insulating layer are required in spaces wider than those of ordinary vias, the degree of undulation can be relatively severe.

[0127] One practical example attempts to solve these problems by forming the cavity sections at different depths, corresponding to the depths of the cavity elements.

[0128] The upper insulating layer 61 is partially embedded within the first cavity 29a and the second cavity 29b, and the surface of the upper insulating layer 61 can be laminated substantially flat on the first surface 213. Because the depths of the first cavity 29a and the second cavity 29b are formed differently from each other, the first surface 213 of the glass substrate 21 can be relatively flat.

[0129] A lower insulating layer 63 can also be formed on the second surface 214 of the glass substrate 21, i.e., the lower surface.

[0130] On the other hand, one or more connecting electrodes 42 may be arranged on the first cavity element 40a in the direction of the first surface 213, and one or more connecting electrodes 42 may be arranged on the second cavity element 40b in the direction of the first surface 213.

[0131] The connecting electrodes 42 may be arranged or formed on the first surface 213, for example, in the direction in which the first cavity portion 29a and the second cavity portion 29b are open. The connecting electrodes 42 can be electrically connected to an upper layer (not shown) that can be placed on top of the glass substrate 21.

[0132] The connecting electrode 42 may be formed as part of the electrodes of the first cavity element 40a and the second cavity element 40b, or it may be formed or connected as a distribution electrode of the upper layer, or it may be configured in a form that includes both of these.

[0133] In other embodiments, the first cavity portion 29a and the second cavity portion 29b may be recessed by opening in the direction of the second surface 214 of the glass substrate 21, rather than the first surface 213. In this case, the connecting electrodes may be arranged or formed so as to be in contact with the first cavity portion 29a and the second cavity portion 29b in the direction of the second surface 214. That is, one of the technical features of the present invention is the generation of cavity portions having different depths in the glass substrate 21, and the shape of the cavity openings can be applied in a variety of ways.

[0134] Furthermore, the first surface 213 and the second surface 214 of the glass substrate 21 refer to two surfaces that are opposite to each other and are not limited to any particular surface. The fact that the cavity portion is recessed and opens toward the first surface can be interpreted as opening toward either of the two opposing surfaces of the glass substrate 21.

[0135] In other embodiments, as shown in Figure 6(b), the core layer may include a second cavity portion 29b having a second depth, which is recessed and opens in the direction of the first surface 213, and a third cavity portion 29c having a third depth h3, which penetrates the first surface 213 and the second surface 214 of the glass substrate 21. The third depth h3 is the same as the height of the glass substrate 21 and is deeper than the second depth h2 of the second cavity portion 29b, which is recessed in only one direction.

[0136] In other words, according to the embodiment, some of the cavity portions having different depths may open in one direction to the glass substrate 21, while other portions may be formed by penetrating the glass substrate 21.

[0137] In the third cavity element 40c mounted in the third cavity portion 29c that penetrates the glass substrate 21, connection electrodes 42 may be arranged or formed on both the upper surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c that penetrates the glass substrate 21, one or more additional connection electrodes may be arranged in the direction opposite to the connection electrodes formed on the first surface 213 (second surface 214) with the third cavity element 40c in between.

[0138] The connecting electrode 42 can also be electrically connected to the upper layer to supply power to the semiconductor chip, or electrically connected to the lower layer to connect to the motherboard.

[0139] Another example is shown in Figure 6(c), where multiple half-cavities recessed in the glass substrate 21 with openings in one direction may have openings in different directions from one another. For example, the first cavity portion 29a may open toward the first surface 213, and the second cavity portion 29b may open toward the second surface 214.

[0140] As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other, and for example, the second depth h2 may be deeper than the first depth h1. Of course, the first depth h1 may also be deeper than the second depth h2.

[0141] In the embodiment, the connecting electrode 42 in contact with the first cavity element 40a may be electrically connected to the upper layer, and the connecting electrode 42 in contact with the second cavity element 40b may be electrically connected to the lower layer.

[0142] Depending on the design of the semiconductor elements or motherboard connected to the upper or lower layers, the role of cavity elements mounted on the packaging substrate may change, and depending on the role of such cavity elements, the opening direction of the cavity may change. Depending on the opening direction of the cavity, the arrangement of the connecting electrodes may also change.

[0143] In other words, a first cavity portion 29a having a first depth h1 may be formed in the glass substrate 21, which is recessed and opens in the direction of the first surface 213 or the second surface 214, and a second cavity portion 29b having a second depth h2 different from the first depth h1 may be formed and opens in the direction of the first surface 213 or the second surface 214.

[0144] As described above, the cavity elements 40a, 40b, and 40c may each be independently passive elements such as MLCCs or active elements such as diodes. These various elements differ in size, area, and height, which can cause undulation during the formation of the RDL (Re-Distribution Layer).

[0145] Therefore, according to the concrete example, when a large number of elements are mounted on the glass substrate 21, cavity portions of different heights can be generated by taking into consideration the design of the elements (i.e., the position in which the elements are arranged, and the area or height of the elements).

[0146] Therefore, by repeatedly applying selective masking and etching when forming the cavity, it is possible to manufacture a packaging substrate having cavity portions of different heights. However, this method has the disadvantage of being complex because it requires repeatedly forming and removing masking on the surface of the glass substrate 21.

[0147] Alternatively, when forming the cavity, defects of varying degrees can be formed by selectively irradiating with lasers of different intensities or by adjusting the laser irradiation time, and the resulting glass substrate 21 with the formed cavity can be etched to manufacture the packaging substrate. Subsequently, the etching of the glass substrate can be performed in a single step. That is, the degree of defects formed on the substrate can be varied depending on the amount of laser irradiation, and through this process, multiple half cavities or full cavities of different heights can be formed. Through this, when mounting various types of elements, undulation caused by the different heights of the elements can be mitigated or eliminated.

[0148] Figures 7(a) to 7(c) are diagrams illustrating in cross-section a portion of a packaging substrate relating to another concrete example.

[0149] As shown in Figure 7(a), the glass substrate 21 may have a first cavity portion 29a having a first depth h1, a second cavity portion 29b having a second depth h2, and a third cavity portion 29c having a third depth h3. The first cavity portion 29a and the second cavity portion 29b are recessed and open in the direction of the first surface 213, and the third cavity portion 29c can penetrate the glass substrate 21.

[0150] The second depth h2 is deeper than the first depth h1, and the third depth h3 is deeper than the second depth h2. Cavity elements having heights corresponding to the respective depths of the first cavity 29a, second cavity 29b, and third cavity 29c may be arranged in the first cavity 29a, second cavity 29b, and third cavity 29c.

[0151] Although the cavity element portions of the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29b have different heights, the upper insulating layer 61, which is placed on the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c, can be formed flat with substantially no waviness.

[0152] Cavity elements 40a, 40b, and 40c, each having a height corresponding to the depth of the first cavity section 29a, the second cavity section 29b, and the third cavity section 29c, can be arranged in the first cavity section 29a, the second cavity section 29b, and the third cavity section 29c, respectively.

[0153] Although the heights of the first cavity element 40a, the second cavity element 40b, and the third cavity portion 29c are different from each other as shown in the figure, the upper insulating layer 61 formed on the first cavity element 40a, the second cavity element 40b, and the third cavity portion 29c can be formed substantially flat without waviness.

[0154] The upper insulating layer 61 is partially embedded within the first cavity 29a, the second cavity 29b, and the third cavity 29c, and its surface can be laminated substantially flat on the first surface 213. Selectively, a lower insulating layer 63 may also be formed on the second surface 214 of the glass substrate 21, i.e., the lower surface.

[0155] The core layer in the embodiment shown in Figure 7(a) may include one or more connecting electrodes 42 arranged on the first cavity element 40a in the direction of the first surface 213, one or more connecting electrodes 42 arranged on the second cavity element 40b in the direction of the first surface 213, and one or more connecting electrodes 42 arranged on the third cavity element 40c in the direction of the first surface 213.

[0156] The connecting electrodes 42 are arranged or formed on the first surface 213 in the direction in which the first cavity portion 29a, the second cavity portion 29b, and the third cavity portion 29c are open, and can be electrically connected to an upper layer (not shown) that may be formed on the upper part of the glass substrate 21.

[0157] Additionally, in the third cavity element 40c mounted in the third cavity portion 29c penetrating the glass substrate 21, connection electrodes 42 may be arranged or formed on both the upper surface facing the first surface 213 and the bottom surface facing the second surface 214. That is, in the case of the third cavity element 40c penetrating the glass substrate 21, one or more additional connection electrodes may be arranged in the direction opposite to the connection electrodes formed on the first surface 213 (second surface 214) with the third cavity element 40c in between.

[0158] The connecting electrode 42 may be formed as part of the electrodes of the first cavity element 40a, the second cavity element 40b, and the third cavity element 40c, or as a distribution electrode of the upper layer, or it may be configured to include both of these.

[0159] The core layer in the embodiment shown in Figure 7(b) includes cavity portions 29a, 29b, and 29c that are recessed and open toward the second surface 214 of the glass substrate 21, i.e., toward the bottom surface of the glass substrate 21.

[0160] In this case, the connecting electrodes 42 may be arranged or formed on the bottom surfaces of the first cavity element 40a, the second cavity element 40b, and the third cavity element 40c. The connecting electrodes 42 facing the bottom surface may be electrically connected to a motherboard (not shown) via a lower layer formed below the core layer.

[0161] In the example of the core layer shown in Figure 7(c), the multiple half cavities recessed in the glass substrate 21 with openings in one direction may have openings in different directions from each other. For example, the first cavity portion 29a may open toward the first surface 213, and the second cavity portion 29b may open toward the second surface 214. As shown in the figure, the first depth h1 of the first cavity portion 29a and the second depth h2 of the second cavity portion 29b are different from each other, and in one example, the second depth h2 may be deeper than the first depth h1. Of course, the first depth h1 may also be deeper than the second depth h2.

[0162] As described above, the connecting electrode 42 in contact with the first cavity element 40a may be electrically connected to the upper layer, and the connecting electrode in contact with the second cavity element 40b may be electrically connected to the lower layer.

[0163] Depending on the design of the semiconductor elements or motherboard connected to the upper or lower layers, the role of cavity elements mounted on the packaging substrate may change, and depending on the role of such cavity elements, the opening direction of the cavity may change. Depending on the opening direction of the cavity, the arrangement of the connecting electrodes may also change.

[0164] Summarizing the cavity shapes shown in Figures 7(a), (b), and (c), a first cavity portion 29a may be formed in the glass substrate 21, recessed with an opening in the direction of the first surface 213 or the second surface 214 and having a first depth h1; a second cavity portion 29b may be formed with a second depth h2 different from the first depth h1, opening in the direction of the first surface 213 or the second surface 214; and a third cavity portion 29c may be formed that penetrates the first surface 213 and the second surface 214.

[0165] Figure 8 is a flowchart illustrating the manufacturing process of a packaging substrate in a cross-sectional view. Referring to Figure 8, the process of mounting cavity elements and forming a core layer in a packaging substrate is specifically described as follows. For illustrative purposes, the explanation will be based on the case of manufacturing a packaging substrate with three cavity sections, but there are no restrictions on the number of cavity sections or the direction of the openings.

[0166] First, as shown in Figure 8(a), defects (or scratches) are formed on the surface of the glass substrate 21. Methods such as mechanical etching and laser irradiation may be used to form these defects (or scratches), and as shown in the figure, defects can be generated by irradiating with lasers (E1, E2, E3) (S1: defect formation step).

[0167] In this process, the degree of the defect, such as its size, width, or depth, can vary depending on the depth of the cavity. A stronger defect can result in a faster etching rate, while weaker defects and a smaller area of ​​formation can lead to a slower etching rate. By adjusting the etching rate, cavities of varying depths can be manufactured. Furthermore, partial masking can be applied to adjust the etching rate if necessary.

[0168] The size of the cavity can be determined in accordance with the elements mounted inside the cavity. In other words, the degree of defects can be controlled according to the height or area of ​​the cavity elements.

[0169] When a defect is formed, an etching step may be performed to form cavities 29a, 29b, and 29c through a physical or chemical etching process, as shown in Figure 8(b). The etching of the cavities can be performed by immersion in an etching solution, allowing for the simultaneous formation of cavities of different depths (S2: cavity formation step).

[0170] As shown in the figure, the depth h1 of the first cavity portion 29a is shallower than the depth h2 of the second cavity portion 29b, and the third cavity portion 29c is a full cavity that penetrates the glass substrate, and its depth h3 may be the same as the height of the glass substrate 21.

[0171] Furthermore, the bottom area or width of the second cavity portion 29b may be larger than that of the first cavity portion 29a, and the area or width of the third cavity portion 29c may be larger than that of the second cavity portion 29b. The degree of defects and the degree of etching can be adjusted according to the number of cavity elements arranged in the cavity portion.

[0172] Core vias (not shown in Figure 8) may be formed in the glass substrate 21 through defect generation and etching processes. The core vias may be formed through the same process as the cavity portion, or through a separate, independent process.

[0173] Although not shown in the diagram, an electrically conductive layer may be formed on the glass surface (including the surface of the glass substrate, the cavity, and the core via) after the etching process. The electrically conductive layer may typically be a metal layer containing copper, but is not limited to this. The electrically conductive layer may be implemented using a dry method, such as sputtering, or a wet method, such as priming.

[0174] After the above process, as shown in Figure 8(c), the glass substrate 21 is attached to an adhesive film 80 such as PI tape (Polyimide Tape), and cavity elements 40a, 40b, and 40c are selected and placed in the cavity portions 29a, 29b, and 29c (S3: Alignment step).

[0175] As shown in the figure, the first cavity element 40a positioned in the first cavity portion 29a is lower in height than the second cavity element 40b or the third cavity element 40c, and the third cavity element 40c can have the greatest height. In other words, the cavity portion is generated based on the height or size of the cavity elements, and the cavity elements are positioned according to that height, so the upper surface of the glass substrate 21 has a substantially flat shape with less waviness than the difference in height of the cavity elements, despite the difference in height of the cavity elements.

[0176] Subsequently, as shown in Figure 8(d), a lamination process (Lamination on top) can be performed on the first surface to form an insulating layer (S4: Insulating layer formation step). When an insulating film such as ABF (Ajinomoto Build-up Film) is laminated over the entire first surface of the glass substrate 21 and cured, the insulator can be embedded even into the internal spaces of the cavity portions 29a, 29b, and 29c. In this embodiment, as shown in Figure 8(e), the upper insulating layer can be formed in a relatively flat form in which undulation is substantially absent.

[0177] For example, the insulating layer may be formed through multiple lamination processes. That is, by performing the process of laminating and curing the insulating film two or more times instead of just once, the warping phenomenon of the glass substrate can be improved and the separation or detachment of the cavity element can be prevented.

[0178] If necessary, the adhesive film may be removed during a subsequent process. For example, the adhesive film may be one whose adhesive strength can be reduced by ultraviolet irradiation or the like. The adhesive film can be easily removed from the glass core by reducing its adhesive strength, either by direct irradiation of the film or by irradiating it with ultraviolet light through the glass core.

[0179] After an insulating layer is formed on the first surface of the glass substrate 21, a lower insulating layer is also formed on the surface of the second surface, as shown in Figure 8(e), and connecting electrodes 42 that are electrically connected to the cavity elements 40a, 40b, and 40c can be formed (S5: connecting electrode formation step). The connecting electrode formation step may be performed after the array step or after the insulating layer formation step.

[0180] Subsequently, an upper layer (not shown) may be placed (or formed) on top of the glass substrate 21, and a lower layer (not shown) may be placed (or formed) on bottom of the glass substrate 21.

[0181] The formation processes of the upper and lower layers are similar to those described with reference to Figures 5(a) to (e), so a redundant explanation will be omitted.

[0182] The packaging substrate and its manufacturing method according to the embodiments described above can compactly mount elements of various shapes and sizes inside a glass substrate, and can mitigate or eliminate undulation that may occur in the core layer.

[0183] The present invention described above has been explained with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person with ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present invention is not limited to the embodiments described above, and various modifications and improvements made by persons skilled in the art using the basic concepts of the embodiments as defined in the attached claims also fall within the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical idea of ​​the attached claims. [Explanation of symbols]

[0184] 100 Semiconductor Equipment 10 Motherboards 20 Packaging substrates 30 Semiconductor element section 32 First Semiconductor Element 34. Second Semiconductor Element 36 Third Semiconductor Device 21,21a Glass substrate 22 core layers 223 Core insulating layer 23 Corevia 24-core distribution layer 241 Core Distribution Pattern 26 Upper layer 28 Cavity section 281 Interior space 282 Cavity Distribution Layer 29a First Cavity Section 29b Second Cavity Section 29c Third Cavity Section 213 Page 1 214 2nd page 25 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connecting layer 271 Top connecting electrode 272 Top connection pattern 40 Cavity elements 42 Connecting electrodes 40a First cavity element 40b Second cavity element 40c Third Cavity Element 60 Cover layer 61a Insulating film 61, 63 Insulating layer

Claims

1. A packaging substrate including a core layer, The aforementioned core layer is A glass substrate including a first surface and a second surface facing each other, It includes at least three or more cavity portions having openings that open in the direction of the first surface or the direction of the second surface, The aforementioned cavity portion is A first cavity portion is recessed and opens in the direction of the first surface, and has a first depth, A second cavity portion is recessed and opens in the direction of the first or second surface, and has a second depth, It includes a third cavity portion having a third depth that penetrates the first surface and the second surface, The second depth is deeper than the first depth. Cavity elements are arranged in the aforementioned cavity portion. The cavity element is, The first cavity elements arranged in the first cavity portion, The second cavity elements arranged in the second cavity portion, It includes a third cavity element arranged in the third cavity portion, A connecting electrode is placed on the first cavity element, A connecting electrode is placed on the second cavity element, A packaging substrate in which one or more connecting electrodes are arranged on the third cavity element in the direction of the first or second plane.

2. The packaging substrate according to claim 1, further comprising an insulating layer embedded inside the cavity and disposed on the surface of the glass substrate where the opening is formed.

3. The packaging substrate according to claim 1, wherein the third cavity element has connecting electrodes arranged in both directions of the first and second surfaces.

4. A method for manufacturing a packaging substrate, A glass substrate is provided, including a first surface and a second surface facing each other, and a defect formation step is made in which a plurality of defects are formed on the first surface or the second surface to different degrees from each other. The step includes etching the glass substrate to form at least three or more cavity portions having different depths, The method for manufacturing the packaging substrate further includes an array step after the cavity formation step, The aforementioned arrangement step is the step of arranging cavity elements in the cavity portion, The cavity portion includes a first cavity portion, a second cavity portion, and a third cavity portion. The first cavity portion is recessed and opens in the direction of the first surface, and has a first depth. The second cavity is recessed and opens in the direction of the first or second surface, and has a second depth that is deeper than the first depth. The third cavity portion penetrates the first and second surfaces and has a third depth. The cavity element includes a first cavity element, a second cavity element, and a third cavity element. The first cavity element is arranged in the first cavity portion, The aforementioned second cavity element is arranged in the aforementioned second cavity portion, The aforementioned third cavity element is arranged in the aforementioned third cavity portion, The method for manufacturing the packaging substrate further includes a step of forming connecting electrodes, A method for manufacturing a packaging substrate, wherein the connection electrode formation step is the step of forming one or more connection electrodes connected to the first cavity element, one or more connection electrodes connected to the second cavity element, and one or more connection electrodes connected to the third cavity element.

5. The method for manufacturing the packaging substrate further includes an insulating layer formation step after the arrangement step, The insulating layer formation step is a step of forming an insulating layer on the surface where the opening of the cavity portion is formed, The method for manufacturing a packaging substrate according to claim 4, wherein the cavity elements arranged in the cavity portion have different heights from each other.

6. The method for manufacturing a packaging substrate according to claim 5, wherein the connection electrode formation step further involves forming connection electrodes on two or more surfaces of the third cavity element.

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