Circuit board and method for manufacturing the same

Abstract

The circuit board of the embodiment includes an insulating layer and a via formed in the insulating layer, wherein the width of the upper surface of the via is greater than the width of the lower surface of the via, and the width of the lower surface of the via is 75% to 95% of the width of the upper surface of the via.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a method for manufacturing the same.

Background Art

[0002] With the acceleration of miniaturization, weight reduction, and integration of electronic components, the line width of circuits is being miniaturized. In particular, as the design rules of semiconductor chips are integrated on the nanometer scale, the circuit line width of package substrates or circuit boards on which semiconductor chips are mounted is being miniaturized to less than a few micrometers.

[0003] In order to increase the circuit integration density of circuit boards, that is, to miniaturize the circuit line width, various manufacturing methods have been proposed. For the purpose of preventing the loss of circuit line width in the etching step for forming a pattern after copper plating, SAP (semi-additive process) method, MSAP (modified semi-additive process), etc. have been proposed.

[0004] After that, in order to realize a finer circuit pattern, an ETS (Embedded Trace Substrate, hereinafter referred to as "ETS") method of embedding a copper foil in an insulating layer has been used in the industry. Since the ETS method manufactures in a form of embedding a copper foil circuit in an insulating layer instead of forming it on the surface of the insulating layer, there is no circuit loss due to etching, which is advantageous for miniaturizing the circuit pitch.

[0005] On the other hand, recently, in order to meet the demand for wireless data traffic, efforts have been made to develop an improved 5G (5th generation) communication system or a pre-5G communication system. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (sub6 giga (6 GHz), 28 giga (28 GHz), 38 giga (38 GHz) or higher frequencies) to achieve a high data transmission rate.

[0006] Furthermore, in order to mitigate path loss in the ultra-high frequency band and increase the transmission distance of radio waves, beamforming, massive MIMO (Multi-Input / Output Multiplexing), and array antennas are being developed for 5G communication systems. Considering that such frequency bands can be composed of hundreds of active antennas with wavelengths, the antenna system becomes relatively large.

[0007] Since such antennas and AP modules are patterned or mounted on a circuit board, low loss on the circuit board is extremely important. This means that the multiple boards that make up the active antenna system—namely the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into a single compact unit.

[0008] On the other hand, such circuit boards include vias. These vias can be formed by creating via holes in an insulating layer and plating a chemical copper plating layer on the surface of the insulating layer and the inner walls of the via holes. In this case, a desmearing process is generally performed after the formation of the via holes to increase the adhesion between the chemical copper plating layer and the insulating layer. The desmearing process roughens the surface of the insulating layer, thereby improving the adhesion between the insulating layer and the chemical copper plating layer.

[0009] However, conventional circuit boards have the problem that the via holes are expanded during the desmear process, making it difficult to form fine vias.

[0010] Therefore, there is a real need for a new method of manufacturing circuit boards that can form fine vias. [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] The embodiment aims to provide a circuit board with a new structure and a method for manufacturing the same.

[0012] Furthermore, the embodiment aims to provide a circuit board containing fine vias and a method for manufacturing the same.

[0013] Furthermore, the embodiment aims to provide a circuit board and a method for manufacturing the same that can minimize the difference between the upper and lower widths of a via.

[0014] Furthermore, the embodiment aims to provide a circuit board and a method for manufacturing the same that can minimize positional deviations in the surface roughness of the insulating layer.

[0015] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by a person with ordinary skill in the art to which the proposed embodiments belong, based on the description below. [Means for solving the problem]

[0016] The circuit board according to the embodiment includes an insulating layer and vias formed in the insulating layer, wherein the width of the upper surface of the via is greater than the width of the lower surface of the via, and the width of the lower surface of the via is 75% to 95% of the width of the upper surface of the via.

[0017] Furthermore, the width of the lower surface of the via is 80% to 90% of the width of the upper surface of the via.

[0018] Furthermore, the surface of the insulating layer has a surface roughness (Ra) in the range of 110 nm to 190 nm.

[0019] Furthermore, the insulating layer has a surface roughness (Ra) deviation of 50 nm or less within a 1 mm x 1 mm area.

[0020] Furthermore, the side surfaces of the vias have a surface roughness (Ra) of 120 nm to 200 nm.

[0021] Also, the insulating layer includes ABF (Ajinomoto Build-up Film).

[0022] On the other hand, the method for manufacturing a circuit board in an embodiment includes preparing an insulating layer in a B-stage state, laminating a metal layer on the upper surface of the insulating layer to impart a surface roughness (Ra) to the upper surface of the insulating layer, removing the metal layer, curing the insulating layer to a C-stage state, forming a via hole in the insulating layer, performing desmear treatment on the upper surface of the insulating layer and the inner wall of the via hole, and forming a via filling the via hole.

[0023] Also, the width of the upper surface of the via is larger than the width of the lower surface of the via, and the width of the lower surface of the via is 75% to 95% of the width of the upper surface of the via.

[0024] Also, the width of the lower surface of the via is 80% to 90% of the width of the upper surface of the via.

[0025] Also, the surface of the insulating layer after desmear treatment has a surface roughness (Ra) in the range of 110 nm to 190 nm.

[0026] Also, the upper surface of the insulating layer after desmear treatment has a deviation in surface roughness (Ra) within a 1 mm * 1 mm area of 50 nm or less.

[0027] Also, the inner wall of the via hole after desmear treatment has a surface roughness (Ra) of 120 nm to 200 nm.

[0028] Also, the width of the upper surface of the via hole after desmear treatment is larger than the width of the upper surface of the via hole before desmear treatment, and the difference between the width of the upper surface of the via hole after desmear treatment and the width of the upper surface of the via hole before desmear treatment is less than 10 μm.

[0029] Also, the insulating layer includes ABF (Ajinomoto Build-up Film).

Advantages of the Invention

[0030] In this embodiment, a uniform surface roughness can be formed on the surface of the insulating layer. Specifically, in this embodiment, a metal layer is laminated on the surface of the insulating layer in the B-stage state, and the surface roughness of the insulating layer is imparted to the surface of the insulating layer in a manner corresponding to the surface roughness formed on the surface of the metal layer. As a result, in this embodiment, the deviation in the surface roughness formed on the surface of the insulating layer can be minimized.

[0031] Furthermore, in the embodiment, fine via holes in the insulating layer and vias that fill them can be formed. Specifically, in the embodiment, via holes are formed in the insulating layer in the C-stage state, thereby desmearing the insulating layer in the C-stage state. As a result, in the embodiment, the size of the via holes before desmearing can be reduced. Moreover, in the embodiment, the difference in size between the via holes before desmearing and the via holes after desmearing can be minimized, thereby enabling the formation of small-diameter via holes. [Brief explanation of the drawing]

[0032] [Figure 1] This diagram shows the manufacturing method of a circuit board according to a comparative example, in order of steps. [Figure 2] Figure 1 is a plan view of the circuit board. [Figure 3] This is a diagram showing a circuit board according to an embodiment. [Figure 4] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 5] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 6] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 7] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 8] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 9] Figure 3 shows the manufacturing process of the circuit board in order of steps. [Figure 10]This figure illustrates the deviation in surface roughness of the insulating layers in the examples and comparative examples. [Figure 11] This is a diagram illustrating the surface roughness of the inner wall of a via hole in a comparative example. [Figure 12] This is a diagram illustrating the surface roughness of the inner wall of the via hole according to the embodiment. [Modes for carrying out the invention]

[0033] The embodiments disclosed herein will be described in detail below with reference to the attached drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are added or used interchangeably to facilitate the preparation of the specification and do not have any mutually distinguishing meaning or role in themselves. Furthermore, in the description of the embodiments disclosed herein, if a specific description of such prior art is deemed to interfere with the gist of the embodiments disclosed herein, such detailed description will be omitted. In addition, the attached drawings are provided to facilitate the understanding of the embodiments disclosed herein, and it should be understood that the attached drawings do not limit the technical idea disclosed herein and include all modifications, equivalents or substitutes that fall within the idea and technical scope of the present invention.

[0034] Terms including ordinal numbers such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. The terms are used solely for the purpose of distinguishing one component from another.

[0035] When it is stated that one component is “linked” or “connected” to another component, it should be understood that it may be directly “linked” or “connected” to the other component, and that other components may exist in between. On the other hand, when it is stated that one component is “directly linked” or “directly connected” to another component, it should be understood that there are no other components in between.

[0036] A singular expression can include multiple expressions unless the context clearly indicates otherwise.

[0037] In this application, terms such as “includes” or “having” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0038] The embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0039] Prior to describing this embodiment, a comparative example that is comparable to this embodiment will be described.

[0040] Figure 1 is a diagram showing the manufacturing method of a circuit board according to a comparative example in order of steps, and Figure 2 is a plan view of the circuit board shown in Figure 1.

[0041] Referring to Figure 1(a), in the comparative example, a first insulating layer 10 is prepared, and a circuit pattern 20 is formed on the upper surface of the first insulating layer 10. Subsequently, in the comparative example, as the circuit pattern 20 is formed, a second insulating layer 30 is laminated on the upper surface of the first insulating layer 10. At this time, the second insulating layer 30 is in the B-stage state. Specifically, the second insulating layer 30 is laminated on the upper surface of the first insulating layer 10 in a semi-cured state.

[0042] Subsequently, referring to Figure 1(b), in the comparative example, a step is performed to form a via hole vh1 in the second insulating layer 30. At this time, the formed via hole vh1 has an upper width and a lower width that are different from each other. That is, the via hole vh1 has an upper surface with a first width vh1 and a lower surface with a second width vh2 that is smaller than the first width vh1. The via hole vh1 as described above is formed by a laser process.

[0043] Subsequently, referring to Figure 1(c), in the comparative example, a desmearing step is performed on the second insulating layer 30. In this case, the desmearing in the comparative example is a wet desmearing step. The desmearing step is a step that imparts a certain level of roughness or higher to the surface of the second insulating layer 30.

[0044] In other words, in the circuit board manufacturing process, once the via holes vh1 are formed, a desmear process is performed to impart a certain level of roughness to the surface of the second insulating layer 30 and the inner wall of the via holes vh1. The desmear process is performed to ensure adhesion between the chemical copper plating layer (not shown) formed on the surface of the second insulating layer 30 and the inner wall of the via holes vh1 and the second insulating layer 30. Specifically, in order to ensure adhesion between the second insulating layer 30 and the chemical copper plating layer, an Ra (average surface roughness) of 110 nm or more must be formed on the second insulating layer 30.

[0045] In the comparative example, when the via hole vh1 is formed during the circuit board manufacturing process, the desmear process is performed to give roughness to the surface of the second insulating layer 30.

[0046] However, in the circuit board of the comparative example, the via holes vh1 are formed in the second insulating layer 30 in the B-stage state, and the desmear process is performed. As a result, in the comparative example, the size of the via holes vh1 changes during the desmear process.

[0047] For example, as shown in Figure 2, the size of the via hole vh2 after the desmear process is completed is larger than the size of the via hole vh1 before the desmear process. That is, the upper surface of the via hole vh2 after the desmear process is completed has a third width w1', and the lower surface has a fourth width w2'. In this case, the third width w1' is larger than the first width w1, and the fourth width w2' is larger than the second width w2. In other words, in the comparative example, by performing the desmear process on the second insulating layer 30 in the B-stage state, the inner wall of the via hole is also etched during the desmear process, resulting in an expansion of the via hole size. As a result, in the comparative example, there is a problem in that it is difficult to miniaturize the size of the via hole and, furthermore, the size of the via.

[0048] For example, the minimum size of the via hole is determined based on the thickness t of the second insulating layer 30. That is, there is a limit to how much the size of the via hole can be reduced depending on the thickness t of the second insulating layer 30. Then, with the minimum size of the via hole determined as described above, the size of the via hole is expanded in the desmear process described above. That is, the difference between the third width w1' of the via hole vh2 after the desmear process in the comparative example and the first width w1 of the via hole vh1 before the desmear process is about 10 μm to 15 μm.

[0049] Therefore, in the comparative example, the expansion of the via hole size as described above makes it difficult to miniaturize the vias, and thus it is difficult to realize small-diameter products.

[0050] Therefore, the embodiment aims to provide a new method for manufacturing a circuit board and a circuit board manufactured thereby, which solves the problem of via hole size expansion in the comparative example described above.

[0051] Figure 3 shows a circuit board according to an embodiment, Figures 4 to 9 show the manufacturing method of the circuit board shown in Figure 3 in sequential order, Figure 10 is a diagram to explain the difference in surface roughness of the insulating layer of the embodiment and comparative example, Figure 11 is a diagram to explain the surface roughness of the inner wall of the via hole according to the comparative example, and Figure 12 is a diagram to explain the surface roughness of the inner wall of the via hole according to the embodiment.

[0052] The following section will provide a detailed explanation of the manufacturing method for circuit boards and the circuit boards manufactured therein, with reference to Figures 3 to 12.

[0053] First, referring to Figure 3, the circuit board in the embodiment includes a first insulating layer 110, a circuit pattern 120, a second insulating layer 130, and vias 140.

[0054] The first insulating layer 110 may have a flat plate structure. The first insulating layer 110 may be a base material for manufacturing the circuit board of the embodiment. The first insulating layer 110 may be a prepreg containing glass fibers. For example, the first insulating layer 110 may be an epoxy resin in which glass fibers and filler are dispersed. As an example, the first insulating layer 110 may be CCL (Copper Clad Laminate).

[0055] The circuit pattern 120 may be arranged on the upper surface of the first insulating layer 110. However, although the drawing shows the circuit pattern 120 being arranged only on the upper surface of the first insulating layer 110, the circuit pattern 120 may be formed not only on the upper surface of the first insulating layer 110 but also on the lower surface.

[0056] The circuit pattern 120 can be made of at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn).

[0057] Furthermore, the circuit pattern 120 may consist of a paste or solder paste containing at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding properties. Preferably, the circuit pattern 120 may consist of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0058] The circuit pattern 120 can be created using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed explanation is omitted here.

[0059] A second insulating layer 130 may be placed on top of the first insulating layer 110. The second insulating layer 130 may be in a fully cured state or an over-cured state. For example, the second insulating layer 130 may contain a resin in a C-stage state.

[0060] The second insulating layer 130 may include materials containing an inorganic filler and an insulating resin, such as a thermosetting resin like epoxy resin, a thermoplastic resin like polyimide, or a resin containing a reinforcing material such as an inorganic filler, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), etc. Preferably, the second insulating layer 130 may include ABF.

[0061] The upper surface of the second insulating layer 130 may be given a rough texture. For example, the Ra of the upper surface of the second insulating layer 130 may be 110 nm to 190 nm. For example, the Ra of the second insulating layer 130 may be 130 nm to 170 nm.

[0062] Furthermore, the positional variation in roughness (maximum Ra to minimum Ra) of the upper surface of the second insulating layer 130 may be 50 nm or less. That is, the upper surface of the second insulating layer 130 in the example can have a more uniform roughness (Ra) compared to the comparative example.

[0063] Via holes (not shown) are formed in the second insulating layer 130, and vias 140 can be formed by filling the formed via holes. In addition, a circuit pattern 150 can be formed on the upper surface of the second insulating layer 130.

[0064] The via 140 is formed by penetrating the second insulating layer 130. The via 140 can electrically connect the circuit pattern 120 located on the upper surface of the first insulating layer 110 and the circuit pattern 150 located on the upper surface of the second insulating layer 130.

[0065] The via 140 may have an upper surface width W1 that differs from the lower surface width W2. Here, the upper surface width W1 of the via 140 may be the diameter of the upper surface of the via 140. For example, the upper surface width W1 of the via 140 may be the width of the upper surface of the via 140 in a first direction. The first direction may be the longitudinal direction or the width direction. The lower surface width W2 of the via 140 may mean the width of the lower surface corresponding to the upper surface of the via 140.

[0066] The width W1 of the upper surface of the via 140 may be greater than the width W2 of the lower surface.

[0067] The width W2 of the lower surface of the via 140 may be 75% to 95% of the width W1 of the upper surface of the via 140. For example, the width W2 of the lower surface of the via 140 may be 77% to 92% of the width W1 of the upper surface of the via 140. For example, the width W2 of the lower surface of the via 140 may be 80% to 90% of the width W1 of the upper surface of the via 140.

[0068] On the other hand, the side surface of the via 140 may have an Ra corresponding to the inner wall of the via hole formed in the second insulating layer 130. For example, the side surface of the via 140 may have an Ra of 120 nm to 200 nm.

[0069] The via 140 and the circuit pattern 150 may be composed of multiple layers. For example, each of the via 140 and the circuit pattern 150 may include a first plating layer (not shown) and a second plating layer (not shown). For example, the first via 140 may include a first plating layer formed on the inner wall of the via hole and a second plating layer disposed on the first plating layer. The circuit pattern 150 may include a first plating layer disposed on the upper surface of the second insulating layer 130 and a second plating layer disposed on the second plating layer. The first plating layer may be a chemical copper plating layer formed by electroless plating. The second plating layer may be an electroplated layer formed by electroplating the first plating layer as a seed layer.

[0070] On the other hand, the structural characteristics of the circuit board described above can manifest through the manufacturing method described below. Below, the structural characteristics of the circuit board described above will be explained in conjunction with the manufacturing method of the circuit board shown in Figures 4 to 9.

[0071] Referring to Figure 4, in this embodiment, a first insulating layer 110 is prepared, and a circuit pattern 120 can be formed on at least one surface of the first insulating layer 110.

[0072] Subsequently, in the embodiment, once the circuit pattern 120 is formed, a step can be performed to laminate a second insulating layer 130 covering the circuit pattern 120 onto the upper surface of the first insulating layer 110. The second insulating layer 130 may, but is not limited to, an ABF (Acoustic Fiber).

[0073] At this time, the second insulating layer 130 may have a first cured state. The first cured state may mean an A-stage state. The A-stage state may mean an uncured state. For example, the A-stage state may mean that the resin is in an uncured state and easily melted state.

[0074] When the second insulating layer 130 in the first cured state is laminated on the first insulating layer 110, a process can be carried out to cure the second insulating layer 130 to a second cured state. The second cured state may mean a B-stage state. The B-stage state may mean a semi-cured state. For example, the B-stage state may mean a soft semi-cured state due to the resin being heated during the curing process.

[0075] On the other hand, the embodiments are not limited thereto. For example, the process of curing the second insulating layer 130 in the A-stage state described above may be omitted by forming the second insulating layer 130 in the B-stage state on the first insulating layer 110.

[0076] When the second insulating layer 130 reaches a B-stage state corresponding to a semi-cured state, in this embodiment, the process of laminating the metal layer 200 onto the upper surface of the second insulating layer 130 can be carried out.

[0077] The metal layer 200 contains copper and may have a surface roughness applied to at least one surface. For example, at least one surface of the metal layer 200 may have an Ra in the range of 60 nm to 100 nm. For example, at least one surface of the second insulating layer 130 may have an Ra in the range of 70 nm to 90 nm.

[0078] For example, the lower surface of the metal layer 200 may have an Ra in the range of 60 nm to 100 nm or 70 nm to 90 nm.

[0079] The metal layer 200 can be pressed against the upper surface of the second insulating layer 130 with its lower surface facing the upper surface of the second insulating layer 130, thereby adhering to the upper surface of the second insulating layer 130. At this time, the second insulating layer 130 is in a B-stage state. As a result, the surface roughness formed on the lower surface of the metal layer 200 can be directly reflected on the upper surface of the second insulating layer 130.

[0080] Therefore, the upper surface of the second insulating layer 130 can have an Ra in the range of 60 nm to 100 nm or 70 nm to 90 nm due to the metal layer 200.

[0081] In this embodiment, as described above, surface roughness is applied to the upper surface of the second insulating layer 130 using the metal layer described above before the desmearing process. This makes it possible to apply a uniform surface roughness to the upper surface of the second insulating layer 130 in accordance with the uniform surface roughness applied to the metal layer 200 in this embodiment.

[0082] Next, referring to Figure 5, in the embodiment, after the metal layer 200 is laminated, the curing process of the second insulating layer 130 can be performed. For example, in the embodiment, once the metal layer 200 imparts surface roughness to the upper surface of the second insulating layer 130, the curing process can be performed so that the second insulating layer 130 reaches a third cured state. The third cured state can mean a C-stage state. For example, the C-stage state can mean a fully cured state or an over-cured state. Thus, in the embodiment, the second insulating layer 130 may be fully cured or over-cured while having been given surface roughness by the metal layer 200.

[0083] Next, referring to Figure 6, in the embodiment, once the second insulating layer 130 reaches the C-stage state, a step can be taken to remove the metal layer 200 located on the upper surface of the second insulating layer 130. The step of removing the metal layer 200 may be carried out using an etching chemical that can remove only the metallic substance corresponding to the metal layer 200 without damaging the second insulating layer 130.

[0084] As described above, when the metal layer 200 is removed, the upper surface of the second insulating layer 130 may be exposed. At this time, the upper surface of the second insulating layer 130 may have an Ra in the range of 60 nm to 100 nm or 70 nm to 90 nm, as described above.

[0085] On the other hand, in the embodiment, the order of the metal layer removal step and the step of curing the second insulating layer 130 to the C-stage state may be reversed. For example, in the embodiment, after the metal layer 200 has been laminated, if Ra corresponding to the metal layer 200 is applied to the upper surface of the second insulating layer 130, the step of removing the metal layer 200 can be performed preferentially. Then, once the metal layer 200 has been removed, in the embodiment, the second insulating layer 130 can be cured to the C-stage state.

[0086] Next, referring to Figure 7, in the embodiment, a step can be performed to form via holes vh1 in the second insulating layer 130 in the C-stage state. The via holes vh1 can be formed by any of the following processing methods: mechanical, laser, or chemical processing. When the via holes vh1 are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; and when they are formed by chemical processing, chemicals containing aminosilanes, ketones, etc. can be used to open the second insulating layer 130.

[0087] On the other hand, the laser processing method is a cutting method that concentrates optical energy on the surface to melt and evaporate a portion of the material, thereby taking on a desired shape. It can easily process complex shapes created by computer programs and can also process composite materials that are difficult to cut by other methods.

[0088] Furthermore, the aforementioned laser processing has the advantage of being able to cut materials down to a minimum diameter of 0.005 mm and having a wide range of thicknesses that can be processed.

[0089] It is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser as the laser processing drill. A YAG laser can process both the copper foil layer and the insulating layer, while a CO2 laser can process only the insulating layer.

[0090] On the other hand, via holes vh1 formed in the second insulating layer 130 can expose the circuit pattern 120 located on the upper surface of the first insulating layer 110. For example, the via holes vh1 may be formed on the second insulating layer 130 in a region that overlaps perpendicularly with the circuit pattern 120, thereby exposing the upper surface of the circuit pattern 120. In this case, the via holes vh1 may have a first size. Furthermore, the inner wall of the via holes vh1 may have a first surface roughness. This will be explained in detail below.

[0091] Next, referring to Figure 8, in the embodiment, a process of desmearing the upper surface of the second insulating layer 130 and the inner wall of the via hole vh1 can be performed. At this time, the second insulating layer 130 in the embodiment is in a C-stage state. This makes it possible to minimize the change in the surface roughness of the upper surface of the second insulating layer 130 and the surface roughness of the inner wall of the via hole vh1 during the desmearing process. As a result, in the embodiment, the degree of expansion of the via hole vh1 can be minimized by the desmearing process. For example, in the embodiment, the expansion of the via hole vh1 due to the desmearing process can be minimized compared to the comparative example. As a result, miniaturization of the via hole vh1 is possible in the embodiment.

[0092] For example, in the embodiment, the desmearing process can surface-treat the upper surface of the second insulating layer 130 and the inner wall of the via hole vh1. As a result, the via hole VH2 after desmearing will have a different surface roughness and size than the via hole vh1 before desmearing. Furthermore, the surface roughness of the upper surface of the second insulating layer 130 before desmearing and the surface roughness after desmearing may differ from each other. This will be explained in more detail below.

[0093] Referring to Figure 9, in this embodiment, the interior of the via hole VH2 after desmearing can be filled with a metallic substance to form a via 140, and a circuit pattern 150 can be formed that protrudes above the upper surface of the second insulating layer 130. The process of forming the via 140 and the circuit pattern 150 may include, as described above, the steps of forming a chemical copper plating layer through electroless plating, forming an electroplated layer by electroplating using the chemical copper plating layer as a seed layer, and etching the chemical copper plating layer.

[0094] As described above, in the embodiment, the metal layer 200 is used to impart surface roughness to the upper surface of the second insulating layer 130, thereby ensuring uniformity of the surface roughness of the second insulating layer 130. Furthermore, in the embodiment, the size accuracy of the via holes can be improved by forming via holes in the second insulating layer 130 in the C-stage state. In addition, in the embodiment, the expansion of the formed via holes can be minimized by performing a desmear process on the second insulating layer 130 in the C-stage state.

[0095] Below, we will compare and explain the circuit board formed by the manufacturing process described above with the circuit board of the comparative example. <Comparison of beer hall sizes>

[0096] In the comparative example, via holes are formed in the B-stage state, followed by a desmearing process. In contrast, in the embodiment, surface roughness is applied to the insulating layer before forming via holes in the B-stage state, and then the desmearing process is performed after the via holes are formed in the C-stage state. Therefore, in the embodiment, the size of the via holes initially formed can be reduced compared to the comparative example, and furthermore, the size expansion of the via holes after desmearing can be minimized.

[0097] Table 1 shows the size of the via holes after desmearing, depending on the thickness of the insulating layer in the comparative example.

[0098] [Table 1]

[0099] Referring to Table 1, in the comparative example, when the thickness of the insulating layer was 12.5 μm, the width of the top surface of the via hole was 30 μm. Furthermore, in the comparative example, the width of the top surface of the via hole increased as the thickness of the insulating layer increased. As a result, in the comparative example, the minimum size of a via hole that could be formed, based on the width of the top surface of the via hole, was approximately 30 μm.

[0100] Table 2 shows the size of the via holes after desmearing, depending on the thickness of the insulating layer in the examples.

[0101] [Table 2]

[0102] As shown in Table 2 above, in the example, when the thickness of the insulating layer was 12.5 μm, the width of the top surface of the via hole was 20 μm. This confirmed that, in the comparative example, the minimum size of a via hole that can be formed is 20 μm, based on the width of the top surface of the via hole.

[0103] The difference in via hole size between the above-described examples and comparative examples is due to whether the via hole formation and desmearing process are performed when the insulating layer is in the B-stage or when it is in the C-stage. <Comparison of beer hall expansion accuracy before and after Desmia>

[0104] In the comparative example, the desmearing process was performed in the B-stage state of the insulating layer, resulting in a large difference in the size of the via holes before and after desmearing. The size difference between the via holes before and after desmearing in the comparative example is shown in Table 3 below.

[0105] [Table 3]

[0106] As shown in Table 3 above, in the comparative example, it was confirmed that the size after desmearing was approximately 10 μm larger than before desmearing, using the top surface of the via hole as the reference point. It was confirmed that the resulting width ratio was approximately 70% of the top surface width of the via hole.

[0107] The size difference between the beer hall before desmearing and the beer hall after desmearing in the example is shown in Table 4 below.

[0108] [Table 4]

[0109] As shown in Table 4 above, in the example, it was confirmed that the size after desmearing was approximately 5 μm larger than before desmearing, relative to the top surface of the via hole, which was confirmed to be 50% of the level of the comparative example. As a result, it was confirmed that the ratio of the bottom width to the top width of the via hole in the example was 80% or more. Specifically, in the comparative example, the width of the bottom surface of the via hole after desmearing was 70% or less of the width of the top surface. Furthermore, in the via hole of the comparative example described above, transmission loss may occur in the via due to the difference between the top width and the bottom width.

[0110] In contrast, in the embodiment, the width of the lower surface of the via hole after desmearing was 75% to 95% of the width of the upper surface. This minimized the difference between the upper and lower widths of the via hole in the embodiment, thereby minimizing the transmission loss through the via. Specifically, in the embodiment, it was confirmed that the difference between the upper surface width before desmearing and the upper surface width after desmearing was less than 10 μm, based on the upper surface width of the via hole. For example, it was confirmed that the difference between the upper surface width before desmearing and the upper surface width after desmearing in the embodiment was 8 μm or less. For example, it was confirmed that the difference between the upper surface width before desmearing and the upper surface width after desmearing was 5 μm or less. <Comparison of surface roughness of insulating layers>

[0111] In the comparative example, a desmear process is performed on the insulating layer in the B-stage state to form surface roughness. In contrast, in the embodiment, a metal layer is laminated on the insulating layer in the B-stage state to form a surface treatment, and then a desmear process is performed on the insulating layer in the C-stage state to form the final surface roughness.

[0112] The changes in the surface roughness of the insulating layer in the comparative example are shown in Table 5 below.

[0113] [Table 5]

[0114] As shown in Table 5 above, in the comparative example, the surface roughness (Ra) of the insulating layer before desmearing was 20 nm, and the final surface roughness (Ra) after desmearing was confirmed to be 250 μm. At this time, as shown in Figure 10(a), in the comparative example, it was confirmed that the roughness deviation from position to position on the surface of the insulating layer became significant when surface roughness was formed in the B-stage insulating layer through desmearing. For example, the roughness deviation from position to position on the surface of the insulating layer in the comparative example was confirmed to be about 100 nm based on Ra.

[0115] The changes in the surface roughness of the insulating layer in the examples are shown in Table 6 below.

[0116] [Table 6]

[0117] As shown in Table 6 above, in the example, it was confirmed that the surface roughness (Ra) of the insulating layer before metal layer lamination was 20 nm, the surface roughness (Ra) after metal layer lamination was 100 nm, and the final surface roughness (Ra) after desmearing was 150 μm. In other words, it was confirmed that the deviation of surface roughness at each location in the insulating layer in the example was 50 nm or less. For example, as shown in Figure 10(b), in the example, it was confirmed that by performing desmearing on the insulating layer in the C-stage state, the deviation of surface roughness at each location in the insulating layer can be reliably reduced compared to the comparative example. For example, it was confirmed that the deviation of surface roughness at each location in the insulating layer of the example was about 40 nm based on Ra, which was confirmed to be 40% of the level of the comparative example. <Comparison of surface roughness of interior walls in beer halls>

[0118] The changes in the surface roughness of the inner walls of the via holes formed in the insulating layer in the comparative example are shown in Table 7 below.

[0119] [Table 7]

[0120] As shown in Table 7 and Figure 11 above, in the comparative example, the surface roughness (Ra) of the via hole before desmearing was 480 nm, and the final surface roughness (Ra) after desmearing was 300 nm. The roughness of the inner wall of the via hole in the comparative example described above was at the 300 nm level, which increased the skin effect through the via and caused signal loss.

[0121] The changes in the surface roughness of the insulating layer in the examples are shown in Table 8 below.

[0122] [Table 8]

[0123] As shown in Table 8 and Figure 12 above, in the comparative example, the surface roughness (Ra) of the via hole before desmearing was 300 nm, and the final surface roughness (Ra) after desmearing was 170 nm. The roughness of the inner wall of the via hole in the example described above is at a lower level of 170 nm than in the comparative example, which minimizes signal loss through the via. For example, the final roughness of the inner wall of the via hole in the example can have an Ra of 120 nm to 200 nm. The example can form a uniform surface roughness on the surface of the insulating layer. Specifically, in the example, a metal layer is laminated on the surface of the insulating layer in the B-stage state, and the surface roughness of the insulating layer is imparted to the surface of the insulating layer to correspond to the surface roughness formed on the surface of the metal layer. As a result, in the example, the deviation of the surface roughness formed on the surface of the insulating layer can be minimized.

[0124] Furthermore, the embodiment can form fine via holes in the insulating layer and vias that fill them. Specifically, in the embodiment, via holes are formed in the insulating layer in the C-stage state, thereby desmearing the insulating layer in the C-stage state. As a result, in the embodiment, the size of the via holes before desmearing can be reduced. Moreover, in the embodiment, the difference in size between the via holes before desmearing and the via holes after desmearing can be minimized, thereby enabling the formation of small-diameter via holes.

[0125] The features, structures, and effects described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to just one embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0126] Furthermore, although the above description has focused on embodiments, these are merely illustrative examples and do not limit the embodiments. Anyone with ordinary skill in the art to which this invention belongs will understand that a variety of modifications and applications not exemplified above are possible, within the bounds of not departing from the essential characteristics of these embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. Such differences in modifications and applications should be interpreted as being included within the scope of the invention as defined in the attached claims.

Claims

1. Prepare a semi-cured insulating layer, A metal layer is laminated on the upper surface of the insulating layer to impart a surface roughness (Ra) to the upper surface of the insulating layer. Remove the aforementioned metal layer, After the metal layer is removed, the insulating layer is completely cured. Via holes are formed that penetrate the upper and lower surfaces of the insulating layer. The upper surface of the insulating layer and the inner wall of the via hole are desmeared. This includes forming via electrodes that fill the via holes, The surface roughness (Ra) of the upper surface of the insulating layer after the desmear treatment satisfies the range of 110 nm to 190 nm. A method for manufacturing a circuit board, wherein the difference between the maximum and minimum surface roughness (Ra) applied to the upper surface of the insulating layer after the desmear treatment is 50 nm or less.

2. The surface roughness (Ra) of the inner wall of the via hole after the desmear treatment satisfies the range of 120 nm to 200 nm. The method for manufacturing a circuit board according to claim 1, wherein the surface roughness (Ra) of the side surface of the via electrode is in the range of 120 nm to 200 nm.

3. The width of the upper surface of the via electrode is greater than the width of the lower surface of the via electrode. The method for manufacturing a circuit board according to claim 1, wherein the width of the lower surface of the via electrode is 75% to 95% of the width of the upper surface of the via electrode.

4. The method for manufacturing a circuit board according to claim 1, wherein the ratio of the thickness of the insulating layer in the vertical direction to the upper width of the via hole is in the range of 63% to 83%.

5. The method for manufacturing a circuit board according to claim 4, wherein the vertical thickness of the insulating layer is in the range of 12.5 μm to 37.5 μm.

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