Drivers, electro-optical devices, and electronic equipment

Abstract

To provide a driver and the like that can change a range of a voltage driving pixels without changing the number of gradations.SOLUTION: A driver 100 includes a first driving circuit 60 and a second driving circuit 70. The second driving circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, and a second feedback capacitor Cfb. One end of the output capacitor CQ is connected with an output node of the operational amplifier 71, and the other end is connected with a signal supply line. One end of the first feedback capacitor Cfa is connected with an inverted input node of the operational amplifier 71, and the other end is connected with the signal supply line. One end of the second feedback capacitor Cfb is connected with the inverted input node of the operational amplifier 71, and the other end is connected with a predetermined potential node. At least one of the first feedback capacitor Cfa and the second feedback capacitor Cfb is a capacitor with a variable capacitance value.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like.

Background Art

[0002] Patent Document 1 discloses a driver that includes a capacitance driving circuit and an amplifier circuit and drives an electro-optical panel. After the capacitance driving for driving the electro-optical panel by the capacitance driving circuit is started, the amplifier circuit performs voltage driving to output a data voltage corresponding to gradation data to a data voltage output terminal. Thereby, since the voltage drop of the data line after the source line switch of the electro-optical panel changes from off to on is compensated by the amplifier circuit, the accuracy degradation of the data voltage in capacitance driving is suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In driving a liquid crystal panel, the range of the driving voltage varies depending on the color of light incident on the liquid crystal panel or the liquid crystal material used for the liquid crystal panel. In Patent Document 1 above, a voltage follower circuit is used as the amplifier circuit and the gain of the amplifier circuit is fixed, so there is a problem that it is difficult to change the range of the driving voltage. For example, in Patent Document 1 above, it is necessary to remake the driving circuit by changing the range of the driving voltage by changing the gradation range, that is, the number of gradations, or by changing the power supply voltage or the gain or the like without changing the number of gradations.

Means for Solving the Problems

[0005] One aspect of the present disclosure includes a first drive circuit that supplies data signals to a signal supply line of an electro-optical panel based on grayscale data; an operational amplifier; an output capacitor, one end of which is electrically connected to the output node of the operational amplifier and the other end of which is electrically connected to the signal supply line; a first feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier and the other end of which is electrically connected to the signal supply line; and a second feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier and the other end of which is electrically connected to a predetermined potential node; and a second drive circuit electrically connected to the signal supply line, wherein at least one of the first feedback capacitor and the second feedback capacitor relates to a driver which is a capacitor with a variable capacitance value.

[0006] Other aspects of this disclosure relate to an electro-optical apparatus including the driver and the electro-optical panel.

[0007] Another aspect of this disclosure is an electronic device characterized by including the above-described driver. [Brief explanation of the drawing]

[0008] [Figure 1] An example of an electro-optical device configuration. [Figure 2] First detailed configuration example of the driver. [Figure 3] A first detailed configuration example of the first drive circuit. [Figure 4] A first detailed configuration example of the second drive circuit. [Figure 5] Detailed configuration example of a variable capacitance capacitor. [Figure 6] A diagram showing the relationship between the color of light incident on a liquid crystal display panel and the transmittance characteristics of the pixels. [Figure 7] A diagram showing the relationship between the grayscale data and voltage input to the first drive circuit. [Figure 8] This diagram shows the relationship between the grayscale data and voltage input to the second drive circuit. [Figure 9] The first waveform example illustrates the operation of the first and second drive circuits. [Figure 10] The second waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 11] The third waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 12] The second detailed configuration example of the driver. [Figure 13] The figure for explaining the relationship between the gradation data, the setting data, and the data voltage. [Figure 14] The second detailed configuration example of the first drive circuit. [Figure 15] The fourth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 16] The second detailed configuration example of the second drive circuit. [Figure 17] The relationship between the gradation data and the D / A conversion voltage. [Figure 18] The fifth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 19] The sixth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 20] The third detailed configuration example of the second drive circuit. [Figure 21] The fourth detailed configuration example of the second drive circuit. [Figure 22] The configuration example of the electronic device.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in these embodiments are essential constituent elements.

[0010] 1. Electro-optical device FIG. 1 shows a configuration example of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. Hereinafter, the electro-optical device 400 using the phase development drive method will be described as an example, but the present invention is not limited thereto. For example, the electro-optical device 400 may be a demultiplex drive method.

[0011] The driver 100 drives the electro-optic panel 200 by outputting a data signal to the signal supply line of the electro-optic panel 200. The voltage written to one pixel at a time is called the data voltage. When multiple pixels are driven in a time series, the data voltage for each pixel is output to the signal supply line as a time series signal, and this signal to the signal supply line is called the data signal.

[0012] The scan line driving circuit for driving the scan lines of the electro-optic panel 200 may be included in the driver 100 or provided outside the driver 100. The driver 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. The driver 100 includes a control circuit 40 and first to k data line driving circuits DD1 to DDk. k is an integer of 2 or more. In the following explanation, the case where k=8 will be used as an example.

[0013] The control circuit 40 outputs corresponding grayscale data to each of the data line drive circuits DD1 to DD8. The control circuit 40 also outputs a control signal ENBX to the electro-optic panel 200 to control the data line switches.

[0014] The data line drive circuits DD1 to DD8 convert grayscale data into data voltages and output these data voltages as output voltages VQ1 to VQ8 to the signal supply lines SPL1 to SPL8 of the electro-optic panel 200. The output voltages VQ1 to VQ8 change according to the time-series grayscale data, and the signals produced by these changing output voltages VQ1 to VQ8 correspond to the data signals described above.

[0015] The electro-optical panel 200 includes the first to eighth signal supply lines SPL1 to SPL8, the first to 1280 data line switches SWEP1 to SWEP1280, and the first to 1280 data lines DL1 to DL1280. The number of data lines may be k × t, where t is an integer greater than or equal to 2. Here, WXGA is used as an example, and t = 160.

[0016] One end of data line switches SWEP((j-1)×k+1) to SWEP(j×k) among data line switches SWEP1 to SWEP1280 is connected to signal supply lines SPL1 to SPL8. j is an integer less than or equal to 160. For example, if j=1, it is data line switches SWEP1 to SWEP8.

[0017] Each of the data line switches SWEP1 to SWEP1280 is composed of, for example, a TFT and is controlled based on the control signal ENBX. TFT stands for Thin Film Transistor. For example, the electro-optic panel 200 includes a switch control circuit (not shown), which controls the data line switches SWEP1 to SWEP1280 to turn on or off based on the control signal ENBX.

[0018] The data line drive circuits DD1 to DD8 perform 160 drives during the horizontal scanning period, and in the j-th drive, data line switches SWEP((j-1)×k+1) to SWEP(j×k) are turned on, while the other data line switches are turned off. As a result, data lines DL((j-1)×k+1) to DL(j×k) are driven in the j-th drive. Focusing on data line drive circuit DD1, during the horizontal scanning period, data line switches SWEP1, SWEP2, ..., SWEP1273 are turned on sequentially, and data line drive circuit DD1 drives data lines DL1, DL2, ..., DL1273 sequentially.

[0019] 2. First Embodiment Figure 2 shows a first detailed configuration example of the driver. The driver 100 includes a data line drive circuit 110 and a control circuit 40. The data line drive circuit 110 corresponds to any one of the data line drive circuits DD1 to DD8 in Figure 1.

[0020] The data line drive circuit 110 includes a first drive circuit 60, a second drive circuit 70, a variable capacitance circuit 30, and a detection circuit 50. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0021] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is an image interface circuit such as an LVDS system, a parallel RGB system, or a DisplayPort system. LVDS stands for Low Voltage Differential Signaling.

[0022] The processing circuit 42 determines the setting data CSW[4:0] for the capacitance value of the variable capacitance circuit 30 during initialization processing when power is applied to the driver 100, and stores the setting data CSW[4:0] in the register circuit 48. During normal operation when driving the electro-optical panel 200, the processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 using the setting data CSW[4:0] read from the register circuit 48. The processing circuit 42 also outputs the gradation data DTH[10:0] to the first drive circuit 60 and the gradation data DTL[10:0] to the second drive circuit 70 based on the gradation data GD[9:0]. The processing circuit 42 also outputs the polarity inversion signal FR to the second drive circuit 70. Depending on the configuration of the second drive circuit 70, the input of the polarity inversion signal FR to the second drive circuit 70 may be omitted.

[0023] Output node NVQ is connected to the data voltage output terminal TVQ, and the voltage of this output node NVQ is defined as the output voltage VQ. The load capacitance of the data voltage output terminal TVQ is defined as the electro-optic panel side capacitance CP.

[0024] The first drive circuit 60 supplies charge corresponding to the grayscale data DTH[10:0] to the output node NVQ by charge redistribution using a capacitor. This charge is then distributed to the variable capacitance circuit 30 and the electro-optic panel side capacitance CP, so that the output voltage VQ becomes the data voltage corresponding to the grayscale data DTH[10:0]. The first drive circuit 60 is composed of circuit elements with a high voltage resistance process that can drive the electro-optic panel 200. For example, if the electro-optic panel 200 is a high-temperature polysilicon type liquid crystal panel, the power supply voltage of the first drive circuit 60 is about 15V to 20V, and the first drive circuit 60 is composed of circuit elements with a voltage resistance higher than that power supply voltage.

[0025] If there is an error in the charge output by the first drive circuit 60, or if charge conservation at the output node NVQ is slightly not maintained, an error will occur between the output voltage VQ due to the charge output by the first drive circuit 60 and the target voltage corresponding to the grayscale data DTH[10:0]. The second drive circuit 70 corrects the output voltage VQ to the target voltage using feedback control with an operational amplifier. At this time, because the error between the output voltage VQ and the target voltage is small, the second drive circuit 70 only needs to output a small amount of charge. Taking advantage of this, the operational amplifier is constructed with circuit elements from a low-voltage process while DC blocking is performed between the operational amplifier and the output node NVQ with a capacitor. As an example, the voltage withstand capability of a low-voltage process is about 1 / 3 to 1 / 10 of the voltage withstand capability of a high-voltage process. The second drive circuit 70 operates at a power supply voltage lower than the voltage withstand capability of the low-voltage process.

[0026] This document describes a method for determining the capacitance value of the variable capacitance circuit 30 and an example configuration of the variable capacitance circuit 30 and the detection circuit 50.

[0027] The detection circuit 50 compares a given detection voltage with the output voltage VQ and outputs the result as a detection signal DET. The detection circuit 50 is, for example, a comparator.

[0028] The processing circuit 42 outputs gradation data DTH[10:0] corresponding to a given data voltage to the capacitor drive circuit 20. At this time, the given detection voltage is set to the same voltage as the given data voltage, which is the expected value of the output voltage VQ. The processing circuit 42 sequentially changes the capacitance value of the variable capacitance circuit 30 by sequentially changing the value of the setting data CSW[4:0]. The processing circuit 42 determines the capacitance value of the variable capacitance circuit 30 based on the detection signal DET at each capacitance value. That is, the processing circuit 42 determines the capacitance value at which the output voltage VQ becomes the given detection voltage based on the detection signal DET, and stores the setting data CSW[4:0] of that capacitance value in the register circuit 48.

[0029] The variable capacitance circuit 30 includes first to fifth adjustment capacitors and first to fifth adjustment switches. One end of the first adjustment switch is connected to the output node NVQ, and the other end is connected to one end of the first adjustment capacitor. The other end of the first adjustment capacitor is connected to the ground node. The same applies to the second to fifth adjustment capacitors and the second to fifth adjustment switches. The capacitance values ​​of the first to fifth adjustment capacitors are binary weighted. The first adjustment switch is controlled on or off by CSW[0]. Similarly, the second to fifth adjustment switches are controlled on or off by CSW[1] to CSW[4].

[0030] The details of the first drive circuit 60, the second drive circuit 70, the variable capacitance circuit 30, and the detection circuit 50 will be described below.

[0031] Figure 3 shows a first detailed configuration example of the first drive circuit. In the following, the same sign used to represent the capacitance value of a capacitor will be used as the sign of the capacitor itself. For example, the capacitance value of capacitor C1 will be denoted as C1.

[0032] The capacitor circuit 10 includes the first to the nth capacitors C1 to Cn. The capacitor drive circuit 20 includes the first to the nth drive circuits DR1 to DRn. The following example describes the case where n=11, but n can be any integer greater than or equal to 2. n should be set to the same number of bits as the grayscale data DTH[10:0].

[0033] One end of capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor drive node NDRi. i is an integer between 1 and n=11. Capacitors C1 to C10 have binary weighted capacitance values. Specifically, the capacitance value of capacitor Ci is 2 (i-1) ×C1

[0034] The processing circuit 42 outputs the i-th bit DTH[i-1] of the grayscale data DTH[10:0] to the input node of the drive circuit DRi. The drive circuit DRi outputs a first voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the first logic level, and outputs a second voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is the low-potential side power supply voltage VSH, and the second voltage level is the high-potential side power supply voltage VDH. The drive circuit DRi is composed of high-voltage process transistors and operates with power supply voltages VDH and VSH. The drive circuit DRi is composed of, for example, a level shifter that level shifts the input logic level to the output voltage level of the drive circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0035] The drive circuits DR1 to DR11 drive capacitors C1 to C11, causing charge redistribution between capacitors C1 to C11, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As a result, a data voltage is output to the output node NVQ.

[0036] The electro-optical panel capacitance CP is the sum of the capacitances visible from the data voltage output terminal TVQ. For example, the electro-optical panel capacitance CP is the sum of the parasitic capacitance of the printed circuit board, which is the board capacitance CP1, and the parasitic capacitance within the electro-optical panel 200, which is the panel capacitance CP2. The printed circuit board is the board on which the driver 100 is mounted and which is connected to the electro-optical panel 200.

[0037] Assume that the sum of the capacitance values ​​of capacitors C1 to C11 is Ctot = C1 + C2 + ... + C11, and the capacitance value of the variable capacitance circuit 30 is CF. For example, CF is set so that Ctot / (CF+CP)=2. In this case, at the maximum gradation value of DTH[10:0] 2047, VQ = 15V × {Ctot / (Ctot+CF+CP)} + 2.5V = 10V + 2.5V = 12.5V. At the minimum gradation value of DTH[10:0] 0, VQ = 0V × {Ctot / (Ctot+CF+CP)} + 2.5V = 0V + 2.5V = 2.5V. The detailed relationship between gradation value and voltage will be described later in Figure 7.

[0038] Figure 4 shows a first detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, a D / A conversion circuit 72, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, and an initialization switch SWR.

[0039] The D / A conversion circuit 72 performs D / A conversion on the grayscale data DTL[10:0] to obtain a D / A conversion voltage DAQ, and outputs this D / A conversion voltage DAQ to the non-inverting input node NAP of the operational amplifier 71. The correspondence between the grayscale data DTL[10:0] and the D / A conversion voltage DAQ will be described later in Figure 8. The D / A conversion circuit 72 includes, for example, a ladder resistor that divides the voltage between the power supply voltage VDL and VSL into multiple voltages, and a switch circuit that selects a voltage corresponding to the grayscale data DTL[10:0] from these multiple voltages.

[0040] The operational amplifier 71 is composed of low-voltage process transistors and operates at power supply voltages VDL and VSL.

[0041] One end of output capacitor CQ is connected to the output node NAMQ of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of first feedback capacitor Cfa is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of second feedback capacitor Cfb is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the node of the low-potential side power supply voltage VSL. The other end of second feedback capacitor Cfb only needs to be connected to a predetermined potential node to which a constant potential is supplied.

[0042] The first feedback capacitor Cfa is a variable capacitance capacitor whose capacitance value is variable. The second feedback capacitor Cfb is a variable capacitance capacitor whose capacitance value is variable. The capacitance value of the first feedback capacitor Cfa is set by the setting data SCfa from the processing circuit 42, and the capacitance value of the second feedback capacitor Cfb is set by the setting data SCfb from the processing circuit 42. For example, the display controller 300 writes the setting data SCfa and SCfb to the register circuit 48 via the interface circuit 44, and the processing circuit 42 outputs the setting data SCfa and SCfb stored in the register circuit 48 to the second drive circuit 70. Note that one of the first feedback capacitor Cfa and the second feedback capacitor Cfb may be a variable capacitance capacitor and the other may be a fixed capacitance capacitor.

[0043] One end of the initialization switch SWR is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NVREF, which is supplied with a reference voltage VREF. The reference voltage VREF is a voltage higher than VSL and lower than VDL. Here, VREF = VCL = 0.9V. The reference voltage VREF is supplied to node NVREF from, for example, a voltage generation circuit (not shown) included in the driver 100. The initialization switch SWR is an analog switch, for example, an N-type transistor, a P-type transistor, or a transfer gate combining them.

[0044] The output voltage VQ is set to a range of 10V, and the D / A conversion voltage DAQ is set to a range of 1V. In this case, the voltage range should be divided in a 9:1 ratio by the first feedback capacitor Cfa and the second feedback capacitor Cfb, so the capacitance values ​​of the first feedback capacitor Cfa and the second feedback capacitor Cfb are set so that Cfb / Cfa = 9. Note that the ratio of Cfb to Cfa is not limited to 9, but is set appropriately according to the ratio of the voltage ranges. Details of this point will be described later in Figures 7 and 8.

[0045] The capacitance value of the output capacitor CQ can be arbitrary, as long as it is set so that the output voltage AMQ of the operational amplifier 71 is within the range of VSL to VDL. For example, the capacitance value of the output capacitor CQ is set to approximately 1 to 10 times the sum of the capacitor circuit 10, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As an example, if the capacitance value of the output capacitor CQ is 4 times the above sum, in order to compensate for an error of 0.1V in the output voltage VQ, the output voltage AMQ of the operational amplifier 71 only needs to change by 0.1V × (5 / 4) = 0.125V.

[0046] Figure 5 shows a detailed configuration example of a variable capacitance capacitor. Figure 5 shows a detailed configuration example of the first feedback capacitor Cfa, but the second feedback capacitor Cfb has a similar configuration. However, the number of capacitors included in each feedback capacitor may differ.

[0047] The first feedback capacitor Cfa includes capacitors Ca1 to Ca5 and switches SWa1 to SWa4. One end of switch SWa1 is connected to the output node NVQ, and the other end is connected to one end of capacitor Ca1. The other end of capacitor Ca1 is connected to the inverting input node NAN of the operational amplifier 71. Similarly, one end of switches SWa2 to SWa4 is connected to the output node NVQ, and the other end is connected to one end of capacitors Ca2 to Ca4. The other ends of capacitors Ca2 to Ca4 are connected to the inverting input node NAN of the operational amplifier 71. Note that switches SWa1 to SWa4 may be located closer to the inverting input node NAN of the operational amplifier 71 than capacitors Ca1 to Ca4. One end of capacitor Ca5 is connected to the output node NVQ, and the other end is connected to the inverting input node NAN of the operational amplifier 71.

[0048] The capacitance values ​​of capacitors Ca1 to Ca4 are binary weighted. That is, Ca4 = 8 × Ca1, Ca3 = 4 × Ca1, and Ca2 = 2 × Ca1. Switch SWa1 is controlled to be on or off by bit SCfa[0] of the setting data SCfa[3:0]. Similarly, switches SWa2 to SWa4 are controlled to be on or off by bits SCfa[1] to SCfa[3] of the setting data SCfa[3:0].

[0049] Figure 6 shows the relationship between the color of light incident on a liquid crystal display panel and the transmittance characteristics of the pixels. The horizontal axis represents the voltage applied to the pixels, and the vertical axis represents the transmittance of the pixels at each applied voltage.

[0050] As shown in Figure 6, the transmittance characteristics of pixels differ depending on the color of light incident on the liquid crystal display panel. Specifically, the longer the wavelength of light, the more the peak of the transmittance characteristic shifts to the higher voltage side. Also, the slope of the characteristic before reaching the peak of the transmittance characteristic differs depending on the color of light. Therefore, the applied voltage at which the same transmittance is achieved differs depending on the color of light. For this reason, it is necessary to set the appropriate applied voltage range according to the color of light. In this embodiment, this corresponds to setting the voltage range of the output voltage VQ according to the color of light. For example, in projectors and the like, there are models in which a light source and panel are provided for each of RGB, and in such models, the applied voltage range is set according to which color light source the panel corresponds to.

[0051] Furthermore, the applied voltage range for each color may be adjusted not only by the color of the light, but also by the type of liquid crystal material, image gamma correction, image white balance correction, or image color adjustment. For example, if the user can adjust the color, the applied voltage range for each color will be set according to that adjustment.

[0052] As described above, it is desirable to be able to arbitrarily set the voltage range of the output voltage VQ. On the other hand, changing the number of gradations or the voltage step of one gradation may degrade image quality, so it is desirable not to change them.

[0053] In this embodiment, in the configuration example shown in Figure 4, the feedback gain Cfa / (Cfa+Cfb) from the output node NVQ to the inverting input node NAN of the operational amplifier 71 is adjusted. At this time, the number of gradations in the gradation data DTH[10:0] input to the first drive circuit 60 changes, but the number of gradations in the gradation data DTL[10:0] input to the D / A conversion circuit 72 and the output voltage range of the D / A conversion circuit 72 do not change. This allows the voltage range of the output voltage VQ to be arbitrarily set while maintaining the number of gradations and the voltage step of one gradation.

[0054] First, we will explain the relationship between feedback gain, grayscale data, and voltage range using Figures 7 and 8.

[0055] Figure 7 shows the relationship between the grayscale data input to the first drive circuit and the voltage. Here, examples with feedback gains of 1 / 10 and 1 / 5 are shown, and it is assumed that the voltage range is maximized when the feedback gain is 1 / 10.

[0056] In Figure 7, VSH=0V and VDH=15V are the low-potential and high-potential power supply voltages of the first drive circuit 60. The common voltage supplied to the counter electrode of the electro-optic panel 200 is VC=7.5V. Also, VSL=0V and VDL=1.8V are the low-potential and high-potential power supply voltages of the second drive circuit 70. The voltage corresponding to the common voltage VC=7.5V is set to VCL=0.9V.

[0057] The processing circuit 42 converts the input gradation data GD[9:0] into gradation data DTH[10:0]. When the feedback gain is 1 / 10, the processing circuit 42 converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] with gradation values ​​from 1023 to 0 in negative polarity drive, and converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] with gradation values ​​from 1024 to 2047 in positive polarity drive. The range of the output voltage VQ is 10V centered around the common voltage VC=7.5V, i.e., 2.5V to 12.5V. The common voltage of the inverting input node NAN of the operational amplifier 71 is set to VCL=VREF=0.9V. Since the output voltage VQ, which has a range of 10V, is fed back with a gain of 1 / 10, the voltage VFB of the inverting input node NAN has a range of 1V centered around 0.9V, i.e., 0.4V to 1.4V.

[0058] When the feedback gain is 1 / 5, the processing circuit 42 reduces the number of gradations of DTH[10:0] to (1 / 10) / (1 / 5)=1 / 2. That is, in negative polarity drive, the processing circuit 42 converts GD[9:0] with gradation values ​​from 0 to 1023 to DTH[10:0] with gradation values ​​from 1023 to 512, and in positive polarity drive, it converts GD[9:0] with gradation values ​​from 0 to 1023 to DTH[10:0] with gradation values ​​from 1024 to 1535. The range of the output voltage VQ is 5V centered around the common voltage VC=7.5V, i.e., 5V to 10V. Since the output voltage VQ range of 10V is fed back with a gain of 1 / 5, the range of the voltage VFB of the inverting input node NAN is 1V centered around 0.9V, i.e., 0.4V to 1.4V.

[0059] Figure 8 shows the relationship between the grayscale data and voltage input to the second drive circuit.

[0060] The processing circuit 42 converts the input grayscale data GD[9:0] into grayscale data DTL[10:0]. Specifically, when driven by negative polarity, the processing circuit 42 sets DTL

[10] =1 and DTL[9:0]=GD[9:0], and when driven by positive polarity, it sets DTL

[10] =0 and DTL[9:0]=XGD[9:0]. XGD[9:0] is data obtained by logically inverting each bit of GD[9:0]. The D / A conversion circuit 72 performs D / A conversion of the grayscale data DTL[10:0]=0~2047 to a voltage range of 0.4V~1.4V.

[0061] The gain of the second drive circuit 70 is the reciprocal of the feedback gain (Cfa + Cfb) / Cfa. That is, when the feedback gain is 1 / 10, the output voltage range of the D / A conversion circuit 72, 0.4V to 1.4V, is amplified by a gain of 10 times, so the voltage range of the output voltage VQ becomes 2.5V to 12.5V. When the feedback gain is 1 / 5, the output voltage range of the D / A conversion circuit 72, 0.4V to 1.4V, is amplified by a gain of 5 times, so the voltage range of the output voltage VQ becomes 5V to 10V.

[0062] As described above, even if the number of gradations in DTH[10:0] changes, the voltage range VFB of the inverting input node NAN remains unchanged. Since the non-inverting input node NAP and the inverting input node NAN of the operational amplifier 71 are virtually short-circuited by the operational amplifier 71, the fact that the feedback voltage range does not change is equivalent to the output voltage range of the D / A conversion circuit 72 remaining unchanged. As a result, the number of gradations and the voltage step of one gradation in the D / A conversion circuit 72 are maintained, as explained in Figure 8. When the number of gradations in DTH[10:0] changes, the number of gradations driven by the first drive circuit 60 changes, but as will be explained later in Figure 9, the difference between the output voltage VQ of the first drive circuit 60 and the target voltage is corrected by the second drive circuit 70. That is, as long as the number of gradations and the voltage step of one gradation in the second drive circuit 70 are maintained, the final output, including the second drive circuit 70, can maintain the number of gradations and the voltage step of one gradation.

[0063] Figure 9 shows a first waveform example illustrating the operation of the first and second drive circuits. Figure 9 shows a waveform example when the feedback gain is 1 / 5.

[0064] Assume that the gradation values ​​of the gradation data DTH[10:0] change from 1024, 1535, and 1024, and the gradation values ​​of DTL[10:0] change from 1024, 2047, and 1024. The target voltage corresponding to DTH[10:0]=1535 is 10.0V.

[0065] Assuming that the second drive circuit 70 is absent and the system is driven only by the first drive circuit 60, when the grayscale value changes from 1024 to 1535, the output voltage VQ changes from 7.5V to 9.9V. The difference from the target voltage of 10.0V is 0.1V. The operation of the second drive circuit 70 in this case will be explained below.

[0066] The D / A conversion circuit 72 changes the D / A conversion voltage DAQ from 0.9V to 1.4V when the grayscale value changes from 1024 to 2047. The output voltage VQ is changed from 7.5V to 9.9V by the first drive circuit 60, so the voltage VFB of the inverting input node NAN of the operational amplifier 71 changes from 0.9V to 0.9V + (9.9V - 7.5V) / 5 = 1.38V. The operational amplifier 71 changes the output voltage AMQ from 0.9V to 0.9V + (10.0V - 9.9V) × (5 / 4) = 1.025V in order to make VFB = DAQ = 1.4V. As a result, the output voltage VQ becomes the target voltage of 10.0V and the voltage VFB becomes 1.4V.

[0067] In this way, the output voltage VQ is determined by the second drive circuit 70 correcting the output voltage of the first drive circuit 60. As mentioned above, the number of gradations and the voltage step of one gradation of the second drive circuit 70 do not change due to the feedback gain, so the range of voltage applied to the pixels can be changed without changing the number of gradations and the voltage step of one gradation of the data voltage output by the data line drive circuit 110.

[0068] Figure 10 shows a second waveform example illustrating the operation of the first and second drive circuits. Figure 10 shows a waveform example when the feedback gain is set to 1 / 5 during the horizontal scanning period in the positive polarity drive period of polarity reversal drive. Here, an example is shown in which grayscale values ​​of 0, 127, ..., 1023 are sequentially written to 9 pixels, but the number of pixels driven during the horizontal scanning period and the grayscale values ​​written to each pixel can be arbitrary.

[0069] The rising edge of the horizontal synchronization signal HSYNC is used as the start timing for the horizontal scanning period. After the horizontal scanning period has started, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. Here, 0 is shown as a low level and 1 as a high level. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0070] Next, the initialization switch SWR switches from off to on, and then from on to off. Here, off is represented by a low level, and on by a high level. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V. The period during which the voltage VFB is initialized is called the initialization period. In Figure 10, the period during which the initialization switch SWR is on corresponds to the initialization period.

[0071] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTL[9:0] with grayscale values ​​0, 127, ..., 1023 and DTH[9:0] with grayscale values ​​0, 63, ..., 511. As a result, the D / A conversion voltage DAQ changes sequentially from 0.9V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 10V. Note that the grayscale values ​​shown here are merely examples of values ​​whose voltage ranges are easy to understand, and as mentioned above, the grayscale values ​​written to each pixel can be arbitrary.

[0072] Figure 11 is a third waveform example illustrating the operation of the first and second drive circuits. Figure 11 shows a waveform example when the feedback gain is set to 1 / 5 during the negative polarity drive period of polarity reversal drive.

[0073] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0074] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V.

[0075] Next, the processing circuit 42 changes DTH

[10] =DTL

[10] from 1 to 0. Then, writing to the pixels begins. The processing circuit 42 sequentially outputs DTL[9:0] for grayscale values ​​0, 127, ..., 1023 and DTH[9:0] for grayscale values ​​511, 757, ..., 1023. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 0.9V, and the output voltage VQ changes sequentially from 5V to 7.5V. Note that the grayscale values ​​shown here are just examples with easily understandable voltage ranges, and the grayscale values ​​written to each pixel can be arbitrary.

[0076] In the above embodiment, the driver 100 includes a first drive circuit 60 and a second drive circuit 70. The first drive circuit 60 supplies a data signal to the signal supply line of the electro-optic panel 200 based on grayscale data GD[9:0]. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, and a second feedback capacitor Cfb. One end of the output capacitor CQ is electrically connected to the output node NAMQ of the operational amplifier 71, and the other end is electrically connected to the signal supply line. One end of the first feedback capacitor Cfa is electrically connected to the inverting input node NAN of the operational amplifier 71, and the other end is electrically connected to the signal supply line. One end of the second feedback capacitor Cfb is electrically connected to the inverting input node NAN of the operational amplifier 71, and the other end is electrically connected to a predetermined potential node. The second drive circuit 70 is electrically connected to the signal supply line. At least one of the first feedback capacitor Cfa and the second feedback capacitor Cfb is a capacitor with a variable capacitance value.

[0077] According to this embodiment, since the capacitance value of at least one of the first feedback capacitor Cfa and the second feedback capacitor Cfb is variable, the feedback gain from the signal supply line to the inverting input node NAN of the operational amplifier 71 and the gain of the second drive circuit 70 can be varied. This makes it possible to change the voltage range of the data voltage output to the signal supply line without changing the number of gradations and the voltage step of one gradation of the second drive circuit 70. As described above, it is necessary to change the range of voltage applied to the pixels depending on the color of the light incident on the electro-optic panel 200, but according to this embodiment, the range of voltage applied to the pixels can be changed while maintaining the number of gradations and the voltage step of one gradation.

[0078] An electrical connection is defined as a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information via electrical signals. An electrical connection may also be a connection mediated by active elements, etc.

[0079] In this embodiment, the second drive circuit 70 also includes a D / A conversion circuit 72. The D / A conversion circuit 72 supplies a D / A conversion voltage DAQ based on the grayscale data GD[9:0] to the inverting input node NAN of the operational amplifier 71.

[0080] According to this embodiment, when a difference occurs between the D / A conversion voltage DAQ and the voltage VFB fed back from the signal supply line to the inverting input node NAN of the operational amplifier 71, the operational amplifier 71 can supply charge to the signal supply line via the output capacitor CQ, thereby correcting the difference between the voltage of the signal supply line and the target voltage corresponding to the grayscale data GD[9:0]. As a result, even if there is an error between the voltage output to the signal supply line by the first drive circuit 60 and the target voltage, the second drive circuit 70 can correct that error.

[0081] Furthermore, since the above error is considered to be sufficiently small compared to the target voltage, the amount of charge that the operational amplifier 71 needs to supply can be considered small. As a result, the voltage change at the output node NAMQ of the operational amplifier 71 is small, making it possible to construct the operational amplifier 71 with transistors having a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0082] In this embodiment, the operational amplifier 71 is composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0083] According to this embodiment, the output node NAMQ of the operational amplifier 71 and the signal supply line are coupled by the output capacitor CQ, and the inverting input node NAN of the operational amplifier 71 and the signal supply line are coupled by the first feedback capacitor Cfa. As a result, the operational amplifier 71 and the signal supply line are DC disconnected, so the operational amplifier 71 can be constructed using transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit 60.

[0084] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit 60 is longer than the source-drain distance of the transistors constituting the second drive circuit 70. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit 60 is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit 70.

[0085] According to this embodiment, the transistors constituting the second drive circuit 70, which includes the operational amplifier 71, can be composed of transistors with a lower breakdown voltage than the transistors constituting the first drive circuit 60.

[0086] Furthermore, the voltage of the signal supply line is divided by the first feedback capacitor Cfa and the second feedback capacitor Cfb and fed back to the inverting input node NAN of the operational amplifier 71. As a result, a voltage lower than the voltage of the signal supply line is applied to the inverting input node NAN of the operational amplifier 71, so the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0087] Furthermore, by configuring the operational amplifier 71 with transistors having a lower voltage rating than the transistors constituting the first drive circuit 60, the operational amplifier 71 can be constructed with high-mobility transistors. This makes it possible to achieve both high amplification and high frequency response characteristics in the operational amplifier. For example, in order to increase the drive speed due to high resolution, it is necessary to increase the frequency response characteristics of the operational amplifier. However, it is possible to increase the frequency response characteristics while maintaining the amplification of the operational amplifier, and thus reduce the power consumption of the operational amplifier.

[0088] Furthermore, in this embodiment, the capacitance value of the second feedback capacitor Cfb is greater than the capacitance value of the first feedback capacitor Cfa.

[0089] The gain of the second drive circuit 70 is (Cfa + Cfb) / Cfa. According to this embodiment, since the gain is greater than 2, the voltage range applied to the operational amplifier 71 becomes smaller than half the voltage range of the signal supply line. As a result, the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0090] In this embodiment, the driver 100 also includes a processing circuit 42 that outputs second grayscale data DTH[10:0] obtained by multiplying grayscale data GD[9:0] with a gain corresponding to a variable capacitance value. The first drive circuit 60 supplies a data signal to the signal supply line based on the second grayscale data DTH[10:0].

[0091] According to this embodiment, the first drive circuit 60 outputs a data voltage based on the second gradation data DTH[10:0], which is obtained by multiplying the gradation data GD[9:0] by a gain corresponding to a variable capacitance value, so that the voltage range changes according to the gain. Then, by canceling the gain that changes the voltage range and the feedback gain, the range of the voltage fed back to the inverting input node NAN of the operational amplifier 71 can be kept constant. As a result, the voltage range of the data voltage output to the signal supply line can be changed without changing the number of gradations of the second drive circuit 70 and the voltage step of one gradation.

[0092] In the example in Figure 7, the gain corresponding to the variable capacitance value is (1 / 10) / (1 / 10)=1 when the feedback gain is 1 / 10, and (1 / 10) / (1 / 5)=1 / 2 when the feedback gain is 1 / 5. The multiplication process is not limited to simply multiplying by the gain. In the example in Figure 7, the multiplication process is the process of multiplying the slope of the second tone data DTH[10:0] by 1 or 1 / 2 with 1024 as the base.

[0093] In this embodiment, the first feedback capacitor Cfa includes a first group of switches and a first group of capacitors, each consisting of a switch and a capacitor pair arranged in parallel between the signal supply line and the inverting input node NAN of the operational amplifier 71. The second feedback capacitor Cfb includes a second group of switches and a second group of capacitors, each consisting of a switch and a capacitor pair arranged in parallel between the inverting input node NAN of the operational amplifier 71 and a predetermined potential node.

[0094] According to this embodiment, when each switch in the first switch group is turned on or off, the capacitor in the first capacitor group that is connected in series with the switched-on switch is connected between the signal supply line and the inverting input node NAN of the operational amplifier 71. This allows the capacitance value of the first feedback capacitor Cfa to be controlled to be variable. Similarly, when each switch in the second switch group is turned on or off, the capacitance value of the second feedback capacitor Cfb is controlled to be variable.

[0095] In the example in Figure 5, capacitors Ca1 to Ca4 correspond to the first capacitor group, and switches SWa1 to SWa4 correspond to the first switch group. For example, switch SWa1 and capacitor Ca1 are connected in series, forming a pair. In the example in Figure 5, four such pairs are connected in parallel.

[0096] In this embodiment, the driver 100 also includes an initialization switch SWR. The initialization switch SWR is turned on during the initialization period and supplies a reference voltage VREF to the inverting input node NAN of the operational amplifier 71.

[0097] According to this embodiment, the inverting input node NAN of the operational amplifier 71 changes with respect to the reference voltage VREF. When the range of the D / A conversion voltage DAQ is expressed as VREF-ΔV1 to VREF+ΔV2, the reference voltage VREF should be set such that VREF-ΔV1 is higher than the low-potential side power supply voltage VSL of the second drive circuit 70, and VREF+ΔV2 is lower than the high-potential side power supply voltage VDL of the second drive circuit 70.

[0098] In this embodiment, the first drive circuit 60 includes a capacitor drive circuit 20 and a capacitor circuit 10. The capacitor drive circuit 20 outputs the first to nth capacitor drive voltages corresponding to the grayscale data DTH[10:0] to the first to nth capacitor drive nodes NDR1 to NDRn, where n is an integer of 2 or more. The capacitor circuit 10 has a signal supply line and first to nth capacitors C1 to Cn arranged between the signal supply line and the first to nth capacitor drive nodes NDR1 to NDRn.

[0099] According to this embodiment, the capacitor drive circuit 20 outputs a first to nth capacitor drive voltage corresponding to the grayscale data DTH[10:0], causing the first to nth capacitors C1 to Cn to output a charge corresponding to the grayscale data DTH[10:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data DTH[10:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0100] 3. Second Embodiment Figure 12 shows a second detailed configuration example of the driver. In this configuration example, the data line drive circuit 110 includes a first drive circuit 60 and a second drive circuit 70. The processing circuit 42 outputs setting data DP[9:0] and DN[9:0] which set the drive capability of the first drive circuit 60 based on the grayscale data GD[9:0]. Since the configuration and operation of the second drive circuit 70 are the same as in the first embodiment, the configuration and operation of the first drive circuit 60 will be mainly described below.

[0101] Figure 13 illustrates the relationship between grayscale data, setting data, and data voltage. The relationship between grayscale data GD[9:0], grayscale data DTH[10:0], and data voltage is the same as in Figure 7. Figure 13 shows an example of DP and DN calculation when the feedback gain is 1 / 5, but the calculation method is the same regardless of the feedback gain.

[0102] Assume that one pixel is driven with a grayscale value DTH1, the next pixel is driven with a grayscale value DTH2, and DTH2-DTH1>0. In this case, the processing circuit 42 outputs DP[9:0]=|DTH2-DTH1| and DN[9:0]=0. Assume that one pixel is driven with a grayscale value DTH3, the next pixel is driven with a grayscale value DTH4, and DTH4-DTH3<0. In this case, the processing circuit 42 outputs DP[9:0]=0 and DN[9:0]=|DTH4-DTH3|. Figure 13 shows an example of positive polarity driving, but the same applies to negative polarity driving.

[0103] Furthermore, since DTH

[10] is canceled when the difference is taken, it is also possible to directly calculate DP[9:0] and DN[9:0] from the grayscale data GD[9:0] without going through DTH[10:0].

[0104] Figure 14 shows a second detailed configuration example of the first drive circuit. In this configuration example, the first drive circuit 60 includes a first drive transistor group TRG1 and a second drive transistor group TRG2.

[0105] The first drive transistor group TRG1 includes P-type transistors TP1 to TP10 connected in parallel between the node of the high-potential side power supply voltage VDH and the output node NVQ. The gate of P-type transistor TP1 is input to the bit signal XDP[0]. Similarly, the gates of P-type transistors TP2 to TP10 are input to the bit signals XDP[1] to XDP[9]. XDP[9:0] is the data obtained by logically inverting each bit of DP[9:0]. The drive capability of P-type transistors TP1 to TP10 is binary weighted. That is, the drive capability of P-type transistor TPi is twice the drive capability of P-type transistor TP1. (i-1) It is double. The driving capability is adjusted by, for example, the gate width of the transistor or the number of unit transistors connected in parallel.

[0106] The second group of drive transistors, TRG2, includes N-type transistors TN1 to TN10 connected in parallel between the output node NVQ and the low-potential power supply voltage VSH. The gate of N-type transistor TN1 is input to the bit signal DN[0]. Similarly, the gates of N-type transistors TN2 to TN10 are input to the bit signals DN[1] to DN[9]. The drive capability of N-type transistors TN1 to TN10 is binary weighted. That is, the drive capability of N-type transistor TNi is twice the drive capability of N-type transistor TN1. (i-1) It is double.

[0107] For example, let Itp1 be the current that flows when a P-type transistor TP1 is ON, and let ton be the ON period for driving one pixel. The charge that the P-type transistor TP1 supplies to the output node NVQ is Itp1 × ton, and the change in output voltage VQ due to that charge is (Itp1 × ton) / CP. Itp1 is set so that this voltage change is 1 LSB, that is, the driving capability of the P-type transistor TP1 is set.

[0108] Figure 15 is a fourth waveform example illustrating the operation of the first and second drive circuits. Figure 15 shows a waveform example when the feedback gain is set to 1 / 5 during the positive polarity drive period.

[0109] After the horizontal scanning period begins, the processing circuit 42 outputs DTL[9:0]=DP[9:0]=DN[9:0]=0 and changes DTL

[10] from 0 to 1. This corresponds to DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0110] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V.

[0111] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTL[9:0] with grayscale values ​​of 0, 127, ..., 1023, and also sequentially outputs DP[9:0]=0, 64, 64, ..., 64. As a result, the D / A conversion voltage DAQ changes sequentially from 0.9V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 10V. Note that Figure 15 shows an example where DP[9:0]>0 and DN[9:0]=0, but when the grayscale value of DTL[9:0] decreases, DP[9:0]=0 and DN[9:0]>0. Note that the grayscale values ​​shown here are just examples that make the voltage range easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0112] The waveform diagram for the negative polarity drive period is omitted. During the negative polarity drive period, the waveforms of SWR, DTL[9:0], DP[9:0], and DN[9:0] are the same as in Figure 15. The waveforms of DTL

[10] , DAQ, and VQ are the same as in Figure 11.

[0113] In the above embodiment, the driver 100 includes a control circuit 40 that controls the first drive circuit 60. The first drive circuit 60 includes a first drive transistor group TRG1 arranged between a node to which a high-potential-side power supply voltage VDH is supplied and a signal supply line, and a second drive transistor group TRG2 arranged between a node to which a low-potential-side power supply voltage VSH is supplied and a signal supply line. The control circuit 40 controls each transistor of the first drive transistor group TRG1 or each transistor of the second drive transistor group TRG2 to be turned on or off based on the grayscale data GD[9:0].

[0114] According to this embodiment, based on the grayscale data GD[9:0], the transistor that is turned on from the first drive transistor group TRG1 or the second drive transistor group TRG2 outputs a charge corresponding to the grayscale data GD[9:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data GD[9:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0115] 4. Third Embodiment In the third embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first embodiment.

[0116] Figure 16 shows a second detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, a D / A conversion circuit 72, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, and a voltage shift circuit 73.

[0117] The processing circuit 42 outputs grayscale data DTM[9:0] based on the grayscale data GD[9:0]. The D / A conversion circuit 72 performs D / A conversion on the grayscale data DTM[9:0] to a D / A conversion voltage DAQ. Figure 17 shows the relationship between the grayscale data and the D / A conversion voltage. The processing circuit 42 sets DTM[9:0]=GD[9:0] in positive polarity drive and DTM[9:0]=XGD[9:0] in negative polarity drive. The D / A conversion circuit 72 outputs DAQ=0.4V~1.4V for DTM[9:0]=0~1023.

[0118] The voltage shift circuit 73 includes an initialization switch SWR, a shift capacitor CFR, and a voltage output circuit DFR.

[0119] One end of the shift capacitor CFR is connected to the inverting input node NAN of the operational amplifier 71. The voltage output circuit DFR receives the signal XFR, which is the logic inverted signal of the polarity inversion signal FR. When the signal XFR is low, the voltage output circuit DFR outputs a signal with a voltage level of VSL=0V to the other end of the shift capacitor CFR, and when the signal XFR is high, it outputs a signal with a voltage level of VDL=1.8V to the other end of the shift capacitor CFR.

[0120] When the output voltage VQ range is 10V, the feedback gain is set to 1 / 10 in the first embodiment, but to 1 / 5 in the third embodiment. As a result, for both positive polarity drive and negative polarity drive, the output voltage VQ range becomes 5V for a D / A conversion voltage DAQ range of 1V. At this time, the voltage division ratio of Cfa and Cfb+CFR is 4:1, so (Cfb+CFR) / Cfa=4. When the output voltage VQ range is 5V, the feedback gain is set to 1 / 5 in the first embodiment, but to 1 / 2.5 in the third embodiment. At this time, the voltage division ratio of Cfa and Cfb+CFR is 1.5:1, so (Cfb+CFR) / Cfa=1.5.

[0121] Furthermore, the capacitance values ​​of CFR and Cfb are set so that when the voltage at the other end of the shift capacitor CFR changes by 1.8V, the voltage VFB changes by 0.5V. In this case, the voltage division ratio of CFR and Cfb is 1.3:0.5, so Cfb / CFR = 1.3V / 0.5V = 2.6.

[0122] Alternatively, a level shifter may be provided before the voltage output circuit DFR. The level shifter shifts the voltage level of the signal XFR to the level of the high-voltage power supply voltages VSH and VDH. In this case, the voltage output circuit DFR is composed of high-voltage transistors and operates at the power supply voltages VSH and VDH.

[0123] Figure 18 is a fifth waveform example illustrating the operation of the first and second drive circuits. Figure 18 shows a waveform example when the feedback gain is set to 1 / 5 during the positive polarity drive period.

[0124] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=511, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0125] Next, the processing circuit 42 changes the signal XFR from a low level to a high level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a high level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a high level to a low level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 0.4V, which corresponds to the initialization voltage for positive polarity. In Figure 18, the period from when the initialization switch SWR is switched from off to on until the signal XFR changes from a high level to a low level corresponds to the initialization period.

[0126] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTM[9:0] with grayscale values ​​0, 127, ..., 1023 and DTH[9:0] with grayscale values ​​0, 63, ..., 511. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 10V. Note that the grayscale values ​​shown here are merely examples of values ​​whose voltage ranges are easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0127] Figure 19 shows a sixth waveform example illustrating the operation of the first and second drive circuits. Figure 18 shows a waveform example when the feedback gain is set to 1 / 5 during the horizontal scanning period in the negative polarity drive period.

[0128] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=511, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0129] Next, the processing circuit 42 changes the signal XFR from a high level to a low level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a low level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a low level to a high level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 1.4V, which corresponds to the initialization voltage for the negative polarity.

[0130] Next, writing to the pixels begins. The processing circuit 42 sets DTH

[10] from 1 to 0, and then sequentially outputs DTM[9:0] with gradation values ​​1023, 895, ..., 0 and DTH[9:0] with gradation values ​​1023, 959, ..., 511. As a result, the D / A conversion voltage DAQ changes sequentially from 1.4V to 0.4V, and the output voltage VQ changes sequentially from 7.5V to 5V. Note that the gradation values ​​shown here are merely examples that make the voltage range easy to understand, and the gradation values ​​written to each pixel can be arbitrary.

[0131] Figure 20 shows a third detailed configuration example of the second drive circuit. In this configuration example, the voltage shift circuit 73 includes a first initialization switch SWRP and a second initialization switch SWRN.

[0132] One end of the first initialization switch SWRP is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NPVR, which is supplied with the initialization voltage PVR for positive polarity. One end of the second initialization switch SWRN is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NNVR, which is supplied with the initialization voltage NVR for negative polarity. The initialization voltages PVR and NVR are supplied to nodes NPVR and NNVR from, for example, a voltage generation circuit (not shown) included in the driver 100.

[0133] The processing circuit 42 controls the first initialization switch SWRP and the second initialization switch SWRN to turn on or off based on the polarity inversion signal. Specifically, during the initialization period of the positive polarity drive period, the first initialization switch SWRP is turned on, and the inverting input node NAN of the operational amplifier 71 is initialized with an initialization voltage PVR = 0.4V. During the initialization period of the negative polarity drive period, the second initialization switch SWRN is turned on, and the inverting input node NAN of the operational amplifier 71 is initialized with an initialization voltage NVR = 1.4V.

[0134] In the above embodiment, the driver 100 includes a voltage shift circuit 73. The voltage shift circuit 73 is electrically connected to the inverting input node NAN of the operational amplifier 71 and shifts the voltage VFB of the inverting input node NAN.

[0135] According to this embodiment, the voltage shift circuit 73 shifts the voltage VFB of the inverting input node NAN, thereby shifting the reference of the voltage VFB of the inverting input node NAN. By dividing the range of the output voltage VQ into multiple ranges and shifting the reference of the voltage VFB for each range, it becomes possible to associate each range of the output voltage VQ with the range of the D / A conversion voltage DAQ. This makes it possible to lower the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 and to lower the number of gradations in the D / A conversion.

[0136] In this embodiment, the voltage shift circuit 73 sets different initialization voltages for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period to the inverting input node NAN of the operational amplifier 71 based on the polarity inversion signal FR.

[0137] For example, in Figure 16, the shift capacitor CFR and the voltage output circuit DFR set the initialization voltage based on the polarity inversion signal. Alternatively, in Figure 20, the first initialization switch SWRP and the second initialization switch SWRN set the initialization voltage based on the polarity inversion signal.

[0138] According to this embodiment, the range of the output voltage VQ during the positive polarity drive period is associated with the range of the D / A conversion voltage DAQ, which is 7.5V to 12.5V, and the range of the output voltage VQ during the negative polarity drive period is associated with the range of the D / A conversion voltage DAQ, which is 7.5V to 2.5V. This makes it possible to reduce the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 to approximately 1 / 2, and to reduce the number of gradations of the D / A conversion from 2048 to 1024 (half of 2048).

[0139] 5. Fourth Embodiment In the third embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first embodiment.

[0140] Figure 21 shows a fourth detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, an initialization switch SWR, capacitors CB1 to CBm+1 for the first to m+1 voltage outputs, and first to m+1 voltage output circuits DB1 to DBm+1. Here, an example with m=10 is described, but m can be any integer greater than or equal to 2. In the fourth embodiment, m+1 should be set to the same number of bits as the grayscale data DTL[10:0].

[0141] One end of the voltage output capacitor CBp is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the output node of the voltage output circuit DBp. p is an integer greater than or equal to 1 and less than or equal to m+1=11. The voltage output capacitors CB1 to CB11 have binary weighted capacitance values. Specifically, the capacitance value of the voltage output capacitor CBp is 2 (p-1) ×CB1

[0142] The voltage output circuit DBp outputs a first voltage level when the bit signal XDTL[p-1], which is the logic inversion signal of the bit signal DTL[p-1], is at the first logic level, and outputs a second voltage level when the bit signal XDTL[p-1] is at the second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is the low-potential side power supply voltage VSH, and the second voltage level is the high-potential side power supply voltage VDH. The voltage output circuit DBp is composed of low-voltage process transistors and operates with power supply voltages VDL and VSL. The voltage output circuit DBp is a buffer circuit that buffers the input signal and outputs it.

[0143] One end of the initialization switch SWR is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NVREF, which is supplied with the reference voltage VREF. The non-inverting input node of the operational amplifier 71 is connected to node NVREF, which is supplied with the reference voltage VREF.

[0144] The initialization switch SWR is off when driving pixels. At this time, the operational amplifier 71 performs feedback control so that the voltage VFB of the inverting input node NAN of the operational amplifier 71 becomes a reference voltage VREF = 0.9V due to a virtual short. As a result, the bit signals XDTL

[10] ~XDTL[0] become 0 or 1 according to the grayscale data DTL[10:0], and the data voltage corresponding to the grayscale data DTL[10:0] is output to the output node NVQ.

[0145] The capacitance values ​​of each capacitor are explained below. In the following, the total capacitance of CB1 to CB11 will be denoted as CB = CB1 + CB2 + ... + CB11.

[0146] For example, let the feedback gain be 1 / 10 and the gain of the second drive circuit 70 be 10. In this case, the range of the output voltage VQ is 10V. When XDTL

[10] to XDTL[0] all change from 1 to 0, that is, when the output voltages of the voltage output circuits DB1 to DB11 all change from VDL=1.8V to VSL=0V, the output voltage VQ should change by 10V, so CB / Cfa = 10V / 1.8V = 50 / 9.

[0147] Conversely, when the first drive circuit 60 changes the voltage of the output node NVQ by 10V, let Vfa be the voltage change fed back to the inverting input node NAN of the operational amplifier 71 via the first feedback capacitor Cfa. Vfa ≤ 1.8V is sufficient, but here we assume Vfa = 1V. In this case, the 10V should be divided in a 9:1 ratio by Cfa and Cfb + CB, so (Cfb + CB) / Cfa = 9.

[0148] For example, let's set the feedback gain to 1 / 5 and the gain of the second drive circuit 70 to 5. In this case, the range of the output voltage VQ is 5V. When XDTL

[10] to XDTL[0] all change from 1 to 0, that is, when the output voltages of the voltage output circuits DB1 to DB11 all change from VDL=1.8V to VSL=0V, the output voltage VQ should change by 5V, so CB / Cfa = 5V / 1.8V = 25 / 9.

[0149] Conversely, when the first drive circuit 60 changes the voltage of the output node NVQ by 5V, the voltage change fed back to the inverting input node NAN of the operational amplifier 71 via the first feedback capacitor Cfa is Vfa = 1V. In this case, 10V should be divided in a 4:1 ratio by Cfa and Cfb + CB, so (Cfb + CB) / Cfa = 4.

[0150] Furthermore, the voltage change at the inverting input node NAN due to the change in XDTL

[10] ~XDTL[0] is a maximum of 1.8V, so it is sufficient if Vfa ≤ 1.8V. If Vfa ≤ 1.8V, the voltage change at the inverting input node NAN due to the change in XDTL

[10] ~XDTL[0] can be balanced with the voltage change at the inverting input node NAN when the first drive circuit 60 changes the voltage of the output node NVQ. In other words, as long as the voltage changes are ideally balanced, the voltage at the inverting input node NAN will be maintained at VFB = 0.9V even if the operational amplifier 71 does not output charge, and only if there is an error in the balance will the operational amplifier 71 need to output charge to correct that error.

[0151] The capacitance value of the output capacitor CQ can be arbitrary, as long as it is set so that the output voltage AMQ of the operational amplifier 71 is within the range of VSL to VDL. For example, the capacitance value of the output capacitor CQ is set to approximately 1 to 10 times the sum of the capacitor circuit 10, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As an example, if the capacitance value of the output capacitor CQ is 4 times the above sum, in order to compensate for an error of 0.1V in the output voltage VQ, the output voltage AMQ of the operational amplifier 71 only needs to change by 0.1V × (5 / 4) = 0.125V.

[0152] In the above embodiment, the driver 100 includes a first drive circuit 60 and a second drive circuit 70. The first drive circuit 60 supplies data signals to the signal supply line of the electro-optic panel 200 based on grayscale data. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, first to m-th voltage output capacitors CB1 to CBm, and first to m-th voltage output circuits DB1 to DBm. One end of the output capacitor CQ is electrically connected to the output node NAMQ of the operational amplifier 71, and the other end is electrically connected to the signal supply line. One end of the first feedback capacitor Cfa is electrically connected to the inverting input node NAN of the operational amplifier 71, and the other end is electrically connected to the signal supply line. The first feedback capacitor Cfa is a capacitor with a variable capacitance value. One end of the first to m-th voltage output capacitors CB1 to CBm is electrically connected to the inverting input node NAN of the operational amplifier 71. The first to m-th voltage output circuits DB1 to DBm output voltages based on grayscale data to the other ends of the first to m-th voltage output capacitors CB1 to CBm. The second drive circuit 70 is electrically connected to the signal supply line.

[0153] According to this embodiment, since the capacitance value of the first feedback capacitor Cfa is variable, the feedback gain from the signal supply line to the inverting input node NAN of the operational amplifier 71, and the gain of the second drive circuit 70 can be varied. This makes it possible to change the voltage range of the data voltage output to the signal supply line without changing the number of gradations and the voltage step of one gradation of the second drive circuit 70. As described above, it is necessary to change the range of voltage applied to the pixels depending on the color of the light incident on the electro-optic panel 200, but according to this embodiment, the range of voltage applied to the pixels can be changed while maintaining the number of gradations and the voltage step of one gradation.

[0154] In this embodiment, the operational amplifier 71 is composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0155] According to this embodiment, the output node NAMQ of the operational amplifier 71 and the signal supply line are coupled by the output capacitor CQ, and the inverting input node NAN of the operational amplifier 71 and the signal supply line are coupled by the first feedback capacitor Cfa. As a result, the operational amplifier 71 and the signal supply line are DC disconnected, so the operational amplifier 71 can be constructed using transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit 60.

[0156] 6. Electronic equipment Figure 22 shows an example of the configuration of an electronic device including the driver of this embodiment. Various electronic devices equipped with a display device can be envisioned as the electronic device of this embodiment. For example, the electronic device may be a projector, television system, information processing device, portable information terminal, car navigation system, or portable game terminal.

[0157] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0158] The electro-optic panel 200 is, for example, a matrix-type liquid crystal display panel. Alternatively, the electro-optic panel 200 may be an EL display panel using self-luminescent elements. EL stands for Electro-Luminescence. The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it consists of buttons, a mouse, a keyboard, or a touch panel attached to the electro-optic panel 200. The data interface unit 340 is an interface unit that performs input and output of image data or control data. For example, it is a wired communication interface such as USB, or a wireless communication interface such as wireless LAN. The storage unit 320 stores the image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as the working memory of the processing unit 310 or the display controller 300. The processing unit 310 performs control processing of various parts of the electronic device and various data processing. The processing unit 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the driver 100. For example, the display controller 300 converts the image data transferred from the data interface unit 340 or the storage unit 320 into a format that the driver 100 can accept, and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on the image data transferred from the display controller 300.

[0159] The driver of this embodiment described above includes a first drive circuit and a second drive circuit. The first drive circuit supplies data signals to the signal supply line of the electro-optical panel based on grayscale data. The second drive circuit includes an operational amplifier. The second drive circuit includes an output capacitor, one end of which is electrically connected to the output node of the operational amplifier and the other end of which is electrically connected to the signal supply line. The second drive circuit includes a first feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier and the other end of which is electrically connected to the signal supply line. The second drive circuit includes a second feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier and the other end of which is electrically connected to a predetermined potential node. The second drive circuit is electrically connected to the signal supply line. At least one of the first feedback capacitor and the second feedback capacitor is a capacitor with a variable capacitance value.

[0160] According to this embodiment, since the capacitance value of at least one of the first and second feedback capacitors is variable, the feedback gain from the signal supply line to the inverting input node of the operational amplifier and the gain of the second drive circuit can be varied. This makes it possible to change the voltage range of the data voltage output to the signal supply line without changing the number of gradations and the voltage step of one gradation in the second drive circuit. It is necessary to change the range of voltage applied to the pixels depending on the color of the light incident on the electro-optic panel, but according to this embodiment, the range of voltage applied to the pixels can be changed while maintaining the number of gradations and the voltage step of one gradation.

[0161] In this embodiment, the second drive circuit may also include a D / A conversion circuit that supplies a D / A conversion voltage based on grayscale data to the inverting input node of the operational amplifier.

[0162] According to this embodiment, when a difference occurs between the D / A conversion voltage and the voltage fed back from the signal supply line to the inverting input node of the operational amplifier, the operational amplifier can supply charge to the signal supply line via the output capacitor, thereby correcting the difference between the voltage of the signal supply line and the target voltage corresponding to the grayscale data. As a result, even if there is an error between the voltage output to the signal supply line by the first drive circuit and the target voltage, the second drive circuit can correct that error.

[0163] In this embodiment, the operational amplifier may be composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0164] In this embodiment, the output node of the operational amplifier and the signal supply line are coupled by an output capacitor, and the inverting input node of the operational amplifier and the signal supply line are coupled by a first feedback capacitor. As a result, the operational amplifier and the signal supply line are DC disconnected, so the operational amplifier can be constructed using transistors with a voltage rating lower than that of the transistors constituting the first drive circuit.

[0165] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit may be longer than the source-drain distance of the transistors constituting the second drive circuit. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit may be thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

[0166] According to this embodiment, the transistors constituting the second drive circuit, which includes an operational amplifier, can be configured with transistors having a lower breakdown voltage than the transistors constituting the first drive circuit.

[0167] In this embodiment, the capacitance of the second feedback capacitor may be greater than the capacitance of the first feedback capacitor.

[0168] According to this embodiment, since the gain of the second drive circuit is greater than 2, the voltage range applied to the operational amplifier becomes less than half the voltage range of the signal supply line. As a result, the operational amplifier can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0169] In this embodiment, the driver may also include a processing circuit that outputs second grayscale data obtained by multiplying the grayscale data with a gain corresponding to a variable capacitance value. The first drive circuit may supply a data signal to the signal supply line based on the second grayscale data.

[0170] According to this embodiment, the first drive circuit outputs a data voltage based on second-level data obtained by multiplying the level data with a gain corresponding to a variable capacitance value, so that the voltage range changes according to the gain. Then, by canceling the gain that changes the voltage range and the feedback gain, the range of the voltage fed back to the inverting input node of the operational amplifier can be kept constant. As a result, the voltage range of the data voltage output to the signal supply line can be changed without changing the number of levels of the second drive circuit or the voltage step of one level.

[0171] In this embodiment, the first feedback capacitor may also include a first group of switches and a first group of capacitors, each consisting of a switch and a capacitor pair arranged in parallel between the signal supply line and the inverting input node of the operational amplifier. The second feedback capacitor may also include a second group of switches and a second group of capacitors, each consisting of a switch and a capacitor pair arranged in parallel between the inverting input node of the operational amplifier and a predetermined potential node.

[0172] According to this embodiment, when each switch in the first switch group is turned on or off, the capacitor in the first capacitor group that is connected in series with the switched-on switch is connected between the signal supply line and the inverting input node of the operational amplifier. This allows the capacitance value of the first feedback capacitor to be variably controlled. Similarly, when each switch in the second switch group is turned on or off, the capacitance value of the second feedback capacitor is variably controlled.

[0173] In this embodiment, the driver may also include an initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier.

[0174] According to this embodiment, the inverting input node of the operational amplifier changes with respect to a reference voltage. When the range of the D / A conversion voltage is expressed as (reference voltage -ΔV1) to (reference voltage +ΔV2), the reference voltage should be set such that (reference voltage -ΔV1) is higher than the low-potential side power supply voltage of the second drive circuit and (reference voltage +ΔV2) is lower than the high-potential side power supply voltage of the second drive circuit.

[0175] In this embodiment, the first drive circuit may also include a capacitor drive circuit that outputs first to nth capacitor drive voltages corresponding to grayscale data to first to nth capacitor drive nodes, and a capacitor circuit having first to nth capacitors arranged between a signal supply line and the first to nth capacitor drive nodes, where n is an integer of 2 or more.

[0176] According to this embodiment, the capacitor drive circuit outputs a first to nth capacitor drive voltage corresponding to the grayscale data, causing the first to nth capacitors to output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0177] In this embodiment, the driver may also include a control circuit for controlling the first drive circuit. The first drive circuit may include a group of first drive transistors arranged between a node to which a high-potential-side power supply voltage is supplied and a signal supply line, and a group of second drive transistors arranged between a node to which a low-potential-side power supply voltage is supplied and a signal supply line. The control circuit may control each transistor in the first drive transistor group or each transistor in the second drive transistor group to be turned on or off based on grayscale data.

[0178] According to this embodiment, based on the grayscale data, the transistors that are turned on from the first group of drive transistors or the second group of drive transistors output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0179] In this embodiment, the driver may also include a voltage shift circuit that is electrically connected to the inverting input node of the operational amplifier and shifts the voltage of the inverting input node.

[0180] According to this embodiment, the voltage shift circuit shifts the voltage at the inverting input node of the operational amplifier, thereby shifting the voltage reference of the inverting input node. By dividing the voltage range output to the signal supply line into multiple ranges and shifting the voltage reference of the inverting input node for each range, it becomes possible to associate each range of voltage output to the signal supply line with the range of D / A conversion voltage. This makes it possible to lower the gain of the second drive circuit and reduce the number of gradations in D / A conversion.

[0181] In this embodiment, the voltage shift circuit may set different initialization voltages at the inverting input node of the operational amplifier for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period, based on the polarity inversion signal.

[0182] According to this embodiment, the range of voltage output to the signal supply line during the positive polarity drive period is associated with the range of the D / A conversion voltage, and the range of voltage output to the signal supply line during the negative polarity drive period is associated with the range of the D / A conversion voltage. This makes it possible to reduce the gain of the second drive circuit 70 to approximately 1 / 2 and to reduce the number of gradations of the D / A conversion to 1 / 2.

[0183] The driver of this embodiment also includes a first drive circuit and a second drive circuit. The first drive circuit supplies data signals to the signal supply line of the electro-optical panel based on grayscale data. The second drive circuit includes an operational amplifier. The second drive circuit includes an output capacitor, one end of which is electrically connected to the output node of the operational amplifier and the other end of which is electrically connected to the signal supply line. The second drive circuit includes a first feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier and the other end of which is electrically connected to the signal supply line, and which is a capacitor with a variable capacitance value. The second drive circuit includes first to m voltage output capacitors, one end of which is electrically connected to the inverting input node of the operational amplifier, where m is an integer of 2 or more. The second drive circuit includes first to m voltage output circuits that output voltages based on grayscale data to the other end of the first to m voltage output capacitors. The second drive circuit is electrically connected to the signal supply line.

[0184] According to this embodiment, since the capacitance value of the first feedback capacitor is variable, the feedback gain from the signal supply line to the inverting input node of the operational amplifier and the gain of the second drive circuit can be varied. This makes it possible to change the voltage range of the data voltage output to the signal supply line without changing the number of gradations and the voltage step of one gradation in the second drive circuit. As described above, it is necessary to change the range of voltage applied to the pixels depending on the color of the light incident on the electro-optic panel, but according to this embodiment, the range of voltage applied to the pixels can be changed while maintaining the number of gradations and the voltage step of one gradation.

[0185] In this embodiment, the operational amplifier may be composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0186] In this embodiment, the output node of the operational amplifier and the signal supply line are coupled by an output capacitor, and the inverting input node of the operational amplifier and the signal supply line are coupled by a first feedback capacitor. As a result, the operational amplifier and the signal supply line are DC disconnected, so the operational amplifier can be constructed using transistors with a voltage rating lower than that of the transistors constituting the first drive circuit.

[0187] Furthermore, the electro-optical device of this embodiment includes a driver as described in any of the above and an electro-optical panel.

[0188] Furthermore, the electronic device of this embodiment includes a driver as described in any of the above.

[0189] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of control circuits, data line drive circuits, drivers, electro-optic panels, electro-optic devices, and electronic equipment are not limited to those described in this embodiment, and various modifications are possible. [Explanation of symbols]

[0190] 10...Capacitor circuit, 20...Capacitor drive circuit, 30...Variable capacitance circuit, 40...Control circuit, 42...Processing circuit, 44...Interface circuit, 48...Register circuit, 50...Detection circuit, 60...First drive circuit, 70...Second drive circuit, 71...Operational amplifier, 72...D / A conversion circuit, 73...Voltage shift circuit, 100...Driver, 110...Data line drive circuit, 200...Electro-optic panel, 300...Display controller, 310...Processing unit, 320...Storage unit, 330...User interface unit, 340...Data interface unit, 400...Electro-optic Device, 500...Electronic equipment, C1~C10...Capacitors, CB1~CB10...Voltage output capacitors, Cfa...First feedback capacitor, Cfb...Second feedback capacitor, DB1~DB10...Voltage output circuit, DR1~DR10...Drive circuit, DTH[10:0]...Gradation data, DTL[10:0]...Gradation data, FR...Polarity inversion signal, GD[9:0]...Gradation data, SPL1~SPL8...Signal supply line, SWR...Initialization switch, TRG1...First drive transistor group, TRG2...Second drive transistor group, VREF...Reference voltage

Claims

1. A first drive circuit that supplies data signals to the signal supply lines of an electro-optical panel based on grayscale data, A second drive circuit is electrically connected to the signal supply line and includes an operational amplifier, an output capacitor with one end electrically connected to the output node of the operational amplifier and the other end electrically connected to the signal supply line, a first feedback capacitor with one end electrically connected to the inverting input node of the operational amplifier and the other end electrically connected to the signal supply line, and a second feedback capacitor with one end electrically connected to the inverting input node of the operational amplifier and the other end electrically connected to a predetermined potential node. Includes, A driver characterized in that at least one of the first feedback capacitor and the second feedback capacitor is a capacitor with a variable capacitance value.

2. In the driver described in claim 1, The second drive circuit is, A driver characterized by including a D / A conversion circuit that supplies a D / A conversion voltage based on the grayscale data to the non-inverting input node of the operational amplifier.

3. In the driver described in claim 1, The aforementioned operational amplifier, A driver characterized by being composed of transistors with a voltage rating lower than that of the transistors constituting the first drive circuit.

4. In the driver described in claim 3, A driver characterized in that the source-drain distance of the transistors constituting the first drive circuit is longer than the source-drain distance of the transistors constituting the second drive circuit, or the thickness of the gate insulating film of the transistors constituting the first drive circuit is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

5. In the driver described in claim 1, The second feedback capacitor is a feedback capacitor with a variable capacitance value. The driver is characterized in that the capacitance value of the second feedback capacitor is set to a capacitance value greater than the capacitance value of the first feedback capacitor.

6. In the driver described in Claim 1, The first feedback capacitor is a feedback capacitor with a variable capacitance value. A driver characterized in that the capacitance value of the first feedback capacitor is set to a capacitance value smaller than the capacitance value of the second feedback capacitor.

7. In the driver described in claim 1, The circuit includes a processing circuit that outputs second grayscale data obtained by multiplying the grayscale data with a gain corresponding to the variable capacitance value, The first drive circuit is, A driver characterized by supplying the data signal to the signal supply line based on the second grayscale data.

8. In the driver described in claim 1, The first feedback capacitor is The pair of switches and capacitors arranged in series between the signal supply line and the inverting input node of the operational amplifier includes a plurality of first switch groups and first capacitor groups arranged in parallel, The second feedback capacitor is The driver is characterized in that the pair of switches and capacitors arranged in series between the inverting input node and the predetermined potential node of the operational amplifier includes a plurality of second switch groups and second capacitor groups arranged in parallel.

9. In a driver according to any one of claims 1 to 7, A driver characterized by including an initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier.

10. In a driver according to any one of claims 1 to 7, The first drive circuit is, A capacitor drive circuit that outputs first to nth capacitor drive voltages (where n is an integer of 2 or more) corresponding to the grayscale data to the first to nth capacitor drive nodes, A capacitor circuit having first to n capacitors arranged between the signal supply line and the first to n capacitor drive node, A driver characterized by including [this].

11. In a driver according to any one of claims 1 to 7, Includes a control circuit for controlling the first drive circuit, The first drive circuit is, A group of first drive transistors is arranged between the node to which the high-potential power supply voltage is supplied and the signal supply line, A second group of drive transistors is positioned between the node to which the low-potential power supply voltage is supplied and the signal supply line, Includes, The aforementioned control circuit is A driver characterized by controlling each transistor in the first drive transistor group or each transistor in the second drive transistor group to be turned on or off based on the aforementioned grayscale data.

12. In a driver according to any one of claims 1 to 7, A driver characterized by including a voltage shift circuit that is electrically connected to the inverting input node of the operational amplifier and shifts the voltage of the inverting input node.

13. In the driver described in claim 12, The aforementioned voltage shift circuit is A driver characterized by setting different initialization voltages for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period at the inverting input node of the operational amplifier, based on a polarity inversion signal.

14. A first drive circuit that supplies data signals to the signal supply lines of an electro-optical panel based on grayscale data, A second drive circuit is electrically connected to the signal supply line and includes an operational amplifier, an output capacitor with one end electrically connected to the output node of the operational amplifier and the other end electrically connected to the signal supply line, a first feedback capacitor which is a variable capacitance capacitor with one end electrically connected to the inverting input node of the operational amplifier and the other end electrically connected to the signal supply line, first to m voltage output capacitors (where m is an integer of 2 or more) with one end electrically connected to the inverting input node of the operational amplifier, and first to m voltage output circuits which output voltages based on the grayscale data to the other end of the first to m voltage output capacitors, A driver characterized by including [this].

15. In the driver described in claim 14, The aforementioned operational amplifier, A driver characterized by being composed of transistors with a voltage rating lower than that of the transistors constituting the first drive circuit.

16. In the driver described in claim 15, A driver characterized in that the source-drain distance of the transistors constituting the first drive circuit is longer than the source-drain distance of the transistors constituting the second drive circuit, or the thickness of the gate insulating film of the transistors constituting the first drive circuit is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

17. A driver according to any one of claims 1 to 7, The aforementioned electro-optical panel, An electro-optical apparatus characterized by including [a certain component].

18. An electronic device characterized by including a driver as described in any one of claims 1 to 7.

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