Compact delay lines and associated circuitry beneficial to broadband phased array systems

Abstract

The phased array system includes a tunable delay element having active delay elements and passive delay elements. A second resolution by the passive delay elements is smaller than the first resolution by the active delay elements, the resolution corresponding to the delay applied to the input signal and having discrete steps for the phases at which the delay elements are operable. For multiple sets of tunable delay elements, the calibration process sets, for one set of delay elements, all but the nth active delay element and the passive delay elements to a first phase and the nth active delay element to a second phase. In the second set of delay elements, all of the active delay elements are set to the first phase and the passive delay elements are set to the second phase. The phase difference is detected and adjusted between the two sets to meet a criterion.

Description

[Technical Field]

[0001] The present invention generally relates to a communication system, and more particularly to a communication device having a delay line and a phased array antenna system. [Background technology]

[0002] The fine resolution of tunable RF (radio frequency) delay lines is critical in many applications, including phased array radars with beam steering. Most conventional implementations of RF delay lines use multiple switches to vary the capacitance and inductance along the line. To improve resolution, the unit sizes of the switches, capacitors, and inductors should be reduced. However, parasitic effects and losses still limit the minimum implementable size.

[0003] While transmission lines with tunable elements can be used, their dimensions are comparable to the wavelength of the waveform. The size of the transmission line is more costly than individual transistors or integrated circuits.

[0004] Therefore, achieving high bandwidth performance is a challenge. [Overview of the Initiative]

[0005] This section is for illustrative purposes only and not to limit.

[0006] In exemplary embodiments, the apparatus comprises a phased array system. The phased array system comprises a set of tunable delay elements comprising at least one active delay element and at least one passive delay element, wherein at least one active delay element provides a first resolution and at least one passive delay element provides a second resolution. The second resolution is smaller than the first resolution, and the resolutions correspond to the delay applied to the input signal by the corresponding one of the active or passive delay elements. The first resolution is a first set of individual steps for the phase on which at least one active delay element can operate, and the second resolution is a second set of individual steps for the phase on which at least one passive delay element can operate. The number of individual steps in the first set is less than the number of individual steps in the second set.

[0007] Another exemplary embodiment is an apparatus comprising a phased array system and a control circuit mechanism. The phased array system comprises a plurality of sets of tunable delay elements, each set comprising at least one active delay element and at least one passive delay element. The at least one active delay element provides a first set of resolution, and the passive delay elements provide a second set of resolution. The number of first sets is less than the number of second sets. The active delay element comprises: a first circuit mechanism comprising a first input stage and a first scaling factor stage, wherein the first input stage outputs to the first scaling factor stage, and the first scaling factor stage adjusts a first scaling factor based on the input to the first scaling factor stage; a second circuit mechanism comprising a second input stage and a second scaling factor stage, wherein the second input stage outputs to the second scaling factor stage, and the second scaling factor stage adjusts a first scaling factor based on the input to the second scaling factor stage; and an adder that adds the outputs from the first and second scaling factor stages to produce an output to the active delay element, wherein adjusting the inputs to the first and second scaling factor stages selects one of a first set of resolutions. The control circuit mechanism is connected to the phased array system and is configured to select and set delays for at least one active delay element and delays for at least one passive delay element for multiple sets of tunable delay elements by using inputs to at least first and second scaling factor stages.

[0008] In a further exemplary embodiment, the method includes performing a calibration process on a phased array system. The phased array system comprises a plurality of sets of tunable delay elements, each set comprising at least one active delay element and at least one passive delay element. The at least one active delay element provides a first set of resolution, and the passive delay element provides a second set of resolution. The number of first sets is less than the number of second sets. The calibration process includes setting all active delay elements in the first set of the sets, except for the nth active delay element, to a first phase, setting the passive delay element in this set to a first phase, and setting the nth active delay element in this set to a second phase. The calibration process also includes setting all active delay elements in the second set of the sets to a first phase, and setting the passive delay element in this set to a second phase. The calibration process further includes detecting the phase difference between the outputs of a first and second set of tuneable delay elements and adjusting the first and second inputs to the first and second scaling factor stages of an nth active delay element until the phase difference meets a criterion. The calibration process also includes storing one or more codes that indicate the first and second inputs to the nth active delay element as calibration points. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram for a broadband timed array with real-time delay, as well as a block diagram of the corresponding input and output signals. [Figure 1A] Figure 1 is a graph of the delay of the circuit mechanism. [Figure 1B] This is a phase graph of the circuit mechanism shown in Figure 1. [Figure 2] This figure shows how a timed array with real-time delay, as shown in Figure 1, can be approximated by a phased array with a narrowband phase shifter via a narrowband approximation. [Figure 3A] This is a diagram of beam squinting. [Figure 3B]It is a diagram of inter-symbol interference regarding the non-real-time delay effect on a phased array. [Figure 4A] It is a block diagram of an all-pass filter using active components. [Figure 4B] It is a structural diagram of an all-pass filter. [Figure 5] It is a diagram of an overview of an exemplary variable delay line using a serial all-pass filtering approach according to an exemplary embodiment. [Figure 5A] It is a diagram of the exemplary variable delay line of FIG. 5 using a more detailed example of a delay element in an exemplary embodiment. [Figure 6] It is a table of scaling factors, output current, and phase shift regarding all-pass (AP: all-pass), low-pass (LP: low-pass), or high-pass (HP: high-pass) filtering approaches in an exemplary embodiment. [Figure 7] It is a table of scaling factors, output current, and phase shift regarding AP, LP, or HP filtering approaches in an exemplary embodiment of variant 1(1) scaling. [Figure 8] It is a table of scaling factors, output current, and phase shift regarding AP, LP, or HP filtering approaches in an exemplary embodiment of variant 2(2) scaling. [Figure 9] It is a diagram of an exemplary delay line configured for calibration of broadband real-time delay and associated circuit mechanisms according to an exemplary embodiment. [Figure 10A] It is a diagram of phase comparison with an adjacent channel for hybrid delay calibration according to an exemplary embodiment. [Figure 10B] It is a diagram of phase comparison with an adjacent channel for hybrid delay calibration implemented in the context of a beam-forming array according to an exemplary embodiment. [Figure 11]This is a flowchart for calibrating two delay lines, also known as a phase shifter chain, according to an exemplary embodiment. [Figure 12] This figure illustrates the use of exemplary tunable delay lines for phase array applications according to an exemplary embodiment. [Figure 13] This figure shows the simulation results for a single active delay element 510 with inductive loading. [Figure 14A] This figure shows the simulation results for standard process (P) and temperature (T) corners, illustrating the amplitude. [Figure 14B] This figure shows the simulation results for standard process (P) and temperature (T) corners, illustrating the phase. [Figure 15A] This figure shows the simulation results of group delay variation for standard P and T corners, illustrating the amplitude. [Figure 15B] This figure shows the simulation results of group delay variations for standard P and T corners, illustrating the phase and group delay. [Modes for carrying out the invention]

[0010] The term “exemplary” is used herein to mean “to serve as an example, case, or illustration.” No embodiment described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other embodiment. All embodiments described in these “Modes for Carrying Out the Invention” are exemplary embodiments provided to enable those skilled in the art to carry out or use the Invention and are not intended to limit the scope of the Invention as defined by the claims.

[0011] As mentioned above, broadband performance can be challenging. Exemplary embodiments address various issues by, for example, combining a staggered analog (e.g., active) delay cell for coarse phase-shift with a T-line based fine delay line. This results in smaller area and lower power consumption compared to prior art. Additionally, multiple staggered phase-shifter stages may lead to process-invariant broadband performance.

[0012] In the context of staggered analog (e.g., active) delay cells, the term "staggered" refers to the frequency response. That is, if there are N stages in series (meaning the output of the Nth stage is supplied to the input of the (N+1)th stage), and the frequency of the maximum gain of the Nth stage is slightly shifted compared to the frequency of the maximum gain of the (N+1)th stage, then the combined frequency response of the two stages (or, in the general sense, the N stages), i.e., the overall frequency response, will be substantially constant over a wide temperature range.

[0013] Therefore, staggering of the frequency response makes the overall (series) frequency response nearly constant over a wide frequency range, resulting in process invariance. When measuring the PVT (process, voltage, temperature) for each process corner, the transconductance g m It can be adjusted.

[0014] Before describing exemplary embodiments, it is helpful to provide an overview of the technical domain to which these exemplary embodiments belong. One such domain includes a broadband timed array 100 with real-time delay, i.e., the circuit configuration shown in Figure 1. In Figure 1, there are N time delays 110, denoted as τ0, ..., (N-1)τ0, Nτ0. There is a distance d between each corresponding amplifier 115 (out of N amplifiers 115) and an antenna 120 (out of N antennas 120). The input signal 105 is given by τ in time pulseThe signal is shown to have been generated by (see reference number 130), and the power is shown at the same time. This pulse is also f c A power frequency spectrum is generated at a frequency with a bandwidth BW centered on the periphery (see reference number 140). Output signals 150 from an array of N antennas 120 are shown, in this case, the individual signals are θ s It is offset by this amount, where Δx = d sin(θ s )

[0015] As shown in Figure 1A, the introduced delay (τ) is a linear multiple of τ0. Figure 1B shows that the phase (θ) is a function θ = -ωτ. Note that the line 3τ0 in Figure 1A corresponds to the bottom phase curve in Figure 1B, and the curve of τ0 in Figure 1A corresponds to the top curve in Figure 1B.

[0016] The real-time delay for the broadband timed array 100 can be a challenge to actually achieve. One potential approach to achieving similar results is through the use of a phased array approximation. Moving on to Figure 2, this figure shows how the timed array with real-time delay in Figure 1 can be approximated via a narrowband approximation by a phased array with a narrowband phase shifter.

[0017] The broadband timed array 100 is shown in block 260 as in Figure 1B (see reference no. 210). A narrowband approximation around frequency ω0 is performed as indicated in reference no. 230, so that the phased array 200 contains N phase shifters θ0, ..., (N-1)θ0, Nθ0 instead of N time delays 110 (shown as τ0, ..., (N-1)τ0, Nτ0 in Figure 1). θ0 = ω0τ0 is used, and reference no. 220 indicates that this is a reasonable approximation of the real time delay centered around θ0.

[0018] The phased array 200 attempts to make a reasonable approximation of the broadband timed array 100 with real-time delay, but this presents problems. In particular, there is the phenomenon of non-real-time delay effects on the phased array. The use of phase shifters without real-time delay characteristics causes beam squinting (see Figure 3A) and intersymbol interference (see Figure 3B), limiting the radar signal bandwidth. For beam squinting in Figure 3A, please refer to Garakoui et al., "Phased-array antenna beam squinting related to frequency dependency of delay circuits," 2011 8th European Radar Conference, Manchester, UK, pp. 416-419, which states that "beam squinting, in words, means that the antenna pattern points to θ0+Δθ at frequency f0+Δf, rather than θ0, which was the direction it pointed to at frequency f0."

[0019] For the intersymbol interference in Figure 3B, please refer to Jang et al., "A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer," IEEE Journal of Solid-State Circuits, Vol. 54, No. 5, pp. 1304-1314, May 2019, doi:10.1109 / JSSC.2019.2894357. There, Figure 3B is shown as Figure 3(a), and the reference states, "In Figure 3(a), D1-D4 represent data symbols. Antenna 1 receives D2, while the other antennas receive D1. Since D1 and D2 are independent, D2 is merely a distortion of D1, and the array performance deteriorates after beamforming. This phenomenon is called array ISI because the subsequent symbol (D2) interferes with the current symbol (D1)."

[0020] There are several categories of phase shifters. One is narrowband phase shifters. One example is called RTPS (Reflection-Type Phase Shifter), in which the phase is constantly controllable by a varactor at the reflection end, but the operating bandwidth is limited and the loss variation with respect to control is relatively large. See Arun Natarajan et al., "W-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS," IEEE Transactions on Microwave Theory and Techniques, Vol. 63, No. 6, June 2015. See also Hanxiang Zhang et al., "A Microstrip line Reflection-Type Phase Shifter for 60 GHz Phased Array," 2019 IEEE / MTT-S International Microwave Symposium. Another is broadband phase shifters, such as artificial transmission lines with individual switches. See WHWoods, A. Valdes-Garcia, H. Ding, and J. Rascoe, "CMOS millimeter wave phase shifter based on tunable transmission lines," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, California, USA, 2013, pp. 1-4, doi:10.1109 / CICC.2013.6658442.

[0021] Another technique is the all-pass filter using active components. Figure 4A shows a block diagram of an all-pass filter using active components, and Figure 4B shows a structural diagram of the all-pass filter. See Garakoui et al., "Compact Cascadable gm-C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency," IEEE Journal of Solid-State Circuits, Vol. 50, No. 3, March 2015, pp. 693-703. A previous implementation of the all-pass filter uses a cascade of gm-C (transconductance-capacitance) structures. Figure 4A shows two amplifiers 1 and 2, amplifier block 410, and adder 420. The structural diagram shows that the amplifiers have transconductance-g m This indicates that it is a transconductor amplifier having a capacitor C, value 1 / g m A resistor having a transconductance of -2g m It is equipped with another transconductor amplifier having the following: These all-pass filters have the following problems.

[0022] 1) These are inherently nonlinear.

[0023] 2) The cascade of the two active stages leads to greater distortion.

[0024] 3) The use of capacitance is suppressed at mmW (millimeter wave) frequencies due to the low Q factor.

[0025] 4) These require an additional stage to provide impedance matching.

[0026] 5) No tuning mechanism is provided to adjust the phase shift.

[0027] Another possibility is to use active interconductors around the T-line (transmission line). See W. Lee and A. Valdes-Garcia, "Tunable Delay Line Using Distributed Inductive / Capacitive Miller Effect," 2018 IEEE / MTT-S International Microwave Symposium-IMS, Philadelphia, Pennsylvania, USA, 2018, pp. 1445-1448, doi:10.1109 / MWSYM.2018.8439492.

[0028] Having provided an overview of the technical domain to which the exemplary embodiment belongs, the exemplary embodiment will now be described. In contrast to what has been described, the exemplary embodiment includes a variable delay line using a series all-pass filtering approach.

[0029] Moving on to Figures 5 and 5A, Figure 5 provides an overview of an exemplary variable delay line using a series all-pass filtering approach according to an exemplary embodiment, while Figure 5A shows the exemplary variable delay line of Figure 5 with a more detailed example of the delay element.

[0030] In Figures 5 and 5A, the delay line 500 includes multiple delay elements 510, 510-1, ..., in this case each of these delay elements 500 is considered to be similar, with one delay element 510 shown as an overview in Figure 5 and in more detail in Figure 5A. There are also fine delay elements 530, such as T-line or analog type, which are also called real-time delay elements in Figure 5A. In these examples, the input 501 of the delay line 500 is connected to a delay element 510, and the output of the delay line 500 is the output of a delay element 530. The delay elements 510 are sometimes referred to as "coarse" delay elements in this specification because the delay caused by the delay element 510 is typically greater than the delay caused by the "coarse" delay element 530. The order of the coarse 510 and fine 530 delay elements is interchangeable. Although multiple coarse delay elements 510 and a single fine delay element 530 are shown, it should be noted that these may be modified (for example, a single coarse delay element 510 may be used, or multiple fine delay elements 530 may be used, or only a coarse delay element 510 may be used).

[0031] In Figure 5, delay elements are indicated by D to indicate that they are delay elements. On the other hand, in Figure 5A, the coarse delay element 510 is assumed to have an adjustable phase Φ (indicated by the arrow) to zero or 45 degrees, or possibly zero, 22.5 and 45 degrees, or zero or 90 degrees, or similar, while the fine delay element 530 is assumed to have a finer phase ψ that can increase in very small increments, such as 1 percent of the phase shift from zero to 45 degrees.

[0032] The delay elements 510 (and 530) may also be considered phase shifters, and it should be noted that the phase is also modified by the delay elements. For clarity, however, this circuit mechanism will still be referred to primarily as a delay element in this specification.

[0033] In the overview of Figure 5, the coarse delay element 510 is shown to have an input 591 with a voltage V which is also the input 501 to the first coarse delay element on the delay line 500, and an output 598. The input 591 to the coarse delay element 510-1 should be the output 598 of the previous delay element 510. That is, the input to a given delay element 510-1 comes from the output of the previous delay element 510 on the delay line 500.

[0034] Input 591 is divided into two degenerate input (i / p) stages 590, namely stage 1 590-1 and stage 2 590-2, each of which is coupled to a corresponding scaling factor stage 595, namely factor 1(α) 595-1 and factor 2(β) 595-1. Scaling factors α and β are produced and manipulated via stage 595 as described with reference to Figure 5A. The outputs 596-1 and 596-2 of scaling factor 595 are added by adder 597, the output of which is output 595 of delay element 510.

[0035] Referring to Figure 5 (and Figure 5A), the following comments are added.

[0036] [1] Input 591 is supplied to two input stages 590-1 and 590-2. Input 591 may be single-ended or differential.

[0037] [2] Input stages 1 590-1 and 2 590-2 provide different individual phase shifts (various combinations are possible, such as zero and 45, or zero, 22.5, and 45 degrees).

[0038] [3] Scaling factors α and β are implemented in current mode (e.g., via current steering).

[0039] [4] The sum of the two paths 596-1 and 596-2 is zero and pole, and the sum is performed in current mode.

[0040] [5] The poles and zeros lead to the formation of an all-pass filter, which results in delay.

[0041] [6] Output matching may be performed using a broadband load (using passive L / C, inductance / capacitance, and components).

[0042] [7] Bypassing this stage (coarse delay element 510) is achieved by setting β=0 (typical examples include stage 1 590-1 which uses a resistive element and stage 2 590-2 which uses a reactive element).

[0043] [8] Degeneracy improves linearity and matching between i / p transistors.

[0044] In Figure 5A, the delay element 510 comprises a transformer (Xfmr) or balun 520, as well as two circuits 580 and 585. Input 591 from Figure 5A is shown as V+ and V-, i.e., one input 591 having voltage V+ and its inverse V-. Circuit 580 includes circuitry for a degenerate input (i / p) stage 1 590-1 and a scaling factor 1(α) stage 595-1. The scaling factor 1(α) stage 595-1 includes a set of transistors 540 corresponding to the scaling factor α, the set including transistors 540-1, 540-2, 540-3, and 540-4. Circuit 580 also includes a degenerate i / p stage 1 590-1, which includes transistors 550-1 and 550-2, impedance 570, and current sources 560-1 and 560-2. Circuit 585 includes circuitry for a degenerate input (i / p) stage 2 590-2 and a scaling factor 2(β) stage 595-2. The scaling factor 1(β) stage 595-2 includes a set of transistors 545 corresponding to the scaling factor β, the set including transistors 545-1, 545-2, 545-3, and 545-4. The degenerate i / p stage 2 590-2 includes transistors 555-1 and 555-2, impedance 575, and current sources 565-1 and 565-2.

[0045] The degenerate i / p stage 590 may also be called a mutual conductor as they convert an input voltage to an output current via the corresponding {Q1,Q2}, where {Q1,Q2} are {Q1A,Q1B} for transistors 550-1 and 550-2 and {Q2A,Q2B} for transistors 555-1 and 555-2. The scaling factor stage 595 may be considered a current steering device. These internal structures are called differential structures, which bring about structural symmetry. For example, each of transistors 540-1, 540-2, transistors 540-3, 540-4, transistors 545-1, 545-2, transistors 545-3, 545-4, transistors 550-1, 550-2, and transistors 555-1, 555-2 has a differential structure.

[0046] The illustrated transistors are BJTs (bipolar junction transistors). The basic technology should work with either MOS (metal oxide semiconductor) transistors or BJTs. For BJTs, the terminals should be the base, emitter, and collector. For MOS, the corresponding terminals should be the gate, source, and drain. The base or gate terminal may be considered a control terminal, and the base / emitter or source / drain can be input / output terminals.

[0047] In this case, the adder 597 includes connections to signal lines that go to and from the transformer or balun 520. The output 598 is shown as being the corresponding currents i in and i out as shown.

[0048] The scaling factor α represents a small portion of the current steered to the load (e.g., bias), and is variable only by V1-V2 in the scaling factor 1(α) stage 595-1. Similarly, the scaling factor β represents a small portion of the current steered to the load, and is variable only by V1-V2 in the scaling factor 2(β) stage 595-2. Once the circuit mechanism for the coarse delay element is fixed, the voltages for V1-V2 in the scaling factor 1(α) stage 595-1 and for the scaling factor 2(β) stage 595-2 depend on how the phase is selected.

[0049] The coarse delay of the coarse delay element 510 is determined by the real and imaginary amplifier transconductance g using a bias current, a degenerate element, or both. m By varying Z1, the system can be tuned at individual steps. Scaling of the transconductance in the real, imaginary, or both parts leads to a change in delay. Z1 and Z2 are impedances that control the delay, DC gain, and input impedance matching, and these functions can be independent or interdependent. Degeneracy can result in higher linearity and input impedance matching compared to not using degeneracy. Regarding degeneracy, this may include the addition of resistors, capacitors, or inductors, or a combination thereof, or other circuit mechanisms to adjust the delay (e.g., including phase) of the coarse delay element 510. These degeneracy elements are not shown.

[0050] Degeneracy is a well-known and widely used technique. The idea of ​​degeneracy is that any amplifier (which can be voltage / current or voltage / current, and all combinations depend on the type of amplifier being dealt with) has an input range over which the amplifier remains linear (i.e., the output is substantially linear with respect to the input). Based on quiescent current, the output signal should have a maximum value, and therefore, the same output signal should be obtained with a larger amplitude at inputs with lower gain. Reduced gain is known as degeneracy, and the amplifier operates linearly over a larger input swing than that of a non-degenerate amplifier.

[0051] Using Z2 as an inductive element leads to a virtually constant input impedance, making it possible to achieve a 50Ω input match. Thus, one example is when Z1 is a resistor and Z2 is an inductor, but other configurations are possible. When Z2 is an inductor of value = L, this becomes a frequency-domain impedance of Z = jωL.

[0052] For the analysis, an example is selected in which Z1 is used as a resistor with value R, and Z2 is used as an inductor with a large Q factor and inductance L. Consider the following analysis for the input current.

[0053]

number

[0054]

number

[0055] Here, Z1 and Z2 have equal transconductances, i.e., g m1 =g m2 =gm We believe this to be the case. This simplifies the equation as follows.

[0056]

number

[0057] g m Regarding R≪1, and

number

[0058] The variable delay line 500 may be used for all-pass (AP), low-pass (LP), or high-pass (HP) filtering approaches. Figure 6 is a table of scaling factors, output currents, and phase shifts for AP, LP, or HP filtering approaches in an exemplary embodiment. Due to the constant gain with respect to frequency, the first two (AP) rows may be chosen as the execution case, while the other options may lead to gain variations with frequency.

[0059] Another exemplary case is the 1(1) scaling variation, in which case g m R=1. In this case,

number

[0060] Another exemplary case is the deformed 2-scaling, in which case g m R=2. In this case,

number

[0061] Another example concerns generic scaling, in this case, g m R=N. In this case,

number

number

number

number

number

[0062] Exemplary embodiments for implementations of delay lines have been described. Additional details regarding the use of delay lines are provided here.

[0063] Calibrating delay lines can be beneficial. Exemplary theories regarding the calibration of broadband real-time delays include the following:

[0064] 1) The inductance value remains the same across the P and T (process, temperature) corners.

[0065] 2) The Q factor changes at the P and T corners.

[0066] 3) One example is to excite delay lines for multiple frequencies and measure the delay using, for example, the least-squares mean (LMS) algorithm.

[0067] 4) The phase difference may be detected by observing the output from the adjacent delay element.

[0068] 5) The accuracy of the passive delay element 530 may be used as a benchmark.

[0069] 6) The coarse delay elements 510 may be calibrated one at a time.

[0070] One possible calibration procedure is as follows:

[0071] 1) By changing the bias current, the transconductance (g m ) changes.

[0072] 2) Use two parts of the DAC, one of which is a constant g m This is a fixed part that provides [something].

[0073] 3) Use the second part of the DAC, which is the corrected part of the DAC based on the LMS.

[0074] 4) Provide multiple frequencies to the hybrid delay cell, one frequency at a time.

[0075] 5) Complete the delay by performing a least-squares mean (LMS) mathematical fit. The intention of using the LMS algorithm is to determine the scaling factors (e.g., coefficients) α and β so that the phase shifter is optimized to operate over a wide frequency range so that the delay is accurately realized.

[0076] Referring to Figure 9, this figure shows an exemplary delay line 500-1 and associated circuitry configured for broadband real-time delay calibration, implemented in a device 900 (such as a receiver or transmitter) according to an exemplary embodiment. A control circuitry 910 is shown, in this example comprising DACs (digital-to-analog converters) 920, 930, and 940, as well as one or more memories 960 (equipped with CPC (computer program code) 950). The control circuitry 910 may comprise one or more special-purpose or general-purpose processors, or application-specific system processors, or other processors such as microcontrollers or DSPs (digital signal processors). Alternatively or additionally, the control circuitry 910 may comprise other hardware such as programmable logic devices, application-specific integrated circuits (ASICs), very large-scale integrated circuits (VLSIs), or the like. The control circuitry 910 may also be programmable, for example, via computer program code 950 in one or more memories 960. One or more memories 960 may include read-only memory, random-access memory, solid-state memory, or any other memory. The CPC 950 or the control circuit mechanism 910 or both may have program and data storage, such as programmed to perform the processes described herein and to store data acquired or used herein. Assuming that the CPC 950 is used, one or more memories 960 and computer program code 950 may be configured by the control circuit mechanism 910 to cause the device 900 to perform one or more of the operations described herein.

[0077] This example has a control circuit mechanism 910 comprising three DACs 920, 930, and 940. This is for ease of reference and clarity, and these DACs can be combined into a single DAC or other corresponding circuit mechanism, or further subdivided. DAC 920 has a constant g mThis is the fixed part of the DAC that provides the constant g. m This is the correction section that applies the corrections to be added. The correction section 930 may use stored codes, in which case each code corresponds to a specific output for D2x (see below). DAC940 is specifically for the fine delay element 530 and further generates an output for adjusting the phase of the fine delay element 530.

[0078] The DAC920 has a constant g. m The DAC930 outputs D1, which is the bias, and D2x, where "x" is A, B, C, ..., and is the corrected DAC signal for the xth delay element coefficient (and the corrected DAC930 is adjusted from the calibration). The bias (such as bias 1, bias 2, bias 3, ..., corresponding to each coarse delay element 500, 500-1, 500-2, ...) is the sum of D1 and D2x, and adjusts the voltage for V1-V2 at the scaling factor 1(α) stage 595-1 and for the scaling factor 2(β) stage 595-2. Thus, a single bias for one delay element 510 is a constant g m The bias may include up to four other signals, as well as two for V1 and V2 in the scaling factor 1(α) stage 595-1, and two more for V1 and V2 in the scaling factor 2(β) stage 595-2. It is also possible to have fewer signals in the scaling factor stages 595-1 and 595-2.

[0079] One exemplary procedure for process, voltage, and temperature (P, V, T) calibration is as follows. This is an overview of one possible process, and Figure 11 includes another example of such a process.

[0080] 1) Select the operating frequency (F1).

[0081] 2) Two adjacent delay elements are used for phase shifter chain 1 (PS1) and phase shifter chain 2 (PS2).

[0082] 3) Maintain specific settings for the coarse 1 510 and coarse 2 510-1 delay elements (min = minimum phase and max = maximum phase, in either min or max).

[0083] 4) Set the coarse delay 510-2 to the lowest target phase shift (e.g., 0°, zero degrees) and the fine delay 530 to a known intrinsic phase shift (e.g., 45°): PS1.

[0084] 5) Set coarse phase 3 to a 45° phase shift and fine phase shift to 0°: PS2.

[0085] 6) Create a phase error difference between PS1 and PS2 by one of the following methods: (a) subtracting the signals, (b) multiplying them so that the vector product is zero (e.g., a mixer-based approach), or (c) performing null detection in the beam pattern.

[0086] 7) Perform the above steps at multiple frequencies F2, F3, ...

[0087] 8) Minimize errors by setting up D2C using the LMS algorithm.

[0088] 9) Repeat the above steps separately for coarse 1 and coarse 2 delay elements.

[0089] 10) Obtain the settings for D2A and D2B.

[0090] 11) The digital algorithm can compensate for residual errors after calibration for further accuracy, if necessary.

[0091] One example of determining the difference in phase errors (see (6) above) is to use a phase comparator. Figure 10A shows a phase comparison of adjacent channels for hybrid delay calibration according to an exemplary embodiment. Two phase shifter chains PS1 1000-1 and PS2 1000-2 are shown, coupled to a phase comparator 1010 via corresponding outputs 1040-1 and 1040-2. Each of the phase shifter chains PS1 1000-1 and PS2 1000-2 is a version of the delay line 500 as described above. The phase shifter chain PS1 1000-1 includes an active broadband time delay section 1020-1 containing several coarse delay elements 510, and a passive broadband real time delay section 1030-1 containing fine delay elements 530. The phase-shift channel PS2 1000-2 includes an active broadband time delay section 1020-2 containing several coarse delay elements 510, and a passive broadband real time delay section 1030-3 containing fine delay elements 530.

[0092] The phase comparator 1010 can be implemented in multiple ways. For example, it may be implemented using a baseband implementation, such as by using a phase detector or by measuring the null of the beamformer. Alternatively, it may be implemented using an RF implementation, such as by using a mixer as a phase detector or by using a subtractor approach.

[0093] Moving to Figure 10B, this figure shows a phase comparison of adjacent channels for hybrid delay calibration performed in a beamforming array setting according to an exemplary embodiment. There are multiple (K) phase shifter channels 1000-1, 1000-2, ..., 1000-k used for the beamforming array. Each phase shifter channel 1000 includes multiple (N) active stages 1020 and one passive stage 1030. This figure shows how phase shifter channel 1000-1 can be tested when phase shifter channels 1000-2, ..., 1000-k have their N active stages 1020 set to zero degrees and their passive stage 1030 set to 45 degrees. Meanwhile, the "n" and corresponding arrows in phase shifter channel 1000-1 indicate delay elements set to various coarse values, such as 45 degrees.

[0094] The following observations are made regarding the calibration of broadband real-time delay.

[0095] 1) The BEOL (Below-Earth) based inductance and capacitance remain the same across the PVT corners.

[0096] 2) The Q factor changes at the PVT corner, but it does not affect the phase.

[0097] 3) It is not necessary to perform delay calibration of the active phase shifter over a wide frequency range.

[0098] The inventors have determined that calibrating active components using the accuracy of passively tunable delays as a benchmark is one method for calibrating delay lines.

[0099] Figure 11 is a flowchart for the calibration of two delay lines, also known as a phase shifter chain, according to an exemplary embodiment. Figure 11 provides a more detailed explanation of what has already been briefly described above. Figure 11 also illustrates the operation of one or more exemplary methods, the result of executing computer program instructions embodied in computer-readable memory, a function performed by logic executed in hardware, or interconnected means for performing the function according to the exemplary embodiment, or a combination thereof. The operation of Figure 11 is assumed to be controlled by a control circuit mechanism 910. It should be noted that the control circuit mechanism 910 may follow a program supplied by the user for some or all of this flow (e.g., in computer program code 950). DACs 920 and 930 are controlled by the control circuit mechanism 910.

[0100] The flow in Figure 11 begins at block 1105, and in block 1110, the control circuit mechanism 910 has a constant g. m The DAC920 is configured to set the bias. The control circuit mechanism 910, in block 1115, sets N frequencies {F1, F2, F3, ..., F NSelect}. In block 1120, the control circuit mechanism 910 sets an intermediate code for DAC correction of DAC 930. The intermediate code is a code that lies in the middle of a range of codes from which the correction can vary, in this case the code corresponds to the correction for the scaling factor stage 595, i.e., factor 1(α)595-1 and factor 2(β)595-1. For example, one example has a correction term given by V1-V2, or ΔV. Typically, one way this can be done is V1=V0+ΔV and V2=V0-ΔV, where V0 is the bias voltage supporting the quiescent operation. Block 1120 (and see also block 1130) may therefore include setting one or more of ΔV for the scaling factor stage 595, i.e., factor 1(α)595-1 and factor 2(β)595-1. These may be set independently, or two may be related to a single voltage difference. constant g m There is an applied total bias, which is the sum of the bias of the code and the bias corresponding to the intermediate code (or multiple biases).

[0101] The flow proceeds to block 1121, where blocks 1130 and 1125 are executed. In block 1130, for the phase shifter chain PS1 (delay line 500), the coarse delay elements 510, which are designated as active elements ("active"), are set to zero degrees (0°) for [1:n-1, n+1:N]. In other words, there are N delay elements 510, and all but the nth one are set to zero degrees. For PS1, the active [n] is set to 45°. The fine delay elements 530, which are designated as passive elements ("passive"), are set to zero degrees (0°). In block 1125, for the phase shifter chain PS2 (another delay line 500), all coarse delay elements 510, which are designated as active elements ("active"), are set to zero degrees (0°) for [1:N]. In other words, there are N delay elements 510, and all are set to zero degrees. The precision delay element 530, which is instructed to be a passive element ("passive") by the PS2, is set to a 45-degree (45°) setting.

[0102] In block 1135, the phase difference (PD) is detected. Block 1140 determines whether the PD is zero. If the PD is not zero, block 1180 = no, and the flow proceeds to block 1185, where the DAC code of PS1 for the nth active delay element 510 is adjusted, and the flow returns to block 1120. This may be an increase or decrease in the code, and it should be noted that block 1185 may then be executed to determine whether to proceed in the direction of the current (increase or decrease) or change direction. For example, if an increase was previously performed and this resulted in a higher PD, a decrease may be performed in block 1185.

[0103] If PD is zero (for example, or within some variance range of zero), block 1145 is yes, and the flow proceeds to block 1150, where it is determined whether all active segments (i.e., coarse delay elements 510) have been performed. If not, block 1174 is no, and the flow proceeds to block 1175, where n=n+1, and the flow returns to block 1130. If all active segments have been performed, block 1155 is yes, and in block 1170, it is determined that all frequencies have been performed. If not, block 1172=no, and the next frequencies are selected in 1190, along with the set of frequencies in block 1115. Note that for LMS analysis in block 1165, the DAC correction codes are stored frequency by frequency for use by the LMS algorithm.

[0104] If all frequencies have been performed, then block 1160 = yes, the LMS algorithm is executed, the DAC is completed (block 1165), and then g for DAC920 m This means that the code for the bias and correction for each of the coarse delay elements of the DAC930 is known and stored. The flow ends in block 1167.

[0105] Figure 11 shows an array with two delay elements, but this can be extended to a fully phased array with three or more delay elements. Differential calibration is repeated for adjacent elements to cover all elements in the phased array.

[0106] Additionally, Figure 11 shows examples of zero and 45 degrees for active delay elements, but the same process may be carried out if the active delay element has more phases (e.g., 90 degrees as well) or different phases (e.g., 0, 22.5, and 45 degrees), for example, as long as the passive delay element supports these phases.

[0107] Figure 12 illustrates the use of exemplary tunable delay lines for a phase array application according to an exemplary embodiment. Device 900-1 is a receiver comprising 16 elements 1220-0 to 1220-15, each of which accepts a 60 GHz input and has an LNA (Low Noise Amplifier), followed by the corresponding delay lines 500-0 to 500-15 and a VGA (Variable Gain Amplifier). Digital beam tables 1050-0 to 1050-15 feed the corresponding delay lines 500-0 to 500-15 and VGA. These are input to a passive / active coupler block 1230, which includes 16 passive couplers 1235 in a first stage, then 4 passive couplers in a second stage, then 2 active couplers 1240, and finally a single passive coupler that outputs to a receiver core 1210.

[0108] The receiver core 1210 includes at least a digital I / O (input / output) register array and a beam control 1260 used to control the receiver core 1210. There is a multiplier that accepts x3 (3 times) from the combiner, which also outputs to a divider (÷2) that outputs from 16.66 GHz to 18.52 GHz, and the divider outputs to an IQ phase rotater. The multiplier outputs to a frequency controller that performs frequency adjustment from 8.33 GHz to 9.26 GHz, and then to an amplifier. The output of the amplifier goes to an AM detector, another multiplier, a frequency controller, an amplifier, another frequency controller, and another amplifier to produce an I output. The output of the amplifier also goes to an FM discriminator, another multiplier, a frequency controller, an amplifier, another frequency controller, and another amplifier to produce a Q output.

[0109] Device 900-1 may also include a control circuit mechanism 1210 that controls the operation of the device. This control circuit mechanism 910, along with other elements in the device, should control each of the 16 elements 1220-0 through 1220-15.

[0110] Moving on to Figure 13, this figure shows the simulation results for a single active delay element 510 with inductive loading. Four curves are shown: curves 1310 and 1320 relate to amplitude in decibels (dB) (see vertical axis V(dB) on the right), and curves 1330 and 1340 correspond to 1310 and 1320, respectively, and show the phase in degrees (see vertical axis V(degrees) on the left). The horizontal axis represents frequency (GHz) from 24.0 to 30.0 GHz. Point 1310-1 is 1.699 dB, and point 1310-2 is 1.378 dB. Point 1320-1 is 1.506 dB, and point 1320-2 is 1.558 dB. Point 1330-1 is -10.39189 degrees, and point 1330-2 is -47.75134 degrees. Point 1340-1 is -47.35073 degrees, and point 1340-2 is -94.09481 degrees.

[0111] As shown in the figure, the amplitude difference has a linear phase and a variation of ~10 degrees across the bandwidth, with a bandwidth of <200 mdB. When using two active delay elements 510, each can provide a 45-degree shift, as in this example. Thus, {0, 45, 90} degrees may be obtained from the two delay elements. Addition of passive fine delay lines for 45-degree interpolation. This may reduce the size of the passive phase shifter by four times per channel.

[0112] Furthermore, Figure 13 may be used to illustrate the following: One aspect of the exemplary embodiment is enabling the natural relative frequency characteristics of an active, coarse variable delay element 510. One idea is to create a phase-frequency gradient that causes the active delay element to behave like a real-time delay over a wide frequency range, similar to the passive delay element described. The active delay takes up a much narrower area and provides overall benefits.

[0113] Regarding the more detailed phase-relative frequency gradient, the real-time delay has a specific phase-relative frequency gradient, as shown in Figure 1B. The physical delay corresponds to the real-time delay, and in this case, at low frequencies, a given phase shift (θ1 = 2πf low There is a corresponding delay (θ² = 2πf), but at higher frequencies, the delay remains the same, but the phase shift increases (θ² = 2πf). high / delay>θ1(f low >f high Typically, active phase shifters do not have this characteristic. Instead, active phase shifters typically provide characteristics similar to those shown in Figure 1A. Having the phase profile of Figure 1B is preferable to having the phase profile of Figure 1A, as shown in comparable examples in Figures 3A and 3B, and Figures 4A and 4B. To achieve this, exemplary circuits herein can have characteristics similar to Figure 1B despite being active circuits, as shown by Figure 13. That is, Figure 13 shows characteristic variations of phase with frequency similar to those in Figure 1B.

[0114] Device 900 and similar devices may be tested for process, voltage, and temperature (P, V, T, or PVT) variations and corresponding corners. Figures 14A and 14B show simulation results over typical process (P) and temperature (T) corners, where Figure 14A shows amplitude and Figure 14B shows phase. Figures 15A and 15B show simulation results for group delay variations over typical P and T corners, where Figure 15A shows amplitude and Figure 15B shows phase and group delay.

[0115] There are several options for measuring corners for this purpose, as described in the nomenclature that may be used, including: The nomenclature S_HV_LT means that this is the “slow” process corner (first letter S), high voltage (second term HV), and low temperature (third term LT). The nomenclature S / F / N means slow / fast / nominal. The nomenclature HV / NV / LV means high voltage, nominal voltage, and low voltage. The nomenclature HT / NT / LT means high temperature, nominal temperature, and low temperature. Essentially, these are used to monitor the robustness of the design against process, voltage, and temperature variations of the transistor. The temperature is the junction temperature, not the ambient temperature. In Figures 14A, 14B, 15A, and 15B, the following nomenclature is shown and interpreted via the previous nomenclature: F_HV_LT, N_NV_RT, N_NV_NT, N_NV_HT, and S_LV_HT.

[0116] For Figures 14A and 14B, a multi-section staggered segment (e.g., delay element 510) can be used in series to achieve a substantially constant phase difference across the two phase settings. The bias current can also be of the P,T tracking type to compensate for fluctuations.

[0117] Figures 15A and 15B provide the phase derivatives of the phase-relative frequency plots shown earlier. These are for a single stage only, and variations can be reduced by a series approach.

[0118] Exemplary embodiments may be considered to implement a hybrid delay approach, for example, between a vector modulation-based implementation and a real-time delay implementation using microwave technology. This is in contrast to the prior art.

[0119] One prior art is a vector modulation-based implementation, which may be considered to have a relatively narrow bandwidth, resolution may be DAC (digital-to-analog converter) based or otherwise digitally controlled, and input matching works for a 50Ω input impedance. The area may be relatively compact, and the input is quadrature. The structure / configuration is active and yields gain. Another prior art is a real-time delay implementation using microwave technology, where the bandwidth may be relatively wide, resolution may be DAC (digital-to-analog converter) based or otherwise digitally controlled. Input matching for this has a low impedance preferred to reduce losses, and the area is relatively large (e.g., by the transmission line). The input can be single-phase or differential-phase, and the structure / configuration is generally passive and yields losses.

[0120] In contrast, the hybrid delay approach described herein combines the beneficial elements of both of these. For example, the exemplary embodiment may be applicable to wide bandwidths, and wide bandwidth or real-time delay is beneficial for phased array applications. The resolution may be DAC (digital-to-analog converter) based and provide digital control. Digital control is preferred for easy reconfiguration / calibration. The exemplary embodiment may provide input matching, such as a 50Ω input impedance. A 50Ω input impedance is preferred in several applications for seamless interface and placement in the architecture. The area may be compact for the exemplary embodiment, and for a given area, the use of transistors and similar devices provides greater density compared, for example, to the use of transmission lines. Having a compact area is preferred in several implementation forms for reducing losses and increasing the number of array elements. The input for the exemplary embodiment may be single-phase or differential-phase, and single-ended / differential is preferred in certain applications for signal distribution, for example, by using a balun to convert between them. The structure of the exemplary embodiment may be hybrid, such as providing signal gain, as this may be required in some implementations to maintain low power.

[0121] Without limiting in any way the scope, interpretation, or use of the claims set forth below, one or more technical effects and advantages of the exemplary embodiments disclosed herein include one or more of the following:

[0122] 1) The proposed delay line can reduce the area required for broadband phased array systems.

[0123] 2) The proposed delay line can provide power gain (unlike the passive delay line).

[0124] 3) The exemplary proposed delay line may provide an input impedance match to 50Ω.

[0125] 4) The exemplary embodiments can be used as single-ended or differential. For example, the exemplary embodiments can be configured for single-ended and differential signal paths.

[0126] 5) Exemplary embodiments can be used to provide a continuous delay (by using Z2 as a tunable transmission line or by changing α and β in small steps).

[0127] 6) Exemplary embodiments include g m This can be done to track P and T fluctuations by performing a ~1 / R operation.

[0128] 7) The order of the delayed cells (coarse, fine) can be changed to provide more functionality.

[0129] 8) Exemplary embodiments can be used instead of distortion cancellers, image rejection mixers, or clock delays.

[0130] 9) The techniques described herein can be used to implement RF (radio frequency) beamforming, LO (local oscillator) beamforming, or IF (intermediate frequency) beamforming, leading to broad flexibility. More specifically, a Cartesian approach of multiplying two waveforms, IF and LO, yields two terms, LO+IF and LO-IF. Beamforming, in practice, means providing different phase shifts to different elements of an array, as well as being possible to do with either LO or IF, and since RF is the linear sum and difference of the LO and IF terms, a phase shift in either one of these will be the same phase shift in the RF domain.

[0131] If necessary, the different functions discussed herein may be performed in different orders, simultaneously, or in combination. Furthermore, if necessary, one or more of the above functions may be selected or combined.

[0132] Various aspects of the present invention are described in the independent claims, and other aspects of the present invention include the described embodiments, or dependent claims having features of the independent claims, or other combinations of features from both, but not merely combinations expressly described in the claims.

[0133] The above describes exemplary embodiments of the present invention, but it is noted herein that these descriptions should not be considered in an restrictive sense. Rather, there are several variations and modifications that can be made without departing from the scope of the present invention as defined in the appended claims.

[0134] In a preferred embodiment of the present invention, there is a plurality of sets of tunable delay elements, each set comprising at least one active delay element and at least one passive delay element, wherein at least one active delay element provides a first set of resolutions, and the passive delay elements provide a second set of resolutions, the number of first sets being less than the number of second sets, and the active delay elements comprise a first circuit mechanism comprising a first input stage and a first scaling factor stage, wherein the first input stage outputs to a first scaling factor stage, and the first scaling factor stage adjusts a first scaling factor based on the input to the first scaling factor stage; and a second circuit mechanism comprising a second input stage and a second scaling factor stage, wherein the second input stage outputs to a second scaling factor stage Apparatus is provided herein comprising a phased array system comprising: a second circuit mechanism that outputs to a stage and a second scaling factor stage adjusts the first scaling factor based on the input to the second scaling factor stage; an adder that adds the outputs from the first and second scaling factor stages to produce an output to an active delay element, wherein adjusting the inputs to the first and second scaling factor stages selects one of a first set of resolutions; and a control circuit mechanism coupled to the phased array system and configured to select and set a delay for at least one active delay element and a delay for at least one passive delay element for a plurality of sets of tuneable delay elements by using the inputs to at least the first and second scaling factor stages. Preferably, the first input stage comprises an impedance Z1, and the second input stage comprises an impedance Z2, where Z1 and Z2 are impedances that control one or more of the delay, DC gain, or input impedance of the active delay element.Preferably, the first and second scaling factor stages are configured to perform current steering towards either impedance Z1 or impedance Z2, respectively, via the adjustment of a first voltage for each of the first and second scaling factor stages, and the active delay element is configured based on the operation of impedances Z1 and Z2, as well as current steering, to enable position-relative frequency characteristics in the active delay element in response to a second voltage being applied to the first and second input stages, the second voltage corresponding to the signal to be delayed. Preferably, impedance Z1 is a resistor and impedance Z2 is an inductor. Preferably, the first scaling factor stage includes a current steering device configured to respond to first and second voltage inputs to the first scaling factor stage by steering the amount of output current directed toward impedance Z1, and the second scaling factor stage includes a current steering device configured to respond to first and second voltage inputs to the second scaling factor stage by steering the amount of output current directed toward impedance Z2.Preferably, at least one active delay element comprises a plurality of active delay elements for a set of tunable delay elements, and the control circuit mechanism is configured to perform a calibration process for at least two of the sets of tunable delay elements, the calibration process comprising the control circuit mechanism setting all active delay elements in a first set of the sets to a first phase, setting the passive delay elements in this set to a first phase, and setting the nth active delay element in this set to a second phase, and the control circuit mechanism... The control circuit mechanism includes setting all active delay elements in a second set of tuneable delay elements to a first phase and setting passive delay elements in this set to a second phase; detecting a phase difference between the outputs of the first and second sets of tuneable delay elements and adjusting the first and second inputs to the first and second scaling factor stages of the nth active delay element until the phase difference meets a criterion; and storing one or more codes that indicate the first and second inputs to the nth active delay element as calibration points. Preferably, the first set of tuneable delay elements has N active delay elements, and the calibration process further includes the control circuit mechanism performing the following for each of the N active delay elements in the first set of tuneable delay elements: setting all active delay elements in the first set except the nth active delay element in the first set to a first phase, setting the nth active delay element in this set to a second phase, detecting the phase difference between the outputs of the first and second sets of tuneable delay elements, adjusting the first and second inputs, and storing the calibration points, which are stored for each of the N active delay elements in the first set of tuneable delay elements. Preferably, adjusting the first and second inputs to the first and second scaling factor stages of the nth active delay element until the phase difference satisfies a criterion includes the control circuit mechanism setting a constant bias to the first and second inputs and the control circuit mechanism setting a code corresponding to an amount of bias added to or subtracted from the constant bias, wherein the total bias of the first and second inputs is a constant bias added to the bias corresponding to the code, and the calibration point includes the code.Preferably, the code corresponds to a voltage change ΔV, where the first input is a voltage V1 and the second input is a voltage V2, with V1 = V0 + ΔV and V2 = V0 - ΔV, where V0 is a bias voltage supporting quiescent operation. Preferably, the first and second scaling factor stages have corresponding scaling factors α and β, and the calibration process further includes performing a calibration process for each of the N active delay elements in a first set of tunable delay elements, generating calibration points for each of the N active delay elements across a plurality of different frequencies, and performing a least-means-squares (LMS) algorithm using at least the calibration points for each of the N active delay elements across a plurality of different frequencies to determine scaling factors α and β such that the corresponding active delay elements are optimized to operate across a selected frequency range so that the delays of the active delay elements are accurately realized.

Claims

1. It is a device, The system includes a phased array system, and the phased array system is A set of tunable delay elements comprising at least one active delay element and at least one passive delay element, wherein the at least one active delay element provides a first resolution, and the at least one passive delay element provides a second resolution. The second resolution is smaller than the first resolution, and the resolution corresponds to the delay applied to the input signal by the corresponding one of the active delay element or the passive delay element. The first resolution is a first set of individual steps for a phase in which the at least one active delay element can operate, and the second resolution is a second set of individual steps for a phase in which the at least one passive delay element can operate, wherein the number of individual steps in the first set is less than the number of individual steps in the second set. Device.

2. The apparatus according to claim 1, wherein with respect to the at least one active delay element, the delay is programmed by adjusting the current in the at least one active delay element.

3. The apparatus according to claim 1, wherein the at least one active delay element provides at least two different delays as the set of separate steps.

4. The at least one active delay element comprises a plurality of delay elements, and the active delay element is A first circuit mechanism comprising a first input stage and a first scaling factor stage, wherein the first input stage outputs to the first scaling factor stage, A second circuit mechanism comprising a second input stage and a second scaling factor stage, wherein the second input stage outputs to the second scaling factor stage, An adder that adds the outputs from the first and second scaling factor stages to produce an output to the active delay element. The apparatus according to claim 1, comprising:

5. The first input stage has an impedance Z １ Equipped with, The second input stage has an impedance Z ２ Equipped with, Z １ and Z ２ However, the impedance is one or more of the delay, DC gain, or input impedance of the active delay element. The apparatus according to claim 4.

6. The first and second scaling factor stages, through the adjustment of the respective first voltages for the first and second scaling factor stages, control the impedance Z １ or impedance Z ２ The active delay element is configured to perform current steering to one of the two, and in response to the application of a second voltage to the first and second input stages, the impedance Z is configured to enable positional relative frequency characteristics in the active delay element. １ and Z ２ The apparatus according to claim 5, further configured based on the operation of the current steering, wherein the second voltage corresponds to a signal that will be delayed.

7. Impedance Z １ is a resistor, and the impedance Z ２ is an inductor, the apparatus according to claim 5.

8. The first input stage comprises two transistors in a differential configuration, the first transistor having a control input connected to the input voltage, the first input / output terminals of which are connected to the first scaling factor stage and the second input / output terminals of which are connected to the first current source, and the second transistor having a control terminal connected inversely to the input voltage, the first input / output terminals of which are connected to the first scaling factor stage and the second input / output terminals of which are connected to the second current source, and the impedance Z １ However, in the first input stage, it is connected between the second input / output terminals of the first and second transistors, The second input stage comprises two transistors: a first transistor having a voltage-connected control terminal, the first input / output terminal of which is connected to the first scaling factor stage and the second input / output terminal of which is connected to the first current source; and a second transistor having a control terminal inversely connected to the voltage, the first input / output terminal of which is connected to the first scaling factor stage and the second input / output terminal of which is connected to the second current source, wherein the impedance Z ２ However, in the second input stage, the second input / output terminals of the first and second transistors are connected, The apparatus according to claim 5.

9. The first scaling factor stage is the impedance Z １ The system includes a current steering device configured to respond to first and second voltage inputs to the first scaling factor stage by steering the amount of output current directed toward the first scaling factor stage, The second scaling factor stage is the impedance Z ２ The system includes a current steering device configured to respond to first and second voltage inputs to the second scaling factor stage by steering the amount of output current directed toward the second scaling factor stage. The apparatus according to claim 5.

10. The current steering device in the first scaling factor stage comprises two sets of differential structures each having two transistors, and each set is A first transistor having a control terminal connected to the first voltage and a first input / output terminal connected to a transformer or balun, A second transistor having a control terminal connected to the second voltage and a first input / output terminal connected to the supply voltage, Equipped with, The second input and output terminals of the first and second transistors are connected together. The second input / output terminal of the first set of the aforementioned sets is connected to the first input to the first input stage. The second input / output terminal of the second set of the aforementioned set is connected to the second input to the first input stage. The apparatus according to claim 9.

11. It is a method, The calibration process includes performing a calibration process on a phased array system, wherein the phased array system comprises a plurality of sets of tunable delay elements, each set comprising at least one active delay element and at least one passive delay element, the at least one active delay element providing a first set of resolutions comprising a plurality of resolutions of different sizes, the passive delay elements providing a second set of resolutions comprising a plurality of resolutions of different sizes, the number of the first sets being less than the number of the second sets, and the calibration process is performed In the first set of the aforementioned sets, all active delay elements except the nth active delay element are set to the first phase, the passive delay elements in the set are set to the first phase, and the nth active delay element in the set is set to the second phase. The method involves setting all of the active delay elements in the second set of the aforementioned set to the first phase, and setting the passive delay elements in the aforementioned set to the second phase, The phase difference between the outputs of the first and second sets of tuneable delay elements is detected, and the voltages of the first and second inputs to the first and second scaling factor stages of the n active delay elements, which each output a signal with a scaling factor applied to the input signal, are adjusted until the phase difference satisfies a criterion. The system stores one or more codes that indicate the first and second inputs to the n active delay element as calibration points. Methods that include...

12. The first set of tunable delay elements includes N active delay elements, and the calibration process is as follows: For each of the N active delay elements in the first set of tunable delay elements, the following are performed: setting all active delay elements in the first set except for the nth active delay element in the first set to the first phase, setting the nth active delay element in the set to the second phase, detecting the phase difference between the outputs of the first and second sets of tunable delay elements, adjusting the first and second inputs, and storing the data. It further includes, Calibration points are stored for each of the N active delay elements in the first set of tunable delay elements. The method according to claim 11.

13. The first and second inputs to the first and second scaling factor stages of the n active delay element are adjusted until the phase difference satisfies the criterion. Setting a certain bias to the first and second inputs, Setting a code corresponding to the amount of bias to be added to or subtracted from the aforementioned constant bias. The total bias of the first and second inputs is the constant bias which is added to the bias corresponding to the code, and the calibration point includes the code. The method according to claim 12.

14. The method according to claim 13, wherein the code corresponds to a voltage change ΔV, the first input is a voltage V1, the second input is a voltage V2, and V1 = V0 + ΔV and V2 = V0 - ΔV, where V0 is a bias voltage that supports stationary operation.

15. The first and second scaling factor stages have corresponding scaling factors α and β, and the calibration process is The calibration process is performed on each of the N active delay elements in the first set of tunable delay elements, and calibration points are generated for each of the N active delay elements across multiple different frequencies. In order to determine the scaling factors α and β that are optimized for the corresponding active delay elements to operate over a selected frequency range, so that the delay of the active delay elements is accurately realized, a least-squares mean (LMS) algorithm is performed using at least the calibration points for each of the N active delay elements over a plurality of different frequencies. The method according to claim 14, further comprising:

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