Optimized contact resistors for multilayer FET devices

The multilayer FET device with wrap-around contacts and local interconnects addresses the complexity and resistance issues in stacked FETs by providing direct, flexible connections, reducing manufacturing costs and improving contact efficiency.

JP7870820B2Active Publication Date: 2026-06-05INTERNATIONAL BUSINESS MACHINE CORPORATION
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
INTERNATIONAL BUSINESS MACHINE CORPORATION
Filing Date
2022-07-11
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Stacking field effect transistors (FETs) leads to increased manufacturing complexity and suboptimal contact resistance due to complex interconnects and limited contact area.

Method used

A multilayer FET device with wrap-around contacts and local interconnects that allow direct contact from the bottom to the top-level FET, eliminating the need for complex interconnects and increasing contact area.

Benefits of technology

Significantly reduces contact resistance and simplifies manufacturing by enabling direct, flexible interconnects that wrap around the source/drain regions of the top-level FET.

✦ Generated by Eureka AI based on patent content.

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Abstract

Stacked FET devices and techniques for forming same are provided, which have wrap-around contacts to optimize contact resistance. In one embodiment, the stacked FET device includes a bottom level FET on a substrate, a lower contact via in an ILD disposed above the bottom level FET, a top level FET above the lower contact via, and a top level FET source / drain contact that wraps around a source / drain region of the top level FET, the lower contact via connecting the top level FET source / drain contact to the source / drain region of the bottom level FET. When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top level FET source / drain contacts. A method of forming the stacked FET device is also provided.
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