Circuit boards and package boards including the same

Abstract

A circuit board according to an embodiment includes an insulating layer, an electrode layer disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an opening vertically overlapping at least a portion of an upper surface of the electrode layer, the electrode layer including a first layer disposed on the insulating layer, a second layer disposed on the first layer, a third layer disposed on the second layer, and a fourth layer disposed on the third layer, wherein a width of the second layer is greater than a width of the third layer, a thickness of the second layer is greater than a thickness of the third layer, and an upper surface of the protective layer is equal to or less than the height of an upper surface of the third layer.

Description

Technical Field

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board including pads with improved bonding properties to an adhesive member and a package substrate including the same.

Background Art

[0002] With the acceleration of miniaturization, weight reduction, and integration of electronic components, the circuit line width is being miniaturized. In particular, as the design rules of semiconductor chips are integrated on the nanometer scale, the circuit line width of package substrates or circuit boards on which semiconductor chips are mounted is being miniaturized to less than several micrometers.

[0003] To increase the circuit integration density of circuit boards (i.e., to miniaturize the circuit line width), various manufacturing methods have been proposed. For example, for the purpose of preventing the loss of circuit line width in the etching step for forming a pattern after copper plating, SAP (semi-additive process) method and MSAP (modified semi-additive process) have been proposed.

[0004] Subsequently, in order to implement a finer circuit pattern, an ETS (Embedded Trace Substrate) method of embedding a copper foil in an insulating layer has been used in the industry. The ETS method is a type of manufacturing in which a copper foil circuit is embedded in an insulating layer instead of being formed on the surface of the insulating layer, so there is no circuit loss due to etching, which is advantageous for miniaturizing the circuit pitch.

[0005] On the other hand, recently, efforts have been made to develop an improved 5G (5th generation) communication system or a pre-5G communication system to meet the demand for wireless data traffic. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (sub6 giga (6 GHz), 28 giga (28 GHz), 38 giga (38 GHz) or higher frequencies) to achieve a high data transmission rate.

[0006] Furthermore, in order to mitigate path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, beamforming, massive MIMO (Multi-Input / Output Multiplexing), and array antennas have been developed for 5G communication systems. Circuit boards applied to such 5G and above (6G, 7G, etc.) communication systems are equipped with various chips that constitute AP modules and include pads for mounting these chips. The performance of the 5G and above communication system can be determined according to the characteristics of the chips mounted on the circuit board. In addition, the performance improvement of the final product can be determined by the bonding properties between the mounted chips and the pads on the circuit board to which they are connected.

[0007] Therefore, there is a need for a circuit board with a structure that can improve the bonding properties of the pads connected to the chip. [Overview of the project] [Problems that the invention aims to solve]

[0008] In this embodiment, we aim to provide a circuit board with a new structure and a package board including the same.

[0009] Specifically, the embodiment aims to provide a circuit board including an electrode layer with improved bonding properties with the chip, and a package board including the same.

[0010] Furthermore, the embodiment aims to provide a circuit board with improved bonding strength between the protective layer and the electrode layer, and a package substrate including the same.

[0011] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those with ordinary skill in the art to which the proposed embodiments belong, based on the following description. [Means for solving the problem]

[0012] The circuit board according to the embodiment includes an insulating layer, an electrode layer disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an opening that overlaps perpendicularly with at least a portion of the upper surface of the electrode layer, wherein the electrode layer includes a first layer disposed on the insulating layer, a second layer disposed on the first layer, a third layer disposed on the second layer, and a fourth layer disposed on the third layer, wherein the width of the second layer is greater than the width of the third layer, the thickness of the second layer is greater than the thickness of the third layer, and the upper surface of the protective layer is less than or equal to the height of the upper surface of the third layer.

[0013] Furthermore, the first layer is a seed layer disposed on the upper surface of the insulating layer, the second layer is a first pattern layer of the circuit pattern layer disposed on the seed layer, the third layer is a second pattern layer of the circuit pattern layer disposed on the first pattern layer of the circuit pattern layer, and the fourth layer is a surface treatment layer disposed on the second pattern layer of the circuit pattern layer.

[0014] Furthermore, the electrode layer is a pad on which the chip is mounted.

[0015] Furthermore, the second layer of the electrode layer contains the same metallic substance as the third layer of the electrode layer.

[0016] Furthermore, the second layer of the electrode layer has a width greater than the width of the fourth layer of the electrode layer.

[0017] Furthermore, the thickness of the second layer of the electrode layer is greater than the thickness of the fourth layer of the electrode layer.

[0018] Furthermore, the upper surface of the protective layer is located lower than the third layer of the electrode layer, and the third layer of the electrode layer includes a protruding region that protrudes from the upper surface of the protective layer.

[0019] Furthermore, the fourth layer of the electrode layer includes a first portion disposed on the upper surface of the third layer of the electrode layer, and a second portion extending from the first portion and disposed on the side surface of the protruding region of the third layer.

[0020] Furthermore, the fourth layer of the electrode layer includes a first portion disposed on the upper surface of the third layer of the electrode layer and a second portion extending from the first portion and disposed on the upper surface of the protective layer.

[0021] Furthermore, at least one side surface of the second and third layers of the electrode layer includes a curved surface. [Effects of the Invention]

[0022] In the embodiment, a circuit pattern layer is included. The circuit pattern layer includes an electrode layer which is a pad on which a chip is mounted. The electrode layer may include a first to fourth layer. For example, the electrode layer may include a seed layer, a first pattern layer, a second pattern layer, and a surface treatment layer. In this case, the surface treatment layer may include a first portion disposed on the upper surface of the second pattern layer and a second portion extending from the first portion and disposed on the upper surface of the protective layer. As a result, the embodiment can secure a wide space for the placement of an adhesive member (not shown) for mounting the chip by the surface treatment layer including the second portion, thereby improving chip bonding performance. That is, in the embodiment, the width of the surface treatment layer can be made larger than the width of the second pattern layer, thereby increasing the contact area with the adhesive member. As a result, in the embodiment, the contact area with the adhesive member can be increased, thereby further improving bonding performance with adhesive members such as solder balls and wires.

[0023] Furthermore, by positioning the second portion on the upper surface of the protective layer, the protective layer is able to support the second portion when an adhesive member (not shown) for mounting the chip is placed. As a result, in this embodiment, unlike conventional overhang structures (for example, structures in which the end of the surface treatment layer is positioned away from the protective layer, the first pattern layer, and the second pattern layer without contact), the surface treatment layer can be prevented from being damaged by the adhesive member.

[0024] Furthermore, in the embodiment, the upper surface of the second pattern layer can be positioned higher than the upper surface of the protective layer. This prevents the resin of the protective layer from remaining on the upper surface of the second pattern layer. As a result, in the embodiment, the entire upper surface of the pad can be used as a space for connection with the chip. Therefore, in the embodiment, the circuit integration density can be improved, and electrical and physical reliability can be improved. Moreover, in the embodiment, the surface treatment layer is also positioned on a part of the protruding side surface of the second pattern layer. This improves the contact area between the surface treatment layer and the second pattern layer. Therefore, in the embodiment, the problem of the surface treatment layer separating from the second pattern layer can be solved, and electrical and physical reliability can be improved as a result.

[0025] Also, in the embodiment, at least one side surface of the seed layer, the first pattern layer, and the second pattern layer constituting the pad has a rounded curved surface. Thereby, in the embodiment, the contact area between the seed layer, the first pattern layer, the second pattern layer, and the protective layer can be increased. Thereby, in the embodiment, in the step of forming the protective layer, the problem of lifting (for example, forming an air layer between the protective layer and the pad) between the pad and the protective layer can be solved. Therefore, in the embodiment, the problem of peeling off where the protective layer is separated from the pad can be solved, and furthermore, the overall physical reliability and electrical reliability of the circuit board can be improved.

Brief Description of the Drawings

[0026] [Figure 1] It is a diagram showing a circuit board according to the first embodiment. [Figure 2] It is an enlarged view of the electrode layer in FIG. 1. [Figure 3] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 4] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 5] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 6] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 7] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 8] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 9] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 10] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 11] It is a diagram showing the first manufacturing method of the circuit board shown in FIG. 1 in the order of steps. [Figure 12]This diagram shows the first manufacturing method of the circuit board shown in Figure 1, in order of the steps involved. [Figure 13] This diagram shows the first manufacturing method of the circuit board shown in Figure 1, in order of the steps involved. [Figure 14] This diagram shows the first manufacturing method of the circuit board shown in Figure 1, in order of the steps involved. [Figure 15] This diagram shows the first manufacturing method of the circuit board shown in Figure 1, in order of the steps involved. [Figure 16] This diagram illustrates the second manufacturing method for the circuit board shown in Figure 1. [Figure 17] This diagram illustrates the second manufacturing method for the circuit board shown in Figure 1. [Figure 18] This figure shows a circuit board according to the second embodiment. [Figure 19] This figure shows a circuit board according to the third embodiment. [Figure 20] This figure shows a package substrate according to an example. [Modes for carrying out the invention]

[0027] The embodiments disclosed herein will be described in detail below with reference to the accompanying drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are added or used interchangeably to facilitate the preparation of the specification and do not have any mutually distinguishing meaning or role in themselves. Furthermore, in the description of the embodiments disclosed herein, if a specific description of such prior art is deemed to interfere with the gist of the embodiments disclosed herein, such detailed description will be omitted. In addition, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed herein, and it should be understood that the accompanying drawings do not limit the technical idea disclosed herein and include all modifications, equivalents or substitutes that fall within the idea and technical scope of the present invention.

[0028] Terms including ordinal numbers such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. The terms are used solely for the purpose of distinguishing one component from another.

[0029] When it is stated that one component is “linked” or “connected” to another component, it should be understood that it may be directly “linked” or “connected” to the other component, and that other components may exist in between. On the other hand, when it is stated that one component is “directly linked” or “directly connected” to another component, it should be understood that there are no other components in between.

[0030] A singular expression can include multiple expressions unless the context clearly indicates otherwise.

[0031] In this application, terms such as “includes” or “having” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0032] The embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0033] Figure 1 shows a circuit board according to the first embodiment, and Figure 2 is an enlarged view of the third circuit pattern layer of Figure 1.

[0034] Referring to Figures 1 and 2, the circuit board includes an insulating layer 110, a circuit pattern layer, vias, and a protective layer.

[0035] The insulating layer 110 can have a multi-layer structure. For example, the insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. In this case, although the circuit board is shown in the drawing as having a three-layer structure based on the number of insulating layers, it is not limited to this. For example, the circuit board may have a structure of two or fewer layers based on the number of insulating layers, or conversely, it may have a structure of four or more layers.

[0036] For example, the first insulating layer 111 may be an inner insulating layer located on the inside in a multilayer structure. The second insulating layer 112 may be a first outermost insulating layer located on the first outermost layer in a multilayer structure. The third insulating layer 113 may be a second outermost insulating layer located on the second outermost layer in a multilayer structure. Although the inner insulating layer has been shown as being composed of one layer, it may be composed of two or more layers.

[0037] The insulating layer 110 can include printed circuit boards, wiring boards, and insulating substrates, all of which are substrates on which electrical circuits can be arranged and on which wiring can be modified, and which are made of insulating material on which a circuit pattern can be formed on the surface.

[0038] For example, at least one of the insulating layers 110 may be rigid or flexible. For example, at least one of the insulating layers 110 may include glass or plastic. More specifically, at least one of the insulating layers 110 may include chemically strengthened / semi-strengthened glass such as soda-lime glass or aluminosilicate glass, or reinforced or ductile plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC), or may include sapphire.

[0039] Furthermore, at least one of the insulating layers 110 may include an isotropic film. For example, at least one of the insulating layers 110 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), isotropic polycarbonate PC (polycarbonate), or isotropic polymethyl methacrylate (PMMA).

[0040] Furthermore, at least one of the insulating layers 110 may be formed from a material containing an inorganic filler and an insulating resin. For example, as the material constituting the insulating layer 110, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, and a resin containing reinforcing materials such as an inorganic filler such as silica or alumina can be used. Specifically, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc., can be used.

[0041] Furthermore, at least one of the insulating layers 110 may have a partially curved surface and bend. That is, at least one of the insulating layers 110 may have a partially flat surface and a partially curved surface and bend. More specifically, at least one of the insulating layers 110 may have a curved end and bend, or have a surface with random curvature and bend or fold.

[0042] A circuit pattern may be arranged on the surface of the insulating layer 110.

[0043] For example, a first circuit pattern layer 120 may be placed on the first surface of the first insulating layer 111. For example, a second circuit pattern layer 130 may be placed on the second surface of the first insulating layer 111. For example, a third circuit pattern layer 140 may be placed on the first surface of the second insulating layer 112. For example, a fourth circuit pattern layer 150 may be placed on the second surface of the third insulating layer 113. The first circuit pattern layer 120 and the second circuit pattern layer 130 can also be called inner circuit pattern layers placed on the surface of the inner insulating layer. The third circuit pattern layer 140 and the fourth circuit pattern layer 150 can also be called outer or outermost circuit pattern layers placed on the outermost insulating layer.

[0044] The first to fourth circuit pattern layers 120, 130, 140, and 150 perform a signal transmission function. The first to fourth circuit pattern layers 120, 130, 140, and 150 can also be called "electrode layers".

[0045] In this case, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are wirings that transmit electrical signals and can be formed from a highly electrically conductive metallic material. For this reason, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 can consist of at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 may consist of a paste or solder paste containing at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 may consist of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0046] The first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 can be manufactured using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed explanation is omitted here.

[0047] On the other hand, the third circuit pattern layer 140 and the fourth circuit pattern layer 150 each include traces and pads. The traces and pads can be distinguished based on either their planar shape or width. For example, the planar shape of the trace may be rectangular. The planar shape of the pad may be circular. For example, at least a portion of the upper surface of the pad may include a curved surface. The width of the trace may be smaller than the width of the pad. That is, the trace can serve to connect multiple pads. As a result, the trace can have a fine line width. The pad can serve as a mounting pad on which a chip is mounted. As a result, the pad can have a width above a certain level to provide chip mounting space.

[0048] Specifically, the third circuit pattern layer 140 may include pads 140P and traces 140T. The fourth circuit pattern layer 150 may also include pads 150P and traces 150T. Traces 140T and 150T refer to long, linear wiring that transmits electrical signals. Pads 140P and 150P may refer to mounting pads on which components such as chips are mounted, or core pads or BGA pads for connecting to an external board. Thus, pad 140P can also be called the "first pad," and pad 150P can be called the "second pad." Furthermore, pads 140P and 150P can also be called the "electrode layer."

[0049] Specifically, the pad 140P of the third circuit pattern layer 140 may be a mounting pad on which components such as chips are mounted. Also, the pad 150P of the fourth circuit pattern layer 140 may be, but is not limited to, a core pad or a BGA pad for connecting to an external board. On the other hand, the pad 140P of the third circuit pattern layer 140 may be even narrower than the pad 150P of the fourth circuit pattern layer 150.

[0050] The pads 140P of the third circuit pattern layer 140 may have their surfaces exposed by a first protective layer 160 disposed on the first surface of the second insulating layer 112. For example, the first protective layer 160 may include openings (not shown). The openings in the first protective layer 160 may overlap perpendicularly with the upper surface of the pads 140P of the third circuit pattern layer 140. Also, the pads 150P of the fourth circuit pattern layer 150 may have their surfaces exposed by a second protective layer 170 disposed on the second surface of the third insulating layer 113. For example, the second protective layer 170 may include openings (not shown). The openings in the second protective layer 170 may overlap perpendicularly with the lower surface of the pads 150P of the fourth circuit pattern layer 150.

[0051] The third circuit pattern layer 140 may have multiple layer structures. In this case, the pads 140P and traces 140T of the third circuit pattern layer 140 may have different layer structures. For example, the number of layers of the pads 140P may be greater than the number of layers of the traces 140T. For example, the traces 140T may include only some of the multiple layers that make up the pads 140P.

[0052] For example, the pads 140P of the third circuit pattern layer 140 may include the first to fourth layers. The traces 140T of the third circuit pattern layer 140 may include only the first and second layers.

[0053] For example, the pad 140P of the third circuit pattern layer 140 may have a four-layer structure. The trace 140T of the third circuit pattern layer 140 may have a two-layer structure.

[0054] For the sake of explanation, the first to fourth layers will be referred to as the seed layer, first pattern, second pattern, and surface treatment layer. For example, the seed layer described below can also be called the "first layer." For example, the first pattern described below can also be called the "second layer." For example, the second pattern described below can also be called the "third layer." For example, the surface treatment layer described below can also be called the "fourth layer." This can also be applied similarly to the fourth circuit pattern layer.

[0055] For example, the pad 140P of the third circuit pattern layer 140 includes a first pattern layer 142 disposed on the first surface of the second insulating layer 112 and a second pattern layer 143 disposed on the first pattern layer 142. In this embodiment, the pad 140P of the third circuit pattern layer 140 can have a two-layer structure. This allows the pad 140P of the third circuit pattern layer 140 to protrude above a certain height relative to the first surface of the second insulating layer 112. As a result, in this embodiment, having the pad 140P of the third circuit pattern layer 140 above a certain height improves the ease of the chip mounting process.

[0056] The first pattern layer 142 and the second pattern layer 143 can each contain the same metallic substance. For example, the first pattern layer 142 can contain copper. The second pattern layer 143 can also contain copper, which is the same metallic substance as the first pattern layer 142.

[0057] Furthermore, the pads 140P of the third circuit pattern layer 140 may include a seed layer 141 disposed between the first surface of the second insulating layer 112 and the first pattern layer 142. The seed layer 141 may be a seed layer used to form the first pattern layer 142 and the second pattern layer 143. For example, the first pattern layer 142 and the second pattern layer 143 may be formed by an electroplating process. Thus, the seed layer 141 may be a seed layer for electroplating the first pattern layer 142 and the second pattern layer 143, respectively.

[0058] The pads 140P of the third circuit pattern layer 140 may include a surface treatment layer 144 disposed on the second pattern layer 143. The surface treatment layer 144 may be formed to protect the surface of the pads 140P or to improve the bonding properties of the pads 140P. The surface treatment layer 144 may include gold (Au). For example, the surface treatment layer 144 may include only a gold metal layer, and the gold metal layer may be formed directly on the second pattern layer 143 which contains copper. Alternatively, the surface treatment layer 144 may be an ENEPIG layer. For example, the surface treatment layer 144 may include a nickel metal layer, a palladium metal layer, and a gold metal layer.

[0059] On the other hand, the trace 140T of the third circuit pattern layer 140 may include only a portion of the layers that constitute the pad 140P. For example, the trace 140T of the third circuit pattern layer 140 may include the seed layer 141 and the first pattern layer 142. Thus, in the embodiment, the seed layer 141 and the first pattern layer 142 can be formed to form a portion of the pad 140P and the trace 140T of the third circuit pattern layer 140. Then, in the embodiment, the pad 140P can be formed by forming the second pattern layer 143 and the surface treatment layer 144 on the region of the formed first pattern layer 142 corresponding to the pad 140P.

[0060] The pad 150P of the fourth circuit pattern layer 150 can have substantially the same structure as the pad 140P of the third circuit pattern layer 140. For example, the pad 150P of the fourth circuit pattern layer 150 may include a seed layer 151, a first pattern layer 152, a second pattern layer 153, and a surface treatment layer 154. In this case, the seed layer 151, the first pattern layer 152, the second pattern layer 153, and the surface treatment layer 154 constituting the pad 150P of the fourth circuit pattern layer 150 have substantially the same layer structure as the seed layer 141, the first pattern layer 142, the second pattern layer 143, and the surface treatment layer 144 constituting the pad 140P of the third circuit pattern layer 140, and therefore a detailed explanation thereof is omitted.

[0061] Furthermore, the trace 150T of the fourth circuit pattern layer 150 may include a seed layer 151 and a first pattern layer 152, which are part of the layers constituting the pad 150P, corresponding to the trace 140T of the third circuit pattern layer 140.

[0062] The third circuit pattern layer may be mounting pads on which components such as chips are mounted. The fourth circuit pattern layer may be a core pad or BGA pad for connecting to an external board. The pads of the fourth circuit pattern layer 150 may be even wider than the pads of the third circuit pattern layer.

[0063] A first protective layer 160 may be disposed on the first surface of the second insulating layer 112. The first protective layer 160 may include solder resist. The first protective layer 160 may include openings (not shown) that expose the surface of the pad 140P of the third circuit pattern layer 140. For example, the first protective layer 160 may expose the surface of the second pattern layer 143 that constitutes the pad 140P of the third circuit pattern layer 140.

[0064] The first protective layer 160 may be positioned to cover the side surface of the seed layer 141 of the third circuit pattern layer 140. The first protective layer 160 may also be positioned to cover the side surface of the first pattern layer 142 of the pad 140P. Furthermore, the first protective layer 160 may be positioned to cover a portion of the upper surface of the first pattern layer 142 of the pad 140P. Finally, the first protective layer 160 may be positioned to cover the side surface of the second pattern layer 143 of the pad 140P.

[0065] In the first embodiment, the upper surface of the first protective layer 160 can be located on the same plane as the upper surface of the second pattern layer 143 of the third circuit pattern layer 140.

[0066] Correspondingly, a second protective layer 170 may be placed on the second surface of the third insulating layer 113. The second protective layer 170 may include solder resist. The second protective layer 170 may include openings (not shown) that expose the surface of the pad 150P of the fourth circuit pattern layer 150. For example, the second protective layer 170 may expose the surface of the second pattern layer 153 that constitutes the pad 150P of the fourth circuit pattern layer 150.

[0067] The second protective layer 170 may be positioned to cover the side surface of the seed layer 151. The second protective layer 170 may also be positioned to cover the side surface of the first pattern layer 152 of the pad 150P of the fourth circuit pattern layer 150. The second protective layer 170 may also cover a portion of the underside of the first pattern layer 152 of the pad 150P of the fourth circuit pattern layer 150. The second protective layer 170 may also be positioned to cover the side surface of the second pattern layer 153 of the pad 150P of the fourth circuit pattern layer 150.

[0068] Furthermore, in the first embodiment, the lower surface of the second protective layer 170 can be located on the same plane as the lower surface of the second pattern layer 153 of the pad 150P of the fourth circuit pattern layer 150.

[0069] On the other hand, the circuit board of the embodiment includes through electrodes. These through electrodes can electrically connect circuit pattern layers arranged on different layers. For example, the through electrodes can also be called "vias" for electrically connecting different circuit pattern layers. For this reason, the through electrodes will be referred to as "vias" in the following description.

[0070] For example, a first via V1 may be formed in the first insulating layer 111. The first via V1 penetrates the first insulating layer 111, thereby electrically connecting the first circuit pattern layer 120 and the second circuit pattern layer 130. For example, a second via V2 may be formed in the second insulating layer 112. The second via V2 penetrates the second insulating layer 112, thereby electrically connecting the first circuit pattern layer 120 and the third circuit pattern layer 140. For example, a third via V3 may be formed in the third insulating layer 113. The third via V3 penetrates the third insulating layer 113, thereby electrically connecting the second circuit pattern layer 130 and the fourth circuit pattern layer 150.

[0071] The vias V1, V2, and V3 described above can be formed by filling the inside of via holes formed within each insulating layer with a metallic substance. The via holes can be formed by any one of the following processing methods: mechanical, laser, or chemical processing. When the via holes are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; and when they are formed by chemical processing, chemicals containing aminosilanes, ketones, etc., can be used to open the insulating layer 110.

[0072] Once the via holes are formed, the interiors of the via holes can be filled with a conductive material to form the vias V1, V2, and V3. The vias V1, V2, and V3 can be formed from any one of the following materials: copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The filling of the conductive material can be carried out using any one of the following methods or a combination thereof: electroless plating, electroplating, screen printing, sputtering, evaporation, inkjet printing, and defencing.

[0073] As described above, the pads 140P and 150P of the third circuit pattern layer 140 and the fourth circuit pattern layer 150, respectively, include a seed layer, a first pattern, a second pattern, and a surface treatment layer. Their structures will be described in detail below. However, since the pad 150P of the fourth circuit pattern layer 150 has substantially the same layer structure as the pad 140P of the third circuit pattern layer 140, the explanation will focus primarily on the structure of the pad 140P of the third circuit pattern layer 140.

[0074] As shown in Figure 2, the third circuit pattern layer 140 includes a pad 140P and a trace 140T. The pad 140P includes a seed layer 141, a first pattern layer 142, a second pattern layer 143, and a surface treatment layer 144. The trace 140T may include the seed layer 141 and the first pattern layer 142. For example, the pad 140P and the trace 140T of the third circuit pattern layer 140 may have different layer structures.

[0075] The first pattern layer 142 may have a first thickness T1. For example, the first thickness T1 of the first pattern layer 142 may satisfy a range of 7 μm to 17 μm. For example, the first thickness T1 of the first pattern layer 142 may satisfy a range of 9 μm to 15 μm. For example, the first thickness T1 of the first pattern layer 142 may satisfy a range of 10 μm to 13 μm. Here, the first pattern layer 142 may be a pattern constituting a pad 140P and a trace 140T.

[0076] The second pattern layer 143 may be placed on the first pattern layer 142 having a second thickness T2 that is thinner than the first thickness T1 of the first pattern layer 142. For example, the second thickness T2 of the second pattern layer 143 can satisfy a range of 5 μm to 15 μm. For example, the second thickness T2 of the second pattern layer 143 can satisfy a range of 7 μm to 13 μm. For example, the second thickness T2 of the second pattern layer 143 can satisfy a range of 8 μm to 11 μm.

[0077] Through this, in the embodiment, the overall thickness of the circuit board can be reduced, and the distance from the uppermost surface of the second insulating layer 112, which is the outermost insulating layer of the circuit board, to the lowest end mounted on the circuit board can be reduced, thereby reducing the overall thickness of the chip package.

[0078] The surface treatment layer 144 may be disposed on the second pattern layer 143 having a third thickness T3 that is thinner than the first thickness T1 and the second thickness T2. For example, the third thickness T3 of the surface treatment layer 144 can satisfy a range of 0.1 μm to 10 μm. For example, the third thickness T3 of the surface treatment layer 144 can satisfy a range of 0.5 μm to 8 μm. For example, the third thickness T3 of the surface treatment layer 144 can satisfy a range of 1 μm to 5 μm. However, the third thickness T3 is the thickness range of the surface treatment layer 144 when the surface treatment layer 144 is composed of the ENEPIG layer described above. For example, the surface treatment layer 144 may include a nickel (Ni) metal layer with a thickness range of 0.002 μm to 0.244 μm formed on the second pattern layer 143, a palladium (Pd) metal layer with a thickness range of 0.049 μm to 4.878 μm formed on the nickel (Ni) metal layer, and a gold (Au) metal layer with a thickness range of 0.049 μm to 4.478 μm formed on the palladium (Pd) metal layer. However, the examples are not limited thereto, and the surface treatment layer 144 may include only a gold (Au) metal layer containing gold (Au). In this case, the third thickness T3 of the surface treatment layer 144 may have a thickness range lower than the thickness range described above. For example, the thickness of the gold (Au) metal layer may be in the range of 0.049 μm to 4.478 μm. For example, the thickness of the gold (Au) metal layer can be in the range of 0.244 μm to 3.902 μm. For example, the thickness of the gold (Au) metal layer can be in the range of 0.488 μm to 2.439 μm.

[0079] The seed layer 141 is disposed between the second insulating layer 112 and the first pattern layer 142, having a fourth thickness T4. For example, the fourth thickness T4 of the seed layer 141 can satisfy a range of 0.5 μm to 5 μm. For example, the fourth thickness T4 of the seed layer 141 can satisfy a range of 0.8 μm to 3.5 μm. For example, the fourth thickness T4 of the seed layer 141 can satisfy a range of 1.0 μm to 2.5 μm. Here, the seed layer 141 may be a pattern constituting the pad 140P and the trace 140T.

[0080] On the other hand, the first circuit pattern layer 120, which corresponds to the inner circuit pattern layer of the circuit board, may have a fifth thickness T5. The fifth thickness T5 of the first circuit pattern layer 120 may correspond to the first thickness T1 of the first pattern layer 142. For example, the fifth thickness T5 of the first circuit pattern layer 120 may satisfy a range of 7 μm to 17 μm. For example, the fifth thickness T5 of the first circuit pattern layer 120 may satisfy a range of 9 μm to 15 μm. For example, the fifth thickness T5 of the first circuit pattern layer 120 may satisfy a range of 10 μm to 13 μm. However, if the first circuit pattern layer 120 includes a seed layer, the first circuit pattern layer 120 may correspond to the fifth thickness T5 described above plus the fourth thickness T4 of the seed layer 141.

[0081] The second insulating layer 112 may have a sixth thickness T6. The sixth thickness T6 of the second insulating layer 112 may correspond to the distance from the upper surface of the first circuit pattern layer 120 to the upper surface of the second insulating layer 112. For example, the sixth thickness T6 of the second insulating layer 112 may satisfy a range of 10 μm to 30 μm. For example, the sixth thickness T6 of the second insulating layer 112 may satisfy a range of 15 μm to 25 μm. For example, the sixth thickness T6 of the second insulating layer 112 may satisfy a range of 18 μm to 23 μm.

[0082] On the other hand, the seed layer 141, the first pattern layer 142, the second pattern layer 143, and the surface treatment layer 144 of the pad 140P that constitute the third circuit pattern layer 140 can have different widths from each other.

[0083] The first pattern layer 142 of the pad 140P may have a first width W1. For example, the first width W1 of the first pattern layer 142 of the pad 140P may satisfy a range of 5 μm to 300 μm. For example, the first width W1 of the first pattern layer 142 of the pad 140P may satisfy a range of 70 μm to 200 μm. For example, the first width W1 of the first pattern layer 142 of the pad 140P may satisfy a range of 100 μm to 150 μm.

[0084] The second pattern layer 143 of the pad 140P may be arranged on the first pattern layer 142 of the pad 140P, having a second width W2 smaller than the first width W1 of the first pattern layer 142. For example, the second width W2 of the second pattern layer 143 of the pad 140P can satisfy a range of 3 μm to 250 μm. For example, the second width W2 of the second pattern layer 143 of the pad 140P can satisfy a range of 50 μm to 150 μm. For example, the second width W2 of the second pattern layer 143 of the pad 140P can satisfy a range of 60 μm to 100 μm.

[0085] As a result, the upper surface of the first pattern layer 142 of the pad 140P may include a first portion that is in direct contact with the lower surface of the second pattern layer 143, and a second portion other than the first portion. The second portion of the upper surface of the first pattern layer 142 may be in direct contact with the first protective layer 160.

[0086] Furthermore, the width of the first portion of the first pattern layer 142 of the pad 140P may be greater than the width of the second portion. By forming a portion of the pad 140P below the first protective layer 160 via the second portion, it is possible to prevent the pad 140P from separating from the circuit board and becoming detached. By forming the first pattern layer 142 to be thicker than the second pattern layer 143, adhesive strength can be ensured so that the pad does not separate from the circuit board even if the second portion is narrower than the first portion. For example, if the thickness of the first pattern layer 142 is thinner than the thickness of the second pattern layer 143, when the second pattern layer 143 becomes detached during connection with a chip mounted on the circuit board, the first pattern layer 142 cannot be supported, and the pad 140P may become detached from the circuit board. In addition, in this embodiment, by forming the width of the first portion to be greater than the width of the second portion, connection with a chip mounted on the circuit board can be facilitated.

[0087] The surface treatment layer 144 may be arranged on the second pattern layer 143, having a third width W3 that is smaller than the first width W1 of the first pattern layer 142 of the pad 140P and larger than the second width W2 of the second pattern layer 143. For example, the third width W3 of the surface treatment layer 144 can satisfy a range of 4 μm to 280 μm. For example, the third width W3 of the surface treatment layer 144 can satisfy a range of 70 μm to 180 μm. For example, the third width W3 of the surface treatment layer 144 can satisfy a range of 80 μm to 120 μm.

[0088] On the other hand, the first pattern layer 142 of the trace 140T may have a different width from the first pattern of the pad 140P. For example, the first pattern layer 142 of the trace 140T may have a fourth width W4 that is narrower than the first width W1 of the first pattern of the pad 140P. The fourth width W4 of the first pattern layer 142 of the trace 140T may satisfy a range of 0.5 μm to 20 μm. For example, the fourth width W4 of the first pattern layer 142 of the trace 140T may satisfy a range of 0.8 μm to 15 μm. For example, the fourth width W4 of the first pattern layer 142 of the trace 140T may satisfy a range of 1.0 μm to 10 μm.

[0089] On the other hand, multiple traces 140T can be formed on the second insulating layer 112 at intervals from each other. In this case, adjacent traces 140T can be spaced apart by a fifth width W5. The fifth width W5 corresponding to the spacing between the traces 140T can satisfy a range of 0.5 μm to 20 μm. For example, the fifth width W5 can satisfy a range of 0.8 μm to 15 μm. For example, the fifth width W5 can satisfy a range of 1.0 μm to 10 μm.

[0090] On the other hand, in the first embodiment, the upper surface of the second pattern layer 143 can be located on the same plane as the upper surface of the first protective layer 160.

[0091] As a result, the surface treatment layer 144 may include a first portion positioned on the upper surface of the second pattern layer 143 and a second portion extending from the first portion. For example, the lower surface of the surface treatment layer 144 may include a first portion of the surface treatment layer 144 that is in direct contact with the upper surface of the second pattern layer 143 and a second portion of the surface treatment layer 144 that is in direct contact with the upper surface of the first protective layer 160. In this embodiment, when forming the surface treatment layer 144, the opening of the mask (not shown) is made to have a third width W3 between the first width W1 and the second width W2. As a result, in this embodiment, the surface treatment layer 144 extends from the upper surface of the second pattern 143 and is partially formed on the upper surface of the first protective layer 160.

[0092] Furthermore, in the embodiment, the surface treatment layer 144 can also be plated using the seed layer 141, the first pattern layer 142, and the second pattern layer 143 without a mask. In this case, the width of the first portion of the surface treatment layer 144 may be greater than the width of the second portion of the surface treatment layer 144. By making the width of the first portion of the surface treatment layer 144, which is in direct contact with the second pattern layer 143, wider, it is possible to prevent the surface treatment layer 144 from falling off the second pattern layer 143, thereby improving the adhesion between the protective layer and the pad 140P. As a result, in the embodiment, a wider space can be secured for arranging adhesive members (not shown) for mounting the chip, thereby improving chip bonding performance. That is, in the embodiment, the width of the surface treatment layer 144 is made larger than the width of the second pattern layer 143, thereby increasing the contact area with adhesive members (not shown) and improving bonding performance with adhesive members such as solder balls and wires.

[0093] On the other hand, the first circuit pattern layer 120 and the third circuit pattern layer 140 can have different surface roughness (Ra). For example, the inner circuit pattern layer in the embodiment can have a different surface roughness (Ra) than the outer circuit pattern layer.

[0094] For example, the first circuit pattern layer 120 may have a first surface roughness (Ra). The first surface roughness (Ra) may be in the range of 0.83 μm to 1.0 μm. That is, the first circuit pattern layer 120 is subjected to a roughening treatment to improve the bonding strength with the second insulating layer 112, thereby having a first surface roughness (Ra) in the range of 0.83 μm to 1.0 μm.

[0095] The third circuit pattern layer 140 may have a second surface roughness (Ra) smaller than that of the first circuit pattern layer 120. For example, the second surface roughness (Ra) can satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the first pattern layer 141 can satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the second pattern layer 142 can satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the surface treatment layer 144 can satisfy a range of 0.70 μm to 0.82 μm.

[0096] That is, in the embodiment, the second surface roughness (Ra) may be greater than the first surface roughness (Ra). The first circuit pattern layer 120 requires a greater roughening treatment to improve bonding strength with the second insulating layer 112, and the pads 140P of the third circuit pattern layer 140 require roughness for contact with the protective layer or the contact member for connecting to the chip mounted on the circuit board or the main printed circuit board, so a relatively smaller roughening treatment may be applied. Furthermore, the pads 140P of the third circuit pattern layer 140 may be formed only by the roughness generated in the etching process of the seed layer 141 as shown in Figure 12, without any further roughening treatment.

[0097] On the other hand, the first protective layer 160 may have a third surface roughness (Ra) between the first surface roughness (Ra) and the second surface roughness (Ra). For example, the third surface roughness (Ra) of the first protective layer 160 can satisfy a range of 0.80 μm to 0.90 μm. The surface roughness of the first protective layer 160 is not limited, but it should be sufficient to ensure bonding strength with the molding layer during the process of mounting and molding a chip on the first protective layer 160.

[0098] Figures 3 to 15 show the first manufacturing method of the circuit board shown in Figure 1 in order of steps, and Figures 16 and 17 are diagrams for explaining the second manufacturing method of the circuit board shown in Figure 1.

[0099] The manufacturing method of the circuit board shown in Figure 1 will be described in detail below, with reference to the attached drawings.

[0100] Referring to Figure 3, in the embodiment, a first insulating layer 111 is prepared. In the embodiment, once the first insulating layer 111 is prepared, a process can be carried out to form a first circuit pattern layer 120, a second circuit pattern layer 130, and a first via V1 on the first insulating layer 111. Briefly explaining this, once the first insulating layer 111 is prepared, a process can be carried out to form a seed layer (not shown) on one or both surfaces of the first insulating layer 111. In this case, the first insulating layer 111 may be CCL (Copper Clad Laminate), and the seed layer may be a copper foil layer constituting the CCL. Alternatively, the seed layer may be formed on at least one of the first and second surfaces of the first insulating layer 111 by electroless plating. Next, in the embodiment, a process can be carried out to form a first via hole on the first insulating layer 111 on which the seed layer has been formed. Subsequently, in the embodiment, a mask (not shown) including an opening is formed on at least one of the first and second surfaces of the first insulating layer 111, and plating is performed inside the opening of the mask to form at least one of the circuit pattern layers of the first circuit pattern layer 120 and the second circuit pattern layer 130 and the first via V1.

[0101] Next, referring to Figure 4, in the embodiment, the steps of laminating the second insulating layer 112 onto the first surface of the first insulating layer 111 and laminating the third insulating layer 113 onto the second surface of the first insulating layer 111 can be performed. At this time, metal layers 141 and 151 can be formed on the first surface of the second insulating layer 112 and the second surface of the third insulating layer 113, respectively. The metal layers 141 and 151 can then be used as seed layers for forming the third circuit pattern layer 140 and the fourth circuit pattern layer 150. Thus, the metal layers 141 and 151 can also be called seed layers.

[0102] Next, referring to Figure 5, in the embodiment, a second via hole VH2 can be formed through the second insulating layer 112 and the seed layer 141 arranged on its first surface, and a third via hole VH3 can be formed through the third insulating layer 113 and the seed layer 151 arranged on its second surface.

[0103] Next, referring to Figure 6, in the embodiment, the step of forming a first mask M1 on the seed layers 141 and 151 can be performed. In this case, the first mask M1 placed on the seed layer 141 on the second insulating layer 112 may include an opening (not shown) that opens up the area where the second via V2 and the third circuit pattern layer 140 are formed. Also, the first mask M1 placed on the seed layer 151 on the third insulating layer 113 may include an opening (not shown) that opens up the area where the third via V3 and the fourth circuit pattern layer 150 are formed.

[0104] Next, referring to Figure 7, in the embodiment, electroplating can be performed using the seed layers 141 and 151. Specifically, in the embodiment, a metallic substance can be filled into the opening of the first mask M1 to form the 1-1 plating layer 142a, the 1-2 plating layer 152a, the second via V2, and the third via V3.

[0105] The first-1 plating layer 142a and the second via V2 can be formed simultaneously. Furthermore, the first-1 plating layer 142a and the second via V2 can be formed simultaneously from the same material.

[0106] In this case, the 1-1 plating layer 142a can correspond to the first pattern layer 142 of the pads 140P and traces 140T of the third circuit pattern layer 140 described above, and the 1-2 plating layer 152a can correspond to the first pattern layer 152 of the pads 150P and traces 150T of the fourth circuit pattern layer 150. However, the 1-1 plating layer 142a may be thicker than the thickness of the first pattern layer 142 of the third circuit pattern layer 140, and the 1-2 plating layer 152a may be thicker than the thickness of the first pattern layer 152 of the fourth circuit pattern layer 150.

[0107] Next, referring to Figures 8 and 9, in the embodiment, a primary grinding step can be performed. In the first grinding step, when the first-1 plating layer 142a and the second via V2 are formed by plating, the second via hole VH2 causes a dimple phenomenon (a phenomenon in which the central part in the width direction of the first-1 plating layer 142a or the second via V2 is formed indented (not shown)). Because the upper surface of the first-1 plating layer 142a is not flat, when forming multiple insulating layers, it is possible to prevent warpage from occurring or poor connections between vias from occurring.

[0108] In this case, the primary grinding step may include a first step of grinding the first mask M1 and the 1-1 plating layer 142a together to form the first pattern layer 142 of the third circuit pattern layer 140, and a second step of grinding the first mask M1 and the 1-2 plating layer 152a together to form the first pattern layer 152 of the fourth circuit pattern layer 150. As a result of the first grinding step, the first pattern layer 142 of the third circuit pattern layer 140 and the first pattern layer 152 of the fourth circuit pattern layer 150 each have the first thickness T1 described above. In this embodiment, once the first grinding step is completed, a step of peeling off the first mask M1 can be performed. However, the embodiment is not limited thereto, and the following steps can be performed without the step of peeling off the first mask M1.

[0109] That is, referring to Figure 10, once the primary grinding process is completed, in this embodiment, a step of forming the second mask M2 can be performed. At this time, the second mask M2 may be formed after the removal of the first mask M1, or, unlike the first mask M1, it may be formed on top of the first mask M1. However, the second mask M2 may have an opening smaller than the opening of the first mask M1. As a result, at least a portion of the second mask M2 may be placed on the first pattern layer 142 of the third circuit pattern layer 140 and the first pattern layer 142 of the fourth circuit pattern layer 150.

[0110] Next, referring to Figure 11, in the embodiment, electroplating can be performed using the seed layers 141 and 151. Specifically, in the embodiment, a metallic substance can be filled into the opening of the second mask M2 to form the second-first plating layer 143a and the second-second plating layer 153a.

[0111] In this case, the 2-1 plating layer 143a can correspond to the second pattern layer 143 of the pad 140P of the third circuit pattern layer 140 described above, and the 2-2 plating layer 153a can correspond to the second pattern 153 of the pad 150P of the fourth circuit pattern layer 150. However, the 2-1 plating layer 143a may be thicker than the second pattern layer 143 of the third circuit pattern layer 140, and the 2-2 plating layer 153a may be thicker than the second pattern layer 153 of the fourth circuit pattern layer 150.

[0112] Next, referring to Figure 12, in the embodiment, a step of removing the second mask M2 can be performed. Then, in the embodiment, once the second mask M2 is removed, a step of etching the seed layers 141 and 151 can be performed. Specifically, in the embodiment, the region of the seed layer 141 that does not overlap with the first pattern layer 141 in the perpendicular direction of the seed layer 141, which is located on the first surface of the second insulating layer 112, can be etched and removed. Also, in the embodiment, the region of the seed layer 151 that does not overlap with the first pattern layer 151 in the perpendicular direction of the seed layer 151, which is located on the second surface of the third insulating layer 113, can be etched and removed.

[0113] Next, referring to Figure 13, in the embodiment, a first solder resist layer 160a can be formed on the second insulating layer 112. In this case, the first solder resist layer 160a can have the same height as the 2-1 plating layer 143a. Also in the embodiment, a second solder resist layer 170a can be formed on the third insulating layer 113. In this case, the second solder resist layer 170a can have the same height as the 2-2 plating layer 153a.

[0114] Next, referring to Figure 14, in the embodiment, a secondary grinding process can be performed. That is, the embodiment may include a first step of grinding the first solder resist layer 160a and the 2-1 plating layer 143a, and a second step of grinding the second solder resist layer 170a and the 2-2 plating layer 153a. As a result, in the embodiment, the first solder resist layer 160a and the 2-1 plating layer 143a can be ground to form the first protective layer 160 and the second pattern layer 143 of the pad 140P of the third circuit pattern layer 140. In addition, in the embodiment, the second solder resist layer 170a and the 2-2 plating layer 153a can be ground to form the second protective layer 170 and the second pattern layer 153 of the pad 150P of the fourth circuit pattern layer 150.

[0115] However, the secondary grinding step can be omitted. For example, the 2-1 plating layer 143a may be formed to a thickness corresponding to the second pattern layer 143 of the pad 140P of the third circuit pattern layer 140, and the 2-2 plating layer 153a may be formed to a thickness corresponding to the second pattern layer 153 of the pad 150P of the fourth circuit pattern layer 150. In such cases, the secondary grinding step can be omitted. However, the secondary grinding step may be added to improve reliability in cases where it is difficult to adjust the process conditions when forming the second pattern layers 143 and 153 of the pads 140P and 150P, and the control of the thickness of the second pattern layers 143 and 153 is incorrect.

[0116] Next, referring to Figure 15, in the embodiment, a step of forming a surface treatment layer 144 on the first protective layer 160 and the second pattern layer 143 of the pad 140P of the third circuit pattern layer 140 can be performed. Also in the embodiment, a step of forming a surface treatment layer 154 on the second protective layer 170 and the second pattern layer 153 of the pad 150P of the fourth circuit pattern layer 150 can be performed.

[0117] On the other hand, in the above-mentioned method, the secondary grinding process was performed during the manufacturing of the circuit board after the solder resist layer forming the first protective layer 160 and the second protective layer 170 had been formed. As a result, the first protective layer 160 and the second protective layer 170 were able to have the same height as the second pattern layers 143 and 153 as a result of the secondary grinding process.

[0118] In contrast, as shown in Figure 16, in other embodiments, a secondary grinding step can be performed to grind the second mask M2 and the 2-1 plating layer 143a and 2-2 plating layer 153a after the manufacturing in Figure 11 is completed. Thus, as shown in Figure 16, the second pattern layers 143 and 153 of the pads 140P and 150P of the third circuit pattern layer 140 and the fourth circuit pattern layer 150 can be formed before the solder resist layer is formed.

[0119] Next, referring to Figure 17, in the embodiment, first and second solder resist layers 160a and 170a can be formed on the second insulating layer 112 and the third circuit pattern layer 140, covering the second pattern layers 143 and 153. In the embodiment, a dipping process can be performed to adjust the height of the first and second solder resist layers 160a and 170a. That is, as shown in Figure 17, the first protective layer 160 and the second protective layer 170 can have the same height as the second patterns 142 and 153 through exposure and development processes, rather than through a grinding process.

[0120] Figure 18 shows a circuit board according to the second embodiment.

[0121] Referring to Figure 18, the circuit board according to the second embodiment is identical to the circuit board of the first embodiment shown in Figures 1 and 2, except for the structure of the second pad and the surface treatment layer. Therefore, only the second pad and the surface treatment layer will be explained.

[0122] The circuit board includes an insulating layer 212, a first circuit pattern layer 212 corresponding to the inner circuit pattern layer, vias V2, pads, and a first protective layer 260.

[0123] The circuit board includes a third circuit pattern layer 240 corresponding to the first outermost circuit pattern layer. The third circuit pattern layer 240 also includes pads 240P and traces 240T.

[0124] The trace 240T of the third circuit pattern layer 240 may include a seed layer 241 and a first pattern layer 242. The pad 240P of the third circuit pattern layer 240 may include a seed layer 241, a first pattern layer 242, a second pattern layer 243, and a surface treatment layer 244.

[0125] In this case, the upper surface of the second pattern layer 143 and the upper surface of the first protective layer 160 of the pad 140P in the first embodiment were located on the same plane.

[0126] In contrast, the upper surface of the second pattern layer 243 of the pad 240P in the second embodiment can be located on a plane different from that of the upper surface of the first protective layer 260. Specifically, the upper surface of the first protective layer 260 can be located lower than the upper surface of the second pattern layer 243.

[0127] That is, the first protective layer 260 is formed by removing the solder resist layer through grinding or dipping, as described above. When the first protective layer 260 is formed through grinding, the solder resist layer may be polished more than the second pattern layer 243 due to the difference in hardness between the second pattern layer 243 and the solder resist layer. As a result, the upper surface of the first protective layer 260 can be positioned lower than the upper surface of the second pattern layer 243, as described above.

[0128] In contrast, in this embodiment, in order to improve the reliability of the surface of the second pattern 243, the upper surface of the first protective layer 260 is positioned lower than the upper surface of the second pattern layer 243, as described above. That is, the first protective layer 260 is formed by removing the solder resist layer covering the surface of the second pattern layer 243, as described above. When grinding or dipping is performed so that the upper surface of the first protective layer 260 is at the same height as the upper surface of the second pattern layer 243, a reliability problem may occur in which the upper surface of the second pattern layer 243 is not completely exposed depending on the process capability. Furthermore, even if the upper surface of the second pattern layer 243 is completely exposed, resin constituting the solder resist layer may remain on the upper surface of the second pattern layer 243. Therefore, in this embodiment, in order to solve the above problems, the upper surface of the first protective layer 260 is positioned lower than the upper surface of the second pattern layer 243.

[0129] As a result, in the second embodiment, the surface treatment layer 244 is formed not only on the upper surface of the second pattern layer 243 but also on a portion of its side surfaces. That is, the second pattern layer 243 includes a protruding region that extends from the upper surface of the first protective layer 260.

[0130] The surface treatment layer 244 may include a first portion positioned on the upper surface of the protruding region of the second pattern layer 243 and a second portion positioned on the side surface of the protruding region of the second pattern layer 243. Similar to the first embodiment, a portion of the second portion of the second pattern layer 243 may be in contact with the upper surface of the first protective layer 260.

[0131] In this case, the protruding region of the second pattern layer 243 may be smaller than the region where the second pattern layer 243 and the first protective layer 260 are in contact. That is, the upper surface of the first protective layer 260 can be positioned slightly lower than the upper surface of the second pattern layer 243. If the protruding region protrudes too far from the upper surface of the first protective layer 260, the adhesive members between chips mounted on the circuit board may become connected to each other, causing disconnections. When forming solder balls on the circuit board to connect to the main printed circuit board, disconnections may occur between the solder balls.

[0132] Figure 19 shows a circuit board according to the third embodiment.

[0133] Referring to Figure 19, the circuit board according to the third embodiment is identical to the circuit board of the first embodiment in all aspects except for the shape of the seed layer, first pattern, and second pattern that constitute the pad of the outermost circuit pattern layer, the third circuit pattern layer. Therefore, only the shape of the seed layer, first pattern, and second pattern that constitute the pad will be explained.

[0134] First, in the first embodiment, the sides of the seed layer 141, the first pattern layer 142, and the second pattern layer 152 of the pad 140P were planes perpendicular to the upper surface of the first protective layer 160.

[0135] In contrast, in the third embodiment, at least one side of the seed layer 341, the first pattern layer 342, and the second pattern layer 343 of the pad 340P may include a rounded curved surface. That is, referring to Figure 12, in the embodiment, the manufacturing process of the circuit board includes a step of etching the seed layer. In this embodiment, the etching process time or etching conditions (e.g., etching rate) of the seed layer is adjusted so that not only the seed layer but also a portion of the side of the first pattern layer 342 and / or the side of the second pattern layer 343 are etched together.

[0136] As a result, in this embodiment, at least one of the side surfaces of the seed layer 341, the first pattern layer 342, and the second pattern layer 343 can be formed into a rounded curved surface by etching.

[0137] On the other hand, as in the first embodiment, in the first embodiment, when the sides of the seed layer 141, first pattern layer 142, and second pattern layer 152 of the pad 140P are perpendicular to the upper surface of the first protective layer 160, a problem occurs in the process of forming the first protective layer 160 in which air fills the interface between them, resulting in a void problem corresponding to the air space.

[0138] In contrast, as in the third embodiment, if at least one side of the seed layer 341, first pattern layer 342, and second pattern layer 343 of the pad 340P has a rounded curved surface, the problem of air filling can be solved, and the reliability problems such as voids caused by this can be solved.

[0139] On the other hand, if at least one side surface of the seed layer 341, first pattern layer 342, and second pattern layer 343 of the pad 340P has a rounded curved surface, the contact area between the interface with the first protective layer can be increased compared to when the side surface is formed as a flat surface, thereby improving the adhesion strength with the first protective layer 360 and preventing the first protective layer 360 from peeling off.

[0140] In the embodiment, a circuit pattern layer is included. The circuit pattern layer includes an electrode layer which is a pad on which a chip is mounted. The electrode layer may include a first to fourth layer. For example, the electrode layer may include a seed layer, a first pattern layer, a second pattern layer, and a surface treatment layer. In this case, the surface treatment layer may include a first portion disposed on the upper surface of the second pattern layer and a second portion extending from the first portion and disposed on the upper surface of the protective layer. As a result, the embodiment can secure a wide space for the placement of an adhesive member (not shown) for mounting the chip by the surface treatment layer including the second portion, thereby improving chip bonding performance. That is, in the embodiment, the width of the surface treatment layer can be made larger than the width of the second pattern layer, thereby increasing the contact area with the adhesive member. As a result, in the embodiment, the contact area with the adhesive member can be increased, thereby further improving bonding performance with adhesive members such as solder balls and wires.

[0141] Furthermore, by positioning the second portion on the upper surface of the protective layer, the protective layer is able to support the second portion when an adhesive member (not shown) for mounting the chip is placed. As a result, in this embodiment, unlike conventional overhang structures (for example, structures in which the end of the surface treatment layer is positioned away from the protective layer, the first pattern layer, and the second pattern layer without contact), the surface treatment layer can be prevented from being damaged by the adhesive member.

[0142] Furthermore, in the embodiment, the upper surface of the second pattern layer can be positioned higher than the upper surface of the protective layer. This prevents the resin of the protective layer from remaining on the upper surface of the second pattern layer. As a result, in the embodiment, the entire upper surface of the pad can be used as a space for connection with the chip. Therefore, in the embodiment, the circuit integration density can be improved, and electrical and physical reliability can be improved. Moreover, in the embodiment, the surface treatment layer is also positioned on a part of the protruding side surface of the second pattern layer. This improves the contact area between the surface treatment layer and the second pattern layer. Therefore, in the embodiment, the problem of the surface treatment layer separating from the second pattern layer can be solved, and electrical and physical reliability can be improved as a result.

[0143] Furthermore, in the embodiment, at least one side of the seed layer, first pattern layer, and second pattern layer constituting the pad is made to have a rounded curved surface. This increases the contact area between the seed layer, first pattern layer, and second pattern layer and the protective layer in the embodiment. This solves the problem of lifting between the pad and the protective layer (for example, the formation of an air layer between the protective layer and the pad) in the process of forming the protective layer in the embodiment. Therefore, in the embodiment, the problem of the protective layer separating from the pad can be solved, and the overall physical and electrical reliability of the circuit board can be improved.

[0144] Figure 20 shows a package substrate according to an embodiment.

[0145] Referring to Figure 20, the package substrate 200 includes at least one of the circuit boards shown in Figures 1, 18, and 19. For convenience of explanation, the following description will focus on a package substrate including the circuit board shown in Figure 1. However, the embodiments are not limited to this, and the package substrates described below may also include the circuit boards shown in Figure 18 or 19.

[0146] Furthermore, the package substrate 200 includes an adhesive member that is placed on the pads of the circuit board.

[0147] Specifically, the package substrate 200 may include a first adhesive member 210 disposed on the pad 140P of the third circuit pattern layer 140 of the circuit board. The package substrate 200 may also include a second adhesive member 240 disposed on the pad 150P of the fourth circuit pattern layer 150 of the circuit board.

[0148] The first adhesive member 210 and the second adhesive member 240 may have different shapes from each other. For example, the first adhesive member 210 may be hexahedral. For example, the cross-section of the first adhesive member 210 may be quadrilateral. For example, the cross-section of the first adhesive member 210 may be rectangular or square. The second adhesive member 240 may be spherical. For example, the cross-section of the second adhesive member 240 may be circular or semicircular. For example, the cross-section of the second adhesive member 240 may be partially or entirely rounded. As an example, the cross-sectional shape of the second adhesive member 240 may be flat on one side and curved on the other side opposite to the flat side. On the other hand, the second adhesive member 240 may be, but is not limited to, a solder ball.

[0149] A chip 220 may be mounted on the first adhesive member 210. For example, the chip 220 may include a drive IC chip. For example, the chip 220 may mean a variety of chips including sockets or elements other than the drive IC chip. For example, the chip 220 may include at least one of the following: a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, or a chip capacitor. For example, the chip 220 may be a power management integrated circuit (PMIC). For example, the chip 220 may be a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory. For example, the chip 220 may be an application processor (AP) chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC). Here, the drawings show that only one chip is mounted on the package substrate 200, but this is not limited to this. For example, the third circuit pattern layer 140 of the circuit board may include a plurality of pads spaced apart from each other. Chips may be mounted on each of these plurality of pads. For example, the plurality of chips may include a first AP chip corresponding to a central processor (CPU) and a second AP chip corresponding to a graphics processor (GPU).

[0150] A molding layer 230 may be formed on the circuit board. The molding layer 230 may be positioned to cover the mounted chip 220. For example, the molding layer 230 may be, but is not limited to, an EMC (Epoxy Mold Compound) formed to protect the mounted chip 220.

[0151] On the other hand, the first spacing of the multiple pads 140P of the third circuit pattern layer 140 in the embodiment may differ from the second spacing of the multiple pads 150P of the fourth circuit pattern layer 150. For example, the first spacing of the multiple pads 140P of the third circuit pattern layer 140 may correspond to terminals (not shown) of the chip 220. Also, the second spacing of the multiple pads 150P of the fourth circuit pattern layer 150 may correspond to terminals (not shown) of an external board (not shown) attached via the second adhesive member 240. In this case, the first spacing of the multiple pads 140P of the third circuit pattern layer 140 may be smaller than the second spacing of the multiple pads 150P of the fourth circuit pattern layer 150. For example, the third circuit pattern layer 140 may be a fine pattern corresponding to terminals (not shown) of the chip 220.

[0152] The vias V1, V2, V3, the first circuit pattern layer 120, and the second circuit pattern layer 130 of the circuit board can connect the multiple pads 140P of the third circuit pattern layer 140 and the multiple pads 150P of the fourth circuit pattern layer 150, which have different spacings from each other.

[0153] In this case, vias V1, V2, and V3 can have different widths from each other in order to connect a pad 140P having a smaller first spacing with a pad 150P having a larger second spacing.

[0154] For example, the second via V2 may have a width corresponding to the first spacing of the pad 140P. For example, the third via V2 may have a width corresponding to the second spacing of the pad 150P. For example, the width of the first via V1 may be between the width of the second via V2 and the width of the third via V3. For example, the widths of vias V1, V2, and V3 in the embodiment may gradually decrease as they get closer to the pad 140P or as they get further away from the pad 150P. For example, the second via V2 in the embodiment may have a minimum width, the third via V3 may have a maximum width, and the first via V1 may have a width between the second via V2 and the third via V3.

[0155] The features, structures, and effects described in the above embodiments are included in at least one embodiment and are not necessarily limited to just one embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0156] While the above description has focused on examples, these are merely illustrative and not limiting. Anyone with ordinary knowledge in the field to which the examples belong will understand that a variety of modifications and applications not illustrated above are possible, as long as they do not deviate from the essential characteristics of these examples. For example, each component specifically shown in the examples can be modified and implemented. Such differences in modifications and applications should be interpreted as being included within the scope of the examples set forth in the attached claims.

Claims

1. Insulating layer and, A protective layer, which includes an opening, is disposed on the insulating layer. The pad portion is disposed on the insulating layer and positioned within the opening, The aforementioned pad portion is A seed layer disposed on the insulating layer, A lower pad placed on the seed layer, An upper pad positioned on the lower pad, The upper pad includes a surface treatment layer disposed on the upper pad, The width of the lower pad is greater than the width of the upper pad. The thickness of the lower pad is greater than the thickness of the upper pad. The upper surface of the protective layer and the upper surface of the upper pad are located on the same plane. The width of the surface treatment layer is smaller than the width of the lower pad and larger than the width of the upper pad. The surface treatment layer includes a first portion disposed on the upper surface of the upper pad and a second portion extending from the first portion and disposed on the upper surface of the protective layer, The second part is a circuit board that does not come into contact with the pad portion.

2. The lower pad of the pad portion is The circuit board according to claim 1, comprising the same metallic substance as the upper pad of the pad portion.

3. The thickness of the lower pad of the pad portion is The circuit board according to claim 1, wherein the thickness of the surface treatment layer on the pad portion is greater than the thickness of the surface treatment layer on the pad portion.

4. The circuit board according to claim 1, wherein at least one side surface of the lower pad and the upper pad of the pad portion includes a curved surface whose width increases toward the upper surface of the insulating layer.

5. The insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer. The circuit board according to claim 1, wherein the seed layer of the pad portion is arranged on the second insulating layer.

6. The invention further includes an interlayer circuit pattern disposed between the first insulating layer and the second insulating layer, The circuit board according to claim 5, wherein the surface roughness (Ra) of the interlayer circuit pattern is different from the surface roughness (Ra) of the lower pad of the pad portion.

7. The circuit board according to claim 6, wherein the surface roughness (Ra) of the interlayer circuit pattern is greater than the surface roughness (Ra) of the lower pad of the pad portion.

8. The circuit board according to claim 7, wherein the surface roughness (Ra) of the protective layer is less than the surface roughness (Ra) of the interlayer circuit pattern and greater than the surface roughness (Ra) of the lower pad of the pad portion.

9. A circuit board according to any one of claims 1 to 8, An adhesive member disposed on the pad portion of the circuit board, A semiconductor chip placed on the adhesive member, A semiconductor package including a molding layer for molding the aforementioned semiconductor chip.

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