Drive device, drive method, and power conversion device

Abstract

To suppress deterioration of a SiC-MOSFET.SOLUTION: A driving device switches a first SiC-MOSFET and a second SiC-MOSFET alternately with a dead time in which the first SiC-MOSFET and the second SiC-MOSFET connected in serial are turned off provided in-between, and comprises: a first driving circuit that sets a gate voltage of the first SiC-MOSFET to a first intermediate voltage higher than a first negative power supply voltage and lower than a first threshold value voltage of the first SiC-MOSFET in the dead time; and a second driving circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage higher than a second negative power supply voltage and lower than a second threshold value voltage of the second SiC-MOSFET in the dead time.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a driving device, a driving method, and a power conversion device.

Background Art

[0002] Conventionally, there has been a power conversion circuit in which two switching elements connected in series are connected in parallel to a DC power supply. In such a power conversion circuit, as disclosed in Patent Document 1 below, during a dead time period, it is known to bias the gate voltages of the two switching elements in the negative direction together so that the switching elements do not turn on simultaneously.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a current flows through the body diode of a SiC-MOSFET, there is a problem that its characteristics deteriorate. When the driving method of Patent Document 1 is applied to drive a SiC-MOSFET, there is a risk that current will flow through the body diode of the SiC-MOSFET during the dead time, and the deterioration of the SiC-MOSFET will progress.

[0005] The present disclosure provides a driving device and a driving method for suppressing the deterioration of a SiC-MOSFET, and a power conversion device including the driving device.

Means for Solving the Problems

[0006] In one aspect of the present disclosure, A drive device that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between during which the first SiC-MOSFET and the second SiC-MOSFET are turned off, A first drive circuit sets the gate voltage of the first SiC-MOSFET to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time, A drive device is provided, comprising a second drive circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time. A power conversion device equipped with the drive device is also provided. [Effects of the Invention]

[0007] According to this disclosure, the degradation of SiC-MOSFETs can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example configuration of a power conversion device according to one embodiment. [Figure 2] This is a timing chart showing the operation of a driving method according to one comparative example. [Figure 3] This figure shows an example of the characteristics of the body diode of a SiC-MOSFET. [Figure 4] This is a timing chart showing the operation of the first driving method of this disclosure. [Figure 5] This figure shows a first configuration example of a drive device included in a power conversion device according to one embodiment. [Figure 6] This is a timing chart showing the operation of a drive unit having the configuration shown in Figure 5. [Figure 7] This figure shows a second example of the configuration of the drive device included in a power conversion device according to one embodiment. [Figure 8] This timing chart shows an example of the operating waveform when the system stops running. [Figure 9]This is a timing chart showing the operation of the second driving method of this disclosure. [Figure 10] This figure shows a third configuration example of the drive device included in a power conversion device according to one embodiment. [Modes for carrying out the invention]

[0009] One embodiment will be described below.

[0010] Figure 1 shows an example configuration of a power conversion device according to one embodiment. The power conversion device 101 shown in Figure 1 may be an inverter that converts DC to AC, or a converter that converts DC to DC. For example, the power conversion device 101 is an inverter that converts DC power supplied from a DC power source 400 into AC power to be supplied to a load 300 such as a motor. The power conversion device 101 comprises a control device 10, a drive device 20, an upper arm Q1, a lower arm Q2, and a DC power source 400.

[0011] Figure 1 shows a single-phase arm in which an upper arm Q1 and a lower arm Q2 are connected in series, and a single-phase drive unit 20 that drives the arm. If the power converter 101 is an inverter that generates, for example, three-phase AC power of U, V, and W, the power converter 101 includes a three-phase arm with the same configuration as the arm shown in Figure 1, and a three-phase drive unit with the same configuration as the drive unit 20 shown in Figure 1. The connection point between the high-side upper arm Q1 and the low-side lower arm Q2 is connected to the load 300.

[0012] The drive unit 20 alternately switches the upper arm Q1 and the lower arm Q2, which are connected in series, with a dead time in between, according to command signals Q1sig and Q2sig supplied from the control device 10. Command signal Q1sig is a control signal that commands the on or off period of the upper arm Q1. Command signal Q2sig is a control signal that commands the on or off period of the lower arm Q2. The drive unit 20 has a first drive circuit 21 and a second drive circuit 22.

[0013] The first drive circuit 21 drives the upper arm Q1 according to the command signals Q1sig and Q2sig. The first drive circuit 21 switches the gate-source voltage VGS1 of the upper arm Q1 to the first positive power supply voltage V1P or the first negative power supply voltage V1N. The second drive circuit 22 drives the lower arm Q2 according to the command signals Q1sig and Q2sig. The second drive circuit 22 switches the gate-source voltage VGS2 of the lower arm Q2 to the second positive power supply voltage V2P or the second negative power supply voltage V2N.

[0014] Both the upper arm Q1 and the lower arm Q2 are SiC-MOSFETs having a gate, a source, and a drain. SiC is silicon carbide, and MOSFET is an abbreviation for metal-oxide-semiconductor field-effect transistor. The SiC-MOSFET has a channel portion between the source and the drain and a body diode whose direction from the source to the drain is the forward direction. The upper arm Q1 is an example of the first SiC-MOSFET. The lower arm Q2 is an example of the second SiC-MOSFET.

[0015] Next, the operation when the driving method performed by the driving device 20 is applied to the driving of one phase (for example, the U-phase arm) of the power conversion device 101 will be described. Note that the other two phases (for example, the V-phase and the W-phase) other than the one phase described below operate in the same manner as this one phase, so the following description of the operation of one phase is applicable to the operations of the other phases.

[0016] First, for the purpose of comparison with the driving method of the present disclosure, a driving method according to a comparative example will be described.

[0017] FIG. 2 is a timing chart showing the operation according to a driving method of a comparative example. In the following description of FIG. 2, for convenience, the reference numerals of the power conversion device 101 shown in FIG. 1 are used for explanation. The switching operation of one phase of the power conversion device 101 is divided into four operations: mode MD1, mode MD2, mode MD3, and mode MD4, as shown in FIG. 2.

[0018] During the operation of mode MD1 from time t1 to time t2, the command signal Q1sig is at a high level and the command signal Q2sig is at a low level. Therefore, the gate-source voltage VGS1 of the upper arm Q1 is the same voltage as the first positive power supply voltage P1, and the gate-source voltage VGS2 of the lower arm Q2 is the same voltage as the second negative power supply voltage V2N.

[0019] Therefore, the upper arm Q1 is ON and the lower arm Q2 is OFF, and the drain current ID1 of the upper arm Q1 flows as the output current Iu to the U-phase coil of the load 300. As a result, the drain current ID1 of the upper arm Q1 increases, and the output current Iu also gradually increases. Furthermore, the output current Iu is a positive value. In mode MD1, the lower arm Q2 is OFF, so the value of the drain current ID2 is 0 [A].

[0020] Next, at time t2, the switching operation of one phase of the power converter 101 switches from mode MD1 to mode MD2. Mode MD2 is a mode in which the upper arm Q1 is switched from the ON state to the OFF state, thereby turning off both the upper arm Q1 and the lower arm Q2 in order to form a first dead time DT1. The first dead time DT1 is a period to prevent a through-current from flowing between the upper arm Q1 and the lower arm Q2 when both the upper arm Q1 and the lower arm Q2 are simultaneously turned ON.

[0021] In Mode MD2 operation, the gate-source voltage VGS1 of the upper arm Q1 becomes equal to the first negative power supply voltage V1N after the Miller period, and the gate-source voltage VGS2 of the lower arm Q2 becomes equal to the second negative power supply voltage V2N. As a result, the upper arm Q1 switches from the ON state to the OFF state, and the lower arm Q2 remains in the OFF state. Therefore, both the upper arm Q1 and the lower arm Q2 are in the OFF state.

[0022] At this time, the freewheeling current flowing through the body diode built into the lower arm Q2 flows to the load 300 as the output current Iu. Since this freewheeling current is based on the inductance of the load 300, the output current Iu gradually decreases while maintaining a positive value. This freewheeling current is the current that passes through the body diode built into the lower arm Q2 and corresponds to the drain current ID2 that flows from the source to the drain of the lower arm Q2. On the other hand, in mode MD2, the upper arm Q1 is in the off state, so the drain current ID1 of the upper arm Q1 decreases to 0 [A].

[0023] Subsequently, at time t3, the switching operation of one phase of the power converter 101 switches from mode MD2 to mode MD3. Mode MD3 is a mode in which the lower arm Q2 switches from the off state to the on state, and the return current flows to both the channel and body diode of the lower arm Q2.

[0024] In mode MD3, the command signal Q2sig inverts from a low level to a high level. The second positive power supply voltage V2P is applied to the gate of the lower arm Q2, and the reference potential M is applied to the source of the lower arm Q2, so the gate-source voltage VGS2 of the lower arm Q2 becomes the second positive power supply voltage VP2. As a result, a forward bias voltage is output to the gate-source voltage VGS2 of the lower arm Q2, and the lower arm Q2 switches from the off state to the on state. When the lower arm Q2 is in the on state, the freewheel current flows through both the channel and the body diode of the lower arm Q2. Therefore, in mode MD3, the on-resistance of the channel and the on-resistance of the body diode of the lower arm Q2 are connected in parallel, resulting in a lower resistance compared to mode MD2, where the freewheel current flows only through the body diode. In mode MD3, the upper arm Q1 remains in the off state.

[0025] In mode MD3, the return current is based on the inductance of the load 300, similar to mode MD2, so the value of the return current gradually approaches 0 (A). Consequently, the output current Iu gradually decreases while maintaining a positive value.

[0026] Subsequently, at time t4, the system switches from mode MD3 to mode MD4. Mode MD4, like mode MD2 described above, is a mode in which the lower arm Q2 is switched from the ON state to the OFF state, thereby turning off both the upper arm Q1 and the lower arm Q2, in order to form a second dead time DT2. The second dead time DT2 is a period to prevent through-current from flowing between the upper arm Q1 and the lower arm Q2 due to both the upper arm Q1 and the lower arm Q2 being turned on simultaneously.

[0027] In Mode MD4 operation, the gate-source voltage VGS2 of the lower arm Q2 becomes equal to the second negative power supply voltage V2N after the Miller period, and the gate-source voltage VGS1 of the upper arm Q1 becomes equal to the first negative power supply voltage V1N. As a result, the lower arm Q2 switches from the ON state to the OFF state, and the upper arm Q1 remains in the OFF state. Therefore, both the upper arm Q1 and the lower arm Q2 are in the OFF state.

[0028] In this state, the freewheeling current flowing through the body diode built into the lower arm Q2 flows to the load 300 as the output current Iu. Since this freewheeling current is based on the inductance of the load 300, the output current Iu gradually decreases while maintaining a positive value. Also, in mode MD4, the upper arm Q1 is in the off state, so the drain current ID1 of the upper arm Q1 remains at 0 [A]. On the other hand, this freewheeling current is the current that flows through the body diode built into the lower arm Q2 and corresponds to the drain current ID2 that flows from the source to the drain of the lower arm Q2.

[0029] Subsequently, at time t5, the switching operation of one phase of the power converter 101 switches from mode MD4 to mode MD1. In mode MD1, as described above, the upper arm Q1 is turned on, and the lower arm Q2 remains off.

[0030] In this mode MD1, the command signal Q1sig inverts from a low level to a high level, while the command signal Q2sig remains at a low level. As a result, the upper arm Q1 switches from the off state to the on state, the drain-source voltage VDS1 of the upper arm Q1 drops from the first positive power supply voltage V1P to "0", and the drain current ID1 increases from zero in the positive direction (from drain to source).

[0031] On the low side, the lower arm Q2 remains in the off state, but when the upper arm Q1 turns on, a high dv / dt occurs in the lower arm Q2 (the drain-source voltage VDS2 rises sharply), and a reverse recovery current due to the high dv / dt flows through the body diode of the lower arm Q2. After the reverse recovery current converges, the drain current ID2 becomes zero.

[0032] However, as explained above, during dead times DT1 and DT2, the freewheeling current flows only through the body diode of the lower arm Q2, which can cause the lower arm Q2, a SiC-MOSFET, to degrade. Also, the on-voltage (forward voltage) of the body diode is relatively high, which can contribute to increased losses in the lower arm Q2.

[0033] Figure 3 shows an example of the characteristics of the body diode of a SiC-MOSFET. The drain-source voltage (voltage across the body diode) on the horizontal axis of Figure 3 is shown as the voltage viewed from the source to the drain, and is therefore represented as a negative value. Increasing the gate-source voltage reduces the drain-source voltage (voltage across the body diode), thus reducing losses. In the driving method shown in Figure 2 above, a reverse bias (negative power supply voltage) is applied between the gate and source during the dead time, resulting in large losses. Focusing on this point, the driving method of this disclosure sets the voltage applied between the gate and source of the SiC-MOSFET (gate voltage) during the dead time to an intermediate voltage that is higher than the negative power supply voltage and lower than the threshold voltage of the SiC-MOSFET. As a result, the on-voltage (forward voltage) of the body diode decreases, reducing the losses of the body diode and suppressing the degradation of the SiC-MOSFET.

[0034] Figure 4 is a timing chart showing the operation of the first driving method of this disclosure. In the following description of Figure 4, the reference numerals of the power converter 101 shown in Figure 1 will be used. The switching operation of one phase of the power converter 101 is divided into four operations, as shown in Figure 4: Mode MD1, Mode MD2, Mode MD3, and Mode MD4.

[0035] During the operation of mode MD1 from time t1 to time t2, the command signal Q1sig is at a high level and the command signal Q2sig is at a low level. Therefore, the gate-source voltage VGS1 of the upper arm Q1 is the same voltage as the first positive power supply voltage P1, and the gate-source voltage VGS2 of the lower arm Q2 is the same voltage as the second negative power supply voltage V2N.

[0036] Therefore, the upper arm Q1 is ON and the lower arm Q2 is OFF, and the drain current ID1 of the upper arm Q1 flows as the output current Iu to the U-phase coil of the load 300. As a result, the drain current ID1 of the upper arm Q1 increases, and the output current Iu also gradually increases. Furthermore, the output current Iu is a positive value. In mode MD1, the lower arm Q2 is OFF, so the value of the drain current ID2 is 0 [A].

[0037] Thus, in mode MD1, the first drive circuit 21 sets the gate voltage of the upper arm Q1 to the first positive power supply voltage V1P, and the second drive circuit 22 sets the gate voltage of the lower arm Q2 to the second negative power supply voltage V2N.

[0038] Next, at time t2, the switching operation of one phase of the power converter 101 switches from mode MD1 to mode MD2. Mode MD2 is the mode for forming the first dead time DT1. The first dead time DT1 is the period immediately after the ON command period of the upper arm Q1 by command signal Q1sig and immediately before the ON command period of the lower arm Q2 by command signal Q2sig.

[0039] In Mode MD2 operation, the gate-source voltage VGS1 of the upper arm Q1 becomes the first intermediate voltage VM1 after the Miller period, and the gate-source voltage VGS2 of the lower arm Q2 becomes the second intermediate voltage VM2. The first intermediate voltage VM1 is higher than the first negative power supply voltage V1N and lower than the first threshold voltage of the upper arm Q1, and is zero in the example shown in Figure 4. The second intermediate voltage VM2 is higher than the second negative power supply voltage V2N and lower than the second threshold voltage of the lower arm Q2, and is zero in the example shown in Figure 4.

[0040] At this time, the second intermediate voltage VM2 is zero, so the channel of the lower arm Q2 opens slightly. As a result, the circulating current (recirculating current) flowing in mode MD2 flows through both the channel and the body diode of the lower arm Q2. Therefore, in mode MD2, the on-resistance of the channel and the on-resistance of the body diode of the lower arm Q2 are connected in parallel. This reduces the voltage between the drain and source of the lower arm Q2, thus reducing the loss of the lower arm Q2. In addition, since the rectified current (recirculating current) is divided between the body diode and the channel, the current flowing through the body diode is reduced, and the progression of degradation caused by current flowing through the body diode can be suppressed.

[0041] In mode MD2, the freewheeling current flowing through the channel and body diode of the lower arm Q2 flows to the load 300 as the output current Iu. Since this freewheeling current is based on the inductance of the load 300, the output current Iu gradually decreases while maintaining a positive value. This freewheeling current is the current that flows through the channel and body diode of the lower arm Q2 and corresponds to the drain current ID2 that flows from the source to the drain of the lower arm Q2. On the other hand, in mode MD2, the upper arm Q1 is in the off state, so the drain current ID1 of the upper arm Q1 decreases to 0 [A].

[0042] Thus, in mode MD2, when the first dead time DT1 begins, the first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first positive power supply voltage V1P to the first intermediate voltage VM1. On the other hand, when the first dead time DT1 begins, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second negative power supply voltage V2N to the second intermediate voltage VM2.

[0043] Subsequently, at time t3, the switching operation of one phase of the power converter 101 switches from mode MD2 to mode MD3. Mode MD3 is a mode in which the lower arm Q2 switches from the off state to the on state, and the return current flows to both the channel and body diode of the lower arm Q2.

[0044] In mode MD3, the command signal Q2sig inverts from a low level to a high level. The second positive power supply voltage V2P is applied to the gate of the lower arm Q2, and the reference potential M is applied to the source of the lower arm Q2, so the gate-source voltage VGS2 of the lower arm Q2 becomes the second positive power supply voltage VP2. As a result, a forward bias voltage is output to the gate-source voltage VGS2 of the lower arm Q2, and the lower arm Q2 switches from the off state to the on state. When the lower arm Q2 is in the on state, the freewheel current flows through both the channel and the body diode of the lower arm Q2. Therefore, in mode MD3, the on-resistance of the channel and the on-resistance of the body diode of the lower arm Q2 are connected in parallel, resulting in a lower resistance compared to mode MD2, where the freewheel current flows only through the body diode. In mode MD3, the upper arm Q1 remains in the off state.

[0045] In mode MD3, the return current is based on the inductance of the load 300, similar to mode MD2, so the value of the return current gradually approaches 0 (A). Consequently, the output current Iu gradually decreases while maintaining a positive value.

[0046] Thus, in mode MD3, when the first dead time DT1 ends, the first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first intermediate voltage VM1 to the first negative power supply voltage V1N. Meanwhile, when the first dead time DT1 ends, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second intermediate voltage VM2 to the second positive power supply voltage V2P.

[0047] Subsequently, at time t4, the mode switches from MD3 to MD4. Mode MD4, like the previously mentioned mode MD2, is a mode for forming a second dead time DT2. The second dead time DT is the period immediately following the ON command period of the lower arm Q2 by command signal Q2sig and immediately following the ON command period of the upper arm Q1 by command signal Q1sig.

[0048] In mode MD4 operation, the gate-source voltage VGS2 of the lower arm Q2 becomes the second intermediate voltage VM2 after the Miller period, and the gate-source voltage VGS1 of the upper arm Q1 becomes the first intermediate voltage VM1. The first intermediate voltage VM1 is higher than the first negative power supply voltage V1N and lower than the first threshold voltage of the upper arm Q1, and is zero in the example shown in Figure 4. The second intermediate voltage VM2 is higher than the second negative power supply voltage V2N and lower than the second threshold voltage of the lower arm Q2, and is zero in the example shown in Figure 4.

[0049] At this time, the second intermediate voltage VM2 is zero, so the channel of the lower arm Q2 opens slightly. As a result, the circulating current (recirculating current) flowing in mode MD4 flows through both the channel and the body diode of the lower arm Q2. Therefore, in mode MD4, the on-resistance of the channel and the on-resistance of the body diode of the lower arm Q2 are connected in parallel. This reduces the voltage between the drain and source of the lower arm Q2, thus reducing the loss of the lower arm Q2. In addition, since the rectified current (recirculating current) is divided between the body diode and the channel, the current flowing through the body diode is reduced, and the progression of degradation caused by current flowing through the body diode can be suppressed.

[0050] In mode MD4, the freewheel current flowing through the channel and body diode of the lower arm Q2 flows to the load 300 as the output current Iu. Since this freewheel current is based on the inductance of the load 300, the output current Iu gradually decreases while maintaining a positive value. This freewheel current is the current that flows through the channel and body diode of the lower arm Q2 and corresponds to the drain current ID2 that flows from the source to the drain of the lower arm Q2. On the other hand, in mode MD4, the upper arm Q1 is in the off state, so the drain current ID1 of the upper arm Q1 remains at 0 [A].

[0051] Thus, in mode MD4, when the second dead time DT2 begins, the first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first negative power supply voltage V1N to the first intermediate voltage VM1. On the other hand, when the first dead time DT1 begins, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second positive power supply voltage V2P to the second intermediate voltage VM2.

[0052] Subsequently, at time t5, the switching operation of one phase of the power converter 101 switches from mode MD4 to mode MD1. In mode MD1, as described above, the upper arm Q1 is turned on, and the lower arm Q2 remains off.

[0053] In this mode MD1, the command signal Q1sig inverts from a low level to a high level, while the command signal Q2sig remains at a low level. As a result, the upper arm Q1 switches from the off state to the on state, the drain-source voltage VDS1 of the upper arm Q1 drops from the first positive power supply voltage V1P to "0", and the drain current ID1 increases from zero in the positive direction (from drain to source).

[0054] On the low side, the lower arm Q2 remains in the off state, but when the upper arm Q1 turns on, a high dv / dt occurs in the lower arm Q2 (the drain-source voltage VDS2 rises sharply), and a reverse recovery current due to the high dv / dt flows through the body diode of the lower arm Q2. After the reverse recovery current converges, the drain current ID2 becomes zero.

[0055] Thus, in mode MD1, when the second dead time DT2 ends, the first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first intermediate voltage VM1 to the first positive power supply voltage V1P. On the other hand, when the second dead time DT2 ends, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second intermediate voltage VM2 to the second negative power supply voltage V2N.

[0056] Next, we will describe a more specific example of a drive system configuration.

[0057] Figure 5 shows a first configuration example of a drive device included in a power converter according to one embodiment. The first drive circuit 21 has a first dead time detection circuit 30 that detects dead times DT1 and DT2 based on the command contents of command signals Q1sig and Q2sig. The second drive circuit 22 has a second dead time detection circuit 40 that detects dead times DT1 and DT2 based on the command contents of command signals Q1sig and Q2sig.

[0058] The first dead time detection circuit 30 includes signal isolation elements 31, 32, an inverting circuit 33, and an exclusive OR gate 34. The second dead time detection circuit 40 also includes signal isolation elements 41, 42, an inverting circuit 43, and an exclusive OR gate 44. Each signal isolation element is a circuit that transfers and outputs an input command signal, such as a photocoupler. Each inverting circuit inverts the logic of the input signal and outputs it. The exclusive OR gate outputs the exclusive OR of two input logic levels.

[0059] Furthermore, the first drive circuit 21 has a first gate drive circuit 35 that drives the upper arm Q1 using the dead time detected by the first dead time detection circuit 30. The second drive circuit 22 has a second gate drive circuit 45 that drives the lower arm Q2 using the dead time detected by the second dead time detection circuit 40.

[0060] The first gate drive circuit 35 includes resistors RG1P, RG1N, and RG1M, and switches P1sw, N1sw, and M1sw. The second gate drive circuit 45 includes resistors RG2P, RG2N, and RG2M, and switches P2sw, N2sw, and M2sw.

[0061] The first dead time detection circuit 30 turns on switch M1sw only during the detected dead times DT and DT2. As a result, the first gate drive circuit 35 applies a first intermediate voltage VM1, which has a voltage value of approximately zero, to the gate of the upper arm Q1.

[0062] The second dead time detection circuit 40 turns on switch M2sw only during the detected dead times DT and DT2. As a result, the second gate drive circuit 45 applies a second intermediate voltage VM2, which has a voltage value of approximately zero, to the gate of the lower arm Q2.

[0063] If the dead time is known, the drive unit 20 may estimate the dead times DT and DT2 using a one-shot circuit or the like.

[0064] Figure 6 is a timing chart showing the operation of the drive unit having the configuration of Figure 5. Switch P1sw, which outputs the first positive power supply voltage V1P, turns on or off according to the command signal Q1sig input from the control unit 10. Switch M1sw, which outputs the first intermediate voltage VM1, operates during the dead time. Switch M1sw turns on or off according to the exclusive OR of the inverted signals Q1sig and Q2sig. Switch N1sw, which outputs the first negative power supply voltage V1N, turns on or off according to the command signal Q2sig input from the control unit 10. By operating in this manner, the first intermediate voltage VM1 can be supplied to the gate of the upper arm Q1 during the dead time. Similarly to Figure 6, the lower arm Q2 can be supplied to the gate of the lower arm Q2 during the dead time by operating in the same manner.

[0065] Figure 7 shows a second configuration example of a drive device included in a power converter according to one embodiment. The drive device 20 shown in Figure 7 differs from the drive device 20 shown in Figure 5 in its gate drive circuit. In Figure 7, the first drive circuit 21 has a first gate drive circuit 36 ​​that drives the upper arm Q1 using the dead time detected by the first dead time detection circuit 30. The second drive circuit 22 has a second gate drive circuit 46 that drives the lower arm Q2 using the dead time detected by the second dead time detection circuit 40.

[0066] The first gate drive circuit 36 ​​includes resistors RG1P, RG1N, RG1Ma, and RG1Mb, and switches P1sw, N1sw, M1sw, and M11sw. The second gate drive circuit 46 includes resistors RG2P, RG2N, RG2Ma, and RG2Mb, and switches P2sw, N2sw, M2sw, and M22sw.

[0067] The first dead time detection circuit 30 turns on switches M1sw and M11sw only during the detected dead times DT and DT2. As a result, the first gate drive circuit 36 ​​applies a first intermediate voltage VM1 to the gate of the upper arm Q1, which is the voltage value obtained by dividing the sum of the absolute values ​​of the first positive power supply voltage and the first negative power supply voltage by resistors RG1Ma and RG1Mb.

[0068] The second dead time detection circuit 40 turns on switches M2sw and M22sw only during the detected dead times DT and DT2. As a result, the second gate drive circuit 46 applies a second intermediate voltage VM2 to the gate of the lower arm Q2, which is the voltage value obtained by dividing the sum of the absolute values ​​of the first positive power supply voltage and the first negative power supply voltage by resistors RG2Ma and RG2Mb.

[0069] According to the configuration shown in Figure 7, the first gate drive circuit 36 ​​can apply a first intermediate voltage VM1 with a voltage value of not only zero, but also a first intermediate voltage VM1 with a positive or negative voltage value to the upper arm Q1 during the dead time. Similarly, the second gate drive circuit 46 can apply a second intermediate voltage VM2 with a voltage value of not only zero, but also a second intermediate voltage VM2 with a positive or negative voltage value to the lower arm Q2 during the dead time.

[0070] For example, the first intermediate voltage VM1 may be a positive voltage higher than zero and lower than the first threshold voltage of the upper arm Q1, and the second intermediate voltage VM2 may be a positive voltage higher than zero and lower than the second threshold voltage of the lower arm Q2. This ensures that the intermediate voltage applied during the dead time is a positive voltage that does not turn on the arms. As a result, the current flowing through the channel increases slightly, the voltage between the drain and source of the arms decreases, losses are reduced, and the progression of degradation is suppressed.

[0071] For example, the first intermediate voltage VM1 may be a negative voltage higher than the first negative power supply voltage V1N and lower than zero, and the second intermediate voltage VM2 may be a negative voltage higher than the second negative power supply voltage V2N and lower than zero. This ensures that the intermediate voltage applied during the dead time is a negative voltage that does not cause the arm to turn on. Therefore, it is possible to suppress the arm from accidentally turning on during the dead time due to noise or other factors.

[0072] Next, we will explain the driving method (second driving method) when the operation is stopped (both command signals Q1sig and Q2sig are off), and an example of the configuration of the drive device that executes the second driving method (third configuration example).

[0073] Figure 8 is a timing chart showing an example of the operating waveform when operation is stopped. Normally, after the dead time DT2, an ON command for the upper arm Q1 is input by the command signal Q1sig (see Figure 4). However, if operation is stopped midway due to the condition for operation stopping being met in the control device 10, the ON command for the upper arm Q1 by the command signal Q1sig is no longer input (see Figure 8). As a result, the gate-source voltage VGS1 of the upper arm Q1 may be held at the first intermediate voltage VM1 (zero in the case of Figure 8), and the gate-source voltage VGS2 of the lower arm Q2 may be held at the second intermediate voltage VM2 (zero in the case of Figure 8). In this case, after time t5, a reverse bias is not applied between the gate and source of the upper arm Q1 and the gate and source of the lower arm Q2, so the upper arm Q1 or lower arm Q2 may malfunction (for example, be turned on) due to noise or other factors. Figure 8 illustrates a scenario where operation is stopped after the start of the second dead time DT2. However, similarly, if operation is stopped after the start of the first dead time DT1, the upper arm Q1 or lower arm Q2 may malfunction (for example, be turned on) due to noise or other factors.

[0074] Figure 9 is a timing chart showing the operation of the second drive method of this disclosure. Figure 9 illustrates a scenario in which the operation is stopped after time t4, when the dead time DT2 begins. In the following explanation of Figure 9, the reference numerals of the power converter 101 shown in Figure 1 will be used for explanation. In addition, in the explanation of the second drive method, the same content as the first drive method will be omitted by referring to the explanation above.

[0075] The first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first intermediate voltage VM1 (zero in this example) to the first negative power supply voltage V1N when off commands for both the upper arm Q1 and the lower arm Q2 are input for a period exceeding the set time of the dead time DT (see time t6). The off command for the upper arm Q1 refers to the off command for the upper arm Q1 given by the command signal Q1sig. The off command for the lower arm Q2 refers to the off command for the lower arm Q2 given by the command signal Q2sig. On the other hand, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second intermediate voltage VM2 (zero in this example) to the second negative power supply voltage V2N when off commands for both the upper arm Q1 and the lower arm Q2 are input for a period exceeding the set time of the dead time DT (see time t6).

[0076] As a result, if an ON command for the upper arm Q1 or lower arm Q2 is not input after the set dead time DT has elapsed, a reverse bias is applied between the gate-source of the upper arm Q1 and the gate-source of the lower arm Q2. This reduces the possibility of the upper arm Q1 or lower arm Q2 malfunctioning (e.g., false ON) due to noise or other factors.

[0077] The dead time DT setting time is a predetermined threshold time used by the drive unit 20 to determine whether the length of the dead time DT, determined by the command signals Q1sig and Q2sig, is acceptable. The dead time DT setting time is a common threshold time for the first dead time DT1 and the second dead time DT2, but the setting time for the first dead time DT1 and the setting time for the second dead time DT2 may be different threshold times.

[0078] Furthermore, if the dead time DT exceeds a predetermined waiting time WT, the first drive circuit 21 may change the gate voltage of Q1 of the upper arm from the first intermediate voltage VM1 (zero in this example) to the first negative power supply voltage V1N (see time t6). On the other hand, if the dead time DT exceeds a predetermined waiting time WT, the second drive circuit 22 may change the gate voltage of Q2 of the lower arm from the second intermediate voltage VM2 (zero in this example) to the second negative power supply voltage V2N (see time t6).

[0079] As a result, for a certain period determined by the waiting time WT, the gate-source voltage VGS1 of the upper arm Q1 is maintained at the first intermediate voltage VM1, and the gate-source voltage VGS2 of the lower arm Q2 is maintained at the second intermediate voltage VM2. When a load 300 with inductance, such as an electric motor, is connected when the system is stopped, a return current flows through the body diodes of the upper arm Q1 or lower arm Q2 for a certain period. In the second driving method, the on-voltage (forward voltage) of the body diode decreases as the gate-source voltage is maintained at the intermediate voltage during the period when current returns through the body diode. As a result, the loss of the body diode is reduced, and the deterioration of the upper arm Q1 or lower arm Q2 can be suppressed.

[0080] For example, in Figure 9, the first drive circuit 21 and the second drive circuit 22 measure the elapsed time since the ON command period for the lower arm Q2 ended at time t4. When the measured elapsed time reaches a predetermined waiting time WT without an ON command being received for the upper arm Q1, the first drive circuit 21 changes the gate voltage of the upper arm Q1 from the first intermediate voltage VM1 to the first negative power supply voltage V1N. When the measured elapsed time reaches a predetermined waiting time WT without an ON command being received for the upper arm Q1, the second drive circuit 22 changes the gate voltage of the lower arm Q2 from the second intermediate voltage VM2 to the second negative power supply voltage V2N. This suppresses the deterioration of the upper arm Q1 or the lower arm Q2.

[0081] Similarly, although not explicitly shown in Figure 9, the first drive circuit 21 and the second drive circuit 22 measure the elapsed time since the ON command period for the upper arm Q1 ended at time t2. When the measured elapsed time of the first drive circuit 21 reaches a predetermined waiting time WT without an ON command being received for the lower arm Q2, the gate voltage of the upper arm Q1 is changed from the first intermediate voltage VM1 to the first negative power supply voltage V1N. When the measured elapsed time of the second drive circuit 22 reaches a predetermined waiting time WT without an ON command being received for the lower arm Q2, the gate voltage of the lower arm Q2 is changed from the second intermediate voltage VM2 to the second negative power supply voltage V2N. This suppresses the degradation of the upper arm Q1 or the lower arm Q2.

[0082] Figure 10 shows a third configuration example of a drive device included in a power converter according to one embodiment. In the description of the third configuration example shown in Figure 10, the same configuration as the first configuration example shown in Figure 5 will be omitted by referring to the above description. The third configuration example shown in Figure 10 shows an example of a circuit configuration of a drive device that performs the second drive method described above. The circuit configuration of a drive device that performs the second drive method is not limited to this configuration.

[0083] The first dead time detection circuit 30 further includes a waiting time circuit 37, an exclusive OR gate 38, and an OR gate 39 compared to the first configuration example.

[0084] The waiting circuit 37 is a delay circuit that delays the output signal of the exclusive OR gate 34, which turns on the switch M1sw for applying the first intermediate voltage VM1, by the waiting time DT. The exclusive OR gate 38 drives the switch M1sw by the exclusive OR of the output signal of the exclusive OR gate 34 and the output signal of the waiting circuit 37. The OR gate 39 drives the switch N1sw for reverse bias output by the OR of the output signal of the signal isolation element 32 and the output signal of the waiting circuit 37. With this configuration, the first drive circuit 21 can turn off switch M1sw and turn on switch N1sw if no ON commands for command signals Q1sig and Q2sig are input between the start of the dead time DT and the end of the waiting time DT. As a result, if the ON command for command signals Q1sig and Q2sig is not input and the waiting time DT has elapsed, the gate-source voltage VGS1 of the upper arm Q1 can be changed from the first intermediate voltage VM1 to the first negative power supply voltage V1N.

[0085] The second dead time detection circuit 40 further includes a waiting time circuit 47, an exclusive OR gate 48, and an OR gate 49 compared to the first configuration example.

[0086] The waiting circuit 47 is a delay circuit that delays the output signal of the exclusive OR gate 44, which turns on the switch M2sw for applying the second intermediate voltage VM2, by the waiting time DT. The exclusive OR gate 48 drives the switch M2sw by the exclusive OR of the output signal of the exclusive OR gate 44 and the output signal of the waiting circuit 47. The OR gate 49 drives the switch N2sw for reverse bias output by the OR of the output signal of the signal isolation element 42 and the output signal of the waiting circuit 47. With this configuration, the second drive circuit 22 can turn off switch M2sw and turn on switch N2sw if no ON commands for command signals Q1sig and Q2sig are input between the start of the dead time DT and the end of the waiting time DT. As a result, if the ON command for command signals Q1sig and Q2sig is not input and the waiting time DT has elapsed, the gate-source voltage VGS2 of the lower arm Q2 can be changed from the second intermediate voltage VM2 to the second negative power supply voltage V2N.

[0087] Although embodiments have been described above, the technology of this disclosure is not limited to the embodiments described above. Various modifications and improvements are possible, such as combinations or substitutions with some or all of the other embodiments.

[0088] Furthermore, the above embodiment described an apparatus in which one phase arm drives an element of a two-level circuit in which an upper arm Q1 and a lower arm Q2 are connected in series. However, the technology of this disclosure may also be applied to a drive apparatus that drives an element of a multilevel circuit with three or more output voltage levels. [Explanation of symbols]

[0089] 10 Control device 20 Drive unit 21 First drive circuit 22 Second drive circuit 30. First Dead Time Detection Circuit 31,32 Signal isolation element 33 Inverting Circuit 34. Exclusive OR Gate 35,36 First gate drive circuit 40. Second Dead Time Detection Circuit 41,42 Signal isolation elements 43 Inverting Circuit 44 Exclusive OR Gate 45,46 Second gate drive circuit 101 Power converter 300 load 400 DC power supply

Claims

1. A drive device that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between for turning them off, A first drive circuit sets the gate voltage of the first SiC-MOSFET to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time, The system includes a second drive circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, When the dead time is the first dead time immediately following the ON command period of the first SiC-MOSFET and immediately following the ON command period of the second SiC-MOSFET, The first drive circuit changes the gate voltage of the first SiC-MOSFET from the first positive power supply voltage to the first intermediate voltage when the first dead time begins, and changes it from the first intermediate voltage to the first negative power supply voltage when the first dead time ends. The second drive circuit is a drive device that changes the gate voltage of the second SiC-MOSFET from the second negative power supply voltage to the second intermediate voltage when the first dead time begins, and changes it from the second intermediate voltage to the second positive power supply voltage when the first dead time ends.

2. When the dead time is the second dead time immediately following the ON command period of the second SiC-MOSFET and immediately following the ON command period of the first SiC-MOSFET, The first drive circuit changes the gate voltage of the first SiC-MOSFET from the first negative power supply voltage to the first intermediate voltage when the second dead time begins, and sets it from the first intermediate voltage to the first positive power supply voltage when the second dead time ends. The drive device according to claim 1, wherein the second drive circuit changes the gate voltage of the second SiC-MOSFET from the second positive power supply voltage to the second intermediate voltage when the second dead time begins, and changes it from the second intermediate voltage to the second negative power supply voltage when the second dead time ends.

3. The drive device according to claim 1 or 2, wherein one or both of the first intermediate voltage and the second intermediate voltage are zero.

4. The first intermediate voltage is a positive voltage that is higher than zero and lower than the first threshold voltage. The drive device according to claim 1 or 2, wherein the second intermediate voltage is a positive voltage that is higher than zero and lower than the second threshold voltage.

5. A drive device that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between for turning them off, A first drive circuit sets the gate voltage of the first SiC-MOSFET to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time, The system includes a second drive circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, The first intermediate voltage is a negative voltage that is higher than the first negative power supply voltage and lower than zero. A drive device in which the second intermediate voltage is a negative voltage that is higher than the second negative power supply voltage and lower than zero.

6. A drive device that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between for turning them off, A first drive circuit sets the gate voltage of the first SiC-MOSFET to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time, The system includes a second drive circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, If an off command is input to both the first SiC-MOSFET and the second SiC-MOSFET for a period exceeding the set time of the dead time, the first drive circuit changes the gate voltage of the first SiC-MOSFET from the first intermediate voltage to the first negative power supply voltage. The second drive circuit is a drive device that, when an off command is input to both the first SiC-MOSFET and the second SiC-MOSFET for a period exceeding the set time of the dead time, changes the gate voltage of the second SiC-MOSFET from the second intermediate voltage to the second negative power supply voltage.

7. A drive device that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between for turning them off, A first drive circuit sets the gate voltage of the first SiC-MOSFET to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time, The system includes a second drive circuit that sets the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, If the dead time exceeds a predetermined waiting time, the first drive circuit changes the gate voltage of the first SiC-MOSFET from the first intermediate voltage to the first negative power supply voltage. The second drive circuit is a drive device that, when the dead time exceeds a predetermined waiting time, changes the gate voltage of the second SiC-MOSFET from the second intermediate voltage to the second negative power supply voltage.

8. The drive device according to claim 7, wherein the waiting time includes a period during which current flows back through the body diode of the first SiC-MOSFET or the second SiC-MOSFET.

9. A driving method that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between during which the first SiC-MOSFET and the second SiC-MOSFET are turned off, The gate voltage of the first SiC-MOSFET is set to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time. A driving method comprising setting the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, When the dead time is the first dead time immediately following the ON command period of the first SiC-MOSFET and immediately following the ON command period of the second SiC-MOSFET, The gate voltage of the first SiC-MOSFET is changed from the first positive power supply voltage to the first intermediate voltage when the first dead time begins, and when the first dead time ends, it is changed from the first intermediate voltage to the first negative power supply voltage. A driving method comprising changing the gate voltage of the second SiC-MOSFET from the second negative power supply voltage to the second intermediate voltage when the first dead time begins, and changing it from the second intermediate voltage to the second positive power supply voltage when the first dead time ends.

10. A driving method that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between during which the first SiC-MOSFET and the second SiC-MOSFET are turned off, The gate voltage of the first SiC-MOSFET is set to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time. A driving method comprising setting the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, The first intermediate voltage is a negative voltage that is higher than the first negative power supply voltage and lower than zero. A driving method wherein the second intermediate voltage is a negative voltage that is higher than the second negative power supply voltage and lower than zero.

11. A driving method that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between during which the first SiC-MOSFET and the second SiC-MOSFET are turned off, The gate voltage of the first SiC-MOSFET is set to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time. A driving method comprising setting the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, If an off command is input to both the first SiC-MOSFET and the second SiC-MOSFET for a period exceeding the set dead time, the gate voltage of the first SiC-MOSFET is changed from the first intermediate voltage to the first negative power supply voltage. A driving method comprising changing the gate voltage of the second SiC-MOSFET from the second intermediate voltage to the second negative power supply voltage when an off command is input to both the first SiC-MOSFET and the second SiC-MOSFET for a period exceeding the set dead time.

12. A driving method that alternately switches the first SiC-MOSFET and the second SiC-MOSFET, which are connected in series, with a dead time in between during which the first SiC-MOSFET and the second SiC-MOSFET are turned off, The gate voltage of the first SiC-MOSFET is set to a first intermediate voltage that is higher than the first negative power supply voltage and lower than the first threshold voltage of the first SiC-MOSFET during the dead time. A driving method comprising setting the gate voltage of the second SiC-MOSFET to a second intermediate voltage that is higher than the second negative power supply voltage and lower than the second threshold voltage of the second SiC-MOSFET during the dead time, If the dead time exceeds a predetermined waiting time, the gate voltage of the first SiC-MOSFET is changed from the first intermediate voltage to the first negative power supply voltage. A driving method comprising changing the gate voltage of the second SiC-MOSFET from the second intermediate voltage to the second negative power supply voltage when the dead time exceeds a predetermined waiting time.

13. A power conversion device comprising a drive device according to any one of claims 1, 2, 5 to 8.

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