Deposition of low-stress boron-containing layers

Abstract

Examples of the technology herein include semiconductor processing methods for forming a boron-containing material on a substrate. An exemplary processing method may include supplying a deposition precursor including a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The method may further include depositing the boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, wherein the substrate is characterized by a temperature of about 50° C. or less. The deposited boron-containing material may be characterized by a surface roughness of about 2 nm or less and a stress level of about −500 MPa or less. In some embodiments, the layer of boron-containing material may function as a hard mask.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Patent Application No. 16 / 987,704, filed 7 August 2020, entitled "DEPOSITION OF LOW-STRESS BORON-CONTAINING LAYERS," which is incorporated herein by reference in its entirety.

[0002]

[0002] The technology described herein relates to methods and systems for semiconductor processing. More specifically, the technology described herein relates to systems and methods for manufacturing low-stress boron-containing layers or semiconductor substrates. [Background technology]

[0003]

[0003] Integrated circuits are made possible by the process of fabricating intricately patterned material layers on a substrate surface. Fabricating patterned material on a substrate requires controlled methods for forming and removing the material. As the size of the device continues to shrink, the impact of the film properties on device performance can become greater. The material used to form the material layers can affect the operating characteristics of the fabricated device. As the thickness of the material continues to decrease, the impact of the deposited film properties on device performance can become greater.

[0004]

[0004] Therefore, improved systems and methods are needed that can be used to manufacture high-quality devices and structures. The technology described in this document addresses this need and other needs. [Overview of the project]

[0005]

[0005] Embodiments of the technology described herein include a semiconductor processing method for forming a boron-containing material on a substrate. An exemplary processing method may include supplying a deposition precursor containing a boron-containing precursor to a processing area of ​​a semiconductor processing chamber. Plasma may be formed from the deposition precursor within the processing area of ​​the semiconductor processing chamber. The method may further include depositing a boron-containing material on a substrate placed within the processing area of ​​the semiconductor processing chamber, wherein the substrate is characterized by a temperature of about 50°C or less in this processing area.

[0006]

[0006] In exemplary embodiments, the boron-containing precursor may include one or more compounds selected from boron carbide, boron nitride, boron carbonitride, boron-containing silicon, boron-containing silicon oxide, boron-and-boron-containing silicon oxide, and boron-containing silicon nitride. The deposition precursor may include, in addition to the boron-containing precursor, one or more of the boron-containing precursor, silicon-containing precursor, and nitrogen-containing precursor. In additional embodiments, in addition to the deposition precursor, an inert precursor may be supplied to the processing area, and the flow rate ratio of the inert precursor to the deposition precursor may be about 10:1 or more. Exemplary inert precursors may include helium or argon. In further embodiments, the semiconductor processing chamber may be characterized by a pressure in the substrate processing area of ​​about 100 mTor or less, and the plasma formed may be a biased plasma formed with a bias power of more than 2000 watts.

[0007]

[0007] An additional embodiment of the semiconductor processing method may include supplying a deposition precursor containing a boron-containing precursor to a processing area of ​​a semiconductor processing chamber. A bias power may be applied to a substrate placed in the processing area of ​​the semiconductor processing chamber, and in this processing area, the bias power is approximately 3000 watts or more. A plasma may be formed in the deposition precursor in the processing area of ​​the semiconductor processing chamber, and the boron-containing material may be deposited on the substrate.

[0008]

[0008] In exemplary embodiments, the bias power may be about 4000 watts or more. In additional exemplary embodiments, in addition to the deposition precursor, an inert precursor may be supplied to the processing area, and the flow rate ratio of the inert precursor to the deposition precursor may be about 10:1 or more. The substrate may be characterized by having a temperature of about 50°C or less in at least part of the deposition of the boron-containing material.

[0009]

[0009] Further additional embodiments of the semiconductor processing method may include supplying a boron-containing precursor to a processing area of ​​a semiconductor processing chamber. An exemplary method may further include forming a plasma of the boron-containing precursor within the processing area of ​​the semiconductor processing chamber and depositing a boron-containing material on a substrate placed within the processing area. This boron-containing material may be characterized by a post-deposition surface roughness of about 2 nm or less.

[0010]

[0010] In exemplary embodiments, the deposited boron-containing material may be characterized by a stress level of about -500 MPa or less. The deposited boron-containing material may also contain carbon, in which case about 60% or more of the carbon atoms are sp 3 It has hybrid bonds. In additional and exemplary embodiments, the boron-containing material may contain about 25 mol% or less of hydrogen. Exemplary boron-containing materials may include one or more compounds selected from boron carbide, boron nitride, boron carbonitride, boron-containing silicon, boron-containing silicon oxide, boron-boron-containing silicon oxide, and boron-containing silicon nitride. In further exemplary embodiments, in addition to the boron-containing precursor, an inert precursor may be supplied to the substrate processing area, and the flow rate ratio of the inert precursor to the boron-containing precursor may be about 10:1 or more. A bias power may be applied to the substrate during the deposition of the boron-containing material, in which case the bias power is about 3000 watts or more. The substrate may be characterized by having a temperature of about 50°C or less during the deposition of the boron-containing material.

[0011]

[0011] Such technologies can offer numerous advantages over conventional systems and techniques. For example, embodiments of the technology described herein produce a deposited boron-containing layer with low surface roughness, making it suitable as a hard mask. In addition, the deposited boron-containing layer has low stress, thereby preventing significant bending or distortion of adjacent substrate features. The above embodiments and other embodiments, along with many of their advantages and features, will be described in more detail below in conjunction with the accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be better understood by referring to the following sections of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] A top view of an exemplary processing system, based on some of the embodiments of the technology described in this book, is shown. [Figure 2A] A schematic cross-sectional view of an exemplary semiconductor processing chamber, based on some of the technical embodiments described in this book, is shown. [Figure 2B] A schematic cross-sectional view of an additional and exemplary semiconductor processing chamber, based on some of the technical embodiments described in this book, is shown. [Figure 3] A schematic cross-sectional view of an exemplary substrate support and electrostatic chuck, based on some embodiments of the technology described in this book, is shown. [Figure 4] This document illustrates a process in a semiconductor processing method, based on some of the embodiments of the technology described in this book. [Modes for carrying out the invention]

[0014]

[0018] Some diagrams are included as schematic representations. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic representations, they are presented to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0015]

[0019] In the accompanying drawings, similar components and / or features may have the same reference numerals. Further, various components of the same type may be distinguished by letters following the reference numeral that distinguish between similar components. If only the first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the subsequent letters.

[0016]

[0020] The technology of this document includes systems and process methods for depositing a boron-containing layer characterized by low roughness and low stress on a semiconductor substrate. Embodiments of these systems and methods address the problem of forming a deposited boron-containing layer characterized by low roughness and low stress that reduces post-deposition processing steps for smoothing the surface roughness and neutralizing the stress. For example, there is increasing interest in a boron-containing layer characterized by low roughness and low stress as a hard mask for patterning the etching of high aspect ratio (HAR) features in the underlying material of the substrate.

[0017]

[0021] Examples of these HAR features include channels and contacts within 3D NAND memory cells that extend through hundreds of silicon-containing layers and can be characterized by an aspect ratio (i.e., the ratio of height to width) of about 70:1 or greater. Conventionally formed boron-containing hard masks are characterized by high selectivity for etching silicon-containing layers on the hard mask, but are also characterized by the height of the surface roughness (e.g., an average surface roughness of about 10 nm or greater) and the height of the stress (e.g., a stress level of about -1000 MPa or less, where in this case, the more negative the stress value, the greater the compressive force generated by the material), and thus problems occur during etching. Such problems include patterning distortion and reduced uniformity of critical dimensions caused by high surface roughness. The problems further include warping and bowing of the underlying substrate stack and mask breakage, all of which are caused by the high stress in the hard mask layer.

[0018]

[0022] Conventional systems and methods address the above problems by performing post-deposition hard mask processing steps (e.g., a chemical mechanical polishing (CMP) step to smooth the rough surface and a thermal or plasma annealing step to neutralize high stress). Additional conventional systems and methods include depositing multiple hard mask layers such that the tensile stress and compressive stress cancel each other out, and the combined stress forms a hard mask stack with neutralized stress. The conventional formation of boron-containing hard masks increases complexity, time, and cost due to these processes.

[0019]

[0023] There are problems with eliminating surface roughness and relieving stress by replacing or removing a boron-containing layer that acts as a hard mask while patterning and etching device features inside and on the surface of a substrate. A boron-containing hard mask is typically deposited between the underlying substrate material and the above-ground energy-sensitive resist layer (e.g., a photoresist layer). The hard mask provides selective resistance to the etchant used to form features in the underlying substrate material according to the pattern fabricated in the energy-sensitive resist layer. The boron in the hard mask further enhances etching selectivity, keeping the underlying substrate features intact during the etching process. If the hard mask layer is removed, or if boron is removed from the hard mask, the etchant is more likely to corrode the parts of the underlying substrate features that should be kept intact, which can lead to erosion (and potentially destruction) of the features.

[0020]

[0024] The techniques described in this book address the above-mentioned problems (including others) by providing systems and process methods for depositing boron-containing materials characterized by at least one of low roughness and low stress. In some embodiments, the deposited boron-containing material may act as a boron-containing hard mask, but may also function as something else. Embodiments of systems and methods deposit boron-containing materials by maintaining one or more process parameters that operate in relation to reducing the growth rate of boron-containing crystals in the deposited material, reducing hydrogen incorporation in the deposited material, improving carbon bonding in the deposited material, and reducing the amount of stress in the deposited material. Some of these parameters, described later, include the substrate temperature, the flow rate ratio of the inert precursor to the hydrocarbon-containing precursor that assists in the formation of the deposition plasma, and the bias power used to generate the deposition plasma (including other process parameters).

[0021]

[0025] Embodiments of the techniques described in this book include systems and methods for inhibiting the crystal growth of boron-containing compounds in deposited boron-containing materials. A reduction in the average crystal size in the deposited material can result in a reduction in surface roughness. In some embodiments, the systems and methods also include depositing a boron-containing material characterized by a low hydrogen content. The reduction in hydrogen content contributes to a reduction in the average size of the boron-containing crystals, which can form a deposited boron-containing film characterized by reduced surface roughness. In additional embodiments, the systems and methods include depositing a boron-carbon-containing film, in which case the increase in the number of carbon atoms is sp 3 Characterized by hybridization. 3 The increase in the number of carbon atoms characterized by hybridization can reduce the average size of boron-containing crystals and form deposited boron-carbon-containing films characterized by reduced surface roughness. Therefore, the techniques described herein include embodiments for forming deposited boron-containing layers characterized by at least one of low surface roughness and low stress. In some embodiments, these systems and methods form low-roughness, low-stress boron-containing layers (e.g., hard mask layers) without using complex, time-consuming, and costly post-deposition processes to reduce surface roughness and neutralize stress within the layer.

[0022]

[0026] The following disclosure specifies, in accordance with the provisions, a particular deposition process utilizing the disclosed technology, but it will be readily apparent that the above system and method are equally applicable to other deposition and processing processes that may be carried out in the described chamber or any other chamber. Therefore, the technology described herein may be implemented in a wide variety of chemical vapor deposition chambers and should not be construed as being limited to use in the specific deposition processes or chambers described above. This disclosure describes one feasible system and chamber that may be used to implement a process method according to some embodiments of the technology described herein, followed by a description of additional modifications and adjustments of this system according to embodiments of the technology described herein.

[0023]

[0027] Figure 1 shows a top view of one embodiment of a semiconductor processing system 100 comprising a deposition chamber, an etching chamber, a baking chamber, and a curing chamber. In this figure, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and vice versa. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including the formation of laminates of semiconductor materials as described herein, in addition to other substrate processes such as plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing and ashing.

[0024]

[0028] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films or other films on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit dielectric material on the substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit an alternating laminate of dielectric films on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in various embodiments. It should be noted that System 100 also envisions additional configurations of chambers for depositing, etching, annealing, and curing dielectric films.

[0025]

[0029] Figures 2A and 2B show schematic cross-sectional views of exemplary semiconductor processing systems 232 and 280, which are part of embodiments of the technology described herein. These figures may illustrate an overview of a system that includes one or more aspects of the technology described herein and / or may be specifically configured to perform one or more steps according to embodiments of the technology described herein. Further details of systems 232 and 280 and the methods performed may be described in the following. While systems 232 and 280 may be used to form a boron-containing layer (e.g., a boron-containing hard mask) according to embodiments of the technology described herein, it should be understood that the method may be similarly performed in any system in which layer formation can be performed.

[0026]

[0030] Referring here to Figure 2A, the semiconductor processing system 232 includes a semiconductor processing chamber 200, which may include an upper wall 224, side walls 201, and a bottom wall 222 defining a substrate processing area 226. A gas panel 230 and a controller 210 may be connected to the processing chamber 200. A substrate support assembly 246 may also be provided within the substrate processing area 226 of the process chamber 200.

[0027]

[0031] The substrate support assembly 246 may include an electrostatic chuck 250 supported by a stem 260. The electrostatic chuck 250 may be manufactured from aluminum, ceramic, and other suitable materials (such as stainless steel). The electrostatic chuck 250 may be moved vertically within the processing chamber 200 using a displacement mechanism (not shown). A temperature sensor 272 (such as a thermocouple) may be embedded in the electrostatic chuck 250 to monitor its temperature. The measured temperature may be used by a controller 210 to control the power supplied to the heating element 270 to maintain the substrate at a desired temperature.

[0028]

[0032] The vacuum pump 202 may be connected to a port formed at the bottom of the process chamber 200. The vacuum pump 202 may be used to maintain a desired gas pressure within the process chamber 200. The vacuum pump 202 may also be used to discharge post-treatment gases and process by-products from the processing chamber 200.

[0029]

[0033] A gas distribution assembly 220 having multiple openings 228 may be positioned above the process chamber 200 above the electrostatic chuck 250. The openings 228 of the gas distribution assembly 220 are used to introduce process gases into the process chamber 200. The openings 228 may have various sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for various process requirements. The gas distribution assembly 220 is connected to a gas panel 230, which allows various gases to flow into the processing space 226 during processing. A plasma is formed from the process gas mixture exiting the gas distribution assembly 220 to deposit material on the upper surface 291 of a substrate 290 placed on the electrostatic chuck 250 by promoting the thermal decomposition of the process gases.

[0030]

[0034] The gas distribution assembly 220 and the electrostatic chuck 250 may form a pair of spaced electrodes within the processing space 226. To facilitate plasma generation between the gas distribution assembly 220 and the electrostatic chuck 250, one or more RF power supplies 240 provide a bias potential to the gas distribution assembly 220 through an (optional) matching network 238. Alternatively, the RF power supplies 240 and the matching network 238 may be connected to the gas distribution assembly 220, to the electrostatic chuck 250, or to both the gas distribution assembly 220 and the electrostatic chuck 250, or to an antenna (not shown) located outside the process chamber 200. In some embodiments, the RF power supplies 240 may generate power at frequencies of approximately 100 kHz or higher, approximately 500 kHz or higher, approximately 1 MHz or higher, approximately 10 MHz or higher, approximately 20 MHz or higher, approximately 50 MHz or higher, or approximately 100 MHz or higher (other frequency ranges may also apply). Specific examples of the frequencies of the power generated by the RF power supply 240 include, among other frequencies, 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, and 162 MHz, but other frequencies may also be used.

[0031]

[0035] The controller 210 includes a central processing unit (CPU) 212, memory 216, and support circuits 214, which are used to control the process sequence and regulate the gas flow from the gas panel 230. The CPU 212 can be any form of general-purpose computer processor that may be used in an industrial setting. Software routines may be stored in memory 216 (such as random access memory, read-only memory, floppy disks, or hard disk drives, or other forms of digital storage). The support circuits 214 are connected to the CPU 212 and may include a cache, clock circuits, input / output systems, power supplies, etc. Bidirectional communication between the controller 210 and various components of the board processing system 232 is handled through a number of signal cables (collectively referred to as the signal bus 218, some of which are shown in Figure 2A).

[0032]

[0036] Figure 2B shows a schematic cross-sectional view of another substrate processing system 280 that may be used to implement the embodiments described herein. The substrate processing system 280 is similar to the substrate processing system 232 in Figure 2A, except that it is configured to flow a processing gas radially from the gas panel 230 through the side wall 201 across the entire top surface 291 of the substrate 290. In addition, the gas distribution assembly 220 shown in Figure 2A is replaced by an electrode 282. The electrode 282 may be configured to generate secondary electrons. In one embodiment, the electrode 282 is a silicon-containing electrode.

[0033]

[0037] Figure 3 shows a schematic cross-sectional view of a substrate support assembly 346 that may be used in an embodiment of the system. The substrate support assembly 346 may include an electrostatic chuck 350, which may include a heating element 370 suitable for controlling the temperature of a substrate 390 supported on its upper surface 392. The heating element 370 may be embedded in the electrostatic chuck 350. The electrostatic chuck 350 may be resistively heated by applying current to the heating element 370 from a heater power supply 306. The heater power supply 306 may be connected via an RF filter 316 to protect the heater power supply 306 from RF energy. The current supplied from the heater power supply 306 is regulated by a controller 310 to control the heat generated by the heating element 370, thereby maintaining the substrate 390 and the electrostatic chuck 350 at a substantially constant temperature during film deposition. The supplied current can be adjusted to selectively control the temperature of the electrostatic chuck 350 between approximately 20°C and approximately 350°C during the deposition of the carbon-containing film on the substrate. A cooling unit (not shown) may also be thermally coupled to the substrate support assembly 346 to selectively control the temperature of the substrate 390 between approximately -50°C and approximately 20°C.

[0034]

[0038] In some embodiments, the electrostatic chuck 350 includes a chuck electrode 410, which may be a mesh of conductive material. The chuck electrode 410 may also be embedded in the electrostatic chuck 350. The chuck electrode 410 is connected to a chuck power supply 412, which, when energized, electrostatically clamps the substrate 390 to the upper surface 392 of the electrostatic chuck 350.

[0035]

[0039] The chuck electrode 310 may be configured as a unipolar or bipolar electrode, or may have another suitable configuration. The chuck electrode 410 may be connected to a chuck power supply 412 via an RF filter 414, which provides direct current (DC) power to electrostatically fix the substrate 390 to the upper surface 392 of the electrostatic chuck 350. The RF filter 414 prevents the RF power used to form plasma in the process chamber from damaging electrical equipment. The electrostatic chuck 350 is made of ceramic material ( It can be manufactured from AlN or Al2O3, etc.

[0036]

[0040] A power supply system 420 is connected to a substrate support assembly 346. The power supply system 420 may include a heater power supply 306, a chuck power supply 412, a first radio frequency (RF) power supply 430, and a second RF power supply 440. In addition, embodiments of the power supply system 420 may also include a controller 310, and a sensor device 450 that communicates with both the controller 310 and the first RF power supply 430 and the second RF power supply 440. The controller 310 may also be used to control plasma from a processing gas by applying RF power from the first RF power supply 430 and the second RF power supply 440 to deposit a layer of material on the substrate 390.

[0037]

[0041] As described above, the electrostatic chuck 350 includes a chuck electrode 410, which in one embodiment may function as a first RF electrode while also functioning to chuck the substrate 390. The electrostatic chuck 350 may also include a second RF electrode 460 together with the chuck electrode 410, to which RF power may be applied to tune the plasma. A first RF power supply 430 may be connected to the second RF electrode 460, and together with this, a second RF power supply 440 may be connected to the chuck electrode 410. A first matching network and a second matching network are provided for the first RF power supply 430 and the second RF power supply 440, respectively. The second RF electrode 460 may be a solid metal plate of conductive material or a mesh of conductive material.

[0038]

[0042] The first RF power supply 430 and the second RF power supply 440 may generate power at the same or different frequencies. In some embodiments, one or both of the first RF power supply 430 and the second RF power supply 440 may individually generate power at frequencies of approximately 100 kHz or higher, approximately 500 kHz or higher, approximately 1 MHz or higher, approximately 10 MHz or higher, approximately 20 MHz or higher, approximately 50 MHz or higher, and approximately 100 MHz or higher (and other frequency ranges). Specific examples of frequencies for power generated individually by the RF power supplies 430 and 440 include, but may be, 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, and 162 MHz. The RF power from one or both of the first RF power supply 430 and the second RF power supply 440 may be varied to tune the plasma.

[0039]

[0043] Figure 4 shows an exemplary step in processing method 400, which is part of an embodiment of the technology described herein. This method can be carried out in a wide variety of processing chambers, including the processing systems 232 and 280 described above. Method 300 may include one or more steps before the commencement of the method steps described above, such one or more steps including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be carried out before the steps described above. The method may include several optional steps, as shown in the figure, which may or may not be specifically related to the method according to the technology described herein. For example, many of these steps are described to broaden the scope of semiconductor processes but are not important to the technology described herein, or can be carried out by alternative methodologies described further later.

[0040]

[0044] Method 400 may include optional steps for developing a semiconductor structure for a particular manufacturing process. In some embodiments, Method 400 may be performed on a base structure, but in some embodiments, this method may also be performed after the formation or removal of other materials. For example, any number of deposition, masking, or removal steps may be performed to fabricate any transistor, memory, or other structural configuration on the substrate. In some embodiments, one or more structures formed on the substrate may be characterized by a thermal balance of about 500°C or less, about 450°C or less, about 400°C or less, or below. Thus, Method 400 and any subsequent steps may be performed at temperatures below the structural thermal balance. The substrate may be placed on a substrate support that can be positioned within the processing area of ​​a semiconductor processing chamber. Steps for fabricating the underlying structure may be performed in the same chamber (in which embodiments of Method 400 may be performed), and one or more steps may be performed in one or more chambers on a platform similar to the chamber in which the steps of Method 400 may be performed, or on other platforms.

[0041]

[0045] In some embodiments, method 400 may include supplying one or more boron-containing precursors to the substrate processing area of ​​the substrate processing chamber 405. Exemplary boron-containing precursors may include boron-hydrogen-containing compounds (such as borane), such as borane (BH3), diborane (B2H6), or other multicenter-bonded boron-hydrogen-containing compounds. Further exemplary boron-containing precursors include boron-containing hydrocarbons (B x -(C y H z This may include boron-carbon-containing compounds, such as (compounds, etc.), other organoboron compounds, and any other boron-containing materials that can be used to produce boron-containing materials.

[0042]

[0046] One or more boron-containing precursors may be combined with at least one inert precursor. In some embodiments, the inert precursor acts as a carrier gas that is mixed with the boron-containing precursor before being supplied to the substrate processing area, thereby assisting in the transport of the boron-containing precursor to the substrate processing area. In additional embodiments, the inert precursor may be supplied through a separate channel from the boron-containing precursor, and these two precursors may be combined within the substrate processing area of ​​the substrate processing chamber. In yet another embodiment, the inert precursor may be both the carrier gas for the boron-containing precursor and an inert precursor supplied separately to the substrate processing area. Exemplary inert precursors include helium and argon, but other inert precursors may also be used.

[0043]

[0047] It has been found that the relative flow rates of the inert precursor and the boron-containing precursor can affect the properties of the deposited boron-containing material (including surface roughness and stress levels in the material). In some embodiments, the flow rate ratio of the inert precursor to the boron-containing precursor may be about 10:1 or greater, about 20:1 or greater, about 30:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or higher. An exemplary flow rate range for the inert precursor may include about 1000 sccm or greater. Additional and exemplary flow rate ranges for the inert precursor may include about 1500 sccm or greater, about 2000 sccm or greater, about 2500 sccm or greater, about 3000 sccm or greater, about 3500 sccm or greater, about 4000 sccm or greater, about 4500 sccm or greater, and about 5000 sccm or greater, or higher. An exemplary flow rate range for the boron-containing precursor may include about 50 sccm or less. Additional and exemplary flow rate ranges may include, or may be, approximately 100 sccm or less, approximately 75 sccm or less, approximately 40 sccm or less, approximately 30 sccm or less, approximately 20 sccm or less, approximately 10 sccm or less, and approximately 5 sccm or less.

[0044]

[0048] It has been found that by diluting a boron-containing precursor in the excess of an inert precursor within the substrate processing region, a layer of deposited boron-containing material on the substrate is formed, which, when coupled with higher plasma power, exhibits reduced stress levels. For example, providing high plasma power to a highly diluted precursor can lead to an increase in plasma density, which includes an increase in the amount of radical emitters. These radical emitters can easily modify the deposited film without being incorporated into the formed film. By forming a biased plasma (e.g., generating plasma from biased power, as opposed to applying a bias to a capacitively coupled plasma) and utilizing high biased power, ion bombardment during deposition can be increased. In such high-power scenarios, if the formation of plasma by the precursor includes increased dilution by the inert precursor, the increased bombardment during formation can lead to effects such as improved deposited film structure due to a decrease in the growth rate of boron-containing crystals and increased hydrogen removal.

[0045]

[0049] In some embodiments, an additional precursor may be supplied to the substrate processing region, along with the boron-containing precursor and the inert precursor. Such additional precursors may include one or more hydrocarbon-containing precursors. In these embodiments, the boron-containing material deposited on the substrate may be characterized as a boron-carbon-containing material. Exemplary hydrocarbon-containing precursors may include acetylene (C2H2). Additional and exemplary hydrocarbon-containing precursors may include hydrocarbon compounds having the general formula C x H y where x has a range between 1 and 20 and y has a range between 1 and 20. Suitable hydrocarbon compounds may include, for example, C3H6, CH4, C4H8, 1,3-dimethyladamantane, bicyclo[2.2.1]hepta-2,5-diene (2,5-norbornadiene), adamantane (C 10 H 16 ), norbornene (C7H 10 ), but other hydrocarbon compounds may also be used. In some embodiments, the ratio of carbon to hydrogen may be maintained at about 4:1 or less, about 3:1 or less, about 2:1 or less, about 1:1 or less, or below these ratios, which may further facilitate the limitation of hydrogen incorporation during film formation. Exemplary flow rate ranges for the hydrocarbon-containing precursor may include about 50 sccm or less. Additional and exemplary flow rate ranges may include about 100 sccm or less, about 75 sccm or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, about 5 sccm or less, or may be below these.

[0046]

[0050] In further embodiments, additional precursors may include nitrogen-containing precursors. In these embodiments, the boron-containing material deposited on the substrate may be characterized as a boron-nitrogen-containing material (e.g., boron nitride). If a carbon-containing precursor is also present, the boron-containing material deposited on the substrate may be characterized as a boron-carbon-nitrogen-containing material. Exemplary nitrogen-containing precursors may include ammonia (NH3), molecular nitrogen (N2), and nitrous oxide (N2O), but other nitrogen-containing precursors may also be present. Exemplary flow rate ranges for nitrogen-containing precursors may include about 20 sccm or less. Additional and exemplary flow rate ranges may include or be less than about 100 sccm or less, about 75 sccm or less, about 50 sccm or less, about 40 sccm or less, about 30 sccm or less, about 10 sccm or less, and about 5 sccm or less.

[0047]

[0051] In some embodiments, a hydrogen-containing precursor or plasma may also be introduced into the substrate processing area. An exemplary hydrogen-containing precursor, such as hydrogen gas (H2), may form hydrogen radicals. These hydrogen radicals may be supplied to the substrate and react with other plasma emitters and / or deposited materials. In some embodiments where hydrocarbon-containing precursors are also present, the hydrogen radicals may form sp 2 It reacts with hybridized carbon atoms, and these are sp 3 It can be converted to hybrid carbon. In some embodiments, hydrogen radicals may be generated in a remote plasma system (RPS) located outside the processing chamber and supplied to the substrate processing area.

[0048]

[0052] In embodiments of the technology described in this book, a precursor is supplied to a substrate processing chamber. This substrate processing chamber has a substrate within its substrate processing area. In some embodiments, the substrate may be placed on a substrate support assembly within the substrate processing area and may be maintained at a temperature of about 50°C or less. In some embodiments, the substrate temperature may be reduced and maintained to about 20°C by a heater element in the substrate support assembly within the substrate processing chamber. In further embodiments, the substrate temperature may be maintained at about 20°C or less by a cooling unit supplying a cooling fluid to the substrate support assembly. Additional substrate temperature ranges include or are below about 40°C or less, about 30°C or less, about 20°C or less, about 10°C or less, about 0°C or less, about -10°C or less, about -20°C or less, and about -30°C or less.

[0049]

[0053] Maintaining the substrate temperature below approximately 50°C during the deposition of boron-containing materials, when combined with at least one of dilution of the boron-containing precursor and the use of high plasma power to generate the boron-containing deposition plasma, is known to form a low-roughness, low-stress layer. As mentioned above, providing high plasma power to a highly diluted precursor can lead to an increase in plasma density, which includes an increase in the amount of radical emitters. These radical emitters can easily modify the deposited film without being incorporated into the formed film. The modified film structure can be characterized by miniaturization of the boron-containing crystals, which reduces surface roughness, and a decrease in hydrogen content, which reduces film stress. Forming the film at a substrate temperature below approximately 50°C makes it possible to reduce the growth rate of the boron-containing crystals and the regrowth rate of boron-containing crystals that have been damaged or prevented from growing excessively by increasing the bombardment of the inert precursor. In addition, film formation at such low substrate temperatures may contribute to the formation of materials with low hydrogen content, which complements the deposition conditions resulting from increased bombardment of inert precursors.

[0050]

[0054] An exemplary substrate provided within the substrate processing area is crystalline silicon (e.g., Si <100> or Si <111> The substrate may include a base substrate, which may include, but may also include, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrates and patterned or unpatterned substrate silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, and sapphire, but may also include other substrate materials. An exemplary substrate may further include one or more layers of material formed on the base substrate. These one or more layers may include layers of conductive material (e.g., metal-containing layers), layers of semiconductor material (e.g., amorphous silicon layers), and layers of insulating material (e.g., silicon nitride or silicon oxide). In some embodiments, the substrate may include a base substrate and multiple layers of material (e.g., about 48 or more, about 65 or more, about 96 or more, about 128 or more, about 256 or more) that constitute a film stack for applications such as 3D NAND structures. The substrate may further include substrate features (such as gaps, vias, trenches, and steps, but other types of features). Substrate features may be formed directly on the base substrate. Alternatively or additionally, substrate features may be formed on layers of insulating, conductive, and / or semiconductor material deposited on the base substrate, forming part of the substrate. Exemplary substrates may take various shapes, such as circular, rectangular, or square, and may have dimensions of, for example, 200 mm, 300 mm, or 450 mm in diameter, side, or diagonal.

[0051]

[0055] In some embodiments, the precursor supplied to the substrate processing region can generate and maintain a processing pressure of about 100 mTor or less within the substrate processing chamber. Additional and exemplary processing pressure ranges include, but may be, pressure ranges of about 1 Tor or less, about 500 mTor or less, about 50 mTor or less, about 10 mTor or less, about 5 mTor or less, about 1 mTor or less, about 0.1 mTor or less, or lower. In some embodiments, reducing the processing pressure can increase ion bombardment by increasing the mean free path between atoms. This can increase the distance traveled between collisions, which can increase energy and bombardment at the film surface. This can further facilitate the reduction of hydrogen and the formation of improved carbon bonds within the formed film, which can reduce stress in the fabricated film.

[0052]

[0056] Embodiments of Method 400 further include supplying plasma power to a substrate processing area 412. In some embodiments, the plasma power may be supplied as bias power generated by an RF power supply that is electrically in contact with an electrostatic chuck that is electrically in contact with the substrate. As previously stated, in some embodiments of the techniques of this document, bias plasma may be generated at higher plasma power to improve the film properties of the deposited material. For example, in some embodiments, bias plasma may be generated at a supplied power of about 2000 W or more, about 2500 W or more, about 3000 W or more, about 3500 W or more, about 4000 W or more, about 4500 W or more, or above. The increase in plasma power (which may be carried out in conjunction with an increase in the supply of inert precursor) may generate from the inert precursor an amount of bombard that can modify the deposited material to improve carbon bonding and reduce hydrogen uptake. RF power supplies can generate power at frequencies ranging from approximately 350 kHz to approximately 162 MHz (e.g., 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, or 162 MHz).

[0053]

[0057] Referring to Figure 3 above, in some embodiments, RF bias power may be supplied to the precursor in the substrate processing area by an electrostatic chuck 350. The electrostatic chuck 350 is supplied with RF power from a second RF power supply 440. In additional embodiments, RF bias power may be supplied entirely or partially by the second RF electrode 460, which electronically communicates with the first RF power supply 430 that supplies a bias voltage to the second RF electrode 460. The first RF power supply 430 may generate power at frequencies from about 350 kHz to about 100 MHz (e.g., 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz).

[0054]

[0058] In some embodiments, step 412 may further include applying a second RF bias power to an electrostatic chuck to adjust film stress, thereby individually controlling the ion density and ion energy. The second RF bias power may be about 10 watts or more and may have a frequency of about 350 kHz or more. Referring to Figure 3, in some embodiments, the second RF bias power is supplied to the substrate 391 via the chuck electrode 410. The chuck electrode 410 may electronically communicate with a second RF power supply 440 that supplies a bias voltage to the chuck electrode 410. The second RF bias power may be supplied with a power of about 10 watts or more. In some embodiments, in step 412, both the RF bias power and the second RF bias power may be supplied to a precursor to generate plasma. In additional embodiments, the RF bias power may be supplied to the substrate via the chuck electrode 410, and the second RF bias power may be supplied via the second RF electrode 460.

[0055]

[0059] In embodiments of Method 400, in step 415, plasma power supplied to the substrate processing area generates a deposited plasma from a precursor supplied to the substrate processing area. The generated deposited plasma may contain boron-containing components. In some embodiments, the generated plasma may also contain one or more hydrocarbon-containing components and nitrogen-containing components. In some embodiments, the plasma may come into direct contact with a substrate placed in the substrate processing area of ​​the substrate processing chamber.

[0056]

[0060] In step 420, the generated plasma deposits a boron-containing material onto the substrate in the substrate processing chamber. In some embodiments, the boron-containing material is deposited onto the substrate at a rate of about 700 A / min or less. Additional and exemplary deposition rate ranges include or are less than about 600 A / min, 500 A / min or less, 400 A / min or less, 300 A / min or less, 200 A / min or less, and 100 A / min or less. The amount of material deposited may be a layer with an average thickness of about 10 A or more. Additional and exemplary average thickness ranges may include or are greater than about 50 A, 100 A or more, 1000 A or more, 5000 A or more, 10,000 A or more, 20,000 A or more.

[0057]

[0061] The amount of boron incorporated into the deposited material can be based on any percentage of incorporation. For example, the deposited material may contain about 5% or more boron incorporation, and in some embodiments, it may contain about 10% or more boron incorporation, about 15% or more boron incorporation, about 20% or more boron incorporation, about 25% or more boron incorporation, about 30% or more boron incorporation, about 35% or more boron incorporation, about 40% or more boron incorporation, about 45% or more boron incorporation, about 50% boron incorporation, about 55% or more boron incorporation, about 60% or more boron incorporation, about 65% or more boron incorporation, about 70% or more boron incorporation, about 75% or more boron incorporation, about 80% or more boron incorporation, about 85% or more boron incorporation, about 90% or more boron incorporation, about 95% or more boron incorporation, or more boron incorporation.

[0058]

[0062] In embodiments of the technology described in this book, deposited boron-containing materials may be characterized by a reduction in hydrogen content. An exemplary range of hydrogen content in deposited boron-containing materials may include about 25 mol% or less. Additional and exemplary ranges of hydrogen content in deposited materials may include about 20 mol% or less, about 15 mol% or less, about 10 mol% or less, or even less. As described above, a reduction in hydrogen content in the material may contribute to a reduction in stress levels in the material.

[0059]

[0063] In some embodiments, the deposited material may contain carbon in addition to boron. The carbon in the deposited material accounts for approximately 60% or more of the carbon atoms in the deposited material. 3 It can be characterized by hybridization. 3 Additional and exemplary ranges of the percentage of hybridized carbon atoms may include or exceed approximately 40% or more, approximately 50% or more, approximately 65% ​​or more, approximately 70% or more, and approximately 80% or more, approximately 90% or more. A high percentage of sp3 hybridized carbon in the material results in a low percentage of sp3 hybridized carbon, and sp 2 Compared to boron-carbon-containing materials with a high percentage of hybridized carbon, the stress level in the material may be reduced. An increase in the amount of carbon atoms with sp3 hybridization increases the number of carbon-carbon single bonds in the shared network, and sp 2 Hybridization imparts more diamond-like carbon characteristics to the deposited layers. In covalently networked carbon, the length and strength of the carbon-carbon bonds are more isotropically distributed compared to graphite-like carbon; in this case, in-plane bonds are shorter and stronger than out-of-plane orthogonal bonds. As a result, sp 3 In boron-carbon-containing layers with an increased number of mixed carbon atoms, sp 2 Layers containing a larger amount of hybridized carbon and with a higher degree of graphite can be deposited under lower stress.

[0060]

[0064] In some embodiments, the boron-containing material may be deposited with low roughness. Exemplary ranges of average surface roughness may be approximately 2 nm or less, approximately 1.5 nm or less, approximately 1.0 nm or less, approximately 0.9 nm or less, approximately 0.8 nm or less, approximately 0.7 nm or less, approximately 0.6 nm or less, approximately 0.5 nm or less, approximately 0.4 nm or less, approximately 0.3 nm or less, approximately 0.2 nm or less, or even lower. In addition, in some embodiments, roughness may be substantially controlled regardless of film thickness. This allows for the avoidance of additional chemical and mechanical polishing steps, as the deposited film may be characterized by one of the above-described average roughness ranges. Furthermore, the deposited boron-containing layer may have a low roughness range (e.g., the difference between the highest and lowest peaks of the formed film). The exemplary roughness range across the entire deposited film may be approximately 10 nm or less, 9 nm or less, 8 nm or less, 7 nm or less, 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, and 1 nm or less, or even less. As a result, improved materials can be produced. This not only provides film and mask advantages that surpass conventional materials and processes, but also potentially reduces the manufacturing process by limiting or eliminating the number of polishing steps.

[0061]

[0065] In additional embodiments, boron-containing materials can be deposited at low stress. Low-stress materials are characterized by internal stress levels close to neutral stress (i.e., 0 MPa). High-stress materials, on the other hand, are characterized by internal stress levels that are significantly above 0 MPa (i.e., high positive (tensile) stress) or significantly below 0 MPa (i.e., high negative (compressive) stress). High positive stress (which can be characterized as tensile stress) can result from the expansion of the material, creating outward pressing forces on adjacent substrate features. High negative stress (which can be characterized as compressive stress) can result from the contraction of the material, creating inward tensile forces on adjacent substrate features. In other words, high-stress materials can be characterized by stress levels that are significantly above 0 MPa in absolute value. Therefore, when a material is characterized by a stress level "above -1000 MPa", this refers to the absolute value of the stress level, including levels such as -1500 MPa and -2000 MPa. Similarly, when a material is characterized by a stress level "below -1000 MPa," this indicates a stress level close to neutral stress (i.e., 0 MPa), including levels such as -500 MPa and -100 MPa, but never reaching positive values ​​above approximately 1000 MPa.

[0062]

[0066] Embodiments of deposited boron-containing materials may be characterized by stress levels of approximately -500 MPa or less, or above. Additional and exemplary stress ranges may include, or may be below, approximately -400 MPa, approximately -300 MPa, approximately -200 MPa, approximately -100 MPa, approximately -50 MPa, and approximately -10 MPa. These low-stress boron-containing materials may be deposited on multiple laminated film layers and can function as highly selective hard masks for pattern etching deep, high-aspect-ratio channels and contacts within the film layers. The low stress in the boron-containing material reduces stresses that can occur in the underlying substrate features (such as film stacks) and cause bending, breakage, and failure of the substrate features.

[0063]

[0067] The embodiments of the technology described in this book may also affect additional properties of deposited boron-containing materials. For example, embodiments of deposited boron-containing materials may be characterized by having a Young's modulus of about 150 GPa or more, and may be characterized by having a Young's modulus of about 160 GPa or more, about 170 GPa or more, about 180 GPa or more, about 190 GPa or more, about 200 GPa or more, or more.

[0064]

[0068] Embodiments of Method 400 may also include an optional step 425 for forming a boron-containing material on a hard mask layer. This step may include forming a pattern within the boron-containing hard mask to pattern etch substrate features onto the underlying substrate. For example, openings may be formed in the deposited boron-containing layer to expose the underlying substrate to dry etching (e.g., plasma etching) (which will form deep (e.g., about 1 μm or more) high aspect ratio (e.g., AR about 50:1 or more) channels or contacts within the substrate).

[0065]

[0069] By embodiments described in Method 400, deposited, low-roughness, low-stress boron-containing materials can be formed. These boron-containing materials may be characterized by low post-deposition roughness, requiring no additional processing steps to smooth the film layer of the deposited material. The boron-containing materials may also be characterized by low post-deposition stress, requiring no additional processing steps to reduce stress in the deposited layer. In some embodiments, the boron-containing materials may be characterized by high light transmittance and selectivity, making them well-suited as hard masks for pattern etching of underlying substrate features, for example. For example, these hard masks may be used for pattern etching of high aspect ratio (HAR) substrate features (such as 3D NAND devices). Embodiments of the techniques described herein include providing boron-containing hard masks in a post-deposition state on a substrate.

[0066]

[0070] In the above description, numerous details are provided for explanatory purposes to facilitate understanding of the various embodiments of the technology described herein. However, it will be obvious to those skilled in the art that certain embodiments can be practiced without some of these details, or with additional details.

[0067]

[0071] While several embodiments are disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the essence of the embodiments. In addition, some well-known processes and elements are not described in order to avoid unnecessarily obscuring the art described herein. Therefore, the above description should not be construed as limiting the scope of the art described herein.

[0068]

[0072] Where a range of values ​​is provided, unless otherwise explicitly stated by the context, each intermediary value between the upper and lower limits of that range is understood to be specifically disclosed, down to the smallest unit of the lower limit. Narrower ranges between any listed values ​​within a given range or between unlisted intermediary values, and any other listed or intermediary values ​​within such ranges, are included. The upper and lower limits of such narrower ranges may, individually, be included in or excluded from this range. Each range in which one, neither, or both of the limit values ​​are included in these narrower ranges is also included in the art of this document, provided that there are limit values ​​specifically excluded within the given range. Where a given range includes one or both of the limit values, it also includes ranges that exclude one or both of such included limit values.

[0069]

[0073] As used in this book and the accompanying claims, the singular forms "a," "an," and "the" include multiple references unless otherwise explicitly indicated by the context. Thus, for example, a reference to "a precursor" includes multiple such precursors, a reference to "the layer" includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0070]

[0074] Furthermore, when used in this specification and subsequent claims, the terms “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are intended to identify the presence of a described feature, integer, component, or process, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, One or more deposition precursors containing a boron-containing precursor are supplied to the processing area of ​​the semiconductor processing chamber, Forming the plasma of the one or more deposition precursors within the processing region of the semiconductor processing chamber, The method involves depositing a boron-containing material on a substrate placed within the processing area of ​​the semiconductor processing chamber, wherein the substrate is characterized by a temperature of approximately 50°C or less, and the semiconductor processing chamber is characterized by a pressure of less than 100 mTor. Semiconductor processing method.

2. The semiconductor processing method according to claim 1, further comprising supplying an inert precursor to the processing region of the semiconductor processing chamber, wherein the flow rate ratio of the inert precursor to the one or more deposition precursors is about 10:1 or more.

3. The semiconductor processing method according to claim 2, wherein the inert precursor comprises at least one of helium or argon.

4. The semiconductor processing method according to claim 1, wherein the semiconductor processing chamber is characterized by a pressure of approximately 50 mTor or less.

5. The semiconductor processing method according to claim 1, wherein the one or more deposition precursors further comprise a boron-carbon-containing precursor.

6. The semiconductor processing method according to claim 1, wherein the one or more deposition precursors further comprises at least one of a silicon-containing precursor or a nitrogen-containing precursor.

7. The semiconductor processing method according to claim 1, wherein the boron-containing material includes at least one of boron carbide, boron nitride, boron carbonitride, boron-containing silicon, boron-containing silicon oxide, boron / boron-containing silicon oxide, or boron-containing silicon nitride.

8. The semiconductor processing method according to claim 1, wherein the plasma is a bias plasma formed with a bias power exceeding 2,000 watts.

9. A semiconductor processing method, One or more deposition precursors containing a boron-containing precursor are supplied to the processing area of ​​the semiconductor processing chamber, Applying a bias power of approximately 3000 watts or more to a substrate placed within the processing area of ​​the semiconductor processing chamber, Forming the plasma of the one or more deposition precursors within the processing region of the semiconductor processing chamber, The method involves depositing a boron-containing material on the substrate, wherein the substrate is characterized by a temperature of approximately 50°C or lower, and includes depositing the boron-containing material. Semiconductor processing method.

10. The semiconductor processing method according to claim 9, wherein the one or more deposition precursors further comprise an inert precursor.

11. The semiconductor processing method according to claim 10, wherein the flow rate ratio of the inert precursor to the boron-containing precursor is about 10:1 or more.

12. The semiconductor processing method according to claim 9, wherein the bias power is approximately 4000 watts or more.

13. A semiconductor processing method, The process involves supplying a boron-containing precursor to the processing area of ​​a semiconductor processing chamber, Applying a bias power exceeding 2000 watts to a substrate placed within the processing area of ​​the semiconductor processing chamber, Forming a plasma of the boron-containing precursor within the processing region of the semiconductor processing chamber, The method includes depositing a boron-containing material on the substrate, wherein the boron-containing material is characterized by a post-deposit surface roughness of about 2 nm or less, and the substrate is characterized by a temperature of about 50°C or less. Semiconductor processing method.

14. The method further includes supplying an inert precursor to the processing region of the semiconductor processing chamber, wherein the flow rate ratio of the inert precursor to the boron-containing precursor is about 10:1 or more. The semiconductor processing method according to claim 13, wherein the bias power is approximately 3,000 watts or more.

15. The semiconductor processing method according to claim 13, wherein the boron-containing material is characterized by a post-deposition stress of approximately -500 MPa or less.

16. The boron-containing material further contains carbon atoms, and about 60% or more of the carbon atoms are sp ３ The semiconductor processing method according to claim 13, comprising a hybrid bond.

17. The semiconductor processing method according to claim 13, wherein the boron-containing material contains approximately 25 mol% or less of hydrogen.

18. The semiconductor processing method according to claim 13, wherein the boron-containing material includes at least one of boron carbide, boron nitride, boron carbonitride, boron-containing silicon, boron-containing silicon oxide, boron / boron-containing silicon oxide, or boron-containing silicon nitride.

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