Printed circuit board and method for manufacturing printed circuit board

Abstract

To use an adhesive layer with excellent high frequency characteristics without redesigning.SOLUTION: A printed circuit board composed of at least one dielectric layer and at least one conductor layer laminated (multilayer printed circuit board 10) includes an adhesive layer 13 interposed between a conductor layer 14 and a dielectric layer 12, and the thickness t (μm) of the adhesive layer 13 is configured such that the impedance change rate p when the impedance of a line formed in the conductor layer is compared with the case of t=0 (μm) satisfies 0%<p≤5%.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a printed circuit board and a method for manufacturing a printed circuit board. [Background technology]

[0002] Patent Document 1 discloses a technology for providing a printed circuit board with good high-frequency characteristics by using a material with excellent high-frequency characteristics in the adhesive layer of a multilayer structure. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication WO2017 / 130945 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] By the way, high-frequency characteristics can be improved by using the technology disclosed in Patent Document 1 and by making the adhesive layer high-performance. However, changing the material of the adhesive layer changes the dielectric constant of the entire printed circuit board.

[0005] For example, if a circuit pattern designed for a conventional printed circuit board that does not use a high-performance adhesive layer is used for a printed circuit board that does use a high-performance adhesive layer, the characteristic impedance at high frequencies changes, and reflection losses due to impedance mismatch increase, which necessitates redesigning the circuit pattern.

[0006] The present invention aims to provide a printed circuit board and a method for manufacturing a printed circuit board that can utilize an adhesive layer with excellent high-frequency characteristics without requiring redesign. [Means for solving the problem]

[0007] In order to solve the above problems, in a printed circuit board composed of at least one dielectric layer and at least two conductor layers laminated, with the conductor layer located in the outermost layer, the conductor layer located in the outermost layer is laminated to the dielectric layer through an adhesive layer. The relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed in the conductor layer when compared with the case where t = 0 (μm) satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.19t 2 -5.25t + 43.5)p / 100 + 1 (Relational expression 3) B = (-0.8t + 22)p / 100, which is characterized by this. According to such a configuration, it becomes possible to use an adhesive layer with excellent high-frequency characteristics without performing redesign.

[0008] Further, in the present invention, in a printed circuit board composed of at least two dielectric layers and at least three conductor layers laminated, with the conductor layer located in the outermost layer, the conductor layer located between the two dielectric layers is laminated to either one of the two dielectric layers through an adhesive layer. The relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed in the conductor layer when compared with the case where t = 0 (μm) satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.44t 2 -12.8t + 108)p / 100 + 1 (Relational expression 3) B = (-0.2t + 26)p / 100, which is characterized by this. According to such a configuration, it becomes possible to use an adhesive layer with excellent high-frequency characteristics without performing redesign.

[0009] Further, the present invention is configured by laminating at least two dielectric layers and at least three conductor layers, and in a printed circuit board in which the conductor layer is located in the outermost layer, two of the conductor layers located in the outermost layer are each laminated via an adhesive layer with respect to the dielectric layer, and the conductor layer located between the two dielectric layers is laminated via an adhesive layer with respect to either one of the two dielectric layers, and the relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed in the conductor layer when compared with the case where t = 0 (μm) satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.3t 2 - 8.7t + 78)p / 100 + 1 (Relational expression 3) B = (-0.2t + 10)p / 100, which is characterized in that. According to such a configuration, an adhesive layer with excellent high-frequency characteristics can be used without performing redesign.

[0010] Further, the present invention is characterized in that the impedance change rate p is 3.5% or less. According to such a configuration, by further suppressing the impedance change rate, the necessity for redesign can be further reduced.

[0011] Further, the present invention is characterized in that the impedance change rate p is 2.5% or less. According to such a configuration, by further suppressing the impedance change rate, the necessity for redesign can be further reduced.

[0012] Further, the present invention is characterized in that the impedance change rate p is 2.0% or less. According to such a configuration, by making the impedance change rate extremely small, the necessity for redesign can be made extremely small.

[0013] Further, the present invention is characterized in that the t (μm) is 15 (μm) or less. According to such a configuration, the adhesion strength between the dielectric layer and the conductor layer can be ensured.

[0014] Further, the present invention is characterized in that the t (μm) is 10 (μm) or less. According to such a configuration, the adhesion strength between the dielectric layer and the conductor layer can be ensured.

[0015] Further, the present invention is characterized in that the t (μm) is 5 (μm) or less. According to such a configuration, the adhesion strength between the dielectric layer and the conductor layer can be ensured.

[0016] Further, the present invention is characterized in that the Rz value indicating the surface roughness of the conductor layer is 1 μm or less. According to such a configuration, even when a conductor layer with a small surface roughness and good high-frequency characteristics is used, the necessity of redesign can be reduced.

[0017] Further, the present invention is characterized in that when the relative permittivity of the dielectric layer is Y and the relative permittivity of the adhesive layer is X, Y = 3.35 or more and 3.85 or less, and X = 2.25 or more and 2.75 or less. According to such a configuration, the impedance change rate can be suppressed, and the necessity of redesign can be surely reduced.

[0018] Further, the present invention provides a printed circuit board manufacturing method for manufacturing a printed circuit board in which at least one dielectric layer and at least two conductor layers are laminated and the conductor layer is located in the outermost layer. The conductor layer located in the outermost layer is laminated on the dielectric layer via an adhesive layer. The relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed on the conductor layer satisfy the following relational expressions 1 to 3, and the printed circuit board is manufactured so that the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.19t 2It is characterized in that B = ((-5.25t + 43.5)p / 100 + 1) (Relationship 3). According to such a method, an adhesive layer with excellent high-frequency characteristics can be utilized without redesign.

[0019] Further, the present invention relates to a printed circuit board manufacturing method for manufacturing a printed circuit board in which at least two dielectric layers and at least three conductor layers are laminated and the conductor layer is located in the outermost layer. In the method, the conductor layer located between the two dielectric layers is laminated via an adhesive layer with respect to either one of the two dielectric layers. The relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed in the conductor layer when compared with the case where t = 0 (μm) satisfy the following relational expressions 1 to 4, and the printed circuit board is manufactured such that the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.44t 2 It is characterized in that B = ((-12.8t + 108)p / 100 + 1) (Relationship 3). According to such a method, an adhesive layer with excellent high-frequency characteristics can be utilized without redesign.

[0020] Further, the present invention relates to a printed circuit board manufacturing method for manufacturing a printed circuit board in which at least two dielectric layers and at least three conductor layers are laminated and the conductor layer is located in the outermost layer. In the method, two conductor layers located in the outermost layer are each laminated via an adhesive layer with respect to the dielectric layer, and the conductor layer located between the two dielectric layers is laminated via an adhesive layer with respect to either one of the two dielectric layers. The relative permittivity Y of the dielectric layer, the relative permittivity X of the adhesive layer, the thickness t (μm) of the adhesive layer, and the impedance change rate p of the circuit formed in the conductor layer when compared with the case where t = 0 (μm) satisfy the following relational expressions 1 to 3, and the printed circuit board is manufactured such that the impedance change rate p satisfies 0% < p ≤ 5%. (Relational expression 1) X < Y < AX + B (Relational expression 2) A = (0.3t 2The equation B = (-0.2t + 10)p / 100 is characterized by the relationship -8.7t + 78)p / 100 + 1 (relationship 3). This method allows for the use of adhesive layers with superior high-frequency properties without requiring redesign. [Effects of the Invention]

[0021] According to the present invention, it is possible to provide a printed circuit board and a method for manufacturing a printed circuit board that can utilize an adhesive layer with excellent high-frequency characteristics without requiring redesign. [Brief explanation of the drawing]

[0022] [Figure 1] This is a cross-sectional view showing an example of the configuration of a printed circuit board according to the first embodiment of the present invention. [Figure 2] This figure shows an example of a simulation configuration for investigating the impedance change rate of the first embodiment shown in Figure 1. [Figure 3] Figure 2 shows an example of a TDR waveform. [Figure 4] This figure shows an example of a method for determining Ta and Tb. [Figure 5] This figure shows the simulation results in Figure 2. [Figure 6] This is a diagram illustrating the tolerances of printed circuit boards. [Figure 7] This figure shows the simulation results in Figure 2. [Figure 8] This is a cross-sectional view showing an example of the configuration of a printed circuit board according to a second embodiment of the present invention. [Figure 9] This figure shows an example of a simulation configuration for investigating the impedance change rate of the second embodiment shown in Figure 8. [Figure 10] Figure 9 shows the simulation results. [Figure 11] Figure 9 shows the simulation results. [Figure 12] Figure 9 shows the simulation results. [Figure 13] This is a cross-sectional view showing an example of the configuration of a printed circuit board according to the third embodiment of the present invention. [Figure 14] Figure 13 shows an example of a simulation configuration for investigating the impedance change rate of the third embodiment. [Figure 15] Figure 14 shows an example of a TDR waveform. [Figure 16] This figure shows an example of a method for determining Ta and Tb. [Figure 17] This figure shows the simulation results. [Figure 18] This figure shows the simulation results. [Figure 19] This figure shows the simulation results. [Figure 20] This figure shows the simulation results. [Figure 21] This is a cross-sectional view showing an example of the configuration of a printed circuit board according to the fourth embodiment of the present invention. [Figure 22] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 23] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 24] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 25] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 26] This is a cross-sectional view of the circuit board when measuring impedance. [Figure 27] This is a cross-sectional view of the circuit board when measuring impedance. [Figure 28] This is an example of a measurement device configuration for measuring impedance. [Figure 29] This figure shows the measured results as shown in Figure 28. [Figure 30] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 31]This is a SEM image of the substrate used when measuring the thickness of the adhesive layer. [Figure 32] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 33] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 34] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 35] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 36] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 37] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 38] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 39] This figure shows the simulation results of a modified embodiment of the present invention. [Figure 40] This figure shows the simulation results of a modified embodiment of the present invention. [Modes for carrying out the invention]

[0023] Next, embodiments of the present invention will be described.

[0024] (A) Description of the first embodiment of the present invention Figure 1 is a cross-sectional view showing an example of the configuration of a printed circuit board according to the first embodiment of the present invention. In the configuration example shown in Figure 1, the printed circuit board 10 is This is the second conductor layer. Ground layer 11, The first dielectric layer Dielectric layer 12, The first adhesive layer Adhesive layer 13, and The first conductor layer It has a conductor layer 14. Note that the first embodiment is an embodiment having a microstrip line.

[0025] Here, the ground layer 11 is made of a highly conductive metal such as copper, and functions as the ground of the circuit.

[0026] The dielectric layer 12 can be made of, for example, epoxy resin, polyamide-imide resin, fluororesin, polyimide resin, polyphenylene ether resin, Teflon® resin, or resins mixed with glass fibers. Alternatively, these materials may be mixed as appropriate. Of course, other materials may also be used.

[0027] The adhesive layer 13 is composed of, for example, epoxy resin, polyamide resin polymer, polyethersulfone resin, polyolefin resin, or polyphenylene ether resin, and has the function of bonding the conductive layer 14 to the dielectric layer 12.

[0028] The conductor layer 14 is made of a highly conductive metal such as copper, and various wiring patterns are formed on it.

[0029] The method for manufacturing the printed circuit board 10 shown in Figure 1 involves first forming a conductive layer 14 having an adhesive layer 13. More specifically, the adhesive layer 13 is formed on one side of an electrolytic copper foil or rolled copper foil having an Rz value of 1 μm or less, by coating or spraying. Here, the Rz value is defined as the value expressed in micrometers (μm) by taking a reference length from the roughness curve in the direction of its average line, measuring the distance between the peak and trough lines of this sampled portion in the direction of the vertical scaling factor of the roughness curve, based on JIS standard B0601. The reason for using electrolytic copper foil or rolled copper foil with an Rz value of 1 μm or less is that electrolytic copper foil or rolled copper foil with a small Rz value has better high-frequency characteristics compared to those with a large Rz value. Specifically, copper foil with a small Rz value has reduced signal transmission loss due to the skin effect compared to those with a large Rz value.

[0030] Next, a ground layer 11 made of electrolytic copper foil or rolled copper foil, a dielectric layer 12 made of a dielectric material, and a conductor layer 14 on which an adhesive layer 13 is formed are laminated in this order, and then bonded together by pressing or the like.

[0031] Next, a photoresist layer (not shown) is formed on the conductive layer 14, and ultraviolet light is irradiated onto it according to the circuit pattern using, for example, an exposure apparatus. This allows the photoresist layer to be cured according to the circuit pattern.

[0032] Next, the printed circuit board 10 with the cured photoresist layer is placed in a solvent to remove the uncured photoresist layer. This forms a photoresist layer on the conductive layer 14 that corresponds to the circuit pattern.

[0033] Next, the printed circuit board 10 is placed in the etching solution. As a result, areas where the photoresist layer is absent are removed by corrosion of the etching solution, forming a conductive layer 14 corresponding to the circuit pattern. In the example shown in Figure 1, a microstrip line is formed.

[0034] Next, the remaining hardened photoresist layer is removed using a solvent or the like. This allows us to obtain the printed circuit board 10 shown in Figure 1.

[0035] Next, a detail of the first embodiment of the present invention will be described.

[0036] As shown in Figure 1, the thickness of the adhesive layer 13 is 15 μm, and the total thickness of the adhesive layer 13 and the dielectric layer 12 is 150 μm. In this case, a simulation is performed using an electromagnetic field simulator that utilizes the finite element method, such as HFSS (High Frequency Structure Simulator) from ANSYS, using a circuit as shown in Figure 2, which has a dielectric layer 12, adhesive layer 13, and conductor layer 14 of similar thickness.

[0037] More specifically, in the example shown in Figure 2, a ground layer 11 (not shown) with a length of 10 mm in the y-axis direction is placed in the xy-plane with its longitudinal center aligned with the y-axis. Above it (above in the z-axis direction), a dielectric layer 12 with a length of 10 mm in the y-axis direction is placed, followed by an adhesive layer 13 with a length of 6 mm in the y-axis direction, and finally a conductor layer 14 with a length of 10 mm in the y-axis direction is placed along the y-axis.

[0038] Then, a pulse signal with a rise time of 25 ps is applied, and the TDR (Time Domain Reflectometry) waveform is measured.

[0039] Figure 3 shows the simulation results. More specifically, Figure 3 shows the reflected wave of a signal input from near the origin of the coordinate system. In Figure 3, the horizontal axis represents time (ps), and the vertical axis represents impedance (Ω). Ta represents the reception time of the reflected wave from point A, and Tb represents the reception time of the reflected wave from point B. Ta and Tb can be set as follows: for example, Ta can be set near the origin (near Ta=0). For Tb, a point can be selected near the peak of the TDR waveform where the slope of the TDR waveform is small, which is common to both materials with high and low relative permittivity. In this embodiment, as an example, as shown in Figure 4, Tb is set to an arbitrary point in the region that is common to both the TDR waveform of the main substrate of the dielectric layer 12 with the highest relative permittivity (Y=5) (dashed curve) and the TDR waveform of the lowest relative permittivity (Y=2) (solid curve) within the analysis range. A flat region can be defined as the region where the curve showing the slope (Ω / ns) of the TDR waveform for the primary substrate with the highest relative permittivity (Y=5) (the double-dotted curve) and the curve showing the slope (Ω / ns) of the TDR waveform for the primary substrate with the lowest relative permittivity (Y=2) (the single-dotted curve) are both, for example, 10 Ω / ns or less. For example, Tb can be set to 0.062 ns, which falls within the range of 0.56 to 0.63 ns shown in Figure 4. In the example shown in Figure 3, Ta=0 ns and Tb=0.062 ns, and the impedance at time Ta is Za and the impedance at time Tb is Zb, so Za can be treated as the impedance of the reflected wave from point A and Zb as the impedance of the reflected wave from point B. Note that the above method of choosing Za and Zb is just one example, and for example, a flat region can be individually selected according to the value of Y to obtain Za and Zb. Alternatively, the impedance of the printed circuit board may be obtained using the TDR waveform obtained by actually measuring the impedance of the printed circuit board, following the procedure described above.

[0040] Based on these simulation results, the impedance change rate [%] is defined as follows.

[0041] Impedance change rate = (Zb - Za) / Za × 100 ... (1)

[0042] More specifically, equation (1) shows the rate of change in impedance between the portion without the adhesive layer 13 (point A) and the portion with the adhesive layer 13 (point B) (where Zb is the impedance of the portion without the adhesive layer 13).

[0043] Figure 5 shows the rate of change in impedance when the relative permittivity of the dielectric layer 12 and the relative permittivity of the adhesive layer 13 are changed in Figure 2. In Figure 5, the horizontal axis shows the relative permittivity of the primer constituting the adhesive layer 13, and the vertical axis shows the relative permittivity of the main substrate constituting the dielectric layer 12.

[0044] Furthermore, in Figure 5, the thin curves indicate boundary lines that delineate regions where the rate of change of impedance falls within a predetermined range. For example, the second curve from the top left is the boundary line that delineates regions where the rate of change of impedance exceeds 20.0%.

[0045] The thick line L1 represents the position where the relative permittivity of the primer and the main substrate are equal. The thick line L2 represents the position where the impedance change rate is 5%. The thick line L3 represents the position where the relative permittivity of the main substrate is 3.00.

[0046] If we let X be the relative permittivity of the primer constituting the adhesive layer 13, and Y be the relative permittivity of the dielectric constituting the dielectric layer 12, then these must satisfy the following two relationships (2) and (3).

[0047] Y>X ···(2)

[0048] In other words, if the material is selected such that the relative permittivity of the adhesive layer 13 is greater than that of the dielectric layer 12, the delay of the signal flowing through the conductor layer 14 will increase. Therefore, it is necessary to select the material such that equation (2) is satisfied.

[0049] Y < 1.38X + 0.50 ... (3)

[0050] The right-hand side of equation (3) represents the thick line L2 shown in Figure 5. By setting the parameters to satisfy equation (3), the rate of change in characteristic impedance can be kept below 5%. The characteristic impedance of typical high-frequency circuit boards is controlled to ±5%, and if the change is below 5%, transmission with low reflection loss is possible even when using circuit patterns designed for conventional printed circuit boards.

[0051] To keep reflected noise below 5% of the signal amplitude, the change in characteristic impedance must be kept within 10%. Therefore, the impedance adjustment specification for circuit boards is considered standard at ±10% (Eric Bogatin, High-Speed ​​Digital Signal Transmission Technology: An Introduction to Signal Integrity (2010), translated and supervised by Toshio Sudo, p. 271).

[0052] The track width generally varies by about twice the copper foil thickness due to etching accuracy, resulting in a variation of approximately ±5% in the track impedance. As mentioned earlier, in order to keep the characteristic impedance variation within ±10%, it is necessary to limit the variation to within 5%. For example, in Figure 6, if the design is to achieve 50Ω at w=0.324mm, and the variation is w ± copper foil thickness of 0.012mm × 2, then w=0.324+0.024mm will be approximately 47.9Ω and w=0.324-0.024mm will be approximately 52.4Ω, resulting in an impedance variation of approximately ±5%.

[0053] Furthermore, since the main substrate constituting the dielectric layer 12 is assumed to be an epoxy-based substrate, its relative permittivity is within the range of equation (4) below. Of course, if a substrate other than epoxy is used, it may be outside this range.

[0054] 3 ≤ Y ≤ 5 ···(4)

[0055] Figure 7 shows the relationship between the impedance change rate, signal delay, and ease of application to existing designs when the relative permittivity of the main substrate constituting the dielectric layer 12 is set to 3 or 5 in Figure 2, and the relative permittivity of the primer constituting the adhesive layer 13 is changed. In Figure 5, "Examples" shows the results according to the first embodiment of the present invention, and "Comparative Examples" shows embodiments different from the first embodiment.

[0056] As shown in Figure 7, in the "Examples" that satisfy equations (2) to (4), the signal delay is "none" in all cases. Furthermore, the ease of application to existing designs is one of the following: the impedance change rate is "3.5 to 5%", indicating that circuit patterns designed for conventional printed circuit boards can be applied ("〇"), the impedance change rate is "2.5 to 3.5%", indicating that circuit patterns designed for conventional printed circuit boards are easily applicable ("◎"), the impedance change rate is "2 to 2.5%", indicating that circuit patterns designed for conventional printed circuit boards are even easier to apply ("◎◎"), or the impedance change rate is "~2%", indicating that circuit patterns designed for conventional printed circuit boards are particularly easy to apply ("◎◎◎").

[0057] On the other hand, in the comparative example, for example, in sample number "293", the relative permittivity Y of the main substrate is 3, while the relative permittivity X of the primer is 3.5, so equation (2) is not satisfied. In this case, the ease of application to existing designs is "◎◎◎", but the signal delay is "present", which is undesirable.

[0058] Furthermore, for sample numbers "378" to "387," equation (2) is satisfied, but equation (3) is not. Therefore, there is "no" signal delay. However, the ease of application to existing designs is one of the following: the impedance change rate is "5-7.5%", indicating that it is difficult to apply circuit patterns designed for conventional printed circuit boards ("△"); the impedance change rate is "7.5-10%", indicating that it is difficult to apply circuit patterns designed for conventional printed circuit boards ("×"); or the impedance change rate is "10% or higher", indicating that it is particularly difficult to apply circuit patterns designed for conventional printed circuit boards ("××"). For these reasons, application to existing designs will be difficult, and it is highly likely that redesign will be necessary.

[0059] As described above, in the first embodiment of the present invention, in the configuration shown in Figure 1, when the relative permittivity of the primer constituting the adhesive layer 13 is X and the permittivity of the dielectric constituting the dielectric layer 12 is Y, the change rate of impedance can be reduced to 5% or less by selecting materials such that X and Y satisfy the aforementioned equations (2) to (4). As a result, in particular, when using a conductor layer 14 with good high-frequency characteristics and an Rz value of 1 μm or less, it becomes necessary to use the adhesive layer 13 to increase the bonding strength. Even in such cases, by selecting materials such that the aforementioned equations (2) to (4) are satisfied, the conventional circuit pattern can be reused without changing the design.

[0060] (B) Description of a second embodiment of the present invention Figure 8 shows an example of the configuration of a printed circuit board according to the second embodiment of the present invention. In the first embodiment shown in Figure 1, the adhesive layer 13 was fixed to a thickness of 15 μm, but in the example in Figure 8, the adhesive layer 13 is t μm thick. Furthermore, the impedance change rate is set to p%, and the relationship between X, Y, t, and p is determined.

[0061] FIG. 9 shows a configuration example that is the subject of the simulation used in the second embodiment. In the example of FIG. 9, compared with FIG. 2, the thickness of the adhesive layer 13 is changed from 15 μm to t μm. That is, in the second embodiment, the simulation was performed while changing the thickness t of the adhesive layer 13.

[0062] FIG. 10 shows the simulation results for the case where t = 15 μm. Further, FIG. 11 shows the simulation results for the case where t = 10 μm. Furthermore, FIG. 12 shows the simulation results for the case where t = 5 μm. From these comparisons, as the thickness t of the adhesive layer 13 decreases, the thin line curve indicating the boundary line of the impedance change rate moves toward the upper left point (1.00, 5.00) and the interval between the curves widens. As a result, the thinner the thickness t of the adhesive layer 13, the wider the region where the impedance change rate falls within the desired range (for example, the impedance change rate p satisfies 0% < p ≦ 5%, that is, the range exceeding 0% and not exceeding 5%), and the range of material selection that can eliminate the need for design changes can be widened. From this perspective, t = 10 μm or less is more preferable, and t = 5 μm or less is even more preferable.

[0063] Also, based on FIGS. 10 to 12, when the relationships of X, Y, t, and p are obtained, the following equations (5) to (7) are obtained.

[0064] X < Y < AX + B ···(5)

[0065] A = (0.19t 2 - 5.25t + 43.5)p / 100 + 1 ···(6)

[0066] B = (-0.8t + 22)p / 100 ···(7)

[0067] The boundary where the impedance change rate p obtained by the above equations falls within a predetermined range is shown as a thick straight line in Figures 10 to 12. The thick straight lines representing the calculation results in these figures and the thin curves representing the results obtained by simulation are in good agreement. Therefore, by substituting the thickness t of the adhesive layer 13 and the desired impedance change rate p into equations (5) to (7) above, the range of the relative permittivity X of the adhesive layer 13 and the relative permittivity Y of the dielectric layer 12 can be determined.

[0068] As described above, in the second embodiment of the present invention, in the configuration shown in Figure 8, when the relative permittivity of the primer constituting the adhesive layer 13 is X, the permittivity of the dielectric constituting the dielectric layer 12 is Y, the thickness of the adhesive layer 13 is t, and the impedance change rate is p, the impedance change rate p can be kept within a desired range by selecting materials such that X, Y, and t satisfy the aforementioned equations (5) to (7). For this reason, when using a conductor layer 14 with good high-frequency characteristics, particularly one with an Rz value of 1 μm or less, it becomes necessary to use the adhesive layer 13 to increase the bonding strength. Even in such cases, by selecting materials such that they satisfy the aforementioned equations (5) to (7), the conventional circuit pattern can be reused without changing the design.

[0069] (C) Description of the third embodiment of the present invention Figure 13 shows an example of the configuration of a printed circuit board according to the third embodiment of the present invention. Compared to Figure 8, the configuration example shown in Figure 13 is as follows: 1 Conductor layer 14 and 1 On top of the adhesive layer 13 2nd Dielectric layer 15 and It is the third conductor layer. A ground layer 16 has been newly added. The rest of the configuration is the same as in Figure 8. Note that the third embodiment is an embodiment that has a strip line.

[0070] Here, the dielectric layer 15 is made of the same material as the dielectric layer 12. That is, the dielectric layer 15 can be made of, for example, epoxy resin, polyamide-imide resin, fluororesin, polyimide resin, polyphenylene ether resin, Teflon® resin, and resins mixed with glass fibers. These materials may also be mixed as appropriate. Of course, other materials may also be used.

[0071] The ground layer 16, like the ground layer 11, is made of a highly conductive metal such as copper and functions as a ground. Alternatively, it may be configured as a power supply layer that supplies positive power instead of a ground layer.

[0072] Furthermore, the printed circuit board 10 shown in Figure 13 can be manufactured by laminating the dielectric layer 15 and the ground layer 16 onto the printed circuit board shown in Figure 8 using a pressing process.

[0073] Figure 14 shows the configuration of the simulation target used in the third embodiment. In the example in Figure 14, a ground layer 11 (not shown) with a length in the y-axis direction of 20 mm is placed in the xy-plane so that its longitudinal center is aligned with the y-axis, a dielectric layer 12 with a length in the y-axis direction of 20 mm is placed on top of it (in the z-axis direction), an adhesive layer 13 with a length in the y-axis direction of 10 mm is placed in the lower half of the figure, a conductor layer 14 with a length in the x-axis direction of 0.09 to 0.29 mm and a length in the y-axis direction of 20 mm is placed on top of that, a dielectric layer 15 with a length in the y-axis direction of 20 mm is placed on top of that, and a ground layer 16 with a length in the y-axis direction of 20 mm is placed on top of that.

[0074] Below Figure 14 are cross-sectional views of points A and B. At point A, dielectric layer 12 and dielectric layer 15 are configured as a single unit. At point B, on the other hand, an adhesive layer 13 with a thickness of t μm is interposed between dielectric layer 12 and dielectric layer 15. The thicknesses of dielectric layer 12, adhesive layer 13, and dielectric layer 15 are 318 μm, and the thickness of the ground layer 16 is 18 μm. Furthermore, the impedance in the region where adhesive layer 13 is not present is adjusted to 50 Ω.

[0075] The configuration shown in Figure 14 is used, and a pulse signal with a rise time of 25 ps is applied to measure the TDR waveform.

[0076] Figure 15 shows the TDR waveform obtained from the simulation. Figure 15 shows the reflected wave of a signal input from near the origin of the coordinate system. The horizontal axis of this figure represents time, and the vertical axis represents impedance. Ta represents the reception time of the reflected wave from point A, and Tb represents the reception time of the reflected wave from point B. In terms of how Ta and Tb are chosen, it is possible to select points in the TDR waveform where the slope of the TDR waveform is small in common for both materials with high relative permittivity and materials with low relative permittivity. In this embodiment, as an example, as shown in Figure 16, within the analysis range, Ta can be any point in the first region where the TDR waveform of the main substrate of the dielectric layer 12 with the highest relative permittivity (Y=5) (dashed line curve) and the TDR waveform of the main substrate with the lowest relative permittivity (Y=2) (solid line curve) are both flat. Within the analysis range, Tb can be any point in the first region where the TDR waveform of the main substrate of the dielectric layer 12 with the highest relative permittivity (Y=5) (dashed line curve) and the TDR waveform of the main substrate with the lowest relative permittivity (Y=2) rise and then become flat. The flat region can be a region where, for example, both the curve showing the slope (Ω / ns) of the TDR waveform of the main substrate with the highest relative permittivity (Y=5) (dotted line curve) and the curve showing the slope (Ω / ns) of the TDR waveform of the main substrate with the lowest relative permittivity (Y=2) (single dashed line curve) are, for example, 10 Ω / ns or less. For example, Ta can be set to 0.050 ns, which falls within the range of 0.026 to 0.088 ns in Figure 16. Similarly, Tb can be set to 0.180 ns, which falls within the range of 0.180 to 0.188 ns shown in Figure 16. In the example shown in Figure 15, Ta = 0.050 ns and Tb = 0.180 ns, and the impedance at time Ta is denoted as Za and the impedance at time Tb as Zb. Thus, Za can be treated as the impedance of the reflected wave from point A, and Zb as the impedance of the reflected wave from point B. Note that the above method of choosing Za and Zb is just one example; for example, a flat region can be individually selected according to the value of Y to obtain Za and Zb. Alternatively, the impedance of the printed circuit board can be obtained by using the TDR waveform obtained by actually measuring the impedance of the printed circuit board and following the procedure described above.

[0077] Figure 17 shows the simulation results of FIG. 14 when the thickness t of the adhesive layer 13 is set to 15 μm. In FIG. 17, the thin-line curve indicates the boundary that divides the region where the impedance change rate falls within a predetermined range. For example, the second thin line from the upper left indicates the boundary where the impedance change rate is 7.5% or more.

[0078] Figure 18 shows the simulation results of FIG. 14 when the thickness t of the adhesive layer 13 is set to 10 μm. In FIG. 18, the thin-line curve indicates the boundary line that divides the region where the impedance change rate falls within a predetermined range. For example, the second thin line from the upper left indicates the boundary where the impedance change rate is 5.0% or more.

[0079] Figure 19 shows the simulation results of FIG. 14 when the thickness t of the adhesive layer 13 is set to 5 μm. In FIG. 19, the thin-line curve indicates the boundary line that divides the region where the impedance change rate falls within a predetermined range. For example, the thin line in the upper left indicates the boundary where the impedance change rate is 2.5% or more.

[0080] From these comparisons, as the thickness t of the adhesive layer 13 decreases, the curve indicating the range of the impedance change rate moves toward the upper left point (1.00, 5.00) and the interval between the curves widens. As a result, the thinner the thickness t of the adhesive layer 13, the wider the region where the impedance change rate falls within the desired range (for example, the range where the impedance change rate p is 0% < p ≤ 5%, that is, the range exceeding 0% and being 5% or less). From this perspective, t = 10 μm or less is more preferable, and t = 5 μm or less is even more preferable.

[0081] Also, based on FIGS. 17 to 19, when obtaining the relationship between X, Y, t, and p, the following equations (8) to (10) are obtained.

[0082] X < Y < AX + B ···(8)

[0083] A = (0.44t 2 -12.8t + 108)p / 100 + 1 ···(9)

[0084] B = (-0.2t + 26)p / 100 ... (10)

[0085] The boundary of the impedance change rate p obtained by the above equations is shown as a thick straight line in Figures 17 to 19. The thick straight line representing the calculation results in these figures and the thin curve representing the results obtained by simulation are in good agreement. Therefore, by substituting the thickness t of the adhesive layer 13 and the desired impedance change rate p into equations (8) to (10) above, the range of the relative permittivity X of the adhesive layer 13 and the relative permittivity Y of the dielectric layer 12 can be determined. This allows the impedance change rate to be suppressed, enabling the reuse of existing designs without modification.

[0086] Figure 20 is a diagram showing the relationship between the impedance change rate, signal delay, and ease of application to existing designs when the relative permittivity of the main substrate constituting the dielectric layer 12 is set to 3 or 5 in Figure 14, and the relative permittivity of the primer constituting the adhesive layer 13 is changed. In Figure 20, "Examples" show the results according to the third embodiment of the present invention, and "Comparative Examples" show embodiments different from the third embodiment.

[0087] As shown in Figure 20, in the "Examples" that satisfy equations (8) to (10), the signal delay is "none" in all cases. Furthermore, the ease of application to existing designs is one of the following: the impedance change rate is "3.5 to 5%", indicating that circuit patterns designed for conventional printed circuit boards can be applied ("〇"), the impedance change rate is "2.5 to 3.5%", indicating that circuit patterns designed for conventional printed circuit boards are easily applicable ("◎"), the impedance change rate is "2 to 2.5%", indicating that circuit patterns designed for conventional printed circuit boards are even easier to apply ("◎◎"), or the impedance change rate is "~2%", indicating that circuit patterns designed for conventional printed circuit boards are particularly easy to apply ("◎◎◎").

[0088] On the other hand, in the comparative example, for instance, in the example of sample number "686", the relative permittivity Y of the main base material is 3, while the relative permittivity X of the primer is 3.5, so X < Y is not satisfied. In this case, the ease of application to the existing design is "◎◎◎", but since there is a signal delay, it is not preferable.

[0089] Also, for sample numbers "771" to "775", although X < Y is satisfied, X < Y < AX + B is not satisfied. So, there is no signal delay, but the ease of application to the existing design shows either "△" indicating that the impedance change rate is "5 - 7.5%" and it is difficult to apply the circuit pattern designed for conventional printed boards, "×" indicating that the impedance change rate is "7.5 - 10%" and it is difficult to apply the circuit pattern designed for conventional printed boards, or "××" indicating that the impedance change rate is "10% - " and it is particularly difficult to apply the circuit pattern designed for conventional printed boards. Therefore, for these cases, since it is difficult to apply to the existing design, there is a high possibility that a new design will be required.

[0090] As described above, in the third embodiment of the present invention, in the configuration shown in FIG. 13, when the relative permittivity of the primer constituting the adhesive layer 13 is X, the permittivity of the dielectric constituting the dielectric layer 12 is Y, the thickness of the adhesive layer 13 is t, and the impedance change rate is p, by selecting the members such that X, Y, and p satisfy the above-described formulas (8) to (10), the impedance change rate p can be kept within a desired range. Therefore, when using the conductor layer 14 with good high-frequency characteristics and an Rz value of 1 μm or less, it is necessary to use the adhesive layer 13 to increase the bonding strength. Even in such a case, by selecting the materials so as to satisfy the above-described formulas (8) to (10), the previous circuit pattern can be reused without design changes.

[0091] (D) Explanation of the Fourth Embodiment of the Present Invention Figure 21 is a diagram showing an example configuration of the fourth embodiment of the present invention. In Figure 21, parts corresponding to the third embodiment shown in Figure 13 are denoted by the same reference numerals, and their descriptions are omitted. Compared with Figure 13, Figure 21 shows: 2nd Adhesive layer 31 and Third An adhesive layer 32 has been added. Other than these, it is the same as in Figure 13. Here, 2nd The adhesive layer 31 is connected to the ground layer 11. 1 This is the layer to which the dielectric layer 12 is bonded. Third The adhesive layer 32 is 2nd This is the layer that bonds the dielectric layer 15 and the ground layer 16. Furthermore, the second adhesive layer 31 and Third The adhesive layer 32 is made of the same material as the first adhesive layer 13.

[0092] Figure 22 shows the simulation results of Figure 21 when the thickness of the adhesive layer 13 is set to t = 15 μm. In Figure 22, the thin curves indicate the boundaries that divide the region where the impedance change rate falls within a predetermined range. For example, the second thin curve from the top left indicates the boundary where the impedance change rate is 15.0% or higher.

[0093] Figure 23 shows the simulation results of Figure 21 when the thickness of the adhesive layer 13 is set to t = 10 μm. In Figure 23, the thin curves indicate boundary lines that divide the region where the impedance change rate falls within a predetermined range. For example, the second thin line from the top left indicates the boundary where the impedance change rate is 10.0% or higher.

[0094] Figure 24 shows the simulation results of Figure 21 when the thickness of the adhesive layer 13 is set to t = 5 μm. In Figure 35, the thin curves indicate boundary lines that divide the region where the impedance change rate falls within a predetermined range. For example, the second thin line from the top left indicates the boundary where the impedance change rate is 5.0% or higher.

[0095] From these comparisons, as the thickness t of the adhesive layer 13 decreases, the curve indicating the range of the impedance change rate moves toward the upper left point (1.00, 5.00), and the interval between the curves widens. As a result, the thinner the thickness t of the adhesive layer 13, the wider the region where the impedance change rate falls within the desired range (for example, the impedance change rate p satisfies 0% < p ≤ 5%, that is, the range exceeding 0% and being 5% or less). From this perspective, t = 10 μm or less is more preferable, and t = 5 μm or less is even more preferable.

[0096] Also, based on FIGS. 22 to 24, when obtaining the relationships of X, Y, t, and p, the following equations (11) to (13) are obtained.

[0097] X < Y < AX + B ···(11)

[0098] A = (0.3t 2 −8.7t + 78)p / 100 + 1 ···(12)

[0099] B = (−0.2t + 10)p / 100 ···(13)

[0100] The boundaries of the impedance change rate p obtained by the above equations are shown in FIGS. 22 to 24 as thick straight lines. The thick straight lines showing the calculation results in these figures and the thin curves showing the results obtained by simulation are in good agreement. Therefore, for the above equations (11) to (13), by substituting the thickness t of the adhesive layer 13 and the desired impedance change rate p for calculation, the ranges of the relative permittivity X of the adhesive layer 13 and the relative permittivity Y of the dielectric layer 12 can be obtained. Thereby, by suppressing the impedance change rate, it can be reused without changing the existing design.

[0101] FIG. 25 is a diagram showing the relationship among the impedance change rate, signal delay, and ease of application to an existing design when the relative permittivity of the main base material constituting the dielectric layer 12 is set to 3 or 5 and the relative permittivity of the primer constituting the adhesive layer 13 is changed in FIG. 21. In FIG. 25, “Example” shows the results according to the fourth embodiment of the present invention, and “Comparative Example” shows an embodiment different from the fourth embodiment.

[0102] As shown in FIG. 25, in the “Examples” that satisfy formulas (11) to (13), there is no signal delay, and the ease of application to an existing design is such that the impedance change rate is “3.5 to 5%”, indicated by “〇” showing that the circuit pattern designed for a conventional printed circuit board can be applied; the impedance change rate is “2.5 to 3.5%”, indicated by “◎” showing that it is easy to apply the circuit pattern designed for a conventional printed circuit board; the impedance change rate is “2 to 2.5%”, indicated by “◎◎” showing that it is even easier to apply the circuit pattern designed for a conventional printed circuit board; and the impedance change rate is “~2%”, indicated by “◎◎◎” showing that it is particularly easy to apply the circuit pattern designed for a conventional printed circuit board.

[0103] On the other hand, in the comparative example, for example, in the case of sample number “1079”, the relative permittivity Y of the main base material is 3, while the relative permittivity X of the primer is 3.5, so X < Y is not satisfied. In this case, although the ease of application to an existing design is “◎◎◎”, there is a signal delay, which is not preferable.

[0104] Also, for sample numbers "1164" to "1170", although X < Y is satisfied, X < Y < AX + B is not satisfied. So, there is no signal delay, but the ease of application to existing designs is as follows: when the impedance change rate is "5 - 7.5%", it is indicated by "△" that it is difficult to apply the circuit pattern designed for conventional printed boards; when the impedance change rate is "7.5 - 10%", it is indicated by "×" that it is difficult to apply the circuit pattern designed for conventional printed boards; when the impedance change rate is "10% -", it is indicated by "××" that it is particularly difficult to apply the circuit pattern designed for conventional printed boards. Therefore, for these, since it is difficult to apply to existing designs, there is a high possibility that re - design will be required.

[0105] As described above, in the fourth embodiment of the present invention, in the configuration shown in FIG. 21, when the relative permittivity of the primer constituting the adhesive layer 13 is X, the permittivity of the dielectric constituting the dielectric layer 12 is Y, the thickness of the adhesive layer 13 is t, and the impedance change rate is p, by selecting the members so that X, Y, p satisfy the above - mentioned formulas (11) to (13), the impedance change rate p can be kept within a desired range. Therefore, when using the conductor layer 14 with good high - frequency characteristics and an Rz value of 1 μm or less, it is necessary to use the adhesive layer 13 to increase the bonding strength. Even in such a case, by selecting materials so as to satisfy the above - mentioned formulas (11) to (13), the conventional circuit pattern can be diverted without design changes.

[0106] Next, the method for actually measuring the line impedance will be described.

[0107] In this embodiment, in order to measure the transmission line impedance, a measurement substrate 10A having a transmission line pattern with an adhesive layer having the layer configuration shown in Figure 26, and a measurement substrate 10B having the same transmission line pattern without an adhesive layer, as shown in Figure 27, are prepared. In the configuration shown in Figure 26, the thickness of the adhesive layers 13, 31, and 32 is t μm, and the thickness of the adhesive layers 13, 31, and 32 and the dielectric layers 12 and 15 is 318 μm. In the configuration shown in Figure 27, the thickness of the dielectric layers 12 and 15 is also 318 μm.

[0108] As shown in Figure 28, patterns for inputting and outputting signals from connectors 61 and 62 are provided at both ends of the lines formed on the measurement boards 10A and 10B. Signals are input to the measurement boards 10A and 10B from the vector network analyzer 50 via connectors 61 and 62 and cables 51 and 52, and the frequency is swept to an arbitrary range to measure the frequency characteristics of the reflection loss of the measurement boards 10A and 10B.

[0109] In the vector network analyzer 50, a step signal is convolved onto the data measured in the frequency domain, and an inverse Fourier transform is performed to obtain a graph of the reflection coefficient, which is the step response data in the time domain. In this embodiment, a Keysight Technologies E8364C is used as the vector network analyzer 50 for the measurement of the transmission line impedance. Furthermore, by setting the reference impedance to the port impedance of the vector network analyzer 50, the impedance is calculated from the reflection coefficient, and a graph is obtained, as shown in Figure 29, where the horizontal axis represents time and the vertical axis represents impedance.

[0110] In the graph shown in Figure 29, there is a flat region and peaks at both ends of it that indicate impedance mismatch between connectors 61 and 62 and the substrate contact area. These two peaks can be considered as corresponding peaks to the line ends, and the area inside these peaks can be considered as the region corresponding to the line. In this measurement, the impedance of the substrate can be determined by averaging the values ​​within a 5% interval between the peaks corresponding to the two line ends, from the center of both line ends to the front and back.

[0111] Figure 29 shows the measured results for a substrate using a dielectric layer 12 with a relative permittivity Y=3.6, an adhesive layer 13 with a relative permittivity X=2.2, and a thickness of 15 μm for the adhesive layer 13. The change in impedance with and without the adhesive layer is approximately 4.9% (=(50.6-48.2) / 48.2×100). The relative permittivity Y of the dielectric layer 12 and the relative permittivity X of the adhesive layer 13 can be measured in accordance with the Japanese Industrial Standard JIS C2138:2007. Figure 30 shows the simulation results for a measurement substrate 10A with a line pattern having an adhesive layer and the layer configuration shown in Figure 26, when the thickness of the adhesive layer 13 is set to 15 μm. More specifically, Figure 30 shows the results when the thickness of the adhesive layer 13 is 15 μm, and the squares in the figure indicate the characteristics when X=2.2 and Y=3.6. The measured results fall within the range of these squares in the figure. Note that the relative permittivity X of the adhesive layer 13 and the relative permittivity Y of the dielectric layer 12 may change depending on the frequency of the input signal. Therefore, although the measurement results are represented by a rectangular area in Figure 30, the values ​​of X and Y may be the respective relative permittivity at a typical frequency (e.g., median or average) within the frequency band of the input signal. In this measurement and simulation, a 10 GHz signal was used.

[0112] Next, we will explain how to measure the thickness of the adhesive layer.

[0113] Figure 31 shows a cross-section of a sample consisting of a resin layer and copper foil. In the example in Figure 31, the substrate sample is processed into small pieces using an ultramicrotome or the like, the observation surface is treated by ion milling, and then an SEM (Scanning Electron Microscope) image is taken. When the resin layer is separated into layers that do not contain filler material or regions of different colors, the layer closest to the copper foil can be defined as the adhesive layer and its thickness can be measured.

[0114] (D) Description of modified embodiments The embodiments described above are merely examples, and it goes without saying that the present invention is not limited to the cases described above. For example, in the embodiments described above, 1 Dielectric layer 12 and 1 Adhesive layer 13 Each Relative permittivity Y, X Although specific examples are not shown, one could, for instance, use a material where X=2.5 and Y=3.6.

[0115] Figures 32 to 34 show the second embodiment. First adhesive layer 13 Assuming relative permittivity X = 2.5 glue Using First dielectric layer 12 Assuming relative permittivity Y = 3.6 Dielectrics The simulation results for setting the thickness of the adhesive layer 13 to 15, 10, and 5 μm are shown. More specifically, Figure 32 shows the results when the thickness of the adhesive layer 13 is 15 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 32, the impedance change rate is 4.2%. Figure 33 shows the results when the thickness of the adhesive layer 13 is 10 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 33, the impedance change rate is 3.0%. Furthermore, Figure 34 shows the results when the thickness of the adhesive layer 13 is 5 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 34, the impedance change rate is 2.2%.

[0116] Figures 35 to 37 show the third embodiment. First adhesive layer 13 Assuming relative permittivity X = 2.5 glue Using First dielectric layer 12 Assuming relative permittivity Y = 3.6 DielectricsThe simulation results for setting the thickness of the adhesive layer 13 to 15, 10, and 5 μm are shown. More specifically, Figure 35 shows the results when the thickness of the adhesive layer 13 is 15 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 35, the impedance change rate is 1.9%. Figure 36 shows the results when the thickness of the adhesive layer 13 is 10 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 36, the impedance change rate is 1.2%. Furthermore, Figure 37 shows the results when the thickness of the adhesive layer 13 is 5 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 37, the impedance change rate is 0.2%.

[0117] Figures 38 to 40 show the fourth embodiment. First adhesive layer 13 Assuming relative permittivity X = 2.5 glue Using First dielectric layer 12 Assuming relative permittivity Y = 3.6 Dielectrics The simulation results for setting the thickness of the adhesive layer 13 to 15, 10, and 5 μm are shown. More specifically, Figure 38 shows the results when the thickness of the adhesive layer 13 is 15 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 38, the impedance change rate is 2.5%. Figure 39 shows the results when the thickness of the adhesive layer 13 is 10 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 39, the impedance change rate is 1.3%. Furthermore, Figure 40 shows the results when the thickness of the adhesive layer 13 is 5 μm, and the circles in the figure indicate the characteristics when X=2.5, Y=3.6. In the example of Figure 40, the impedance change rate is 0.5%.

[0118] From the above, in both microstrip and strip tracks, First adhesive layer 13 As an example, use an adhesive with a relative permittivity X = 2.5. First dielectric layer 12 Assuming relative permittivity Y = 3.6 DielectricsBy using this method and setting the thickness of the adhesive layer 13 to 15, 10, and 5 μm, the impedance change rate falls within the range of 0.2 to 4.2%. Therefore, depending on the material selection described above, it is possible to achieve an impedance change rate that does not require any design changes. In the above example, X=2.5 and Y=3.6 were used, but a material with a dielectric constant within a predetermined range centered around these values ​​may be used. For example, X could be set to 2.25 or more and 2.75 or less, and Y to 3.35 or more and 3.85 or less.

[0119] In the first embodiment, there is one dielectric layer 12 and two conductive layers (ground layer 11 and conductive layer 14), and in the third and fourth embodiments, there are two dielectric layers 12, 15 and three conductive layers (ground layers 11, 16 and conductive layer 14). However, the number of dielectric layers and conductive layers may be set to any other number.

[0120] Furthermore, in each of the above embodiments, the thickness t of the adhesive layer 13 was set to 5 ≤ t ≤ 15, but it may be set to t < 5 if necessary.

[0121] Furthermore, in each of the above embodiments, the relative permittivity was adjusted by selecting the materials of the dielectric layers 12, 15 and the adhesive layer 13. However, the relative permittivity may also be adjusted by their shapes, for example. For example, the relative permittivity may be adjusted by providing a plurality of air holes.

[0122] Furthermore, since equations (1) to (16) above are approximations, the constants included in them are merely examples and not limiting. Also, it is expected that these constants will vary to some extent depending on the environment, etc., and therefore have a certain range. [Explanation of symbols]

[0123] 10 Printed circuit boards 11 Ground Layer 12 Dielectric layer 13 Adhesive layer 14 Conductor layer 15 Dielectric layer 16 Ground Layer

Claims

1. In a printed circuit board constructed by stacking one dielectric layer and two conductive layers, The aforementioned dielectric layer is the first dielectric layer, The material of the first dielectric layer is an epoxy resin, a polyamide-imide resin, a fluororesin, a polyimide resin, a polyphenylene ether resin, or a Teflon® resin, or a glass fiber mixed resin obtained by mixing glass fibers with any of these resins. The two conductor layers are a first conductor layer laminated on one surface of the first dielectric layer via a first adhesive layer, and a second conductor layer directly laminated on the other surface of the first dielectric layer. When the relative permittivity of the first dielectric layer is Y, the relative permittivity of the first adhesive layer is X, the thickness of the first adhesive layer is t (μm), and the impedance change rate of the line formed in the first conductor layer compared to the case where t = 0 (μm) is p (%), The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t of the first adhesive layer (where 5 ≤ t ≤ 15), and the impedance change rate p satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.19t) ２ -5.25t+43.5)p / 100+1 (Relationship 3) B = (-0.8t + 22)p / 100 A printed circuit board characterized by the following features.

2. In a printed circuit board constructed by stacking two dielectric layers and three conductive layers, The two dielectric layers are a first dielectric layer and a second dielectric layer laminated on one side of the first dielectric layer with a first adhesive layer in between. The material of the first dielectric layer is an epoxy resin, a polyamide-imide resin, a fluororesin, a polyimide resin, a polyphenylene ether resin, or a Teflon® resin, or a glass fiber mixed resin obtained by mixing glass fibers with any of these resins. The three conductor layers are: a first conductor layer laminated between one surface of the first dielectric layer and the second dielectric layer via the first adhesive layer; a second conductor layer directly laminated on the other surface of the first dielectric layer; and a third conductor layer directly laminated on the surface of the second dielectric layer opposite to the surface facing the first conductor layer. When the relative permittivity of the first dielectric layer is Y, the relative permittivity of the first adhesive layer is X, the thickness of the first adhesive layer is t (μm), and the impedance change rate of the line formed in the first conductor layer compared to the case where t = 0 (μm) is p (%), The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t of the first adhesive layer (where 5 ≤ t ≤ 15), and the impedance change rate p satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.44t) ２ -12.8t+108)p / 100+1 (Relational expression 3) B=(-0.2t+26)p / 100 A printed circuit board characterized by the following features.

3. In a printed circuit board constructed by stacking two dielectric layers and three conductive layers, The two dielectric layers are a first dielectric layer and a second dielectric layer laminated on one side of the first dielectric layer with a first adhesive layer in between. The material of the first dielectric layer is an epoxy resin, a polyamide-imide resin, a fluororesin, a polyimide resin, a polyphenylene ether resin, or a Teflon® resin, or a glass fiber mixed resin obtained by mixing glass fibers with any of these resins. The three conductor layers are: a first conductor layer laminated between one surface of the first dielectric layer and the second dielectric layer via the first adhesive layer; a second conductor layer laminated on the other surface of the first dielectric layer; and a third conductor layer laminated on the surface of the second dielectric layer opposite to the surface facing the first conductor layer. A second adhesive layer is provided between the first dielectric layer and the second conductor layer. A third adhesive layer is provided between the second dielectric layer and the third conductive layer. When the relative permittivity of the first dielectric layer is Y, the relative permittivity of the first adhesive layer is X, the thickness of the first adhesive layer is t (μm), and the impedance change rate of the line formed in the first conductor layer compared to the case where t = 0 (μm) is p (%), The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t of the first adhesive layer (where 5 ≤ t ≤ 15), and the impedance change rate p satisfy the following relational expressions 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.3t) ２ -8.7t+78)p / 100+1 (Relational expression 3) B=(-0.2t+10)p / 100 A printed circuit board characterized by the following features.

4. The printed circuit board according to any one of claims 1 to 3, characterized in that the impedance change rate p is 3.5% or less.

5. The printed circuit board according to any one of claims 1 to 3, characterized in that the impedance change rate p is 2.5% or less.

6. The printed circuit board according to any one of claims 1 to 3, characterized in that the impedance change rate p is 2.0% or less.

7. The printed circuit board according to any one of claims 1 to 6, characterized in that the t (μm) is 15 (μm) or less.

8. The printed circuit board according to any one of claims 1 to 6, characterized in that the t (μm) is 10 (μm) or less.

9. The printed circuit board according to any one of claims 1 to 8, characterized in that the Rz value indicating the surface roughness of the first conductor layer is 1 μm or less.

10. The printed circuit board according to any one of claims 1 to 9, characterized in that the relative permittivity Y of the first dielectric layer is 3.35 or more and 3.85 or less, and the relative permittivity X of the first adhesive layer is 2.25 or more and 2.75 or less.

11. In a method for manufacturing a printed circuit board comprising at least one dielectric layer and at least two conductive layers stacked together, A first conductor layer, which is one of the at least one dielectric layers, is laminated on one surface of a first dielectric layer, which is one of the at least two conductor layers, via a first adhesive layer, and a second conductor layer, which is the other of the at least two conductor layers, is laminated on the other surface of the first dielectric layer, either directly or via a second adhesive layer. When the relative permittivity of the first dielectric layer is Y, the relative permittivity of the first adhesive layer is X, the thickness of the first adhesive layer is t (μm), and the impedance change rate of the line formed in the first conductor layer compared to the case where t = 0 (μm) is p, X < Y < AX + B (where A and B are constants in the approximate formula Y = AX + B, which is derived from simulation results using an electromagnetic field simulator employing the finite element method, with the relative permittivity Y and the relative permittivity X as variables, such that the impedance change rate p obtained from the simulation results is 5%. This formula is obtained by substituting the numerical values ​​of the thickness t and the impedance change rate p (where p is 5% or less) into the approximate formula which includes the thickness t and the impedance change rate p as variables.) That is, A method for manufacturing a printed circuit board, characterized in that the impedance change rate p is in the range of 0% < p ≤ 5% by selecting the first dielectric layer and the first adhesive layer such that the relative permittivity X of the first adhesive layer is smaller than the relative permittivity Y of the first dielectric layer, and the relative permittivity Y of the first dielectric layer is smaller than the value obtained when the relative permittivity X of the first adhesive layer is substituted into AX + B in the relational expression.

12. In a method for manufacturing a printed circuit board, in which one dielectric layer and two conductive layers are stacked, The one dielectric layer is the first dielectric layer, and the two conductor layers are the first conductor layer laminated on one surface of the first dielectric layer via the first adhesive layer, and the second conductor layer directly laminated on the other surface of the first dielectric layer. The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t (μm) of the first adhesive layer, and the impedance change rate p satisfy the following relational equations 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.19t) ２ -5.25t+43.5)p / 100+1 (Relationship 3) B = (-0.8t + 22)p / 100 The method for manufacturing a printed circuit board according to feature 11.

13. In a method for manufacturing a printed circuit board, in which two dielectric layers and three conductive layers are stacked, The two dielectric layers are the first dielectric layer and the second dielectric layer which is laminated on one side of the first dielectric layer with the first adhesive layer and the first conductor layer in between. The three conductive layers are a third conductive layer directly laminated on the surface of the first conductive layer, the second conductive layer, and the second dielectric layer opposite to the surface facing the first conductive layer. The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t (μm) of the first adhesive layer, and the impedance change rate p satisfy the following relational equations 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.44t) ２ -12.8t+108)p / 100+1 (Relational expression 3) B=(-0.2t+26)p / 100 The method for manufacturing a printed circuit board according to feature 11.

14. In a method for manufacturing a printed circuit board, in which two dielectric layers and three conductive layers are stacked, The two dielectric layers are the first dielectric layer and the second dielectric layer which is laminated on one side of the first dielectric layer with the first adhesive layer and the first conductor layer in between. The three conductive layers are a third conductive layer laminated on the surface of the first conductive layer, the second conductive layer, and the second dielectric layer opposite to the surface facing the first conductive layer. A second adhesive layer is provided between the first dielectric layer and the second conductor layer. A third adhesive layer is provided between the second dielectric layer and the third conductive layer. The relative permittivity Y of the first dielectric layer, the relative permittivity X of the first adhesive layer, the thickness t (μm) of the first adhesive layer, and the impedance change rate p satisfy the following relational equations 1 to 3, and the impedance change rate p satisfies 0% < p ≤ 5%. (Relationship 1) X < Y < AX + B (Relationship 2) A = (0.3t) ２ -8.7t+78)p / 100+1 (Relational expression 3) B=(-0.2t+10)p / 100 The method for manufacturing a printed circuit board according to feature 11.

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