Semiconductor devices and power converters

Abstract

This semiconductor device includes: a gate voltage control circuit that applies on-bias and off-bias to a gate terminal of a power semiconductor element in accordance with a first drive signal; and an off-bias voltage control circuit that changes a voltage level of the off-bias in accordance with the first drive signal and a second drive signal and controls an application period of the changed off-bias.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and to the drive of a power semiconductor device.

Background Art

[0002] One of the problems related to the reliability of power semiconductor devices is gate false arcing. When gate false arcing occurs, the high-voltage side power supply on the upper arm side of the faulty phase and the low-voltage side power supply on the lower arm side in a power inverter are short-circuited. As a result, a large short-circuit current flows between the power supplies, causing an increase in the losses of the inverter device, and in the worst case, it may lead to thermal runaway.

[0003] As a countermeasure against gate false arcing, a method of applying a negative bias between the gate and source of a power semiconductor device is widely known. Gate false arcing is caused by displacement current generated during the turn-on operation of a power semiconductor device on the opposite arm side. Since this displacement current is proportional to the voltage change rate of the power conversion device on the opposite arm side, the displacement current increases as the switching speed increases, and as a result, false arcing of the switching side device is more likely to occur. Here, if a negative bias is applied at the timing of false arcing, the short-circuit between the upper and lower arm devices can be avoided without exceeding the gate threshold voltage, and the greater the negative bias, the greater the effect of preventing false arcing.

[0004] On the other hand, when applying a negative bias between the gate and source, conventionally, the gate is driven to always apply a negative bias during the off operation of the power semiconductor device. When the application time of such a negative bias is long, stress is applied to the gate oxide film of the power semiconductor device. Among reports on metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) using silicon nitride as a material, it has been reported that when the stress on the gate oxide film increases, it causes deterioration of the characteristics and failure of the power semiconductor device. As a result, it also leads to a decrease in the reliability of the entire power inverter system. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2013-219874 [Non-patent literature]

[0006] [Non-Patent Document 1] Andreas Marz, and 3 others, “Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules”, EPE, 2017. [Overview of the project] [Problems that the invention aims to solve]

[0007] Patent Document 1 describes a power semiconductor element that has two voltages applied to its gate terminal: a first voltage and a second voltage at a lower voltage level than the first voltage. The power semiconductor element's turn-off operation is performed using the first voltage, but the first voltage is generally not higher than the negative bias applied to the gate terminal. In other words, the switching loss of the power semiconductor element increases compared to when the second voltage is used. On the other hand, increasing the first voltage improves the switching loss by speeding up the turn-on operation, but a negative bias with a higher voltage than the first voltage (e.g., the second voltage) must be continuously applied to the gate until the turn-on operation of the power semiconductor element on the opposing arm is completed, including the dead time after the turn-off operation. Therefore, the aforementioned problem of stress on the gate oxide film arises, and the reliability of the entire power converter decreases, creating a dilemma.

[0008] In the case of Non-Patent Literature 1, a negative bias is applied to the gate terminal of the arm element from the start of the turn-off operation of the power semiconductor element to the end of the turn-on operation of the power semiconductor element on the opposing arm side. In other words, a negative bias is continuously applied to the gate terminal of the arm element during the dead time period and the switching period. Therefore, in systems with a large set value for the dead time, there is a concern that the effect of reducing stress on the gate oxide film may be insufficient.

[0009] This disclosure aims to solve the above-mentioned problems and to provide a semiconductor device and a power converter that can improve the reliability of power semiconductor elements. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment includes a gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a first drive signal, and an off-bias voltage control circuit that changes the voltage level of the off-bias according to the first drive signal and the second drive signal, and controls the application period of the changed off-bias.

[0011] A power converter according to one embodiment includes a first power semiconductor element, a second power semiconductor element provided on the opposing arm side connected in series with the first power semiconductor element, and first and second gate drive circuits provided corresponding to the first and second power semiconductor elements, respectively, for driving the corresponding power semiconductor elements according to first and second drive signals. Each gate drive circuit includes a gate voltage control circuit that applies on-bias and off-bias to the gate terminal of the power semiconductor element according to the corresponding drive signal, and an off-bias voltage control circuit that changes the voltage level of the off-bias according to the first and second drive signals and controls the application period of the changed off-bias. [Effects of the Invention]

[0012] Semiconductor devices and power converters according to this disclosure can improve the reliability of power semiconductor elements.

Brief Description of the Drawings

[0013] [Figure 1] It is a block diagram for explaining the function of the gate drive circuit 100 of the semiconductor device for power use according to Embodiment 1. [Figure 2] It is a diagram for explaining the specific configurations of the first control circuit 21 and the second control circuit 31 according to Embodiment 1. [Figure 3] It is a diagram for explaining the timing chart when the gate drive circuit 100 according to Embodiment 1 controls the gate of the semiconductor element 10 for power use. [Figure 4] It is a diagram for explaining the gate drive circuit 101 according to Embodiment 2. [Figure 5] It is a diagram for explaining the timing chart when the gate drive circuit 101 according to Embodiment 2 controls the gate of the semiconductor element for power use. [Figure 6] It is a block diagram for explaining the function of the gate drive circuit 100# of the semiconductor device for power use according to Embodiment 3. [Figure 7] It is a diagram for explaining the specific configurations of the first control circuit 21# and the second control circuit 31# according to Embodiment 3. [Figure 8] It is a diagram for explaining the waveform of the gate voltage Vgs of the SiC-MOSFET to which the gate drive circuit 100 of the present disclosure is applied. [Figure 9] It is a diagram for explaining the timing chart when the gate drive circuit 101 according to Embodiment 5 controls the gate of the semiconductor element for power use. [Figure 10] It is a block diagram for explaining the function of the integrated drive circuit 102 according to Embodiment 6. [Figure 11] It is a block diagram showing the configuration of the power conversion system according to Embodiment 7.

Modes for Carrying Out the Invention

[0014] Embodiment 1. The gate drive circuit of a semiconductor device for power, which is an example of the present disclosure, will be described below.

[0015] FIG. 1 is a block diagram for explaining the function of a gate drive circuit 100 according to Embodiment 1.

[0016] Referring to FIG. 1, the gate drive circuit 100 controls the gate of a power semiconductor device 10 connected between DC high-voltage power supplies in accordance with the input of an external drive signal IN1 and an external drive signal IN2. Specifically, the gate drive circuit 100 controls a so-called switching operation for switching the on / off operation of the power semiconductor device 10.

[0017] The power semiconductor device 10 corresponds to a main circuit switching element in an inverter circuit of a power conversion device. For example, it is one element of a 2-in-1 half-bridge circuit, a 4-in-1 full-bridge circuit, or a 6-in-1 three-phase inverter. Since these circuit configurations generate an inverter output voltage by PWM control, a high voltage of several hundred V or more is applied between the drain and source of an element during the off operation. Also, a large current corresponding to the system of the power conversion device flows through the element during the on operation. These operating states are controlled by a gate voltage that turns on and off the power semiconductor device 10 in accordance with the external drive signal IN1.

[0018] The gate drive circuit 100 includes a gate voltage control circuit 20 and an off-bias voltage control circuit 30.

[0019] The gate voltage control circuit 20 controls the on-bias and off-bias of the gate of the power semiconductor device 10.

[0020] The gate voltage control circuit 20 includes a first control circuit 21 and a first switching circuit 22. The first control circuit 21 controls the gate control signal so that the power semiconductor element 10 performs the desired switching operation in response to the input external drive signal IN1. Specifically, the gate control signal is set to "1" during the period when the power semiconductor element 10 should be ON, and the gate control signal is set to "0" during the period when the power semiconductor element 10 should be OFF. These binary voltage signals can be generated by generating pulse waveforms using communication signal sources such as the 5V system and 3.3V system of the logic circuit.

[0021] The first switching circuit 22 is positioned between the gate of the power semiconductor element 10 and the first control circuit 21. The high side of the first switching circuit 22 is connected to the positive voltage source Vdd, and the low side is connected to the second switching circuit 32.

[0022] The first switching circuit 22 includes an NPN transistor 22A, a PNP transistor 22B, and a resistor 22C.

[0023] NPN transistor 22A and PNP transistor 22B are connected in series. NPN transistor 22A is connected to the positive voltage source Vdd and to the output node.

[0024] The PNP transistor 22B is connected to the output node and to the output node of the second switching circuit 32.

[0025] The gates of the NPN transistor 22A and the PNP transistor 22B are connected to the first control circuit 21 via the resistor element 22C.

[0026] The first switching circuit 22 can switch the current path according to the gate control signal output from the first control circuit 21. This changes the path through which the gate current of the power semiconductor element 10 flows, which is equivalent to switching between charging and discharging the gate. Therefore, the first switching circuit 22 switches the gate voltage applied to the gate of the power semiconductor element 10 and controls the on / off operation of the power semiconductor element 10.

[0027] The off-bias voltage control circuit 30 controls the level of off-bias applied to the gate during the off-operation of the power semiconductor element 10 according to the external drive signals IN1 and IN2. Specifically, since the off-bias voltage control circuit 30 controls the voltage level during the off-operation of the power semiconductor element 10, a positive value could exceed the gate threshold voltage of the power semiconductor element 10, so it is always set to be 0V or less.

[0028] Furthermore, the number of off-bias level switches is set to two as an example. In this embodiment, external drive signals IN1 and IN2 are used to switch between the two off-bias levels. External drive signal IN1 is the same as the input signal to the first control circuit 21. External drive signal IN2 is necessary to provide the gate drive circuit 100 with timing information for the gate misfire (also called the self-turn-on phenomenon) of the power semiconductor element 10, which will be described later. External drive signal IN2 is provided by a means separate from external drive signal IN1.

[0029] The off-bias voltage control circuit 30 includes a second control circuit 31 and a second switching circuit 32. The second control circuit 31 outputs an off-bias voltage control signal that allows arbitrary adjustment of the off-bias voltage level and off-bias application period applied to the gate of the power semiconductor element 10 based on the inputs of external drive signals IN1 and IN2. The specific method will be described later.

[0030] The second switching circuit 32 is connected to the second control circuit 31, the first switching circuit 22, and the source electrode of the power semiconductor element 10.

[0031] The high side of the second switching circuit 32 is connected to the source electrode of the power semiconductor element 10, and the low side is connected to the negative voltage source Vneg.

[0032] The second switching circuit 32 includes an NPN transistor 32A, a PNP transistor 32B, and a resistor 32C.

[0033] NPN transistor 32A and PNP transistor 32B are connected in series. The NPN transistor 32A is connected to the source electrode of the power semiconductor element 10 and to the output node. The output node is connected to the first switching circuit 22.

[0034] The PNP transistor 32B is connected to the output node and the negative voltage source Vneg. The gates of the NPN transistor 32A and the PNP transistor 32B are connected to the second control circuit 31 via the resistor element 32C.

[0035] The second switching circuit 32 switches the gate off-bias level in accordance with the off-bias voltage control signal generated by the second control circuit 31. Specifically, it switches between a reference potential Vs, which is based on the source potential of the power semiconductor element 10, and a negative voltage source Vneg. That is, by switching the source potential of the power semiconductor element 10, the off-bias level applied to the gate of the power semiconductor element 10 is switched.

[0036] Hereafter, the state with the reference potential Vs connected will also be referred to as "shallow off-bias," and the state with the negative voltage source Vneg connected will be referred to as "deep off-bias," as needed.

[0037] However, the shallow off-bias and deep off-bias applied to the gate of the power semiconductor element 10 are contingent on the power semiconductor element 10 being in the off-operation state. Therefore, the operation of the second switching circuit 32 alone does not uniquely determine the off-bias; rather, the first switching circuit 22 switches between the shallow off-bias and deep off-bias applied to the gate of the power semiconductor element 10 only during the period when the power semiconductor element 10 is in the off-operation state. In other words, the off-bias level applied to the gate of the power semiconductor element 10 is controlled based on the state of the gate voltage control circuit 20 and the off-bias voltage control circuit 30.

[0038] The components not shown, namely the first control circuit 21 and the second control circuit 31, may consist of passive elements such as resistors, capacitors, and diodes, and RC filters. A Schmitt trigger element may also be included to regulate the transmitted signal. The first control circuit 21 includes a delay line (which can be implemented with a delay IC or buffer circuit) to delay the transmitted signal for a certain period of time, and the second control circuit 31 includes a logic operation circuit that performs logical operations such as logical OR and logical AND of the transmitted signal.

[0039] Furthermore, although not shown, the first switching circuit 22 and the second switching circuit 32 are totem-pole circuit structures with switching elements arranged on the upper and lower arms, and it is sufficient if the output can be controlled in two stages according to the input gate control signal. Specifically, they may be configured as push-pull circuits in which the high-side element is an NPN transistor and the low-side element is a PNP transistor, as described above, or other configurations may be adopted.

[0040] Figure 2 is a diagram illustrating the specific configurations of the first control circuit 21 and the second control circuit 31 according to Embodiment 1.

[0041] Referring to Figure 2, the first control circuit 21 includes a control unit 21A and a delay circuit 21B. The control unit 21A receives the external drive signal IN1 as an input signal and is responsible for generating a regulated signal. For example, this can be achieved using a capacitor for voltage retention, a diode element for preventing reverse conduction, and a Schmitt trigger element for regulating the transmitted signal.

[0042] The delay circuit 21B receives the output signal from the control unit 21A, delays that output signal for a certain amount of time, and generates a delayed signal. For example, it can be a delay line that delays the transmitted signal for a certain period of time, and that delay line can be made up of a logic IC or a buffer element.

[0043] By configuring the first control circuit 21 in this way, the gate control signal input to the first switching circuit 22 shown in Figure 1 is delayed by a certain amount of time relative to the external drive signal IN1. Depending on the delay amount of the gate control signal, the operation of the first switching circuit 22 can also be delayed by the same amount of time. Therefore, the timing of the switching operation of the power semiconductor element 10 is also delayed by the same amount of time overall. Furthermore, the gate delay amount of the power semiconductor element 10 can be set to be variable by having multiple terminals per logic IC or buffer element that constitute the delay line, setting the delay amounts of the logic IC and buffer element separately, or switching the connection destination of the circuit using jumper pins.

[0044] The second control circuit 31 includes delay circuits 31A and 31B, inverters IV0 and IV1, AND circuits AD0 and AD1, and a NOR circuit NR.

[0045] The AND circuit AD0 receives the external drive signal IN1 via the delay circuit 31A and the external drive signal IN1 via the inverter IV0, and outputs the result of the AND logic operation to the NOR circuit NR.

[0046] The AND circuit AD1 receives the external drive signal IN2 via the delay circuit 31B and inverter IV1, and outputs the result of the AND logic operation to the NOR circuit NR.

[0047] The NOR circuit NR receives inputs from AND circuits AD0 and AD1 and outputs the result of the NOR logic operation.

[0048] Delay circuits 31A and 31B are delay circuits that generate delayed signals. For example, they can be composed of RC filters, which are common delay time adjustment circuits, and it is even better if they are equipped with Schmitt trigger elements to adjust the transmitted signal. The delay amounts of delay circuits 31A and 31B can be adjusted to be different.

[0049] A NOR gate (NR) typically outputs an off-bias voltage control signal ("1"). As a result, the NPN transistor 32A of the second switching circuit 32 is turned ON.

[0050] Meanwhile, as the external drive signal IN1 changes from "1" to "0", the AND circuit AD0 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31A. In response to this, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the duration of the one-shot pulse signal.

[0051] Furthermore, as the external drive signal IN2 changes from "0" to "1", the AND circuit AD1 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31B. In response to this, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the duration of the one-shot pulse signal.

[0052] The second control circuit 31 is a logic circuit that receives two external drive signals, IN1 and IN2, performs logical operations such as logical OR and logical AND on these two signals, and generates a single off-bias voltage control signal from the two output signals. For example, it may be composed of a discrete IC element with only one built-in element, or it may be composed of a 2-in-1 logic IC with two logic functions. It may also be configured to have at least one AND element and at least one OR element for performing logical operations.

[0053] By providing delay circuits 31A and 31B, it is possible to generate off-bias voltage control signals according to external drive signals IN1 and IN2, and to adjust the timing of these signals.

[0054] Specifically, it is possible to determine the application timing and duration of the deep off-bias Vneg applied to the gate of the power semiconductor element 10 according to the delay amount of the delay circuits 31A and 31B. In addition, the resistors and capacitors of the RC filters of the delay circuits 31A and 31B may be composed of variable resistors and variable capacitances. With such a configuration, it becomes possible to variably set the application timing and duration of the deep off-bias Vneg applied to the power semiconductor element 10.

[0055] According to Embodiment 1, the gate voltage control circuit 20 includes a control unit 21A and a delay circuit 21B inside the first control circuit 21, and the off-bias voltage control circuit 30 includes delay circuits 31A and 31B inside the second control circuit 31, thereby enabling the generation of an appropriate off-bias level control signal, and allowing the application timing and duration of a deep off-bias Vneg to the power semiconductor element 10 to be determined. As a result, the reliability of the power semiconductor element 10 is improved.

[0056] Next, the specific operation of the gate drive circuit 100 according to Embodiment 1 will be described. Figure 3 illustrates the timing chart when the gate drive circuit 100 according to Embodiment 1 controls the gate of the power semiconductor element 10.

[0057] Referring to Figure 3, the differences in operation between the gate drive circuit 100 according to Embodiment 1 and the comparative example are shown. The horizontal axis represents time, and the vertical axis represents the external drive signal IN1, the external drive signal IN2, and the gate voltage Vgs of the power semiconductor element 10, respectively.

[0058] At time t0, as the external drive signal IN1 changes from "1" to "0", the gate drive circuit 100 begins to discharge the gate of the power semiconductor element 10. That is, the power semiconductor element 10 turns off. As the gate charge accumulated during the ON operation is withdrawn, the gate voltage Vgs of the power semiconductor element begins to drop.

[0059] First, the gate voltage Vgs drops sharply from the on-bias voltage Vdd. Next, as the drain-source voltage Vds (not shown) of the power semiconductor element 10 begins to rise, the gate voltage Vgs maintains a certain voltage value. This period is called the Miller period and continues until the change in gate-drain parasitic capacitance dependent on the drain-source voltage Vds disappears (generally, in the case of SiC-MOSFETs, the Miller period is very short). After the end of the Miller period, the gate voltage Vgs begins to fall again, and the turn-off operation ends when it reaches a deep off-bias Vneg. Here, there is a significant difference between the gate drive circuit according to Embodiment 1 and the comparative example (here, the configuration according to Patent Document 1).

[0060] The biggest difference is the presence or absence of a deep off-bias Vneg. The gate drive circuit 100 according to Embodiment 1 has a function to apply a deep off-bias Vneg to the gate, which increases the turn-off speed of the power semiconductor element 10 compared to the case without the deep off-bias application function according to the Comparative Example. In the interval from time t0 to the start of the Miller period and from the end of the Miller period to the end of the turn-off operation, the absolute value of the rate of change of the gate voltage Vgs dVgs / dt is larger in the configuration according to Embodiment 1 than in the configuration according to the Comparative Example.

[0061] This effect makes it possible to improve the turn-off loss of the power semiconductor element 10, resulting in benefits such as reduced heat generation in the power converter and miniaturization of the cooler.

[0062] On the other hand, in the configuration following the comparative example, the turn-off operation is performed with a shallow off-bias Vs, raising concerns that the reduction in the turn-off loss of the power semiconductor element 10 is insufficient. Furthermore, there are differences in the behavior of the gate voltage Vgs after the turn-off operation is completed.

[0063] The configuration according to Embodiment 1 includes a deep off-bias Vneg, so the gate voltage Vgs drops from a shallow off-bias Vs to a deep off-bias Vneg.

[0064] In the gate drive circuit 100 according to Embodiment 1, the turn-off operation of the power semiconductor element 10 is completed at time t1 when the gate voltage Vgs reaches a deep off-bias Vneg.

[0065] According to the configuration of the gate drive circuit 100 in Embodiment 1, a deep off-bias Vneg is applied to the gate of the power semiconductor element 10 from time t1. This may cause characteristic degradation or failure due to stress on the gate oxide film, as mentioned above. However, the period from time t1 to time t2, when the deep off-bias Vneg begins to return to a shallow off-bias Vs, is sufficiently shorter than the dead time period Td (when both the upper and lower arms are in the off position) set in the inverter circuit of the power converter. In other words, the actual stress on the gate oxide film is very small. Therefore, high reliability of the power semiconductor element 10 can be ensured.

[0066] In this example, a deep off-bias Vneg is applied to the gate of the power semiconductor element 10 during the period from time t0 to time t2. This period is defined as the first period. Next, we will explain the period from time t2 onward.

[0067] During the dead time period Td, the gate voltage Vgs of the power semiconductor element 10 is set to a shallow off-bias Vs, and the external drive signals IN1 and IN2 are set to "0".

[0068] Here, the external drive signal IN2 has the function of indicating the timing of the gate misfire of the power semiconductor element 10, that is, the turn-on timing of the opposing arm element.

[0069] Therefore, at the end of the dead time period Td, the external drive signal IN2 changes from "0" to "1".

[0070] The gate drive circuit 100 determines that it is time for the opposing arm element of the power semiconductor element 10 to turn on according to the change in the external drive signal IN2, and changes the gate voltage Vgs of the power semiconductor element 10 again from a shallow off-bias Vs to a deep off-bias Vneg. Subsequently, as the opposing arm element turns on, the gate voltage Vgs of the power semiconductor element 10 rises from the deep off-bias Vneg. Here, by setting the value of the deep off-bias Vneg to be greater than the voltage value at which the gate voltage Vgs rises, the gate voltage Vgs will not exceed 0V. In other words, there is sufficient margin for the gate threshold voltage of the power semiconductor element 10.

[0071] Here, the period ton from time t3 to when the opposing arm element of the power semiconductor element 10 actually starts turning on coincides with the delay amount of the gate control signal to the opposing arm element. Since it takes time for the deep off-bias Vneg applied to the gate voltage Vgs of the power semiconductor element 10 to be established, a delay in the gate control signal to the opposing arm element is inserted. In this way, complete prevention of misfiring of the gate of the power semiconductor element 10 can be achieved.

[0072] At time t4, after the turn-on of the opposing arm element of the power semiconductor element 10 is complete, the gate voltage Vgs of the power semiconductor element 10 begins to return from a deep off-bias Vneg to a shallow off-bias Vs. In other words, the stress on the gate oxide film of the power semiconductor element 10 is very small. That is, a deep off-bias Vneg is applied to the gate of the power semiconductor element 10 during the period from time t3 to time t4. Here, the period from the end of the dead time period Td until a shallow off-bias is applied to the gate of the power semiconductor element 10 is defined as the second period. In other words, the period from time t3 to time t4 is included in the second period.

[0073] The gate drive circuit 100 according to Embodiment 1 improves switching losses by applying a deep off-bias to the power semiconductor element 10, while limiting the application time of the deep off-bias to limited intervals of the first and second periods, thereby improving the reliability of the power semiconductor element 10. This leads to a longer lifespan for the power semiconductor element and makes it possible to realize an economical power converter system.

[0074] Embodiment 2. In Embodiment 2, the operation of a gate drive circuit 101, which includes a gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22, will be described.

[0075] Figure 4 is a diagram illustrating a gate drive circuit 101 according to Embodiment 2. Referring to Figure 4, the gate drive circuit 101 differs from the gate drive circuit 100 according to Embodiment 1 in that it includes a gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22. The other configurations are the same, so a detailed explanation will not be repeated.

[0076] The gate resistor control circuit 40 includes a gate resistor 41 and a bypass switching element 42 connected in parallel across the gate resistor 41.

[0077] The gate resistor 41 adjusts the switching speed of the power semiconductor element 10, specifically the turn-on speed and the turn-off speed.

[0078] When the resistance value of the gate resistor 41 is large, the surge voltage of the drain-source voltage Vds and electromagnetic noise during switching can be reduced, but the switching loss increases. Conversely, when the resistance value of the gate resistor 41 is small, the relationship between the surge voltage of the drain-source voltage Vds, electromagnetic noise and switching loss is the opposite of that when the resistance value is large.

[0079] The bypass switching element 42 performs turn-on and turn-off operations in response to the ON / OFF command of the gate control signal. The bypass switching element 42 is connected in parallel with the gate resistor 41. After the bypass switching element 42 is turned on, the gate current flows through the bypass switching element 42, and after the turn-off operation, it flows through the gate resistor 41.

[0080] The timing for turning on the bypass switching element 42 according to Embodiment 2 and bypassing the gate resistor 41 is when switching the gate off-bias level between a deep off-bias Vneg and a shallow off-bias Vs.

[0081] Specifically, during the first period, the bypass switching element 42 remains in the off position until the turn-off operation of the power semiconductor element 10 is completed. From the point when the turn-off operation of the power semiconductor element 10 is completed and a deep off-bias Vneg is established, the bypass switching element 42 is turned on until it switches to a shallow off-bias Vs.

[0082] As an example, the bypass switching element 42 is turned ON during the period from time Tb1 to Tb2.

[0083] Similarly, the timing for turning off the bypass switching element 42 according to Embodiment 2 and switching to the path via the gate resistor 41 is from the time when the dead time period Td ends and the system switches from a shallow off-bias Vs to a deep off-bias Vneg in preparation for the turn-on operation of the opposing arm element, until the start of the turn-on operation of the opposing arm element.

[0084] Specifically, during the second period, the bypass switching element 42 remains in the ON position from the shallow off-bias Vs to the establishment of a deep off-bias Vneg, and is turned OFF before the opposing arm element turns ON.

[0085] As an example, the bypass switching element 42 is turned ON during the period from time T3 to Tb3.

[0086] By performing the operation of the bypass switching element 42 as described above, a bypass path that does not go through the gate resistor 41 is utilized only for switching between the deep off-bias Vneg and the shallow off-bias Vs applied to the gate of the power semiconductor element 10.

[0087] As described above, in Embodiment 1, the second switching circuit 32 operates in conjunction with the first switching circuit 22. In other words, the switching speed between deep off-bias Vneg and shallow off-bias Vs depends on the circuit constants of the discharge path of the power semiconductor element 10. In short, the larger the value of the gate resistor 41, the slower the switching speed between deep off-bias Vneg and shallow off-bias Vs becomes. Embodiment 2 makes it possible to speed up the switching speed between deep off-bias Vneg and shallow off-bias Vs by providing a bypass path that does not go through the gate resistor 41. In other words, it is possible to suitably control the level and timing of the off-bias applied to the gate of the power semiconductor element 10.

[0088] Furthermore, the gate resistor 41 is effective against gate misfires. If the gate resistor 41 is a small value (e.g., 0 ohms), vibrations due to the stray inductance component of the gate wiring of the power semiconductor element 10 may occur, potentially causing gate misfires. Also, increased susceptibility to electromagnetic noise can similarly trigger gate misfires. To counter these phenomena, when a gate misfire occurs, i.e., when the opposing arm element is turned on, the bypass switching element 42 is turned off and configured to use a path through the gate resistor 41.

[0089] Next, the specific operation of the gate drive circuit 101 according to Embodiment 2 will be described. Figure 5 illustrates the timing chart when the gate drive circuit 101 according to Embodiment 2 controls the gate of a power semiconductor element.

[0090] Referring to Figure 5, the basic operation of the gate drive circuit 101 according to Embodiment 2 and the gate drive circuit 100 according to Embodiment 1 are the same, so a detailed explanation will not be repeated.

[0091] At time t0, the power semiconductor element 10 starts turning off. As shown in the figure, the gate voltage of the power semiconductor element 10 is lowered to a deep off-bias Vneg, and the deep off-bias Vneg is established at time t1. Then, at time t2, in order to shorten the application time of the deep off-bias Vneg, it is switched from a deep off-bias Vneg to a shallow off-bias Vs.

[0092] Here, the difference from the gate drive circuit 100 according to Embodiment 1 is that at time tb1 within the interval between time t1 and time t2 included in the first period, the bypass switching element 42 turns on. By adding this operation of the embodiment at time tb1, the gate voltage of the power semiconductor element 10 changes at time t2. Specifically, the switching speed from deep off-bias Vneg to shallow off-bias Vs becomes faster, and as shown in the figure, it is possible to quickly return to shallow off-bias Vs. Because it returns to shallow off-bias Vs quickly, the application time of deep off-bias Vneg can be reliably shortened compared to Embodiment 1. At time tb2, the bypass switching element 42 turns off.

[0093] Furthermore, after the dead time period Td has elapsed, the external drive signal IN2, which indicates the timing of the turn-on operation of the opposing arm element, changes from "0" to "1". In other words, the dead time period Td ends at time t3.

[0094] At time t3, the gate voltage of the power semiconductor element 10 switches again from a shallow off-bias Vs to a negative bias Vneg.

[0095] At time t3, the bypass switching element 42 is turned on. As a result, the switching speed from a shallow off-bias Vs to a deep off-bias Vneg is faster than in Embodiment 1 because the gate resistor 41 is bypassed, and as shown in the figure, it is possible to quickly apply a deep off-bias Vneg to the gate of the power semiconductor element 10.

[0096] Then, at time tb3, the bypass switching element 42 turns off.

[0097] At the subsequent time ton, the opposing arm element turns on, causing a gate misfire of the power semiconductor element 10. At this point, within the interval between time t3 and time ton included in the second period, at time tb3, the bypass switching element 42 turns off.

[0098] Thus, by adding the operation of the gate resistance control circuit 40 according to Embodiment 2 at time tb3, it is possible to prevent the gate misfiring of the power semiconductor element 10 due to the effects of the aforementioned stray inductance and electromagnetic noise. Specifically, by turning off the bypass switching element 42 and providing the gate resistor 41, it is possible to obtain the same gate misfiring tolerance as in Embodiment 1, as shown in the figure.

[0099] During the dead time period Td, specifically from time tb2 onward, that is, during the off-bias period of the power semiconductor element 10, the gate resistance control circuit 40 turns off the bypass switching element 42 and connects the gate resistor 41. By keeping the gate resistor 41 connected even when the power semiconductor element 10 is off, it is possible to dampen gate vibrations caused by external factors. As a result, misfiring of the gate of the power semiconductor element 10 can be prevented.

[0100] The ON operation period (tb1-tb2, t3-tb3) of the bypass switching element 42 can be set using the components described in Embodiment 1. Specifically, this can be achieved by combining an RC filter that delays the period from time t0 to tb1, and the logic circuit described in Embodiment 1 that creates a one-shot pulse using external drive signals IN1 and IN2. Furthermore, the ON operation period (bypass period) of the bypass switching element 42 can also be set arbitrarily, and it is possible to switch between ON and OFF operations at multiple points.

[0101] The gate resistor 41 is composed of general-purpose circuit elements such as lead resistors and chip resistors, and only requires circuit constants and power capacity that conform to the switching operation conditions of the power semiconductor element 10. The number of circuit elements constituting the gate resistor 41 does not matter, and the circuit configuration does not matter, whether it is in series or parallel. The bypass switching element 42 can be an inexpensive discrete circuit element as long as it can match the gate capacitance of the power semiconductor element 10. The bypass switching element 42 is desirable as high-speed response performance is desired. A high gate threshold voltage reduces the risk of malfunction but decreases high-speed response performance, while a low gate threshold voltage improves high-speed response performance but increases the risk of malfunction performance.

[0102] The gate drive circuit 101 according to Embodiment 2 includes a gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22, which makes it possible to further shorten the period of deep off-bias Vneg applied to the gate of the power semiconductor element 10. Furthermore, the reliability of the power semiconductor element 10 is further improved by speeding up the switching from shallow off-bias Vs to deep off-bias Vneg.

[0103] Therefore, the lifespan of the power semiconductor element 10 can be further extended, and the use of economical power converter systems can be promoted.

[0104] Embodiment 3. Embodiment 3 describes a switching circuit configuration that differs from that of Embodiment 1.

[0105] Figure 6 is a block diagram illustrating the function of the gate drive circuit 100# of a power semiconductor device according to Embodiment 3.

[0106] Referring to Figure 6, the gate drive circuit 100# differs from the gate drive circuit 100 in that the gate voltage control circuit 20 is replaced with the gate voltage control circuit 20#, and the off-bias voltage control circuit 30 is replaced with the off-bias voltage control circuit 30#.

[0107] The other configurations are the same as those of the gate drive circuit 100 according to Embodiment 1, so a detailed explanation will not be repeated.

[0108] The gate voltage control circuit 20# differs from the gate voltage control circuit 20 in that the first control circuit 21 is replaced by the first control circuit 21#, and the first switching circuit 22 is replaced by the first switching circuit 22#.

[0109] The off-bias voltage control circuit 30# differs from the off-bias voltage control circuit 30 in that the second control circuit 31 is replaced by the second control circuit 31#, and the second switching circuit 32 is replaced by the second switching circuit 32#.

[0110] The first switching circuit 22# includes a PMOSFET 22P on the high side and an NMOSFET 22N on the low side.

[0111] The PMOSFET22P and NMOSFET22N are connected in series. The PMOSFET22P is connected to a positive voltage source Vdd and to the output node.

[0112] The NMOSFET22N is connected to the output node and to the output node of the second switching circuit 32.

[0113] The second switching circuit 32# includes a PMOSFET 32P on the high side and an NMOSFET 32N on the low side.

[0114] The PMOSFET32P and NMOSFET32N are connected in series. The PMOSFET32P is connected to the source electrode of the power semiconductor element 10 and to the output node. The output node is connected to the first switching circuit 22#.

[0115] The NMOSFET32N is connected to the output node and the negative voltage source Vneg. The switching circuit according to Embodiment 3 is particularly effective for power converters applied to high-frequency drive applications, for example, by using wide-bandgap semiconductors.

[0116] A CMOS circuit consisting of PMOSFET22P and NMOSFET22N and PMOSFET32P and NMOSFET32N according to Embodiment 3 will be described.

[0117] Since both the upper and lower arm elements are composed of MOSFETs, power consumption is lower compared to cases where bipolar transistors are used. Furthermore, as the switching frequency of the power inverter increases, the number of switching cycles in the gate drive circuit also increases proportionally. In other words, it is extremely useful for the high-frequency drive applications mentioned earlier.

[0118] The output lines of the PMOSFET22P and NMOSFET22N swing with the power supply voltage Vdd applied to the high side of the PMOSFET22P and the potential of the low side (shallow off-bias Vs or deep off-bias Vneg). Furthermore, a constant drive capability is obtained regardless of the difference between the input voltage from the power supply voltage and the output voltage of the output line. This type of drive output makes it possible to realize a gate drive circuit 100# that has both high drive capability and high stability.

[0119] On the other hand, in a typical push-pull circuit, the swing range of the output line is narrowed by the gate threshold voltage of the transistor elements in the upper and lower arms. In other words, when the output voltage is outside the swing range, the output of the push-pull circuit becomes floating and exhibits unstable operation.

[0120] The gate drive circuit 100# according to Embodiment 3 achieves high drive capability and stable operation by implementing the switching circuit with a CMOS circuit. These effects are expected to improve the characteristics of the power semiconductor element 10 and suppress oscillation phenomena caused by fluctuations in the gate potential.

[0121] While the advantages of CMOS circuits have been discussed above, they also have disadvantages. During switching of the upper and lower arm elements, a shoot-through current may flow between the high-side power supply voltage and the low-side reference potential. This shoot-through current can increase the power consumption of the gate drive circuit 100. Increased power consumption means that it is unsuitable for high-frequency drive operation, which contradicts the aforementioned advantages.

[0122] Therefore, a dead time period may be generated between the upper and lower arms in the preceding stages of PMOSFET22P, NMOSFET22N and PMOSFET32P, NMOSFET32N. By providing an appropriate dead time period, it is possible to reduce the through-current flowing into the CMOS circuit. For example, the signals applied to the gates of PMOSFET22P, NMOSFET22N and PMOSFET32P, NMOSFET32N may be controlled independently.

[0123] Figure 7 illustrates the specific configurations of the first control circuit 21# and the second control circuit 31# according to Embodiment 3. The basic component configurations are the same as those of the first control circuit 21 and the second control circuit 31 shown in Figure 2, so repeated explanations are omitted.

[0124] Referring to Figure 7, the first control circuit 21# includes a control unit 21A# and a delay circuit 21B#.

[0125] The second control circuit 31# includes delay circuits 31A# and 31B#, inverter IV, AND circuit AD, and OR circuit OR.

[0126] The AND circuit AD receives an external drive signal IN2 via the delay circuit 31B# and inverter IV, as well as an external drive signal IN2 that does not go through any elements or additional circuits, and outputs the result of the AND logic operation to the OR circuit OR.

[0127] The OR circuit receives an external drive signal IN1 via the delay circuit 31A# and the input of the AND circuit AD, and outputs the result of the OR logic operation.

[0128] Delay circuits 31A# and 31B# are delay circuits that generate delayed signals. For example, they can be composed of RC filters, which are common delay time adjustment circuits, and it is even better if they are equipped with Schmitt trigger elements to adjust the transmitted signal. The delay amounts of delay circuits 31A# and 31B# can be adjusted to be different.

[0129] The OR circuit outputs an off-bias voltage control signal ("1") when the power semiconductor element 10 is in a steady-state ON state and not switching, and an off-bias voltage control signal ("0") when it is in a steady-state OFF state and not switching.

[0130] As a result, the PMOSFET 32P of the second switching circuit 32# repeatedly switches between on and off at a constant cycle.

[0131] On the other hand, during the transient timing of switching operation, the output of the off-bias voltage control signal changes in a complex manner. As the external drive signal IN1 changes from "1" to "0", the OR circuit OR maintains an output of "1" for a period proportional to the delay amount of the delay circuit 31A#. In response to this, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the period during which the output of "1" is maintained.

[0132] Furthermore, as the external drive signal IN2 changes from "0" to "1", the AND circuit AD outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31B#. In response to this, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the duration of the one-shot pulse signal.

[0133] According to this embodiment, the first control circuit 21 included in the gate voltage control circuit 20 contains a PMOSFET 22P and an NMOSFET 22N, and the second control circuit 31 included in the off-bias voltage control circuit 30 contains a PMOSFET 32P and an NMOSFET 32N. This makes it possible to bring out the high characteristics of the power semiconductor element 10 while suppressing gate oscillation and other issues that are problematic in high-frequency applications.

[0134] Furthermore, it is also possible to apply the configuration of the gate resistance control circuit 40 according to Embodiment 2.

[0135] Embodiment 4. Embodiment 4 describes another form relating to the control of the off-bias level applied to the gate of the power semiconductor element 10.

[0136] Figure 8 illustrates the waveform of the gate voltage Vgs of a SiC-MOSFET to which the gate drive circuit 100 of this disclosure is applied.

[0137] Refer to Figure 8 to see the case where the duration of applying a deep off-bias is adjusted. Here, the gate on-bias is set to +20V, the shallow off-bias Vs to 0V, and the deep off-bias Vneg to -5V. Except for the period of deep off-bias Vneg, all driving conditions were the same.

[0138] Waveform LA is shown to represent a case where the off-bias application period is shorter compared to waveform LB. In other words, these waveforms differ in the duration of deep off-bias Vneg.

[0139] The period of deep off-bias Vneg is adjusted by adjusting the time constant of the RC filter that constitutes the delay circuit included in the off-bias voltage control circuit 30.

[0140] Specifically, the delay amount of the delay circuit is adjusted by adjusting the capacitance of the capacitor, thereby adjusting the duration of off-bias application.

[0141] Specifically, when two types of capacitors, 470pF and 680pF, are provided for the delay circuit, setting the capacitor capacity to "470pF" makes it possible to shorten the period of deep off-bias Vneg. This makes it possible to further reduce stress on the gate oxide film.

[0142] For example, by using a variable capacitance element for the capacitor, it is possible to set the optimal capacitor capacitance and adjust the off-bias Vneg period to the optimal duration.

[0143] Embodiment 5. Embodiment 5 describes another form relating to the operation of the gate drive circuit 100, which includes a gate resistance control circuit 40 according to Embodiment 2.

[0144] Figure 9 illustrates the timing chart when the gate drive circuit 101 according to Embodiment 5 controls the gate of a power semiconductor element.

[0145] Referring to Figure 9, the basic operation of the gate drive circuit 101 according to Embodiment 5 and the gate drive circuit 100 according to Embodiment 2 are the same, so a detailed explanation will not be repeated.

[0146] Compared to the timing chart in Figure 5, the bypass switching element 42 included in the gate resistance control circuit 40 described in Figure 3 is turned on during the period between times tb4 and tb5, which lies between time ton and time t4.

[0147] As a result of this operation, as shown in Figure 9, the gate voltage Vgs of the power semiconductor element 10 is quickly switched from a deep off-bias Vneg to a shallow off-bias Vs. This reliably shortens the time that the deep off-bias Vneg is applied to the gate of the power semiconductor element 10.

[0148] The time tb4 at which the bypass switching element 42 turns on is set to fall between the end of the turn-on operation of the opposing arm element of the power semiconductor element 10 and time t4. This setting suppresses vibration of the gate of the power semiconductor element 10 during the turn-on period of the opposing arm element, thus avoiding the risk of false firing. Furthermore, it is possible to shorten the application time of the deep off-bias Vneg of the power semiconductor element 10.

[0149] This embodiment can be realized by adding an additional element to the configuration shown in Figure 4. The additional element provides a function to control the gate resistance control circuit 40 so that the value of the gate resistance 41 becomes small, and to determine the time tb3 which is the timing for the turn-on operation of the bypass switching element 42.

[0150] Specifically, the timing information for time ton, which is the timing of the turn-on operation of the opposing arm element of the power semiconductor element 10, is used to determine time tb4.

[0151] For example, timing information for time ton can be obtained by providing an overvoltage detection circuit or a voltage change rate dVds / dt detection circuit between the drain electrode and source electrode of the power semiconductor element 10. Alternatively, a gate current detection circuit may be connected in series adjacent to the gate resistance control circuit 40. By synchronizing the detection information from these detection circuits with the signal of the second control circuit 31 included in the off-bias voltage control circuit 30, it is possible to adjust the timing of time tb3 appropriately.

[0152] Alternatively, a state timer with a pre-set time may be provided in the second control circuit 31 included in the off-bias voltage control circuit 30. The time tb4 may also be set by conducting prior experiments, for example, by measuring the time required for the opposing arm element turn-on operation of the power semiconductor element 10.

[0153] In Embodiment 5, the configuration according to Embodiment 2 is further enhanced by adding a timing for the turn-on operation of the bypass switching element 42 included in the gate resistance control circuit 40. This makes it possible to more effectively shorten the application time of the deep off-bias Vneg applied to the gate of the power semiconductor element 10.

[0154] Embodiment 6. Embodiment 6 describes the configuration of the integrated drive circuit 102.

[0155] Figure 10 is a block diagram illustrating the function of the integrated drive circuit 102 according to Embodiment 6.

[0156] Referring to Figure 10, the integrated drive circuit 102 according to Embodiment 6 is characterized by having two drive circuits, gate drive circuit 100P and gate drive circuit 100N, compared to the gate drive circuit 100, and being an integrated circuit that incorporates these two gate drive circuits.

[0157] An integrated type, for example, is an upper and lower arm unit in which power semiconductor elements are connected in series. As shown in Figure 10, it can be applied to the half-bridge circuit configuration commonly seen in power modules where power semiconductor elements are packaged in a 2-in-1 configuration.

[0158] The power semiconductor elements 10P and 10N, which are connected in series with each other, are driven by a single drive circuit called an integrated drive circuit 102, which drives the power semiconductor elements of the upper and lower arms.

[0159] The input signals are external drive signal IN1 and external drive signal IN2. As described in Embodiment 1, any logic-based pulse signal will suffice in which the external drive signal IN is set to "1" during the period when the corresponding power semiconductor element should be turned on, and the external drive signal IN is set to "0" during the period when the corresponding power semiconductor element should be turned off.

[0160] Here, the external drive signal IN1 controls the gate of the power semiconductor element 10P of the upper arm element and is input to the gate voltage control circuit 20P. The external drive signal IN2 controls the gate of the power semiconductor element 10N of the lower arm element and is input to the gate voltage control circuit 20N.

[0161] As described in Embodiment 1, the off-bias voltage control circuit 30P receives an external drive signal IN2 that indicates the timing of the turn-on operation of the power semiconductor element 10N, which is the lower arm element and an opposing arm element. The off-bias voltage control circuit 30N receives an external drive signal IN1 that indicates the timing of the turn-on operation of the power semiconductor element 10P, which is the upper arm element and an opposing arm element.

[0162] With this configuration, the same operation as the gate drive circuit 100 described in Embodiment 1 is performed.

[0163] The gate drive circuits 100P and 100N included in the integrated drive circuit 102 have basically the same circuit configuration. However, if there is variation in the element characteristics between the power semiconductor elements 10P and 10N of the upper and lower arm elements, internal fine-tuning may be performed using the off-bias voltage control circuits 30P and 30N. For example, by adjusting the timing of the deep off-bias Vneg and the shallow off-bias Vs for the off-bias voltage control circuits 30P and 30N, more favorable operation of the power semiconductor elements can be achieved.

[0164] In Embodiment 6, the external drive signal IN1 and the external drive signal IN2 are separated by an isolation element such as a photocoupler or an isolation transformer, or by an isolation element with sufficient dielectric strength located inside the gate voltage control circuit 20P and the gate voltage control circuit 20N, and the off-bias voltage control circuit 30P and the off-bias voltage control circuit 30N. The isolation element may also be a multi-input, multi-output isolator IC, and in such a configuration, the isolation treatment between the gate voltage control circuit 20P and the off-bias voltage control circuit 30P can be made common.

[0165] The positive voltage source Vdd_P supplied to the gate drive circuit 100P is always an isolated power supply, and the potential of the positive voltage source Vdd_P is a floating potential relative to the ground potential. Furthermore, the deep off-bias Vneg_P and shallow off-bias Vs_P provided inside the gate drive circuit 100P are also floating potentials relative to the ground potential. Since the positive voltage source Vdd_P is a floating power supply, it is possible to generate an arbitrary potential using, for example, a three-terminal regulator to create appropriate deep off-bias Vneg_P and shallow off-bias Vs_P.

[0166] By fulfilling this configuration, the power semiconductor element 10P, which corresponds to the upper arm in the half-bridge circuit, can be electrically and safely operated by the gate drive circuit 100P included in the integrated drive circuit 102.

[0167] In this example, the configuration of a half-bridge circuit is described, but the method according to Embodiment 5 can also be applied to a power module for a three-phase inverter in which power semiconductor elements are packaged in a 6-in-1 configuration.

[0168] The configuration according to Embodiment 6 includes an integrated drive circuit 102 that combines the drive circuits for the upper and lower arms in order to drive the upper and lower arm elements in the half-bridge circuit of the power converter. As a result, the power semiconductor element 10P of the upper arm element and the power semiconductor element 10N of the lower arm element can be driven with a simple circuit configuration without requiring the addition of extra external drive signals or complex procedures.

[0169] Embodiment 7. Embodiment 7 applies the power conversion device according to the above-described embodiment to a power conversion system. This disclosure is not limited to a specific power conversion device, but below, Embodiment 7 will describe the case in which this disclosure is applied to a three-phase inverter.

[0170] Figure 11 is a block diagram showing the configuration of a power conversion system according to Embodiment 7. Referring to Figure 11, the power conversion system according to Embodiment 7 includes a power supply 1000, a power conversion device 1001, and a load 1004. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 1001. The power supply 1000 can be composed of various components, for example, a DC grid, a solar cell, or a storage battery, or it may be composed of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 1000 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0171] The power converter 1001 is a three-phase inverter connected between the power supply 1000 and the load 1004. It converts the DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 1004. The power converter 1001 includes a main conversion circuit 1002 that converts DC power into AC power and outputs it, and a control circuit 1003 that outputs a control signal to the main conversion circuit 1002 to control the main conversion circuit 1002.

[0172] Load 1004 is a three-phase motor driven by AC power supplied from power converter 1001. Note that load 1004 is not limited to a specific application; it is a motor mounted in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0173] The details of the power converter 1001 are described below. The main conversion circuit 1002 is equipped with a power semiconductor element and a freewheeling diode (not shown), and the power semiconductor element switches to convert the DC power supplied from the power supply 1000 into AC power, which is then supplied to the load 1004.

[0174] While there are various specific circuit configurations for the main converter circuit 1002, the main converter circuit 1002 in this embodiment is a two-level, three-phase full-bridge circuit and can be composed of six power semiconductor elements and six freewheeling diodes antiparallel to each power semiconductor element. The six power semiconductor elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes one of the phases (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main converter circuit 1002, are connected to the load 1004.

[0175] The main conversion circuit 1002 can be fitted with the gate drive circuits described in Embodiments 1 to 6 for driving each power semiconductor element.

[0176] The gate drive circuit generates gate control signals to drive the power semiconductor elements of the main conversion circuit 1002 and supplies them to the control electrodes of the power semiconductor elements of the main conversion circuit 1002. Specifically, the control circuit 1003 outputs an external drive signal to turn on the power semiconductor elements and an external drive signal to turn off the power semiconductor elements to the control electrodes of each power semiconductor element. When the switching element is kept in the ON state, the external drive signal is a voltage signal (ON signal) that is above the threshold voltage of the power semiconductor element, and when the switching element is kept in the OFF state, the external drive signal is a voltage signal (OFF signal) that is below the threshold voltage of the power semiconductor element.

[0177] The control circuit 1003 controls the power semiconductor elements of the main converter circuit 1002 so that the desired power is supplied to the load 1004. Specifically, it calculates the time (on time) that each power semiconductor element of the main converter circuit 1002 should be in the ON state based on the power to be supplied to the load 1004. For example, the main converter circuit 1002 can be controlled by PWM control, which modulates the on time of the power semiconductor elements according to the voltage to be output. Then, it outputs a control command (external drive signal) to the gate drive circuit of the main converter circuit 1002 so that an ON signal is output to the power semiconductor elements that should be in the ON state at each point in time, and an OFF signal is output to the power semiconductor elements that should be in the OFF state.

[0178] In the power conversion device according to this embodiment, the gate drive circuit described above, which constitutes the main conversion circuit 1002, is applied, thereby improving reliability.

[0179] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0180] Furthermore, the power conversion device to which this disclosure is applied is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0181] The embodiments disclosed herein should be considered illustrative and not restrictive in all respects. Furthermore, it goes without saying that there is no problem in suitably combining multiple embodiments, and it is desirable to further enhance the effects of each embodiment in order to make efficient and economical use of the power conversion device.

[0182] The scope of this disclosure is indicated by the claims rather than the above description, and all changes within the meaning and scope of the claims are intended. [Explanation of Symbols]

[0183] 10, 10N, 10P Power semiconductor elements, 20, 20N, 20P Gate voltage control circuits, 21 First control circuit, 22 First switching circuit, 30, 30N, 30P Off-bias voltage control circuits, 31 Second control circuit, 32 Second switching circuit, 40 Gate resistor control circuit, 41 Gate resistor, 42 Bypass switching elements, 100, 100N, 100P, 101 Gate drive circuits, 102 Integrated drive circuit, 1000 Power supply, 1001 Power converter, 1002 Main converter circuit, 1003 Control circuit, 1004 Load.

Claims

1. A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a first external drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first external drive signal and the second external drive signal, and controls the application period of the changed off-bias, The aforementioned off-bias voltage control circuit is During the period in which the off-bias is applied, the voltage level of the off-bias is changed during a first period in accordance with the first external drive signal. During the period in which the off-bias is applied, the voltage level of the off-bias is changed during a second period in accordance with the second external drive signal. The second external drive signal is a control signal for applying on-bias and off-bias to the gate terminal of the power semiconductor element on the opposing arm side, which is connected in series with the power semiconductor element. The semiconductor device wherein the second period includes the turn-on operation completion period of the power semiconductor element on the opposing arm side after the dead time period.

2. A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a first external drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first external drive signal and the second external drive signal, and controls the application period of the changed off-bias, The off-bias voltage control circuit sets the first off-bias to a second off-bias that is lower than the first off-bias, according to the first and second external drive signals, in a semiconductor device.

3. A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a first external drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first external drive signal and the second external drive signal, and controls the application period of the changed off-bias, A semiconductor device further comprising a gate resistance control circuit provided between the power semiconductor element and the gate voltage control circuit, for controlling the gate resistance of the power semiconductor element.

4. The semiconductor device according to claim 3, wherein the gate resistance control circuit controls the gate resistance when changing the off-bias voltage level.

5. The semiconductor device according to claim 4, wherein the gate resistance control circuit sets the gate resistance to be large before changing the off-bias voltage level, and sets the gate resistance to be small when changing the off-bias voltage level.

6. The gate resistance control circuit is A resistive element is provided between the power semiconductor element and the gate voltage control circuit, The semiconductor device according to claim 3, further comprising a bypass circuit for bypassing the resistive element.

7. A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a first external drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first external drive signal and the second external drive signal, and controls the application period of the changed off-bias, The aforementioned off-bias voltage control circuit is A first delay circuit that delays the first external drive signal, A second delay circuit that delays the second external drive signal, A logic circuit that generates a switching signal based on a combination of the delay signal of the first delay circuit and the delay signal of the second delay circuit, A semiconductor device comprising a switching circuit that changes the off-bias voltage level based on the switching signal.

8. A first power semiconductor element, A second power semiconductor element is provided on the opposing arm side and connected in series with the first power semiconductor element, The system comprises first and second gate drive circuits, each provided corresponding to the first and second power semiconductor elements, which drive the corresponding power semiconductor elements according to first and second external drive signals, Each of the gate drive circuits is, A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a corresponding drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first and second external drive signals and controls the application period of the changed off-bias, The aforementioned off-bias voltage control circuit is During the period in which the off-bias is applied, the voltage level of the off-bias is changed during a first period in accordance with the first external drive signal. During the period in which the off-bias is applied, the voltage level of the off-bias is changed during a second period in accordance with the second external drive signal. The second external drive signal is a control signal for applying on-bias and off-bias to the gate terminal of the power semiconductor element on the opposing arm side, which is connected in series with the power semiconductor element. The power converter device wherein the second period includes the turn-on operation completion period of the power semiconductor element on the opposing arm side after the dead time period.

9. A first power semiconductor element, A second power semiconductor element is provided on the opposing arm side and connected in series with the first power semiconductor element, The system comprises first and second gate drive circuits, each provided corresponding to the first and second power semiconductor elements, which drive the corresponding power semiconductor elements according to first and second external drive signals, Each of the gate drive circuits is, A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a corresponding drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first and second external drive signals and controls the application period of the changed off-bias, The off-bias voltage control circuit is a power converter that sets the first off-bias to a second off-bias lower than the first off-bias according to the first and second external drive signals.

10. A first power semiconductor device, A second power semiconductor element is provided on the opposing arm side and connected in series with the first power semiconductor element, The system comprises first and second gate drive circuits, each provided corresponding to the first and second power semiconductor elements, which drive the corresponding power semiconductor elements according to first and second external drive signals, Each of the gate drive circuits is, A gate voltage control circuit that applies on-bias and off-bias to the gate terminal of a power semiconductor element according to a corresponding drive signal, The system includes an off-bias voltage control circuit that changes the off-bias voltage level according to the first and second external drive signals and controls the application period of the changed off-bias, A power conversion device further comprising a gate resistance control circuit provided between each of the power semiconductor elements and the gate voltage control circuit, for controlling the gate resistance of each of the power semiconductor elements.

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