Power conversion circuits, power modules, converters, and inverters

Abstract

To prevent a short circuit between a switching element and a synchronous rectifier element and reduce power loss thereof.SOLUTION: Provided is a power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and a source inductance of the switching transistor is smaller than a source inductance of the synchronous rectifier transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This embodiment relates to a power conversion circuit, a power module, a converter, and an inverter. [Background technology]

[0002] In half-bridge and full-bridge circuits, which connect two elements (a switching element and a synchronous rectifier element) in series, turning on both elements simultaneously causes a short circuit between the power supply and ground, resulting in a large shoot-through current. This large shoot-through current can cause losses in the switching element or even destroy the switching element itself.

[0003] To suppress through-current, a pause period (dead time) is required during the transition period between the on / off states of the elements, during which all elements are turned off. However, when one element is turned on from the dead time state where all elements are off, a phenomenon can occur where the gate of the other element turns on due to a change in drain voltage (false arc activation or false on). This is a problem that can occur, for example, in three-phase inverters for motor drive and synchronous DC / DC converters.

[0004] Furthermore, in recent years, numerous research institutions have been conducting research and development on silicon carbide (SiC) devices. SiC power devices are characterized by their superior low on-resistance, high-speed switching, and high-temperature operation compared to conventional Si power devices. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 5-226994 [Overview of the project] [Problems that the invention aims to solve]

[0006] Generally, when using high-speed switching elements, source-sense signal wiring is connected to the switching element. This prevents the electromotive force of the inductance at the source of the switching element from affecting the gate circuit, and ensures a sufficient potential difference for charging the gate oxide film of the switching element. As a result, the rate of current change can be increased, and consequently, the losses (switching losses) that occur when the switching element is turned on or off are reduced.

[0007] On the other hand, in the voltage change region, the current change is only contributed by the charge and discharge current, so this contribution is relatively small, and the difference in voltage change of the switching element with or without the connection of the source sense signal wiring is small, almost equivalent.

[0008] Furthermore, the switching characteristics of a synchronous rectifier element are determined by the operation of the switching element. In a half-bridge circuit, a problem arises when a synchronous rectifier element is mistakenly turned on, causing a short circuit between the series-connected switching element and the synchronous rectifier element.

[0009] Short circuits occur in the voltage change region, but the electromotive force of the inductance of the freewheeling source in the current change region that precedes the voltage change region significantly influences the short circuit. The direction of electromotive force of the inductance of the source of the synchronous rectifier element in the current change region is the same as the direction of electromotive force of the inductance of the source of the switching element, and the voltage of the gate oxide film of each element rises in the positive direction in the voltage change region.

[0010] In synchronous rectifier elements not connected to source sense signal wiring, the source inductance is shared with the gate circuit, causing the electromotive force to negatively charge the gate oxide film. This lowers the starting point of the voltage rise in the voltage change region, making short circuits less likely.

[0011] In elements connected to source-sense signal wiring, the source signal wiring is isolated, so the electromotive force of the source inductance does not affect the gate oxide film voltage. For this reason, it is susceptible to the effects of voltage increases in the voltage change region, and short circuits are likely to occur.

[0012] When a short circuit occurs, it increases the power loss of the element. A half-bridge circuit composed of elements connected to the source sense signal wiring may lose the advantage of low power loss obtained by improving the switching characteristics of the elements connected to the source sense signal wiring due to the short circuit.

[0013] In order to suppress the short circuit, it is necessary to suppress the mis-turn-on of the synchronous rectifier element. However, the switching characteristics including the synchronous rectifier element are determined by the switching element.

[0014] One aspect of the present embodiment provides a power conversion circuit that suppresses short circuits of a switching element and a synchronous rectifier element and reduces power loss. Another aspect of the present embodiment provides a power module including the power conversion circuit. Another aspect of the present embodiment provides a converter and an inverter including the power module.

Means for Solving the Problems

[0015] In the present embodiment, in a power conversion circuit, by using in combination a switching element connected to the source sense signal wiring and a synchronous rectifier element not connected to the source sense signal wiring, while taking advantage of the switching characteristics of the switching element connected to the source sense signal wiring, the short circuit of the synchronous rectifier element is suppressed.

[0016] One aspect of the present embodiment is a power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and the inductance of the source of the switching transistor is smaller than the inductance of the source of the synchronous rectifier transistor.

[0017] Another aspect of the present embodiment is a power module including the power conversion circuit.

[0018] Another aspect of this embodiment includes an insulating layer having a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern, and a fifth wiring pattern formed on its surface; a first transistor having a first surface electrode and a first control electrode on its surface and a first back electrode on its back surface, the first back electrode being arranged on the first wiring pattern and electrically connected; and a second surface electrode and a second control electrode on its surface and a second back electrode on its back surface, the second back electrode being The aforementioned The device comprises a second transistor arranged on a second wiring pattern and electrically connected, wherein the first surface electrode comprises a plurality of first For the source It is connected to the third wiring pattern via a wire, For source sense 1 Connected to the fourth wiring pattern via a wire, the second surface electrode has multiple For source 2 Connected to the first wiring pattern via a wire, via the first wiring pattern and the second source sense wire The fifth wiring pattern is connected, and each of the first, second, third, fourth, and fifth wiring patterns is connected to the corresponding external output terminal. Therefore, the inductance of the first source sense wire and the fourth wiring pattern is smaller than the inductance of the second source sense wire and the fifth wiring pattern. It is a power module. Another aspect of this embodiment includes an insulating layer having a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern, and a fifth wiring pattern formed on its surface; a first transistor having a first surface electrode and a first control electrode on its surface and a first back electrode on its back surface, the first back electrode being arranged on the first wiring pattern and electrically connected; and a second surface electrode and a second control electrode on its surface and a second back electrode on its back surface, the second back electrode being The aforementioned The device comprises a second transistor arranged on a second wiring pattern and electrically connected, wherein the first surface electrode comprises a plurality of first For the source The second surface electrode is connected to the third wiring pattern via a wire, and the second surface electrode is connected to a plurality of For source 2 Connected to the first wiring pattern via a wire, For source sense 2The fifth wiring pattern is connected via a wire, and each of the first, second, third, fourth, and fifth wiring patterns has a corresponding terminal for external connection. Furthermore, a sixth wiring pattern and a seventh wiring pattern are formed on the surface of the insulating layer, the sixth wiring pattern is connected to the third wiring pattern via a first source sense wire, the seventh wiring pattern is connected to the first wiring pattern via a third source sense wire, and the inductance of the second source sense wire and the fifth wiring pattern is smaller than the inductance of the plurality of first source wires, the third wiring pattern, the first source sense wire and the sixth wiring pattern. It is a power module.

[0019] Another embodiment of this model is a converter or inverter equipped with the power module. [Effects of the Invention]

[0020] According to this embodiment, a power conversion circuit can be provided that suppresses short circuits of switching elements and synchronous rectifier elements while reducing power loss. Another embodiment can provide a power module equipped with the power conversion circuit. Another embodiment can provide a converter and inverter equipped with the power module. [Brief explanation of the drawing]

[0021] [Figure 1] Figure 1 shows a power conversion circuit according to one embodiment of this model. [Figure 2] Figure 2 shows a power conversion circuit according to one embodiment of this design, and is a schematic circuit diagram of a half-bridge circuit. [Figure 3] Figure 3 shows a power conversion circuit according to one embodiment of this design, and is a schematic circuit diagram of a half-bridge circuit. [Figure 4] Figure 4 is a schematic cross-sectional view of a SiC DIMISFET, which is an example of a semiconductor device applicable to a power conversion circuit according to one embodiment of this model. [Figure 5] Figure 5 is a schematic cross-sectional view of a SiC TMISFET, which is an example of a semiconductor device applicable to a power conversion circuit according to one embodiment of this model. [Figure 6] Figure 6 shows a power conversion circuit according to another embodiment of this model. [Figure 7] Figure 7 shows a power conversion circuit according to another embodiment of this model. [Figure 8] Figure 8 shows a power conversion circuit according to another embodiment of this model. [Figure 9] Figure 9 shows a power module according to this embodiment, and is a simplified schematic planar pattern configuration diagram of a half-bridge-integrated module before the resin layer is formed. [Figure 10] Figure 10 shows a power module according to this embodiment, and is a simplified schematic planar pattern configuration diagram of a half-bridge-integrated module before the resin layer is formed. [Figure 11] Figure 11 shows a power module according to this embodiment, and is a simplified schematic planar pattern configuration diagram of a half-bridge-integrated module before the resin layer is formed. [Figure 12] Figure 12 shows circuit diagrams with transistors, (a) Circuit A having a transistor not connected to the source sense signal wiring, and (b) Circuit B having a transistor connected to the source sense signal wiring. [Figure 13] Figure 13 shows the change in voltage across the gate oxide film in the non-driving element. [Figure 14] Figure 14 is a circuit diagram of a converter according to this embodiment, which is a current-mode synchronous rectification step-down DC / DC converter. [Figure 15] Figure 15 is a circuit diagram of a converter according to this embodiment, which is a current-mode synchronous rectification boost type DC / DC converter. [Figure 16] Figure 16 is a circuit diagram of the circuit used for the double pulse test. [Figure 17]Figure 17 is a circuit diagram showing combinations of circuits A' and B' shown in Figure 16, and includes: (a) a combination in which circuit A' has a transistor that is not connected to the source sense signal wiring and circuit B' has a transistor that is connected to the source sense signal wiring; (b) a combination in which both circuits A' and B' have transistors that are not connected to the source sense signal wiring; and (c) a combination in which both circuits A' and B' have transistors that are connected to the source sense signal wiring. [Figure 18] Figure 18 shows the operating waveforms of the transistor included in circuit B', where (a) gate voltage, (b) drain current, and (c) drain voltage are the operating waveforms. [Figure 19] Figure 19 shows the losses of transistors included in circuits A' and B', where (a) the synchronous rectification element losses of the transistors included in circuit A' and (b) the switching element losses of the transistors included in circuit B'. [Modes for carrying out the invention]

[0022] Next, this embodiment will be described with reference to the drawings. In the drawings described below, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and planar dimensions of each component may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts in the drawings where the relationships and ratios of dimensions differ from those of other parts.

[0023] Furthermore, the embodiments described below are illustrative examples of devices and methods for realizing the technical concept, and do not specify the material, shape, structure, arrangement, etc., of each component. Various modifications can be made to these embodiments within the scope of the claims.

[0024] One aspect of this embodiment is as follows:

[0025] [1] A power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, wherein the inductance of the source of the switching transistor is smaller than the inductance of the source of the synchronous rectifier transistor.

[0026] [2] The power conversion circuit according to [1] further comprising a capacitor electrically connected to the switching transistor and the synchronous rectifier transistor.

[0027] [3] The power conversion circuit according to [2] further comprising an output terminal electrically connected to the capacitor.

[0028] [4] The power conversion circuit according to any one of [1] to [3] further comprises a power terminal electrically connected to the drain of the switching transistor.

[0029] A power module comprising the power conversion circuit described in item 1 in any of [5][1] to [4].

[0030] [6] A power module comprising: a first transistor having the function of exciting a first inductor and connected to a first source sense signal wire; a second transistor having the function of releasing the power stored in the first inductor; a first gate signal wire and a first source sense signal wire electrically connected to the gate of the first transistor; and a second gate signal wire and a first source signal wire electrically connected to the gate of the second transistor, wherein the first transistor is connected in series with the second transistor, and the first inductor is connected to the connection point between the first transistor and the second transistor.

[0031] [7] The power module described in [6], wherein the inductance of the source of the first transistor is smaller than the inductance of the source of the second transistor.

[0032] [8] The power module according to [6] or [7] further comprising capacitors electrically connected to the first transistor and the second transistor.

[0033] [9] The power module described in [8] further comprises an output terminal electrically connected to the capacitor.

[0034]

[10] The power module according to any one of the items [6] to [9] further comprising a power terminal electrically connected to the drain of the first transistor.

[0035]

[11] A power module as described in any one of the following [6] to

[10] , wherein the first transistor functions as a switching element and the second transistor functions as a synchronous rectifier.

[0036]

[12] The power module described in any one of the following paragraphs [6] to

[11] , wherein the second transistor outputs a signal to the first source signal wiring via the drain of the first transistor.

[0037]

[13] The power module described in any one of the items [6] to

[11] , wherein the second transistor outputs a signal to the first source signal wiring via the source of the second transistor.

[0038]

[14] The power module as described in

[13] , further comprising a second source signal wire electrically connected to the first transistor and a second source sense signal wire electrically connected to the second transistor, wherein the first transistor outputs a signal to the second source signal wire via the drain of the second transistor.

[0039]

[15] The power module described in

[12] , wherein the drain of the second transistor and the drain of the first transistor are connected by a first wiring, and a signal is output from the gate of the second transistor to the first source signal wiring, the current tolerance of the first wiring is greater than the current tolerance of the wiring directly connected to the second gate signal wiring.

[0040]

[16] When a signal is output from the gate of the second transistor to the first source signal wiring, the current tolerance of the second wiring through the source of the second transistor is greater than the current tolerance of the wiring directly connected to the second gate signal wiring.

[13] The power module described above.

[0041] A converter comprising the power module described in item 1 of any of

[17] [5]~

[16] .

[0042] An inverter equipped with a power module as described in item 1 of any of

[18] [5]~

[16] .

[0043] (Power conversion circuit) The power conversion circuit according to this embodiment will be described.

[0044] Figure 1 shows a power conversion circuit according to one embodiment of this product, comprising a transistor U1 which is a synchronous rectifier element, a transistor U4 which is a switching element, and a gate resistor R g1 , R g4 , and gate drive circuit V G1 , V G4 The power conversion circuit includes multiple insulated-gate field-effect transistors (MISFETs: Metal-Insulator-Semiconductor Field Effect Transistors). Transistor U1 includes a MISFET chip Q1 that functions as a synchronous rectifier, and the wiring of transistor U1 has an inductance L1. Transistor U4 includes a MISFET chip Q4 that functions as a switching element and a source-sensing signal wiring SS4, and the wiring of transistor U4 has an inductance L4.

[0045] Furthermore, a first inductor (not shown) can be connected to the connection point between transistor U1 and transistor U4 (● in Figure 1). Also, the gate drive circuit V G1The source of the MISFET chip Q1 is monitored via the inductance L1 of the wiring, and the gate resistor R is selected according to the monitoring result. g1 A drive signal is supplied to the gate of the MISFET chip Q1 via this. The inductance L1 is the current path through which the current flowing between the source and drain of the MISFET chip Q1 passes. Also, the gate drive circuit V G4 The source of the MISFET chip Q4 is monitored via the source-sensing signal line SS4, and the gate resistor R is selected based on the monitoring result. g4 A drive signal is supplied to the gate of the MISFET chip Q4 via this. Note that inductance L4 is the current path through which the current flows between the source and drain of the MISFET chip Q4, while source sense signal wiring SS4 is a separate signal path provided in addition to that current path.

[0046] Furthermore, MISFET chip Q4 has the function of exciting a first inductor (not shown), and MISFET chip Q1 has the function of releasing the power stored in the first inductor. A smaller source inductance enables high-speed switching operation, and a larger source inductance makes short circuits less likely to occur during high-speed switching operation. Therefore, by using a transistor with a small source inductance and source signal wiring as the switching element that excites the first inductor, which determines the switching characteristics, and using a transistor with a large source inductance and no source signal wiring as the switch (synchronous rectifier element) that releases the power stored in the inductor, which determines the degree of short circuit occurrence, it is possible to configure a power conversion circuit that is high-speed, low-loss, and less prone to short circuits.

[0047] The power conversion circuit shown in Figure 1 will be explained in more detail using Figures 2 and 3. The circuits shown in Figures 2 and 3 are power conversion circuit 1, and are an example of a schematic circuit configuration of a half-bridge circuit. Note that the power conversion circuit 1 according to this embodiment is not limited to a half-bridge circuit, but can also be applied to a full-bridge circuit or a three-phase bridge circuit, etc.

[0048] As described above, the power conversion circuit 1 includes a transistor U1 which is a synchronous rectifier element and a transistor U4 which is a switching element equipped with a source sense signal wiring SS4. Here, we will explain the characteristics of the element (transistor) depending on whether or not it is connected to the source sense signal wiring.

[0049] Figure 12(a) shows circuit A, which has a MISFET chip Q that is not connected to the source sense signal wiring, and Figure 12(b) shows circuit B, which has a MISFET chip Q that is connected to the source sense signal wiring SS.

[0050] Figure 13 shows the change in gate voltage at the non-driven element, which is either a switching element or a synchronous rectifier element and is not performing switching operations.

[0051] In the current change region (current change period) shown in the diagram, in circuit A, the source inductance is shared with the gate circuit, so the electromotive force negatively charges the gate oxide film. In contrast, in circuit B, the element is connected to the source sense signal wiring, and the source signal wiring is isolated, so the electromotive force of the source inductance does not affect the voltage of the gate oxide film.

[0052] In the voltage change region (voltage change period) shown in the diagram, circuit A has a low starting point for the voltage increase, while circuit B has a high starting point for the voltage increase. Circuit B is prone to exceeding the threshold voltage of the element and is prone to false turning on, but circuit A is less likely to exceed the threshold voltage of the element because of its low starting point for the voltage increase, and is more likely to operate normally.

[0053] Therefore, in order to ensure high-speed and normal operation of the power conversion circuit, it is effective to use both a switching element connected to the source sense signal wiring and a synchronous rectifier element not connected to the source sense signal wiring. With this configuration, it is possible to utilize the switching characteristics of the switching element connected to the source sense signal wiring while suppressing false on-on events and ensuring operational stability by taking advantage of the low voltage rise starting point of the synchronous rectifier element not connected to the source sense signal wiring.

[0054] Furthermore, the operating waveforms and losses of transistors in the power conversion circuit of this embodiment and conventional power conversion circuits under double pulse testing will be compared. Figure 16 shows the circuit used in the double pulse test (DPT (Double Pulse Test) circuit). Here, the configurations of circuits A' and B' are exemplified by the power conversion circuit of this embodiment, but the operating waveforms and losses of transistors due to the differences in the configurations of circuits A' and B' will be compared.

[0055] As shown in Figure 16, in the configuration of the transistors in circuit A' and circuit B', a power supply E, a capacitor C, an inductor L, and a constant current source I are connected to circuits A' and B'. The transistors in circuit A' function as synchronous rectifiers, and the transistors in circuit B' function as switching elements.

[0056] Here, the power supply E of the DPT circuit is set to 800 V, and the constant current source I is set to 16 A. Also, FIG. 17 shows a circuit diagram showing the combination of circuit A' and circuit B' of the DPT circuit. FIG. 17(a) is a circuit including a transistor (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) where circuit A' is not connected to the source sense signal wiring, and circuit B' is a circuit including a transistor (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) connected to the source sense signal wiring. FIG. 17(b) is a combination of circuits including transistors (SCT3080KL manufactured by Rohm Co., Ltd.) where neither circuit A' nor circuit B' is connected to the source sense signal wiring. FIG. 17(c) is a combination of circuits including transistors (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) where both circuit A' and circuit B' are connected to the source sense signal wiring.

[0057] In the above DPT circuit, the circuit shown in FIG. 17(a) is the configuration of Example 1 including the power conversion circuit of the present embodiment, the circuit shown in FIG. 17(b) is the configuration of Comparative Example 1 including the conventional power conversion circuit, and the circuit shown in FIG. 17(c) is the configuration of Comparative Example 2 including the conventional power conversion circuit. Note that the circuit symbols etc. shown in FIGS. 17(a) to (c) are omitted because the circuit symbols etc. shown in FIGS. 12(a) and 12(b) can be adopted.

[0058] In the above power conversion circuit, the operation waveforms and losses of the transistors by the double pulse test are shown in FIGS. 18 and 19. FIG. 18(a) is a diagram showing the operation waveform of the gate voltage (V ox,L ) of the transistor included in circuit B'. FIG. 18(b) is a diagram showing the operation waveform of the drain current (I d,L ) of the transistor included in circuit B'. FIG. 18(c) is the operation waveform of the drain voltage (V ds,L ) of the transistor included in circuit B'. FIG. 19(a) is a diagram showing the synchronous rectifier element loss (P H (W)) of the transistor included in circuit A'. FIG. 19(b) is a diagram showing the switching element loss (P L (W)) of the transistor included in circuit B'.

[0059] As shown in Figure 18(a), there is little difference in the gate voltage waveform between Example 1 and Comparative Examples 1 and 2. On the other hand, as shown in Figure 18(b), the drain current waveform shows a large change in Comparative Example 2, making it prone to false-on, while Example 1 shows a gradual change in current, similar to Comparative Example 1. Furthermore, as shown in Figure 18(c), the drain voltage waveform shows that the starting point of the voltage change in Comparative Example 1 is later than in Comparative Example 2, while the starting point of the voltage change in Example 1 is earlier than in Comparative Example 1, similar to Comparative Example 2. For this reason, as shown in Figure 19(a), Example 1 has lower synchronous rectification element losses compared to Comparative Examples 1 and 2, and as shown in Figure 19(b), Example 1 has lower switching element losses compared to Comparative Examples 1 and 2.

[0060] As explained above, by using a transistor that functions as a switching element connected to the source sense signal wiring and a transistor that functions as a synchronous rectifier not connected to the source sense signal wiring in combination, the synchronous rectifier element loss and the switching element loss can be reduced compared to conventional power conversion circuits, resulting in a power conversion circuit that operates at high speed and functions correctly.

[0061] The power conversion circuit 1 may also include a control circuit, which will be described later, and may, for example, include a gate diode as shown in Figure 3.

[0062] As shown in Figure 3, between the gate terminal GT1 and source terminal ST1 of the external output and the gate G1 and source S1 of the MISFET chip Q1, there is a parasitic inductance L due to the gate terminal GT1 and source terminal ST1, as well as the routing of electrode wiring. GP1 and L SP1There exists a parasitic inductance L between the externally extracted gate terminal GT4 and source sense terminal SST4 and the gate G4 and source sense signal wiring SS4 of the MISFET chip Q4, due to the gate terminal GT4 and source sense terminal SST4, as well as the routing of electrode wiring. GP4 and L SP4 Such inductance components exist in the gate closed circuit of the MISFET chip, causing operational delays in gate driving of the MISFET chip and increased gate-source-sense voltage fluctuations when the drain-source voltage changes.

[0063] To suppress parasitic effects caused by such inductance components, the shorter the distance from the diode's cathode and anode to the gate pad and source pad electrodes, the more effective it is. The gate pad and source pad electrodes of a MISFET are formed on the surface of the MISFET. Therefore, the gate diode can be fabricated on the same chip as the MISFET, or the anode of the gate diode chip can be directly soldered onto the source pad electrode of the MISFET.

[0064] Furthermore, while gate diodes may be grouped together for each MISFET arranged in parallel, it is more effective to connect them individually to each of the multiple MISFETs.

[0065] Furthermore, the MISFET can be constructed using SiC MISFETs. Here, Figure 4 shows a schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET, which is an example of a semiconductor device 100 applicable to the power conversion circuit 1.

[0066] As shown in Figure 4, the SiC DIMISFET is n - A semiconductor substrate 26 consisting of a high-resistance layer, a p-body region 28 formed on the surface side of the semiconductor substrate 26, and an n-body region formed on the surface of the p-body region 28. +A gate insulating film 32 is disposed on the surface of the semiconductor substrate 26 between the source region 30 and the p-body region 28, a gate electrode 38 is disposed on the gate insulating film 32, a source electrode 34 is connected to the source region 30 and the p-body region 28, and n is disposed on the back surface of the semiconductor substrate 26 opposite to the front surface. + drain region 24 and n + It comprises a drain electrode 36 connected to a drain region 24.

[0067] In Figure 4, the semiconductor device 100 has a p-body region 28 and n formed on the surface of the p-body region 28. + A source region 30 is formed by double ion implantation (DI), and a source pad electrode SP is connected to a source electrode 34 that is connected to the source region 30 and the p-body region 28. A gate pad electrode (not shown) is connected to a gate electrode 38 located on a gate insulating film 32. The source pad electrode SP and the gate pad electrode (not shown) are also located on an interlayer insulating film 44 for passivation that covers the surface of the semiconductor device 100, as shown in Figure 4.

[0068] As shown in Figure 4, the SiC DIMISFET has n sandwiched between p-body regions 28. - Because a depletion layer, as shown by the dashed line, is formed within the semiconductor substrate 26 consisting of a high-resistance layer, the channel resistance R associated with the junction FET (JFET) effect is formed. JFET A body diode BD is formed between the p-body region 28 and the semiconductor substrate 26.

[0069] Furthermore, the MISFET can be constructed as a SiC trench (T: Trench) MISFET. Here, Figure 5 shows a schematic cross-sectional structure of a SiC TMISFET, which is an example of a semiconductor device 100 applicable to the power conversion circuit 1.

[0070] As shown in Figure 5, the SiC TMISFET consists of a semiconductor substrate 26N made up of n layers, a p-body region 28 formed on the surface side of the semiconductor substrate 26N, and n-body region 28 formed on the surface of the p-body region 28. +A trench gate electrode 38TG is formed within a trench that penetrates the source region 30 and the p-body region 28 and extends to the semiconductor substrate 26N, via a gate insulating film 32 and interlayer insulating films 44U and 44B, and n + Source electrodes 34 connected to source region 30 and p-body region 28, and n arranged on the back surface opposite to the front surface of the semiconductor substrate 26N + drain region 24 and n + It comprises a drain electrode 36 connected to a drain region 24.

[0071] In Figure 5, the semiconductor device 100 has a trench gate electrode 38TG formed in a trench that penetrates the p-body region 28 and extends to the semiconductor substrate 26N, via a gate insulating film 32 and interlayer insulating films 44U and 44B. The source pad electrode SP is connected to a source electrode 34 connected to the source region 30 and the p-body region 28. A gate pad electrode (not shown) is connected to a gate electrode 38 placed on the gate insulating film 32. The source pad electrode SP and the gate pad electrode (not shown) are also placed on an interlayer insulating film 44U for passivation that covers the surface of the semiconductor device 100, as shown in Figure 5.

[0072] In SiC TMISFETs, the channel resistance R is associated with the junction FET (JFET) effect, similar to that of SiC DIMISFETs. JFET It is not formed. Also, the p-body region 28, the semiconductor substrate 26, and n + A body diode BD is formed between the drain regions 24.

[0073] Furthermore, the semiconductor devices 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1 can also be replaced with GaN-based FETs or the like instead of SiC-based MISFETs.

[0074] Furthermore, the semiconductor devices 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1 can be semiconductors with a bandgap energy of, for example, 1.1 eV to 8 eV.

[0075] (modified version) Furthermore, the connection relationship between the switching element and the synchronous rectifier element of the power conversion circuit 1 may be such that, as shown in Figure 6, the source S4 of the MISFET chip Q4, which operates as a switching element, is electrically connected to the drain D1 of the MISFET chip Q1, which operates as a synchronous rectifier element, via the inductance L4. In addition, as shown in Figures 7 and 8, the power conversion circuit shown in Figures 1 and 6 may be further configured to include a power supply E, a capacitor C, and an inductor L.

[0076] (Power module) As mentioned above, the power module equipped with the power conversion circuit 1 can have a half-bridge integrated module configuration. The power module has MISFET chips Q1 and Q4 integrated into a single module. Figure 3 shows an example in which four MISFET chips Q1 and Q4 are arranged in parallel.

[0077] Figures 9-11 show an example of a simplified schematic planar pattern configuration in a power module.

[0078] As shown in Figure 9, the transistor including the MISFET chip Q1 has a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 has a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via wiring W11. The gate of the MISFET chip Q1 is also electrically connected to the source signal wiring pattern SL1 via wirings W1 and W2, and the transistor including the MISFET chip Q4 (specifically, the drain D4). The current path through wirings W1 and W2 and the transistor including the MISFET chip Q4 can carry a large current because its current tolerance is greater than that of the current path through wiring W11. Furthermore, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via wiring.

[0079] Furthermore, as shown in Figure 10, the transistor including the MISFET chip Q1 has a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 has a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via wiring W12. The gate of the MISFET chip Q1 is also electrically connected to the source signal wiring pattern SL1 via wirings W3 and W4 and the source S1 of the MISFET chip Q1. The current path through wirings W3 and W4 and the source S1 of the MISFET chip Q1 can carry a large current because its current tolerance is greater than that of the current path through wiring W12. Furthermore, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via wiring.

[0080] Furthermore, as shown in Figure 11, the transistor including the MISFET chip Q1 includes a source-sensing signal wiring pattern SSL1, a source-sensing signal wiring pattern SL1, and a gate-sensing signal wiring pattern GL1, while the transistor including the MISFET chip Q4 includes a source-sensing signal wiring pattern SSL4, a source-sensing signal wiring pattern SL4, and a gate-sensing signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate-sensing signal wiring pattern GL1 via wiring W12. The gate of the MISFET chip Q1 is also electrically connected to the source-sensing signal wiring pattern SL1 via wirings W3 and W4, and the source S1 of the MISFET chip Q1. The current paths through wirings W3 and W4, and the source S1 of the MISFET chip Q1, have a larger current tolerance than the current path through wiring W12, allowing for larger currents to flow. In addition, the gate of the MISFET chip Q4 is directly connected to the gate-sensing signal wiring pattern GL4 and the source-sensing signal wiring pattern SSL4 via wiring. Furthermore, the gate of the MISFET chip Q4 is electrically connected to the source signal wiring pattern SL4 via wirings W1 and W2 and the transistor containing the MISFET chip Q1 (specifically, the drain D1). The current path through wirings W1 and W2 and the transistor containing the MISFET chip Q1 can carry a large current because its current tolerance is greater than that of the current path through wiring W11.

[0081] In the power module shown in Figure 11, either MISFET chip Q1 or MISFET chip Q4 functions as a switching element. The source-sense signal wiring of the transistor containing the MISFET functioning as the switching element should be controlled to connect to the MISFET.

[0082] Note that each signal wiring of the power module shown in Figures 9-11 is connected to an external output terminal (not shown in the symbols).

[0083] (converter) Figure 14 is a circuit diagram showing a current-mode synchronous rectification step-down DC / DC converter equipped with a power module according to this embodiment. The DC / DC converter 51 steps down the input voltage Vin supplied to the input terminal VIN to generate a desired output voltage Vout at the output terminal VOUT.

[0084] The DC / DC converter 51 includes a switching element T11, a rectifier element T12, a drive circuit 53, a feedback voltage generation circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generation circuit 61, an inductor L11, and a smoothing capacitor C1.

[0085] The switching element T11 is an N-channel type MOS (Metal Oxide Semiconductor) field-effect transistor connected to the drive circuit 53, the output current detection unit 54, and the rectifier element T12. It functions as a switching transistor that controls the current flowing through the inductor L11 by repeatedly switching on and off. The drain D of the switching element T11 is connected to the input terminal VIN. The source S of the switching element T11 is connected to the drain D of the rectifier element T12. A gate signal GH is applied to the gate G of the switching element T11 from the drive circuit 53. The source voltage of the switching element T11 is also fed back to the drive circuit 53 via the source sense signal wiring SS. The switching element T11 is off when the gate signal GH is low level and on when the gate signal GH is high level. The rectifier element T12 supplies current to the inductor L11 when the switching element T11 is off.

[0086] The rectifier element T12 is an N-channel MOS field-effect transistor connected to the switching element T11 and the drive circuit 53, and operates synchronously and complementaryly with the switching element T11 as a synchronous rectifier transistor. The drain D of the rectifier element T12 is connected to the source S of the switching element T11. The common connection point between the rectifier element T12 and the switching element T11 is shown as node N1. The rectifier element T12 is turned on when the switching element T11 is off, and turned off when the switching element T11 is on. The source S of the rectifier element T12 is connected to ground potential GND. A gate signal GL is applied to the gate G of the rectifier element T12 from the drive circuit 53. The rectifier element T12 is turned on when the gate signal GL is at a high level, and turned off when the gate signal GL is at a low level.

[0087] By switching the switching element T11 and the rectifying element T12 on and off in a complementary manner, a rectangular wave switching voltage Vsw appears at node N1. By smoothing this switching voltage Vsw with inductor L11 and smoothing capacitor C1, the output voltage Vout is obtained at the output terminal VOUT. Inductor L11 and smoothing capacitor C1 are connected in series between node N1 and ground potential GND, and their common connection point is indicated by node N2. At node N2, the voltage generated across smoothing capacitor C1, i.e., the output voltage Vout, is generated.

[0088] In the DC / DC converter 51, a step-down type switch output stage is formed by using a switching element T11, a rectifier element T12, an inductor L11, and a smoothing capacitor C1 to step down the input voltage Vin supplied to the input terminal VIN and generate a desired output voltage Vout at the output terminal VOUT.

[0089] When integrating the components of the DC / DC converter 51 into an IC, the switching element T11 and the rectifier element T12 can be built into the IC or attached externally. If attached externally, external terminals are required for external output of the gate signal GH and the gate signal GL, respectively. An N-channel MOS field-effect transistor can also be used as the switching element T11. IGBTs can also be used as the switching element T11 and the rectifier element T12. Furthermore, the switching element T11 and the rectifier element T12 may be composed of bipolar transistors.

[0090] The drive circuit 53 is provided with a section (so-called dead time) in which the gate signal GH is low and the gate signal GL is low, so as to prevent excessive through-current flowing from the switching element T11 to the rectifier element T12, while the gate signal GH is high and the gate signal GL is not high.

[0091] Furthermore, the drive circuit 53 also has a function to forcibly stop the switching operation of the switch output stage in response to an abnormal protection signal (not shown) (a function that sets the gate signal GH output to the switching element T11 to a low level and the gate signal GL output to the rectifier element T12 to a low level).

[0092] The feedback voltage generation circuit 56 consists of resistors R1 and R2 connected in series between the output terminal VOUT and the ground potential GND, and outputs a feedback voltage Vfb from node N3, which is their common connection point. The feedback voltage Vfb is a voltage proportional to the voltage generated across the smoothing capacitor C1, and is also a DC voltage proportional to the output voltage Vout generated at the output terminal VOUT.

[0093] The error amplifier 57 generates an error voltage Verr according to the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (-). The error voltage Verr rises when the feedback voltage Vfb is lower than the reference voltage Vref, and falls when the feedback voltage Vfb is higher than the reference voltage Vref. The error voltage Verr is output from the output side of the error amplifier 57. Alternatively, the error amplifier 57 can output the error voltage as a current instead of a voltage. An error amplifier with this configuration is known as a transconductance error amplifier.

[0094] The phase compensation circuit 58 consists of a series circuit of a resistor R3 and a capacitor C3 connected in series between the output terminal of the error amplifier 57 and the ground potential GND. It is well known that such a phase compensation circuit is used in DC / DC converters. The phase compensation circuit 58 is used to increase the phase margin, that is, the difference relative to the 180-degree phase delay in the DC / DC converter 51. For example, if the phase when the loop gain of the DC / DC converter 51 is 0 dB (gain 1) is, for example, 120 degrees, then the phase margin is 180 degrees - 120 degrees = 60 degrees. It is said that a phase margin of, for example, 45 degrees or more is sufficient.

[0095] The PWM comparator 60 compares the error voltage Verr applied to the inverting input terminal (-) with the slope signal Vsl applied to the non-inverting input terminal (+) to generate a pulse width modulated signal pwm. Based on the pulse width modulated signal pwm, the DC / DC converter 51 performs PWM control.

[0096] The pulse width modulated signal pwm output from the PWM comparator 60 is applied to the subsequent drive circuit 53, which complementaryly turns the switching element T11 and the rectifier element T12 on and off. Inside the drive circuit 53, a sequential circuit (e.g., an RS flip-flop) is provided (not shown). A clock signal is applied to the set terminal of this RS flip-flop, and the pulse width modulated signal pwm is applied to the reset terminal. In this case, the clock signal corresponds to the set signal of the RS flip-flop, and the pulse width modulated signal pwm corresponds to the reset signal of the RS flip-flop.

[0097] The slope voltage generation circuit 61 generates a slope signal Vsl in order to operate the PWM comparator 60 with pulse width modulation. The slope signal Vsl is a triangular waveform signal generated based on the clock signal.

[0098] The converter equipped with the power module according to this embodiment employs a power conversion circuit that includes a switching element connected to the source sense signal wiring and a rectifier element not connected to the source sense signal wiring. This allows for the utilization of the switching characteristics of the switching element connected to the source sense signal wiring, while also utilizing the low starting point of voltage rise of the rectifier element not connected to the source sense signal wiring to suppress false on-on events and ensure operational stability.

[0099] Figure 15 is a circuit diagram showing a current-mode synchronous rectification boost type DC / DC converter equipped with a power module according to this embodiment. The DC / DC converter 72 boosts the input voltage Vin supplied to the input terminal VIN to generate a desired output voltage Vout at the output terminal VOUT.

[0100] The DC / DC converter 72 includes a switching element T21, a rectifier element T22, a drive circuit 53, a feedback voltage generation circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generation circuit 61, an inductor L12, and a smoothing capacitor C2.

[0101] The DC / DC converter 72 differs from the step-down type shown in Figure 14 in the circuit section after the drive circuit 53. The other circuit sections are the same. This section will explain the differences between the two circuits.

[0102] The switching element T21 is an N-channel MOS field-effect transistor connected to the rectifier element T22, the drive circuit 53, and the inductor L12. It functions as a switching transistor that controls the current flowing through the inductor L12 by repeatedly switching on and off. The switching element T21 operates synchronously and complementaryly with the rectifier element T22. The source S of the switching element T21 is connected to ground potential GND. The drain D of the switching element T21 is commonly connected to the source S of the rectifier element T22 and one end of the inductor L12. This common connection point is indicated by node N1. A gate signal GL is applied to the gate G of the switching element T21 from the drive circuit 53. In addition, the source voltage of the switching element T21 is fed back to the drive circuit 53 via a source sense signal wiring SS. The switching element T21 turns on when the gate signal GL is high level and turns off when the gate signal GL is low level.

[0103] The other end of inductor L12 is connected to input terminal VIN, to which the input voltage Vin is supplied. In other words, the switching element T21 is coupled to the input voltage Vin via inductor L12. The current flowing through inductor L12 is controlled by the switching element T21.

[0104] The source S of the rectifier element T22 is connected to the drain D of the switching element T21 and one end of the inductor L12. The drain D of the rectifier element T22 is connected to node N2, i.e., the output terminal VOUT. A gate signal GH is applied to the gate G of the rectifier element T22 from the drive circuit 53. The rectifier element T22 is turned off when the gate signal GH is low level and turned on when the gate signal GH is high level.

[0105] A smoothing capacitor C2 is connected between node N2, i.e., the output terminal VOUT, and the ground potential GND. The smoothing capacitor C2, along with the inductor L12 and the rectifier element T22, performs rectification and smoothing operations.

[0106] This explains how the synchronous rectification boost DC / DC converter 72 differs from the synchronous rectification buck DC / DC converter 51 shown in Figure 14. The other circuit parts are the same as in Figure 14, so their explanation is omitted. In the DC / DC converter 72 as well, switching elements connected to the source sense signal wiring and rectifier elements not connected to the source sense signal wiring are used. Although the DC / DC converter shown in Figure 14 is an example of a buck type and the DC / DC converter shown in Figure 15 is an example of a boost type, it goes without saying that this can also be applied to so-called buck-boost DC / DC converters that can switch between buck and boost modes.

[0107] Furthermore, although not shown in the diagram, it is also possible to configure an inverter equipped with the power conversion circuit of this embodiment. In order to make it function as an inverter, when the elements within the inverter are to function as switching elements, it is sufficient to control them so that the elements connected to the source sense signal wiring are used.

[0108] [Other embodiments] As described above, several embodiments have been described, but the descriptions and drawings that constitute part of the disclosure are illustrative and should not be understood as limiting. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure. Thus, this embodiment includes various embodiments and the like that are not described herein. [Explanation of symbols]

[0109] 10... Circuit board 24…n + Drain region 26, 26N... Semiconductor substrate (drift layer) 28...p body region 30…Source area 32…Gate insulating film 34…Source electrode 36... Drain electrode 38… Gate stop gate 38TG... Trench gate electrode 44, 44U, 44B... Interlayer insulating film 51, 72…DC / DC converters 53…Drive circuit 56…Feedback voltage generation circuit 57…Error Amplifier 58...Phase compensation circuit 60...PWM comparator 61... Slope voltage generation circuit 100... Semiconductor devices BD...Body Diode C, C3... Capacitors C1, C2... Smoothing Capacitors D, D1, D4... Drain D G1 , D G4 ...gate diode E…Power supply G, G1, G4... Gate GH, GL... Gate signals GL1, GL4…Gate signal wiring patterns GND…Ground potential GT1, GT4... Gate terminals I…constant current source IL…Load current L, L11, L12... Inductors L1, L2, L4, L GP1 , L SP1 , L GP4 , L SP4 ...inductance N... Negative power terminal N1, N2, N3... nodes O, VOUT…Output terminals P... Positive power terminal PWM... Pulse Width Modulation Signal Q, Q1, Q4…MISFET chips R1, R2, R3…Resistance R g1 , R g4 ...gate resistor RJFET ...channel resistance Ron...On-resistance S, S1, S4... Source SL1, SL4… Source signal wiring patterns ST1…Source terminal SP...Source pad electrode SS, SS1, SS4... Source sense signal wiring SSL1, SSL4... Source sense signal wiring patterns SST4... Source sense terminal SSW4... Source sense wire T11, T21... Switching elements T12, T22... Rectifier elements U1, U4... Transistors Verr…Error voltage Vfb...Feedback voltage V G1 , V G4 ...gate drive circuit Vin…Input Voltage VIN…Input terminal Vout… Output voltage Vref…Reference voltage Vsl... Slope signal W1, W2, W3, W4, W11, W12… Wiring

Claims

1. An insulating layer having a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern, and a fifth wiring pattern formed on its surface, A first transistor having a first surface electrode and a first control electrode on its surface, and a first back electrode on its back surface, wherein the first back electrode is arranged on the first wiring pattern and electrically connected, A second transistor having a second surface electrode and a second control electrode on its surface, and a second back surface electrode on its back surface, wherein the second back surface electrode is arranged on the second wiring pattern and electrically connected, Equipped with, The first surface electrode is connected to the third wiring pattern via a plurality of first source wires and to the fourth wiring pattern via a first source sense wire. The second surface electrode is connected to the first wiring pattern via a plurality of second source wires, and to the fifth wiring pattern via the first wiring pattern and second source sense wires. Each of the first wiring pattern, the second wiring pattern, the third wiring pattern, the fourth wiring pattern, and the fifth wiring pattern is connected to the corresponding external output terminal. The inductance of the first source sense wire and the fourth wiring pattern is smaller than the inductance of the second source sense wire and the fifth wiring pattern. Power module.

2. The first transistor and the second transistor are each made of SiCMISFETs. The first surface electrode is the source electrode, The first control electrode is an electrode, The first back electrode is a drain electrode. The power module according to claim 1.

3. The first wiring pattern is connected to the output terminal. The third wiring pattern is connected to the low-potential power supply terminal. The second wiring pattern is connected to the high-potential side power supply terminal. The fourth wiring pattern is connected to the source sense terminal. The power module according to claim 1.

4. The power module according to any one of claims 1 to 3, wherein the fourth wiring pattern is arranged on the opposite side of the third wiring pattern so as to sandwich the first transistor in a plan view.

5. A sixth wiring pattern is formed on the surface of the insulating layer. The current tolerance of the plurality of second source wires is greater than the current tolerance of the gate wire that directly connects the sixth wiring pattern and the second control electrode. The power module according to claim 1.

6. An insulating layer having a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern, and a fifth wiring pattern formed on its surface, A first transistor having a first surface electrode and a first control electrode on its surface, and a first back electrode on its back surface, wherein the first back electrode is arranged on the first wiring pattern and electrically connected, A second transistor having a second surface electrode and a second control electrode on its surface, and a second back surface electrode on its back surface, wherein the second back surface electrode is arranged on the second wiring pattern and electrically connected, Equipped with, The first surface electrode is connected to the third wiring pattern via a plurality of first source wires. The second surface electrode is connected to the first wiring pattern via a plurality of second source wires and to the fifth wiring pattern via a second source sense wire. Each of the first wiring pattern, the second wiring pattern, the third wiring pattern, the fourth wiring pattern, and the fifth wiring pattern is connected to a corresponding terminal for external connection. A sixth wiring pattern and a seventh wiring pattern are formed on the surface of the insulating layer. The sixth wiring pattern is connected to the third wiring pattern via the first source sense wire. The seventh wiring pattern is connected to the first wiring pattern via a third source-sensing wire. The inductance of the second source sense wire and the fifth wiring pattern is smaller than the inductance of the plurality of first source wires, the third wiring pattern, the first source sense wire and the sixth wiring pattern. Power module.

7. The first transistor and the second transistor are each made of SiCMISFETs. The second surface electrode is the source electrode, The second control electrode is an interface electrode, The second back electrode is the drain electrode. The power module according to claim 6.

8. The first wiring pattern is connected to the output terminal. The third wiring pattern is connected to the low-potential power supply terminal. The second wiring pattern is connected to the high-potential side power supply terminal. The fifth wiring pattern is connected to the source sense terminal. The power module according to claim 6.

9. The power module according to any one of claims 6 to 8, wherein the fourth wiring pattern is arranged on the opposite side from the third wiring pattern so as to sandwich the first transistor in a plan view.

10. An eighth wiring pattern is formed on the surface of the insulating layer. The current tolerance of the plurality of first source wires is greater than the current tolerance of the gate wire that directly connects the eighth wiring pattern and the first control electrode. The power module according to claim 6.

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