Oxidation barrier using CVD immersion process

Abstract

A method of forming an oxide barrier layer in a semiconductor structure includes forming a contact layer on an exposed surface of a semiconductor region of the semiconductor structure in a first processing chamber, where the semiconductor region includes silicon germanium doped with a p-type dopant, and the contact layer includes silicon germanium (SiGe) having a germanium (Ge) ratio in the range between 60% and 100%, forming the contact layer, and forming an oxide barrier layer containing gallium (Ga) on the contact layer by applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer in the first processing chamber.

Description

[Technical Field]

[0001] The embodiments described herein relate generally to semiconductor device manufacturing, and more specifically to systems and methods for forming contacts within semiconductor structures. [Background technology]

[0002] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), such as complementary metal-oxide-semiconductor (CMOS) devices, present manufacturability challenges due to their three-dimensional (3D) design and small size. In advanced CMOS devices, contact resistivity is 10 -9 Ωcm 2To reduce the contact resistance to a certain level and achieve the performance required for advanced CMOS technology, an epitaxial layer of silicon-containing material (e.g., boron-doped p-type silicon germanium, or phosphorus-doped n-type silicon) formed at the bottom of the trench contact is often utilized. Generally, the p-type epitaxial layer is formed from silicon germanium (SiGe) with a high germanium (Ge) concentration, e.g., about 60% and about 80%, or in some cases 100%, to minimize contact resistance. However, it is known that silicon germanium (SiGe) epitaxial layers with high germanium (Ge) concentrations undergo rapid surface oxidation in an atmospheric environment, thereby forming germanium oxides and suboxides. These oxide layers introduce residual oxygen at the interface between the silicon germanium (SiGe) epitaxial layer and the metal silicide layer formed on top of the epitaxial layer, which can increase contact resistance. These oxide layers can be removed by sputtering-based pre-cleaning processes, but such pre-cleaning processes can have adverse effects, including the generation of crystal defects, dopant deactivation, and material removal in the epitaxial layer, all of which can lead to a degradation of electrical performance. Sputtering-based pre-cleaning processes can also cause degradation of the surrounding dielectric structure (e.g., expansion of the trench limit dimension (CD), top corner rounding).

[0003] Therefore, there is a need for methods and systems that can prevent or delay the oxidation of a portion of a silicon germanium (SiGe) semiconductor device with a high germanium (Ge) concentration in an atmospheric environment. [Overview of the project]

[0004] Embodiments of the present disclosure provide a method for forming an oxide barrier layer in a semiconductor structure. The method includes forming a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in a first processing chamber, wherein the semiconductor region comprises silicon germanium doped with a p-type dopant, and the contact layer comprises silicon germanium (SiGe) having a germanium (Ge) ratio in the range of 60% to 100%, and forming a gallium (Ga)-containing oxide barrier layer on the contact layer by coating the surface of the contact layer in the first processing chamber with a gallium (Ga)-containing liquid precursor.

[0005] Embodiments of the present disclosure also provide a method for forming electrical contacts in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor region comprising a first material, wherein the exposed surface of the semiconductor region is positioned within an opening formed in a dielectric layer disposed above the semiconductor region; performing a selective epitaxial deposition process, including a first deposition process and a first etching process, to form a contact layer comprising a second material on the exposed surface of the semiconductor region; performing an immersion process to form an oxide barrier layer on the contact layer; performing a second deposition process to form a metal layer on the oxide barrier layer; and performing a metal filling process to form a contact plug in an opening in the dielectric layer, wherein the selective epitaxial deposition process and the immersion process are performed without disrupting the vacuum environment.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber and a system controller, the system controller configured to cause the processing system to perform the following actions in the first processing chamber: form a contact layer on an exposed surface of a semiconductor region of a semiconductor structure, wherein the semiconductor region comprises silicon germanium doped with a p-type dopant, and the contact layer comprises silicon germanium (SiGe) with a germanium (Ge) ratio in the range of 60% to 100%; and form an oxide barrier layer containing gallium (Ga) on the contact layer in the first processing chamber.

[0007] A more detailed description of the Disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings, so that the features described above can be understood in more detail. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the Disclosure, and therefore should not be considered to limit the scope of the Disclosure, as the Disclosure may allow for other equally effective embodiments. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2A] This is a cross-sectional view of a processing chamber according to one or more embodiments. [Figure 2B] This is a magnified view of a portion of the processing chamber shown in Figure 2A. [Figure 3] This is a cross-sectional view of a processing chamber according to one or more embodiments. [Figure 4] This diagram shows a process flow diagram of a method for forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure. [Figures 5A-5E] Figure 4 shows a cross-sectional view of a portion of the semiconductor structure corresponding to various states of the method. [Modes for carrying out the invention]

[0009] To facilitate understanding, equivalent reference numerals are used where possible to specify equivalent elements common to the figures. Elements and features of one embodiment are intended to be advantageously incorporated in other embodiments without further description.

[0010] Embodiments described herein provide a method and system for forming contacts comprising an epitaxial layer of silicon-containing material (e.g., boron-doped p-type silicon-germanium) having an oxide barrier layer thereon, in a selected portion of a structure used to form a CMOS device (e.g., on an exposed surface of a silicon-germanium layer). The method and system may be particularly useful for selectively forming an epitaxial layer of silicon-germanium with a high germanium concentration on an exposed surface of silicon-germanium material within an opening or feature (e.g., a contact trench) formed in a dielectric layer in a semiconductor structure having a region containing silicon-germanium and a dielectric layer formed thereon. Unlike conventional processes that require an etching process to remove germanium oxides from the surface of the epitaxial layer after exposure to an atmospheric environment, which tend to damage the manufactured semiconductor structure, the process described herein is configured to form an oxide barrier layer on the epitaxial layer that avoids or delays oxidation of the epitaxial layer in an atmospheric environment during the transition from the epitaxy process to subsequent processes such as silicification and patterning.

[0011] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with their respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., an atmospheric environment such as that which may be present in a manufacturing plant). For example, substrates can be processed in various chambers maintained in a low-pressure or vacuum environment without disrupting the low-pressure (e.g., about 300 Torre or less) or vacuum environment during various processes performed on the substrates in the processing system 100 and transferred between such various chambers. Therefore, the processing system 100 can contribute to an integrated solution for some kind of processing of the substrate.

[0012] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems commercially available from Applied Materials, Inc., Santa Clara, California. Other processing systems (including those from other manufacturers) are intended to be adapted to benefit from the embodiments described herein.

[0013] In the illustrated example in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate substrate transfer. The docking station 132 is adapted to receive one or more forward-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 positioned on one end of each factory interface robot 134, adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014] The load lock chambers 104 and 106 have ports 140 and 142, respectively, connected to the factory interface 102, and ports 144 and 146, respectively, connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150, respectively, connected to the holding chambers 116 and 118, and ports 152 and 154, respectively, connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158, respectively, connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166, respectively, connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be slit valve openings with slit valves, for example, for passing substrates through the slit valves by transfer robots 112 and 114, and for providing a seal between the chambers to prevent gas from passing between them. Generally, one of the ports is open for transferring substrates through it. In other cases, the ports are closed.

[0015] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluid-coupled to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), a gas source, various valves, and conduits fluid-coupled to the various chambers. During operation, the factory interface robot 134 transfers the substrate from FOUP 136 through port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 104 or 106 facilitates passing the substrate between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0016] Using the substrate in the pumped-down load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through port 144 or 146 into the transfer chamber 108. The transfer robot 112 can then transfer the substrate to any of the processing chambers 120, 122 through their respective ports 152, 154 for processing, and to any of the holding chambers 116, 118 through their respective ports 148, 150 for holding awaiting further transfer, and / or between them. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 through port 156 or 158 and transfer the substrate to any of the processing chambers 124, 126, 128, 130 through their respective ports 160, 162, 164, 166 for processing, and to any of the holding chambers 116, 118 through their respective ports 156, 158 for holding awaiting further transfer, and / or between them. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0017] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing a substrate. In some examples, the processing chamber 120 can be capable of performing an etching process, the processing chamber 122 can be capable of performing a cleaning process, and the processing chambers 126, 128, 130 can each be capable of performing an epitaxial growth process. The processing chamber 120 can be a Selectra (trademark) Etch chamber available from Applied Materials of Santa Clara, California. The processing chamber 122 can be a SiCoNi (trademark) Pre-clean chamber available from Applied Materials of Santa Clara, California. The processing chamber 126, 128, or 130 can be a Centura (trademark) Epi chamber available from Applied Materials of Santa Clara, California.

[0018] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. During operation, the system controller 168 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0019] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuitry 174. The CPU 170 can be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of digital storage, local or remote. The support circuitry 174 is coupled to the CPU 170 and can include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. The various methods disclosed herein can generally be implemented under the control of the CPU 170 by, for example, the CPU 170 executing computer instruction code stored in the memory 172 (or the memory of a particular processing chamber) as software routines. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to execute a process according to various methods.

[0020] Other processing systems can have other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0021] FIG. 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments adapted to perform a pre-cleaning process detailed below. The processing chamber 200 can be the processing chamber 122 shown in FIG. 1. FIG. 2B is an enlarged view of a portion of the processing chamber 200 of FIG. 2A.

[0022] The processing chamber 200 may be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at the upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed within the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling the processes within the processing chamber 200.

[0023] The lid assembly 204 includes stacked components adapted to supply a precursor gas and / or plasma to a processing area 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power source (not shown) for supplying plasma to a conical chamber 222 formed within the lid assembly 204. The lid assembly 204 may also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma cavity (e.g., the processing area 214, the first plate 216, and the second plate 218 in Figures 2A–2B) is coupled to a gas source 226 via the remote plasma source 224 (or, if there is no remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 may include a gas source adapted to supply helium, argon, or other inert gas. In some configurations, the gas supplied by the gas source 226 can be energized to become plasma supplied to the lid assembly 204 by the use of a remote plasma source 224. In an alternative embodiment, the gas source 226 may supply a process gas that can be activated by the remote plasma source 224 before being introduced onto the surface of a substrate disposed within the processing chamber 200. Referring to Figure 2B, the conical chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 into a volume 230 formed in the fourth plate 232 of the lid assembly 204.

[0024] In some configurations of the lid assembly 204, plasma is generated within the conical chamber 222 by the application of energy supplied from a plasma source. In one example, the energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy with the gas located within the conical chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 may not be used and may not be located within the lid assembly 204.

[0025] The central conduit 234, formed in the fourth plate 232, is adapted to supply plasma-generating species from the volume 230 through the fifth plate 236 to the mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204. The central conduit 234 connects to the mixing chamber 238 through an opening 242 in the fifth plate 236. The opening 242 may have a diameter smaller than the diameter of the central conduit 234, a diameter larger than the diameter of the central conduit 234, or the same diameter as the central conduit 234. In the embodiment of Figure 2B, the opening 242 has the same diameter as the central conduit 234.

[0026] The fourth plate 232 also includes inlets 244 and 246 adapted to supply gas to the mixing chamber 238. Inlet 244 is coupled to the first gas source 248, and inlet 246 is coupled to the second gas source 250. The first gas source 248 and the second gas source 250 may contain a process gas as well as an inert gas, such as argon and / or helium used as a carrier gas. The first gas source 248 may contain ammonia (NH3) and argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) and argon (Ar).

[0027] As shown in Figure 2B, in some configurations, the inlet 244 is connected to the mixing chamber 238 through a cylindrical channel 252 (shown by a hidden line) and a hole 254 formed in the fifth plate 236. The inlet 246 is connected to the mixing chamber 238 through a cylindrical channel 256 (shown by a hidden line) and a hole 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized so that their holes allow for a uniform flow of gas supplied into the mixing chamber 238 from their respective gas sources 248, 250. In one configuration, the holes 258 have a diameter smaller than the width of the opening defined by the opposite side wall of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are generally distributed around the centerline of the cylindrical channel 256 to provide a uniform fluid flow into the mixing chamber 238. In one configuration, the holes 254 have a diameter smaller than the width of the opening defined by the opposite side wall of the cylindrical channel 252 formed in the fourth plate 232. The holes 254 are generally distributed around the centerline of the cylindrical channel 252 to provide a uniform fluid flow in the mixing chamber 238.

[0028] Inlets 244 and 246 pass laterally through the fourth plate 232, turn toward the fifth plate 236, penetrate the fifth plate 236, and provide their respective fluid passages to the mixing chamber 238. The lid assembly 204 also includes a seventh plate or a first gas distributor 260, which may be a gas distribution plate such as a showerhead, and the various gases mixed in the lid assembly 204 flow through through-holes 262 formed in the lid assembly 204. The through-holes 262 are fluidly connected to the mixing chamber 238 to provide a passage from the mixing chamber 238 through the first gas distributor 260. Referring again to Figure 2A, a blocker plate 264 and gas distribution plates such as a second gas distributor 266, which may be a gas distribution plate such as a showerhead, are disposed below the lid assembly 204.

[0029] Alternatively, different cleaning processes may be used to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 through the lid assembly 204, or ammonia (NH3) may be injected directly into the processing chamber 200 via a separate gas inlet 268 located on the side of the chamber body 202 and coupled to a gas source (not shown).

[0030] The support assembly 206 may include a substrate support 270 for supporting a substrate 272 on it during processing. The substrate support 270 may be coupled to an actuator 274 by a shaft 276 extending through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by a bellows (not shown) to prevent vacuum leakage around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below an opening in a tunnel (not shown) formed in the side wall of the chamber body 202.

[0031] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. For some process operations, the substrate support 270 can be raised to a position very close to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated via radiation emitted from a second gas distributor 266 or another radiation source, or by convection or conduction from the second gas distributor 266 through an intervening gas. In some process operations, the substrate can be positioned on a lift pin 278 to perform additional heat treatment steps, such as performing an annealing step.

[0032] Figure 3 is a cross-sectional view of a processing chamber 300 according to one or more embodiments adapted to perform the epitaxial (Epi) deposition process detailed below. The processing chamber 300 may be the processing chambers 126, 128, or 130 shown in Figure 1.

[0033] The processing chamber 300 includes a housing structure 302 manufactured from a process-resistant material, such as aluminum or stainless steel, for example, 316L stainless steel. The housing structure 302 encloses various functional elements of the processing chamber 300, including a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, both containing the processing volume 310. A gas distribution assembly 312 supplies the reaction species to the quartz chamber 304, and processing byproducts are removed from the processing volume 310 by an outlet port 314, which is generally connected to a vacuum source (not shown).

[0034] The substrate support 316 is adapted to receive the substrate 318 transferred to the processing volume 310. The substrate support 316 is positioned along the longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be manufactured from a ceramic or graphite material coated with a silicon material, such as silicon carbide or other process-resistant material. Reactants from a precursor reactant material are added to the surface 322 of the substrate 318, and then by-products can be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing volume 310 may be performed by radiation sources such as the upper lamp module 324A and the lower lamp module 324B.

[0035] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from lamp modules 324A and 324B travels through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. Cooling gas for the upper quartz chamber 306 enters through the inlet 330 and exits through the outlet 332, if necessary. Precursor reactant material, as well as dilution gas, purge gas, and vent gas for the processing chamber 300, enters through the gas distribution assembly 312 and exits through the outlet port 314. Although the upper quartz window 326 is shown as curved or convex, the upper quartz window 326 can be flat or concave, since the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0036] The low-wavelength radiation in the processing volume 310, used to energize the reactants and assist in the adsorption of reactants from the surface 322 of the substrate 318 and the desorption of process by-products, is generally in the range of about 0.8 μm to about 1.2 μm, for example, between about 0.95 μm and about 1.05 μm, and various combinations of wavelengths are given depending on the composition of the film being epitaxially grown.

[0037] The component gases enter the processing volume 310 via a gas distribution assembly 312. The gases flow out of the gas distribution assembly 312 and exit through an outlet port 314, as generally indicated by a flow path 334. The combination of component gases used to clean / passivate the substrate surface or to form a silicon and / or germanium-containing film being epitaxially grown is generally mixed before entering the processing volume 310. The overall pressure in the processing volume 310 can be regulated by a valve (not shown) on the outlet port 314. At least a portion of the inner surface of the processing volume 310 is covered by a liner 336. In one embodiment, the liner 336 comprises an opaque quartz material. In this way, the chamber walls are insulated from the heat in the processing volume 310.

[0038] The surface temperature in the processing volume 310 can be controlled within a temperature range of approximately 200°C to approximately 600°C or higher by the flow of cooling gas entering through the inlet 330 and exiting through the outlet 332, combined with radiation from the upper lamp module 324A located above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of approximately 200°C to approximately 600°C or higher by adjusting the speed of a blower unit (not shown) and by radiation from the lower lamp module 324B located below the lower quartz chamber 308. The pressure in the processing volume 310 can be between approximately 0.1 Torre and approximately 600 Torre, such as between approximately 5 Torre and approximately 30 Torre.

[0039] The temperature on the surface 322 of the substrate 318 can be controlled by power adjustment for the lower lamp module 324B in the lower quartz chamber 308, or by power adjustment for both the upper lamp module 324A above the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing volume 310 is approximately 80 W / cm². 2 ~Approx. 120W / cm 2 For example, approximately 40W / cm² 2 And approximately 400W / cm² 2 It could be between these two.

[0040] In one embodiment, the gas distribution assembly 312 is positioned perpendicular to the longitudinal axis 320 of the processing chamber 300 or the substrate 318, or radially 338 relative to the longitudinal axis 320 of the processing chamber 300 or the substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas radially 338 across the surface 322 of the substrate 318, or parallel to the surface 322 of the substrate 318. In one processing application example, the process gas is preheated at the time of introduction into the processing chamber 300 in order to initiate preheating of the gas before introduction into the processing volume 310 and / or to break certain bonds in the gas. In this way, the surface reaction characteristics can be modified independently of the thermal temperature of the substrate 318.

[0041] During operation, precursors used to form silicon (Si) and silicon germanium (SiGe) blankets or selective epitaxial films are supplied to the gas distribution assembly 312 from one or more gas sources 340A and 340B. An IR lamp 342 (only one is shown in Figure 3) may be used to heat the precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A and 340B may be coupled to the gas distribution assembly 312 in a manner adapted to facilitate introduction zones within the gas distribution assembly 312, such as radially outer and radially inner zones between the outer zones when viewed in plan. The gas sources 340A and 340B may include valves (not shown) for controlling the rate of change of introduction into the zones.

[0042] Gas sources 340A and 340B may contain silicon precursors such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher-order silanes, their derivatives, and combinations thereof. Gas sources 340A and 340B may also contain germanium-containing precursors such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), their derivatives, and combinations thereof. Silicon and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. Gas sources 340A and 340B may contain one or more silicon and germanium-containing precursors in one or both of gas sources 340A and 340B.

[0043] The precursor material, in one embodiment, is a quartz material having pores 344 formed through it, enters the processing volume 310 through the openings or pores 344 (only one is shown in Figure 3) in the perforated plate 346 in this excited state. The perforated plate 346 may be made from a transparent quartz material that transmits IR energy. In other embodiments, the perforated plate 346 may be any material that transmits IR energy and is resistant to process chemistry and other processing chemistry. The energized precursor material flows toward the processing volume 310 through the pores 344 in the perforated plate 346 and through the channel 348 (only one is shown in Figure 3). Also, a portion of the photons and non-thermal energy from the IR lamp 342 are facilitated by a reflective material and / or surface disposed on the inner surface of the gas distribution assembly 312, passing through the pores 344, the perforated plate 346, and the channel 348, thereby illuminating the flow path 334 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained from the time of its introduction into the processing volume 310 along the flow path.

[0044] Figure 4 shows a process flow diagram of a method 400 for forming a contact layer in a semiconductor structure 500 formed on a substrate, according to one embodiment of the present disclosure. Figures 5A, 5B, 5C, 5D, and 5E are cross-sectional views of portions of the semiconductor structure 500 corresponding to various states of the method 400. It should be understood that Figures 5A, 5B, 5C, 5D, and 5E are only partial schematic diagrams of the semiconductor structure 500, and the semiconductor structure 500 may include any number of transistor sections and additional materials having the embodiments shown in the figures. Also note that although the method shown in Figure 4 is described sequentially, other process sequences including one or more operations, which may be omitted and / or added, and / or rearranged in a different preferred order, fall within the scope of the embodiments of the present disclosure provided herein.

[0045] As used herein, the term "substrate" refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate can be a silicon-based material or any suitable insulating or conductive material, as needed. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon (developed by IBM), silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0046] As shown in FIG. 5A, the semiconductor structure 500 includes a semiconductor region 502 formed on a substrate (not shown). The semiconductor region 502 is formed from a first material, such as silicon germanium (SiGe) or germanium tin (GeSn), and can be doped with a p-type dopant, such as boron (B) or gallium (Ga), having a concentration between about 10 20 cm -3 and 5×10 21 cm -3 The semiconductor structure 500 further includes a dielectric layer 504 having an opening 506 formed on the semiconductor region 502. The dielectric layer 504 can be formed from a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0047] The semiconductor region 502 can be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the opening 506 can be formed by patterning techniques, such as lithography and etching processes.

[0048] The semiconductor region 502 can be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the opening 506 can be formed by patterning techniques, such as lithography and etching processes.

[0049] Method 400 begins with a pre-cleaning process in block 410. The pre-cleaning process may be performed in an etching chamber, such as the processing chamber 122 shown in Figure 1, or the processing chamber 200 shown in Figure 2.

[0050] The pre-cleaning process removes contaminants such as native oxide layers or patterning residues (e.g., carbon fluoride) formed on the exposed surface of the semiconductor region 502 within the opening 506. The pre-cleaning process is used to prepare the exposed surface of the semiconductor region 502 within the opening 506 so that an epitaxial layer may be formed on such exposed surface during the subsequent epitaxial deposition process.

[0051] The pre-cleaning process may include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process using a plasma formed from a gas containing argon (Ar), helium (He), or a combination thereof. The plasma ejecta strike the residual dielectric layer in the aperture 506 in one direction, removing the residual dielectric layer.

[0052] The pre-cleaning process may include an isotropic plasma etching process, such as a SiCoNi® dry chemical etching process, using a plasma formed from a gas containing ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. Dry chemical etching processes are selective for oxide layers and therefore do not readily etch silicon, germanium, or nitride layers, whether those layers are amorphous, crystalline, or polycrystalline. The selectivity of dry chemical etching processes for oxides to silicon or germanium is at least about 3:1, typically 5:1 or higher, and sometimes 10:1. Dry chemical etching processes are also highly selective for oxides to nitrides. The selectivity of dry chemical etching processes for nitrides is at least about 3:1, typically 5:1 or higher, and sometimes 10:1.

[0053] The pre-cleaning process may include an inductively coupled plasma (ICP) etching process using a plasma formed from a gas containing chlorine (Cl2) and hydrogen (H2) and a carrier gas containing argon (Ar) and helium (He).

[0054] In block 420, as shown in Figure 5B, a selective epitaxial deposition process is performed to epitaxially form a contact layer 508 on the exposed surface of the semiconductor region 502 within the opening 506. The selective epitaxial deposition process may be performed in an epi chamber, such as the processing chambers 126, 128, or 130 shown in Figure 1, or the processing chamber 300 shown in Figure 3.

[0055] The contact layer 508 is formed as an interface between the semiconductor region 502 and a metal contact plug to be formed in the opening 506 to minimize parasitic resistance. The contact layer 508 may be formed from a second material, such as silicon germanium (SiGe), in which the germanium (Ge) ratio is in the range of about 20% to about 100%, for example, between about 60% and about 80%, between about 60% and about 100%, or between about 80% and about 100%. Depending on the desired conductivity of the contact layer 508, the contact layer 508 is formed from about 10 20 cm -3 and 5 x 10 21 cm -3 It can be doped with p-type dopants such as boron (B) or gallium (Ga) in concentrations between 1 and 2.

[0056] In some embodiments, the selective epitaxial deposition process includes a first deposition process and a first etching process, the first deposition process being an epitaxial deposition process. The selectivity in the selective epitaxial deposition process may arise from the difference between nucleation of a second material on the exposed surface of a semiconductor region 502 (e.g., silicon germanium (SiGe)) and nucleation of a dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) on the exposed surface. Nucleation can occur at a faster rate of change on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)) than on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). Therefore, an epitaxial layer of the second material can be formed on the exposed surface of the semiconductor region 502 (e.g., silicon germanium (SiGe)), while an amorphous layer of the second material can be formed on the exposed surface of the dielectric layer 504 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) when the semiconductor structure 500 is exposed to the deposition gas during the first deposition process. In a subsequent first etching process, the amorphous layer of the second material formed on the exposed surface of the dielectric layer 504 can be removed by a suitable etching gas at a faster rate of change than the epitaxial layer of the second material formed on the exposed surface of the semiconductor region 502. Therefore, as an overall result of combining the first deposition process and the first etching process, epitaxial growth of the second material on the exposed surface of the semiconductor region 502 becomes possible while minimizing the growth of the second material on the exposed surface of the dielectric layer 504, if any.

[0057] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10), or combinations thereof. Germanium-containing precursors may include germanium (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). Dopant sources may include boron or gallium, for example, depending on the desired conductivity of the contact layer 508. Dopant sources may include precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas may include halogen-containing gases such as hydrogen chloride (HCl), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0058] The first deposition process and the first etching process can be carried out at low temperatures below approximately 450°C and at pressures between 5 Torre and 600 Torre.

[0059] The cycle of the first deposition and the first etching process may be repeated as needed to obtain the desired thickness of the contact layer 508. The thickness of the contact layer 508 may be between approximately 30 Å and approximately 100 Å.

[0060] In block 430, a CVD immersion process is performed to form an oxide barrier layer 510 on the contact layer 508, as shown in Figure 5C. The CVD immersion process may be performed in situ within the same epi chamber as in the selective epitaxial deposition process in block 420, such as in the processing chambers 126, 128, or 130 shown in Figure 1, or the processing chamber 300 shown in Figure 3.

[0061] In the CVD immersion process, the surface of the contact layer 508 is exposed to a gallium (Ga)-containing liquid precursor at a temperature in the range of approximately 300°C to approximately 400°C in order to form a thin gallium layer (e.g., an oxide barrier layer 510) on the contact layer 508. The processing chamber or semiconductor structure 500 may be heated to a temperature in the range of approximately 300°C to approximately 400°C. The CVD immersion process may last for a time period of approximately 1 second to approximately 60 seconds, for example, approximately 2 seconds to approximately 30 seconds. In the CVD immersion process, gallium atoms in the gallium-containing liquid precursor diffuse and deposit on the surface of the contact layer 508 to form a thin gallium layer. This thin gallium layer acts as an oxide barrier layer 510, which can avoid or delay oxidation of the contact layer 508 during air isolation for transferring the semiconductor structure 500 from the epi chamber to another processing chamber for subsequent processes, such as a deposition process in block 440 or a patterning process.

[0062] In block 440, a second deposition process is performed, as shown in Figure 5D. The second deposition process may be performed in a different processing chamber than the epi chambers in blocks 420 and 430, such as processing chambers 126, 128, or 130 shown in Figure 1, or processing chamber 300 shown in Figure 3. The semiconductor structure 500 may be exposed to the atmosphere during transfer from the epi chambers used in blocks 420 and 430 to the processing chamber used in block 440. However, the oxide barrier layer 510 on the contact layer 508 may protect the contact layer 508 from oxidation during transfer, or delay the oxidation of the contact layer 508.

[0063] In the second deposition process, a metal layer 512 is formed on the oxide barrier layer 510. The metal layer 512 contacts the contact layer 508, maintaining electrical connections through it, and provides an electrical connection between the contact plug to be formed in the opening 506 and the semiconductor region 502. The metal layer 512 may be formed from a metallic material such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta), or their silide.

[0064] In some embodiments, the metal source may include a precursor comprising titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo), or a combination thereof. The second deposition process may be carried out at temperatures between approximately 300°C and approximately 800°C, and at pressures between 1 Torre and 50 Torre, respectively.

[0065] The second deposition process performed in block 440 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), at temperatures between approximately 100°C and 300°C.

[0066] In block 450, a metal filling process is performed to form a contact plug 514 in the opening 506, as shown in Figure 5E. The contact plug 514 may be formed from a contact plug metal material such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The contact plug 514 may contain a metal having a desired work function. The metal filling process in block 450 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor such as WF6 or a cobalt-containing precursor in a processing chamber, such as processing chambers 126, 128, or 130 shown in Figure 1.

[0067] After the metal filling process, the semiconductor structure 500 can be planarized using a chemical mechanical planarization (CMP) process.

[0068] Embodiments described herein provide a method and system for forming a contact epitaxial layer having an oxide barrier layer within a trench on a semiconductor device. The contact trench structure includes a metal contact plug formed within the trench and contacts that interface between the contact plug and a silicon-based channel in the semiconductor device. The contacts are formed from silicon germanium with a high germanium concentration by a selective epitaxial deposition process, thereby reducing parasitic resistance. The oxide barrier layer is formed from gallium (Ga) by a CVD immersion process. The method and system does not require an etching process to remove germanium (Ge) oxides, and therefore damage to the fabricated semiconductor structure is reduced.

[0069] The foregoing applies to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming an oxide barrier layer in a semiconductor structure, The method involves forming a contact layer on an exposed surface of a semiconductor region of a semiconductor structure in a first processing chamber, wherein the semiconductor region contains silicon germanium doped with a p-type dopant, and the contact layer contains silicon germanium (SiGe) in a germanium (Ge) ratio between 60% and 100%. By applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer in the first processing chamber, an oxide barrier layer containing gallium (Ga) is formed on the contact layer. Methods that include...

2. Forming the aforementioned contact layer The method according to claim 1, comprising selective epitaxial deposition of silicon germanium (SiGe) on the exposed surface of the semiconductor region.

3. The method according to claim 1, wherein the application of the gallium (Ga)-containing liquid precursor is performed at a temperature in the range of 300°C to 400°C.

4. The pre-cleaning process is performed on the exposed surface of the semiconductor region in the second processing chamber before forming the contact layer, wherein the exposed surface of the semiconductor region is placed within an opening formed in a dielectric layer disposed on top of the semiconductor region. After forming the oxide barrier layer, a deposition process is carried out in a third processing chamber to form a metal layer on the oxide barrier layer. The method according to claim 1, further comprising:

5. A metal filling process is performed to form a contact plug in the opening in the dielectric layer. The method according to claim 4, further comprising:

6. The method according to claim 5, wherein the metal layer comprises a material selected from titanium (Ti) silide, cobalt (Co) silide, nickel (Ni) silide, molybdenum (Mo) silide, and tantalum (Ta) silide.

7. The method according to claim 5, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

8. A method for forming an electrical contact in a semiconductor structure, Performing a pre-cleaning process on an exposed surface of a semiconductor region containing a first material, wherein the exposed surface of the semiconductor region is placed within an opening formed in a dielectric layer disposed on the semiconductor region. To form a contact layer containing a second material on the exposed surface of the semiconductor region, a selective epitaxial deposition process including a first deposition process and a first etching process is performed. An immersion process is performed to form an oxide barrier layer on the contact layer, A second deposition process is performed to form a metal layer on the aforementioned oxide barrier layer, A metal filling process is performed to form a contact plug in the opening in the dielectric layer. Includes, A method wherein the selective epitaxial deposition process and the immersion process are carried out without disrupting the vacuum environment.

9. The method according to claim 8, wherein the first material comprises silicon germanium doped with a p-type dopant.

10. The method according to claim 8, wherein the second material comprises silicon germanium (SiGe) having a germanium (Ge) ratio in the range of 60% to 100%.

11. The first deposition process includes epitaxial deposition of the second material on the exposed surface of the semiconductor region, The first etching process includes an etching process for removing an amorphous layer of the second material formed on the exposed surface of the dielectric layer. The method according to claim 8.

12. The immersion process includes applying a gallium (Ga)-containing liquid precursor to the surface of the contact layer at a temperature in the range of 300°C to 400°C. The said oxide barrier layer contains gallium (Ga), The method according to claim 8.

13. The method according to claim 8, wherein the metal layer comprises a material selected from titanium (Ti) silide, cobalt (Co) silide, nickel (Ni) silide, molybdenum (Mo) silide, and tantalum (Ta) silide.

14. The method according to claim 8, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

15. The first processing chamber and System controller and A processing system including, the system controller, The first processing chamber is used to form a contact layer on an exposed surface of a semiconductor region of a semiconductor structure, wherein the semiconductor region contains silicon germanium doped with a p-type dopant, and the contact layer contains silicon germanium (SiGe) in a germanium (Ge) ratio between 60% and 100%. In the first processing chamber, an oxide barrier layer containing gallium (Ga) is formed on the contact layer. A processing system configured to cause the aforementioned processing system to perform the above.

16. The processing system according to claim 15, wherein the application of the gallium (Ga)-containing liquid precursor is performed at a temperature in the range of 300°C to 400°C.

17. The second processing chamber, The third processing chamber and The system controller further includes, The pre-cleaning process is performed on the exposed surface of the semiconductor region in the second processing chamber before forming the contact layer, wherein the exposed surface of the semiconductor region is placed within an opening formed in a dielectric layer disposed on top of the semiconductor region. After forming the oxide barrier layer, a deposition process is carried out in the third processing chamber to form a metal layer on the oxide barrier layer. The processing system according to claim 15, further configured to cause the processing system to perform the above.

18. Fourth processing chamber It further includes, The aforementioned system controller A metal filling process is performed to form a contact plug in the opening in the dielectric layer. The processing system according to claim 17, further configured to cause the processing system to perform the above.

19. The processing system according to claim 18, wherein the metal layer comprises a material selected from titanium (Ti) silide, cobalt (Co) silide, nickel (Ni) silide, molybdenum (Mo) silide, and tantalum (Ta) silide.

20. The processing system according to claim 18, wherein the contact plug comprises a material selected from tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

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